Cortex-M3: Exceptions

o Asynchronous Exceptions = Interrupts

n Generated by hardware peripherals (when enabled):
o Signal toggle (I/O ports).
o Data receive (Serial peripherals)
o A/D conversion finished
o - …….

o Synchronous Exceptions = Exceptions

n Generated after instruction execution errors such as:
o Unauthorized Memory region access.
o Overflow.
o Divide by 0.
o - …..

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 Cortex-M3: Exceptions

o Exceptions are numbered 1 to 15 for system

exceptions and the rest 240 for external
interrupt inputs.(Total 256 entries in vector table)

o Most of the exceptions have programmable

priority, and a few have fixed priority.

o The value of the current running exception is

indicated by the special register IPSR or from the
NVIC’s Interrupt Control State Register.

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 Cortex-M3: Exceptions

Exception Exception Type Priority Description

Number
1 Reset -3 (Highest) Reset

2 NMI -2 Nonmaskable interrupt (external NMI

input)
3 Hard Fault -1 All fault conditions, if the corresponding
fault handler is not enabled
4 MemManage Programmable Memory management fault; MPU
Fault violation or access to illegal locations
5 Bus Fault Programmable Bus error, like Prefetch abort

6 Usage Fault Programmable Exceptions due to program error or trying

to access coprocessor
7-10 Reserved N/A —

11 SVCall Programmable System Service call

12 Debug Monitor Programmable Debug monitor

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 Cortex-M3: Exceptions

13 Reserved N/A —

14 PendSV Programmable Pendable request for system device

15 SYSTICK Programmable System Tick Timer

16 External Interrupt #0 Programmable External Interrupt

17 External Interrupt #1 Programmable External Interrupt

… … … …

255 External Interrupt #239 Programmable External Interrupt

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Cortex-M3: Exceptions (Vector Table)

o Vector Table contains

addresses (vectors) of
exception handlers and
ISRs.
o Main Stack Pointer initial value
in location 0.
n Set up by hardware during Reset.

o Vector Table can be relocated

to SRAM.
n Via the Vector Table Offset
(Register contained in the NVIC)

o The least-significant bit of

each vector must be 1,
indicating that the exception
handler is Thumb code.
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 LPC17xx: Interrupt Number Definition

o System_LPC17xx.c

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 LPC17xx: Vector Table definition

o Startup_LPC17xx.s

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 NVIC: Characteristics

o Nested Vector Interrupt Controller.

o NVIC is integrated into Cortex-M3 core.
o Supports 240 interrupt sources.
o 256 priority levels for each interrupt.
o NVIC hardware supports nested interrupts.
o Fast context switch.
o 12-cycle typical.
o Advanced features:
n Priority pre-emption
n Tail-chaining
n Late-arrival

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 NVIC: Interrupt sequence

o Pre-emption & Exit

n Stacking – Unstacking
o PC, xPSR, r0-r3, r12, LR
n Vector fetch.
n Register update:
o SP,PSR,PC,LR

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 NVIC: Interrupt Latency

o Deterministic interrupt latency

n Cortex-M3 has an interrupt latency of 12 cycles and
12 cycles to return from servicing.
o ARM7 does not have deterministic interrupt latency (24
to 42 cycles )
n Latency includes stacking the registers, vector fetch,
and fetching instructions for the interrupt handler.

IRQ

Cortex-M3 PUSH ISR PUSH

12 12

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NVIC: Interrupt Tail Chaining

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NVIC: Interrupt Pre-emption

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NVIC: Interrupt Late Arriving

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 NVIC: Exception States

o Inactive:
n The exception is not active and not pending.
o Pending:
n The exception is waiting to be serviced by the processor.
n An interrupt request from a peripheral or from software can
change the state of the corresponding interrupt to pending.
o Active:
n An exception that is being serviced by the processor but has not
completed.
n An exception handler can interrupt the execution of another
exception handler. In this case both exceptions are in the active
state.
o Active and pending
n The exception is being serviced by the processor and there is a
pending exception from the same source.

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NVIC: Interrupt Inputs and Pending Behavior

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NVIC: Interrupt Inputs and Pending Behavior

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 NVIC: Registers (I)

o Each interrupt input has several registers to control it:

n Enable/Disable Bit (ISERn/ICERn)

o Enable or disable the interrupt
o Can be set, cleared or read
n Pending Bit (ISPRn/ICPRn)
o If the pending bit is set, then the interrupt is pending
o An interrupt can be “pended” by setting the pending bit
o Pending bit can be set, cleared or read
n Active Bit (IABRn)
o A bit is set if the interrupt is executing or “active-stacked”
o Active register is normally read only
n Priority field (IPRn)
o 5 bits of priority for each interrupt

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NVIC: Registers (II)

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 NVIC: Registers (III)

o To disable exceptions:
n PRIMASK
o A 1-bit register, when this is set, it allows nonmaskable
interrupt (NMI) and the hard fault exception; all other
interrupts are masked.

n FAULTMASK
o A 1-bit register, when this is set, it allows only the NMI and all
other interrupts and fault handling exceptions are disabled.

n BASEPRI
o A register of up to 8-bits (depending on the bit-width
implemented for the priority level). It defines the masking
priority level. When this is set, it disables all interrupts of the
same or lower level; higher priority interrupts are still allowed.

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 NVIC: Software Interrupts (I)

o There are several ways to trigger an interrupt:

n External interrupt input.
n Setting an Interrupt Pending Register.
n Via the Software Trigger Interrupt Register (STIR) in
the NVIC.
o In most cases, some of the external interrupts are
unused and can be used as software interrupts.

o Software interrupts can work like Supervisor Calls to

allow access to system services.

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 NVIC: Software Interrupts (II)

o Supervisor Calls (SVC) are a common way to allow user

applications to access the application programming interface
(API) of an OS.
o By using an SVC instruction applications only need to know
what parameters to pass to the OS; they don’t need to know
the memory address of the OS function being called.
o SVCs are often used to call device drivers (operating
system functions that control peripherals).

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 Cortex-M3: Exceptions (Priority Level)

o A higher-priority exception can preempt a lower-priority

exception.
o Reset, NMI, and hard fault have fixed priority levels.
o Supports 256 levels of programmable priority.
o The reduction of priority levels can be implemented by cutting
out several lowest bits of the priority configuration register:

n 3 bits of priority level

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Implemented Not implemented, read as zero

n 4 bits of priority level

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Implemented Not implemented, read as

zero

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Cortex-M3: Exceptions (Priority Level)

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 System Control Block (SCB)

o Exception enables.
o Setting or clearing exceptions to/from the
pending state.
o Exception status (Inactive, Pending, or Active).
Inactive is when an exception is neither Pending nor
Active.
o Priority setting (for configurable system
exceptions)
o The exception number of the currently executing
code and highest pending exception.

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SCB: Registers (I)

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SCB: Registers (II)

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SCB: AIRCR register

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 SHPRx: System Handler Prority Registers

o The SHPR1-SHPR3 registers set the priority level (0 to 31, in

LPC17xx), of the exception handlers that have configurable
priority.
o SHPR1-SHPR3 are byte accessible.
o The system fault handlers, the priority field and register for
each handler are:

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SYSTICK: Exception Priority level

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 Cortex-M3: Exceptions (Priority Level)

o Examples of available exception priority levels for devices with

3-bits, 5-bits, and 8-bits priority registers:

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 Cortex-M3: Exceptions (Priority Level Register)

o This register is further divided into two parts: preempt

priority and subpriority.
o Using a Priority Group register, the priority-level configuration
register can be divided into two halves, i.e., the upper half
(preempt priority ) and the lower half (subpriority).
n Preempt priority: an interrupt or exception with a higher preempt
priority can preempt one with a lower preempt priority.
n Subpriority: the order when multiple interrupts or exceptions with the
same preempt priority occur at the same time.

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 Cortex-M3: Exceptions (Priority Level Register)

o Deciding the Effective Preempt priority and Subpriority Levels:

n 3-bits Priority Level Register.
n Priority Group set to 5.

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 AIRCR: Interrupt priority grouping field

o The PRIGROUP field allows us to change the size of the preemption group
field and priority subgroup. On reset this field defaults to priority group
zero.
o So, for example, if our MCU has four active priority bits we could select
priority group 5, which would give us four levels of preemption each with four
levels of subpriority.

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 NVIC: LPC17xx

o LPC17xx supports 35 vectored interrupts.

n ARM allows manufacturers flexibility to implement fewer than 240
o 32 interrupt priority levels.
n ARM allows flexibility to implement fewer than 256 levels
o Priority.
n A programmable priority level of 0-31 for each interrupt.
n A higher level corresponds to a lower priority, so level 0 is the highest
interrupt priority.
n Grouping of priority values into group priority and sub-priority fields.
o Stack Operations.
n The processor automatically stacks its state on exception entry and
unstacks this state on exception exit, with no instruction overhead.
o An External Non-Maskable Interrupt (NMI).
o Includes Wake-up Interrupt Controller (WIC).
n WIC only available in Cortex-M3 rev2

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NVIC: Registers

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 LPC17xx: Config. Interrupts priority

o Each priority register is divided into four eight bit priority fields,
each field being assigned to an individual interrupt vector.
o LPC176x Interrupt Vectors starts at ISR #16 (vector offset
0x40)
o Lower numbers are higher priority.
o The LPC17xx only uses 5 bits of this field to implement 32
levels of priority.
n However, you should note that the active priority bits are in the upper 5
bits of each priority field.
o By default the priority field defines levels of priority with level
zero the highest and 32 the lowest.
o Format the priority field into priority groups (pre-emption) and
subgroups (sub-levels).

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 LPC17xx: Config. Interrupts priority

o Interrupt source has an 5-bits interrupt priority value.

o The 5 bits are divided into preempting priority levels and
non-preempting “sub-priority” levels.
n Sub-priority levels only have an effect if the pre-empting priority levels are
the same.
n The software programmable PRIGROUP register field of the NVIC chooses
how many of the 5-bits are used for “group-priority” and how many are
used for “sub-priority”.
n Group priority is the pre-empting priority.

o Hardware interrupt number is lowest level of prioritization.

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 LPC17xx: Config. Interrupts priority

o The 5-bits interrupt priority value, are

divided into pre-empting priority levels
and non-preempting “sub-priority”
levels.
o The software programmable PRIGROUP
register field of the NVIC chooses how
many of the 5-bits are used for “group-
priority” and how many are used for “sub-
priority”.

Pre-empting Priority Sub-Priority

PRIGROUP Binary Point (Group Priority) (Sub-Level)
(3 bits) (Group: sub)
Bits Levels Bits Levels
2 5:0 5 groups, 0 sub-priority 5 32 0 0
3 4:1 4 groups, 1 sub-priority 4 16 1 2
4 3:2 3 groups, 2 sub-priorities 3 8 2 4

5 2:3 2 groups, 3 sub-priorities 2 4 3 8

6 1:4 1 group, 1 sub-priorities 1 2 4 16

7 0:5 0 group, 1 sub-priority 0 0 5 32

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 Ejemplo: Config. Interrupts priority

o We have two interrupts in our system - EINT0 and GPIO Interrupt (shared
with EINT3 channel) and we want to assign both interrupts under different
groups where EINT0 has a higher pre-empting priority than GPIO
Interrupt (EINT3):
n We can set PRIGROUP to 4 which will define 3 groups (3 bits) and 2 sub-levels (2 bits).
n We set priority field (bit 23:19) of EINT0 to 0 so it will 00000 which means EINT0 is from
group 0 and has sub-priority of 0 within group 0.
n We set priority field (bit 15:11) of GPIO Interrupt (EINT3) to 4 so it will be 00100 which
means GPIO Interrupt (EINT3) is from group 1 and has sub-priority of 0 within group 1.
n So if GPIO Interrupt is in the process of being serviced and if EINT0 is triggered, then EINT0
will be immediately serviced and upon completion, CPU will finish where if left off in the GPIO
Interrupt ISR routine (example of Nested Interrupt – Pre-emption).

Pre-empting Priority Sub-Priority

PRIGROUP Group: Sub (Group Priority) (Sub-Level)
(3 bits)
Bits Levels Bits Levels
2 5:0 5 groups, 0 sub-priority 5 32 0 0
3 4:1 4 groups, 1 sub-priority 4 16 1 2
4 3:2 3 groups, 2 sub-priorities 3 8 2 4

5 2:3 2 groups, 3 sub-priorities 2 4 3 8

6 1:4 1 group, 1 sub-priorities 1 2 4 16

7 0:5 0 group, 1 sub-priority 0 0 5 32

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 Ejemplo: Config. Interrupts priority

o We have two interrupts in our system - EINT0 and GPIO Interrupt (shared
with EINT3 channel) and we want to assign both interrupts under the
same group with different sub-priorities where GPIO Interrupt has a
higher sub-priority than EINT0:
n We can set PRIGROUP to 4 which will define 3 groups (3 bits) and 2 sub-levels (2 bits).
n We set priority field (bit 23:19) of EINT0 to 2 so it will 00010 which means EINT0 is from
group 0 and has sub-priority of 2 within group 0.
n We set priority field (bit 15:11) of GPIO Interrupt (EINT3) to 1 so it will be 00001 which
means GPIO Interrupt (EINT3) is from group 0 and has sub-priority of 1 within group 0.
n So if both interrupts take place at the same time, GPIO Interrupt will be serviced first and then
EINT0 Interrupt (example of Tail-Chaining)

Pre-empting Priority Sub-Priority

PRIGROUP Group: Sub (Group Priority) (Sub-Level)
(3 bits)
Bits Levels Bits Levels
2 5:0 5 groups, 0 sub-priority 5 32 0 0
3 4:1 4 groups, 1 sub-priority 4 16 1 2
4 3:2 3 groups, 2 sub-priorities 3 8 2 4

5 2:3 2 groups, 3 sub-priorities 2 4 3 8

6 1:4 1 group, 1 sub-priorities 1 2 4 16

7 0:5 0 group, 1 sub-priority 0 0 5 32

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LPC17xx: Interrupt Priority Registers

31 24 23 16 15 8 7 0

(19) (18) (17) (16)

Timer2 Timer1 Timer0 WDT IPR0
(23) (22) (21) (20)
UART2 UART1 UART0 Timer3 IPR1
(27) (26) (25) (24)
I2C1 I2C0 PWM1 UART3 IPR2
(31) (30) (29) (28)
SSP1 SSP0 SPI I2C2 IPR3
(35) (34) (33) (32)
EINT1 EINT0 RTC PLL0 IPR4
(39) (38) (37) (36)
BOD ADC EINT3 EINT2 IPR5
(43) (42) (41) (40)
I2S GP DMA CAN USB IPR6
(47) (46) (45) (44)
QEI MC PWM RI Timer Ethernet IPR7
(50) (49) (48)
CAN Active USB Active PLL1 IPR8

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 NVIC: Bus Fault Exception

o Bus faults are produced when an error response is

received during a transfer on the AHB interfaces.
o Bus fault due to:
n 1. Instruction prefetch abort.
n 2. Data read/write abort.
n 3. Stack PUSH in the beginning of interrupt processing.
n 4. Stack POP at the end of interrupt processing.
n 5. Reading of an interrupt vector address when the
processor starts the interrupt-handling sequence.

o Bus Fault Status Register (BFSR) is used in the

exception handler to determine the cause of the
fault.

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 NVIC: Memory Management Fault Exception

o Common memory manage faults include:

n 1. Access to memory regions not defined in MPU setup.
n 2. Execute code from nonexecutable memory regions.
n 3. Writing to read-only regions.
n 4. An access in the user state to a region defined as
privileged access only.

o Memory Management Fault Status Register

(MFSR) is used in the exception handler to
determine the cause of the fault.

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 NVIC: Usage Fault Exception

o Usage faults can be caused by:

n 1. Undefined instructions.
n 2. Coprocessor instructions.
n 3. Trying to switch to the ARM state (This can happen if
you load a new value to PC with the LSB equal to 0).
n 4. Invalid interrupt return (Link Register contains
invalid/incorrect values)
n 5. Unaligned memory accesses using multiple load or
store instructions.
n 6. Divide by zero.

o Usage Fault Status Register (UFSR) is used in

the exception handler to determine the cause of
the fault.

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 NVIC: Hard Fault Exception

o The hard fault handler can be caused by:

n Usage faults, bus faults, and memory
management faults if their handler cannot be
executed.
n A bus fault during vector fetch.

o Hard Fault Status Register (HFSR) is used in the

exception handler to determine the cause of the
fault.

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 SYSTICK Timer

o SYSTICK timer is a 24-bit down counter. The counter loads the

reload value from the RELOAD register when it reach zero.

o It always run until the enable bit in the SYSTICK Control and
Status register is cleared.

o 2 configurable Clock
sources.

o Suitable for Real Time OS

or other scheduled tasks.

o With 100 MHz bus clock,

decrements every 10ns.

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 SYSTICK configuration

o Initialization (3 steps)
n Step1: Specify the RELOAD value.
n Step2: Clear the counter via NVIC_CURRENT
n Step3: Set CLK_SRC=1, interrupt action (INTEN), and enable counter
(ENABLE) via NVIC_CTRL.
Address 31-24 23-17 16 15-3 2 1 0 Name
$E000E010 0 0 COUNT 0 CLK_SRC INTEN ENABLE NVIC_ST_CTRL_R
$E000E014 0 24-bit RELOAD value NVIC_ST_RELOAD_R
$E000E018 0 24-bit CURRENT value of SysTick counter NVIC_ST_CURRENT_R

o CMSIS function:
n SysTick_Config(uint32_t ticks)

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 CMSIS: Cortex Microcontroller Software Interface Standard

o CMSIS is a vendor-independent
hardware abstraction layer (HAL)
for the Cortex-M processor series.

o CMSIS enables consistent and simple software interfaces to

the processor and the peripherals, simplifying software re-
use, reducing the learning curve for new microcontroller
developers and reducing the time to market for new devices.

o Standardizing the software interfaces across all Cortex-M

silicon vendor products.

o Significant cost reductions in software development!

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 CMSIS: Cortex Microcontroller Software Interface Standard

o The CMSIS consists of the following components:

n CMSIS-CORE: provides an interface to Cortex-M0, Cortex-M3, Cortex-
M4, SC000, and SC300 processors and peripheral registers.
n CMSIS-DSP: DSP library with over 60 functions in fixed-point
(fractional q7, q15, q31) and single precision floating-point (32-bit)
implementation.
n CMSIS-RTOS API: standardized programming interface for real-time
operating systems for thread control, resource, and time management.
n CMSIS-SVD: System View Description XML files that contain the
programmer's view of a complete microcontroller system including
peripherals.

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 CMSIS: Cortex Microcontroller Software Interface Standard

o Hardware Abstraction Layer (HAL) for Cortex-M processor

registers:
n NVIC, MPU
o Standardized system exception names. For example:
n void SVC_Handler()
n void UART0_IRQHandler()
o Standardized method of header file organization.
o Common method for system initialization.
n SystemInit()
o Standardized intrinsic functions. For example:
n void __disable_irq(void), void __enable_irq(void)
o Common access functions for communication.
o Standardized way for embedded software to determine
system clock frequency:
n SystemFrequency variable is defined in device driver code.
n SystemCoreClock, in Keil !!!!!!
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CMSIS: Accessing Core Registers

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 CMSIS: NVIC functions

o In addition, the CMSIS provides a number of functions for NVIC

control:

Only Ext.
Interrupt.

o The CMSIS standard provides the macro __NVIC_PRIO_BITS,

which specifies the number of NVIC priority bits defined in
a given ARM Cortex-M implementation.

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NVIC access: CMSIS examples (I)

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 NVIC access: CMSIS examples (II)

o CMSIS NVIC functions NVIC_EnableIRQ(), NVIC_GetActive()

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 CMSIS: Peripheral Access

o Describes naming conventions, requirements, and optional

features for accessing peripherals.
o Each peripheral provides a data type definition with a name that
is composed of a prefix <device abbreviation>_ and the
<peripheral name>_
n for example, LPC_UART for the device LPC and the peripheral UART.
n The intention is to avoid name collisions caused by short names.
n If more peripherals exist of the same type, identifiers have a postfix
consisting of a digit or letter, for example LPC_UART0, LPC_UART1.
o The data type definition uses the standard C data types from
the ANSI C header file <stdint.h>.
n IO Type Qualifiers are used to specify the access to peripheral variables.
n IO Type Qualifiers are indented to be used for automatic generation of
debug information of peripheral registers and are defined as shown below:

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 CMSIS: Peripheral Access (example)

o The following typedef is an example for a UART.

n <device abbreviation>_UART_TypeDef: defines the generic register layout for all UART channels
in a device.

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 CMSIS: Peripheral Access (ex: cont.)

o To access the registers of the UART defined above, pointers to a

register structure are defined.

o In this example <device abbreviation>_UART# are two pointers to

UARTs defined with above register structure:
n #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
n #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )

o The registers in the various UARTs can now be referred in the user
code as shown below:
n LPC_UART1->DR // is the data register of UART1.

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 CMSIS: Peripheral access (min. requirements)

o To access the peripheral registers and related function in a device, the

files device.h and core_cm3.h define as a minimum:
n The Register Layout Typedef for each peripheral that defines all register names.
RESERVED is used to introduce space into the structure for adjusting the addresses
of the peripheral registers.

n Base Address for each peripheral.

o #define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */

n Access Definitions for each peripheral. In case of multiple peripherals that are using
the same register layout typdef, multiple access definitions exist (LPC_UART0,
LPC_UART2).
o #define SysTick ((SysTick_Type *) Systick_BASE) /* SysTick access definition */

o These definitions allow accessing peripheral registers with simple

assignments:
n SysTick->LOAD= 0xFFFF; // 65636 counts

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 CMSIS: Files for the LPC17xx (NXP)

core_cmInstr.h

No añadir en la
nueva versión !! core_cmFunc.h

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CMSIS: Files for LPC17xx (NXP)

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 CMSIS: system_LPC17xx.c file

o system_LPC17xx.c

uint32_t SystemCoreClock
= __CORE_CLK;
/*!< System Clock
Frequency (Core Clock)*/

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 CMSIS: core_cm3.h file

o As the LPC17xx is Cortex-M3 based, the core files are

“core_cm3.h” and “core_cm3.c”.
o The files “core_cm3.h” and “core_cm3.c” are standard across all
vendor devices that have the Cortex-M3 at their core.
o A fragment of “core_cm3.h” is shown in the figure:

5 bits
(LPC17xx)

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 CMSIS: SYSTICK configuration

o core_cm3.h:

#define Ftick 100 // SYSTICK Frequency interrupt.

SysTick_Config(SystemCoreClock/Ftick); // 100 Hz.

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 CMSIS: startup_LPC17xx.s

o The key variations in startup_LPC17xx.s for the different compilers:

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