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Digital Integrated Circuits Problem Sheet 2: OL OH M

1. The document contains 7 problems related to digital integrated circuits and CMOS inverters. It involves calculating voltages levels like VOH, VOL, VIL, VIH and propagation delays given transistor parameters like threshold voltages and sizing for different inverter configurations operating between 0-5V. 2. Problem 1 asks to calculate voltage levels for a given inverter assuming nMOS transistors are velocity saturated. Problem 2 involves plotting the transfer characteristics of a circuit and finding VOH and VOL. 3. Problems 3-7 involve calculating voltage levels, power dissipation, operating modes and propagation delays for various inverter circuits and a low swing driver given transistor parameters and sizing for 0.25um technology.

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Chanandler Bong
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89 views2 pages

Digital Integrated Circuits Problem Sheet 2: OL OH M

1. The document contains 7 problems related to digital integrated circuits and CMOS inverters. It involves calculating voltages levels like VOH, VOL, VIL, VIH and propagation delays given transistor parameters like threshold voltages and sizing for different inverter configurations operating between 0-5V. 2. Problem 1 asks to calculate voltage levels for a given inverter assuming nMOS transistors are velocity saturated. Problem 2 involves plotting the transfer characteristics of a circuit and finding VOH and VOL. 3. Problems 3-7 involve calculating voltage levels, power dissipation, operating modes and propagation delays for various inverter circuits and a low swing driver given transistor parameters and sizing for 0.25um technology.

Uploaded by

Chanandler Bong
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital 

Integrated Circuits 
Problem sheet ‐2 
1. 
Find VOL, VOH and VM for the given inverter. Assume 
the  nMOS  transistors  to  be  velocity  saturated 
MOSFETS.  Also  find  VIL,  VIH,  NMH  and  NML. 
Assume kn′=115μA/V2 ; γ=λ=0. 

2. 
Consider the circuit given . Assume VDD=3.3V, VTOn=0.75V, 
VTOp=‐0.9V,  |2ΦF|=0.58V,  γ=0.071V‐0.5  for  nMOS  and  
|2ΦF|=0.6V,  γ=‐0.135V‐0.5  for  pMOS.  Plot  roughly  the  VTC 
of the circuit and fing VOH and VOL of the circuit.

   
3. 
(i) Find VOL, VOH, VIL and VIH of the given inverter. 
(ii)  Find NMH and NML. 
(iii) Compute  the  average  power  dissipation  for   
(a) Vin=0V (b) Vin=2.5V. 
k’=115μAV‐2,  λ=0.06V‐1,  VTO=0.43V  and  VDSAT=0.63V. 
Assume the transistor is a velocity saturated nMOST. 
 

4. 
In the given circuit nMOS transistors M1 and M2 are similar except 
that M2 has a negative threshold voltage =‐0.4V. Assume Vin has a 
swing of 0 to 2.5V. 
(i) If Vin=0V what is Vout? In what mode M1 is operating? 
(ii) Find out for Vin=2.5V. In what mode M2 is operating? 
M1 → k’=115μAV‐2, VTO=0.43V and λ=γ=0. Assume both M1 and M2 
are long channel MOSTs. 

 
5.  Consider a CMOS inverter with VDD=5V, |VTp|=VTn=1V, kn=kp=100μA/V2. Find VIL, VIH, VOL, VOH 
and VM. Assume long channel MOSTs 
 
6.  Design a minimum size CMOS inverter of 0.25μm technology with switching threshold of 1.25V 
 
7.  Consider the following low swing driver consisting of NMOS devices M1 and M2 (0.25μ CMOS 
technology). Assume an NWELL implementation. Assume that the inputs IN and IN′ have a 0V 
to  2.5V  swing  and  that  IN  =  0V  when  IN′=  2.5V  and  vice‐versa.  Also  assume  that  there  is  no 
skew between IN and IN′ (i.e., the inverter delay to derive IN from IN is zero). 
To what voltage is the bulk terminal of M2 connected? 
What is the voltage swing on the output node as the inputs swing from 0V to 2.5V. Find the low 
value and the high value. 
Assume that the inputs IN and IN have zero rise and fall times. Assume a zero skew between 
IN  and  IN.  Determine  the  low  to  high  propagation  delay  for  charging  the  output  node 
measured from the 50% point of the input to the 50% point of the output. Assume that the total 
load capacitance is 1pF, including the transistor parasitics. 

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