CHAPTER 1

Introduction To Microprocessors and

The 8085/8086 Microprocessor
Architecture
 CONTENTS
 Introduction
 Definitions
 Microprocessor based
system
 Evolution of microprocessor
 8085 architecture
 General Information
 Bus structure
 ALU
 Registers
 Control Unit
 Interrupts
 Pin Diagrams

2
INTRODUCTION
 Microprocessor
 is the logic circuitry that responds to and processes
the basic instructions that drives a computer
 silicon chip which includes
 ALU,
 register circuits and
 control circuits

 The microprocessor is a programmable device that takes

in numbers, performs on them arithmetic or logical
operations according to the program stored in memory and
then produces other numbers as a result 3
MICROPROCESSOR BASED SYSTEM
 Block diagram

INPUT OUTPUT
MICROPROCESSOR

4
MEMORY
MICROPROCESSOR BASED SYSTEM
 Block diagram

INPUT/OUTPUT ALU

SYSTEM BUS
Register Control

MEMORY

5
MICROPROCESSOR BASED SYSTEM
 System bus interface

ADDRESS BUS
Microprocessor

CONTROLBUS

DATABUS

INTERFACE

RAM ROM

PHERIPHERAL 6
EVOLUTION OF MICROPROCESSOR
 1st generation microprocessor:
 In 1971
 Intel 4004
 4 bit processing
 Speed: 108KHz

 PMOS transistors

 addressed 4096

 45 instruction set

 Problem
 Low Speed , not compatible with TTL
 small number of Instruction , for video game and control
application
 Memory size, less memory address 7
 Word width, 4/8 – bit width
EVOLUTION OF MICROPROCESSOR
 1st generation microprocessor cont..
 4-bit Microprocessors
 INTEL 4004
 INTEL 4040

 FAIRCHILD PPS-25

 ROCKWELL PPS-4

 NATIONAL IMP-4

 8-bit Microprocessors
 INTEL 8008
 NATIONAL IMP-8

 ROCKWELL PPS-8

 AMI 7200

 MOSTEK 5065 8
EVOLUTION OF MICROPROCESSOR
 2nd generation Microprocessor:
 NMOS technology
 faster speed, higher density and better reliability
 addressed an expanded memory size (64K bytes)
 48 Instruction set
 More number of on-chip decoded timing signals,
 address more I/O Ports
 Better Interrupt handling capabilities
 Problem:
 Memory size
 Speed

 Instruction set limitation

9
EVOLUTION OF MICROPROCESSOR
2nd generation Microprocessor cont..
 Examples:
 8-bit Microprocessors
 INTEL 8080
 INTEL 8085

 FAIRCHILD F8

 MOTOROLA M6800

 ZILOG Z-80

 SIGNETICS 2650

 12-bit Microprocessors
 INTERSIL 6100
 TOSHIBA TLCS-12

10
EVOLUTION OF MICROPROCESSOR
3rd generation Microprocessor
 Introduced in 1978.
 16-bit microprocessors
 HMOS (High Density MOS) technology.
 better speed and higher packing density than
NMOS.
 Size of internal registers were 8/16/32 bits,
 had the multiply/divide/arithmetic hardware
 Physical memory space was from 1 to 16 MB
 powerful interrupt and hardware capabilities
 Segmented address and virtual memory features.
11
EVOLUTION OF MICROPROCESSOR
3rd generation Microprocessor cont..
 Examples
 16-bit Microprocessors
 INTEL 8086
 INTEL 8088

 INTEL 80186

 INTEL 80286

 MOTOROLA-68000

 MOTOROLA-68010

 NATIONAL NS-16016

 TEXAS INSTRUMENTTMS-99000

 INTERSIL 6100

 TOSHIBA TLCS-12

 ZILOG Z-8000 12
EVOLUTION OF MICROPROCESSOR
4th generation microprocessor:
 32 bit microprocessor
 HCMOS(High-density n- type CMOS transistor
technology)
 addressed up to 4G bytes of memory
 Examples
 INTEL 80386
 INTEL 80486
 NATIONAL NS16022
 MOTOROLA MC 88100
 MOTOROLA M-68020
 MOTOROLA M-68030
 BELLMAC-32 13
EVOLUTION OF MICROPROCESSOR
 5th generation microprocessor:
 Introduced by INTEL Corporation in 1993
 PENTIUM with 64 data bus.
 Clock frequency of 60 MHz and 66 MHz
 Speed of 110 MIPS

14
ARCHITECTURE OF 8085
General information
 8-bit general purpose µp
 NMOS technology
 Capable of addressing 64 k of memory
 216 ---> 64k
 Address bus: 16, A0 to A15
 Data bus : 8, D0 to D7
 supports external interrupt request
 Six 8-bit general purpose register arranged in pairs:
BC, DE, HL.
 DIP (Dual in line package) of 40 pins
 Requires +5 v power supply
 Can operate with 3 MHz clock
15

8085 MICROPROCESSOR
ARCHITECTURE OF 8085

16

8085 MICROPROCESSOR
8085 BUS STRUCTURE
 Address bus
 Control bus

 Data bus

ADDRESS BUS

CONTROL BUS
8085

DATA BUS

INTERFACE

RAM ROM

17
PHERIPHERAL
8085 ARCHITECTURE
8085 BUS STRUCTURE: ADDRESS BUS
 16 lines generally : A0 to A15.
 unidirectional: bits flow from the MPU to peripheral devices.
 The MPU uses the address bus to perform the first function:
identifying a peripheral or a memory location.

ADDRESS BUS
Microprocessor

INTERFACE
RAM ROM
18
8085 ARCHITECTURE
PHERIPHERAL
8085 BUS STRUCTURE: DATA BUS
 Group of 8 lines used for data flow.
 bi-directional
 data flow between the MPU and memory and peripheral devices.
 The MPU uses the data bus to perform the second function:
 transferring binary information.
 8-bit data ranging from 00 to FF (28 = 256 numbers)
8085

DATA BUS

INTERFACE
RAM ROM 19

8085 ARCHITECTURE PHERIPHERAL

8085 BUS STRUCTURE: CONTROL BUS
 Synchronization and timing
 MPU generates specific control signals for every
operation it performs.
 to identify a device type with which the MPU wants
to communicate.

CONTROL BUS
8085

INTERFACE
RAM ROM 20

8085 ARCHITECTURE PHERIPHERAL

8085 BUS STRUCTURE:
ADDRESS BUFFER AND ADDRESS-DATA BUFFER
 The address bus has :
 8 signal lines A8 – A15 which are unidirectional.
 8 address bits are multiplexed (time shared) with the 8 data bits.
 AD0 – AD7 are bi-directional

 During the execution of the instruction, these lines

carry the address bits during the early part, then
during the late parts of the execution, they carry the 8
data bits.
 The high order bits of the address remain on the bus for three clock
periods
 the low order bits remain for only one clock period

 to separate the address from the data, we can

use a latch
21

8085 ARCHITECTURE
8085 ARITHMETIC AND LOGICAL UNIT
 Arithmetic & logic circuits
 carries out the arithmetic and logic calculations
 The arithmetic operations are:
 ADD, SUB, compare, increments, decrements and
complements etc.
 logical operations are:
 AND, OR, XOR and Rotate.
 Consists of accumulator (A),
 flag register (F)
 a temporary register
 not accessible by the programmer
 result
of these operations could be placed in the
accumulator or elsewhere through the internal
bus. 22

8085 ARCHITECTURE
REGISTERS OF 8085
 General Purpose Registers
 B, C, D, E, H & L (8 bit registers)
 Can be used singly
 Can be used as 16 bit register pairs
 BC, DE, HL
 H & L can be used as a data pointer (holds memory
address)
.

B C
D E
H L
23

8085 ARCHITECTURE
 Accumulator Flag
REGISTERS OF 8085 B C
 Special Purpose Registers D E
H L
 Accumulator (8 bit register)
 Store 8 bit data
 Store the result of an operation

 Store 8 bit data during I/O transfer

 Flag register
 8 bit register
 shows the status of the microprocessor before/after an

operation
 S (sign flag), Z (zero flag), AC (auxiliary carry flag),
P (parity flag) & CY (carry flag)

D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY
24

8085 ARCHITECTURE
REGISTERS OF 8085
 Special Purpose Registers
 Flag register
 Sign flag bit
 Used for indicating the sign of the data in the

accumulator
 The sign flag is set if negative (1 – negative)
 The sign flag is reset if positive (0 –positive)

D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY

25

8085 ARCHITECTURE
REGISTERS OF 8085
 Special Purpose Registers
 Flag register
 Zero Flag
 Is set if result obtained after an operation is 0

 Is set following an increment or decrement operation

of that register

D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY

26

8085 ARCHITECTURE
REGISTERS OF 8085
 Special Purpose Registers
 Flag register
 Carry Flag
 Is set if there is a carry or borrow from arithmetic

operation

 1011 0101
+ 0110 1100
---------------
Carry 1 0010 0001

D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY
27

8085 ARCHITECTURE
REGISTERS OF 8085
 Special Purpose Registers
 Flag register
 Auxiliary Carry Flag
 Is set if there is a carry out of bit 3

D7 D6 D5 D4 D3 D2 D1 D0
S Z X AC X P X CY

 Parity Flag
 Is set if parity is even

 Is cleared if parity is odd

 Program status word(PSW): accumulator + flag register

28

8085 ARCHITECTURE
REGISTERS OF 8085
 Special Purpose Registers
 The Program Counter (PC)
 is used to control the sequencing of the execution of
instructions.
 holds the address of the next instruction.

 16 bits wide.

Accumulator Flag
B C
D E
H L
Program counter(PC)

29

8085 ARCHITECTURE
 REGISTERS OF 8085:
 Special Purpose Registers
 The Stack pointer
 16-bit register that is used to point into memory.
 points to is a special area called the stack.

 The stack is an area of memory used to hold

data that will be retrieved soon.

 The stack is usually accessed in a Last In First

Out (LIFO) fashion.

Accumulator Flag
B C
D E
H L
Program counter(PC)
30
Stack pointer
8085 ARCHITECTURE
REGISTERS OF 8085: TIMING AND CONTROL UNIT
 Timing and Control Unit
 Instruction Register and Decoder
 Control signals

 Instruction Register(IR) & Decoder

 Non Programmable Registers
 Instruction is stored in IR after fetched by processor
 Decoder decodes instruction in IR

31

8085 ARCHITECTURE
REGISTERS OF 8085: TIMING AND CONTROL UNIT
Control Signals
 X1, X2 and CLK Out
 Two pins X1 and X2 are provided to be externally
connected to a quartz crystal
 Clock signal of fixed frequency is generated through
the internal circuitry of the processor.
 half of the crystal frequency.
 quartz crystal of 6.144 MHz is used in this processor.
 clock frequency of 3.072 MHz

32

8085 ARCHITECTURE
REGISTERS OF 8085: TIMING AND CONTROL UNIT
Control Signals
 Address Latch Enable (ALE)
 During the first clock cycle of the machine cycle
ALE is high
 which enables the lower 8-bit of the address to be latched
either into the memory or external latch.
 IO/ M (Input Output / Memory)
 address and data is meant for either I/O devices or memory
 high (1) to the I/O devices

 low (0) to the memory

33

8085 ARCHITECTURE
REGISTERS OF 8085: TIMING AND CONTROL UNIT
Control Signals
 /RD (Read ) Signal
 active low signal
 connected to output enable signal of memories to read or

 Connected to enable input / output buffer to read.

 /WR (Write) Signal

 active low.
 used to write to the memory or input / output devices.

34

8085 ARCHITECTURE
 REGISTERS OF 8085: TIMING AND CONTROL UNIT
Control Signals
o Status Signals (S0, S1)
o along with IO/ M signal indicate the type of machine
cycle in progress.
o type of machine cycle are :
o op code fetch cycle
o memory read cycle
o memory write cycle
o I/O read cycle or I/O write cycle

35

8085 ARCHITECTURE
REGISTERS OF 8085: TIMING AND CONTROL UNIT
Control Signals
o Hold and HLDA
o used for DMA (Direct Memory Access) operation.
o HOLD signal is high,
o CPU temporarily relinquishes its operation by floating the
address, data and control buses;
o DMA operation is started.
o A high HLDA (Hold Acknowledge) signal is also sent to
DMA controller
o Whenever the data transfer is complete, then the
control to CPU is returned back by sending
o A low HOLD and HLDA signal
36

8085 ARCHITECTURE
REGISTERS OF 8085: TIMING AND CONTROL UNIT
Control Signals
o READY signal (Input)
o To synchronize the speed of CPU and peripheral
devices
o If the READY signal is high the peripheral device is
ready and the processor can complete the data
transfer.
o If this signal is low the microprocessor waits (by
generating a number of NOP T-states) till
it goes high.

37

8085 ARCHITECTURE
INTERRUPT OF 8085:
 Interruption of main program in response to event from I/O
device.
 Interrupt signals
 initiated by an external device to request the microprocessor
to do a particular task or work.
 five hardware interrupts signals
Types of interrupt priority
 TRAP 1
 RST 7.5 2
 RST 6.5 3
 RST 5.5 4
 INTR 5
 microprocessor acknowledges the interrupt by the active
low INTA (Interrupt Acknowledge) signal.

38

8085 ARCHITECTURE
INTERRUPT 8085:
 All interrupts of 8085 are vector interrupt except
INTR
 They referenced for address of the interrupt
subroutines
 All interrupt except TRAP are Maskable
 Maskable: if particular input is enabled interrupted

39

8085 ARCHITECTURE
PIN DESCRIPTION OF 8085

40

8085 ARCHITECTURE
PIN DESCRIPTION OF 8085

41

8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 PIN NOS. 1 and 2: X1 and X2
 connected to an external quartz crystal, L-C or R-C
 drives the internal clock generator.
 divides the frequency by a factor of two.
 The circuit produces two clock signals
 Φ1 (CLK) and Φ2 (CLK ) to derive the internal circuit of the
microprocessor.
 A 6.144 MHz crystal is used to provide 3.072 MHz
internal clock frequency.
 PIN NO. 3 :RESET OUT
 indicates that CPU is being reset.
 When it is Set(1) , system is reset. 42

8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 PIN NO . 4 and 5: SOD/SID
 SOD (Serial Out Data) and SID (Serial In Data)
terminals respectively.
 The SOD output pin can deliver a serial data stream
to a peripheral device.
 PIN NOS. 6 to 11: Interrupt
 TRAP (Pin No.6) I Priority
 RST 7.5 (Pin No. 7) II Priority
 RST 6.5 (Pin No. 8) III Priority
 RST 5.5 (Pin No. 9) IV Priority
 INTR (Pin No. 10) V Priority
43

8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 TRAP, RST 7.5, RST 6.5 and RST 5.5 are also called
vector interrupts,
 has fixed memory location (vector location) for the transfer
of control from the normal execution of the routine.
 The vector locations of these
Interrupts Memory locations
 TRAP 0024 H
 RST 7.5 003C H
 RST 6.5 0034 H
 RST 5.5 002C H
 INTR pin 10
 is enabled or disabled by the instructions ET (Enable
Interrupts) or DI (Disable Interrupts)respectively.
 /INTA: pin11
44
 Interrupt acknowledge
8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 PIN NOS. 12 to 19
 AD0-AD7 form bi-directional multiplexed
Address/Data Bus.
 The least significant 8 bits of the memory address (or
I/O Address) appear on the bus during the first T-
states of a machine cycle.
 It then becomes the data bus during the next T-
states.
 PIN NO. 20
 is the ground terminal.
 PIN NOS. 21 to 28
 A8-A15 form unidirectional most significant 8 bits of 45
memory address or 8 bits of the I/O address.
8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 PIN NOS. 29 and 33
 Status signals , S0 and S1 respectively
 PIN NO. 30
 ALE (Address Latch Enable) terminal.
 High(1)
 the AD0-AD7 is the lower 8 bits of the address.
 Low(0)
 The AD0- AD7 is data bit for data transfer
 separates the low order address and data from the
multiplexed Address/data Bus.

46

8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 PIN NO. 31
 /WR (Write bar)
 A low generated by the microprocessor sends (writes) data
into I/O devices or memory.
 PIN NO. 32
 A low RD signal generated by the microprocessor reads
(receives) the data from the I/O devices or memory
locations.
 PIN NO. 34
 IO/M signal which is one of the status signals.
 PIN NO. 35
 READ signal forces the microprocessor to wait till the data
become available from the memory or input/output devices.
 to synchronize the speed of the microprocessor with I/O
devices or memory as the memory or I/O devices are not as
fast as the microprocessor. 47

8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 PIN NO. 36 /RESETIN
 operated by the operator using the RESET button or
from the other source.
 When this signal is low, the CPU will reset the
 program counter,
 instruction register,

 all interrupts (except TRAP) are disabled,

 SOD signal becomes low and

 Data, address and control buses are floated.

 PIN NO. 37
 CLK OUT signal.
 it is derived from the on-chip oscillator
48
 goes to peripherals to synchronize their timings.
8085 ARCHITECTURE
PIN DESCRIPTION OF 8085
 PIN NOS. 38-39
 HOLD and HLDA (Hold Acknowledge) signals
respectively.
 re used in DMA (Direct Memory Access) operations.
 when any I/O device indicates that the data are ready
for DMA transfer, a high HOLD signal is sent by the
DMA controller
 The microprocessor then sends a high signal to DMA
controller
 PIN NO. 40
 +VCC,
 to be externally connected to +5 volt d.c. supply. 49

8085 ARCHITECTURE