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8086 - Memory Interfacing

The 8086 microprocessor uses a 20-bit address to access 1MB of memory divided into two 512KB banks. Two 4KB RAM chips and two 4KB ROM chips are interfaced with the 8086. The RAM chips are mapped to the lower addresses from 00000H to 01FFFH. The ROM chips are mapped to the higher addresses from FE000H to FFFFFH.

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0% found this document useful (0 votes)
766 views5 pages

8086 - Memory Interfacing

The 8086 microprocessor uses a 20-bit address to access 1MB of memory divided into two 512KB banks. Two 4KB RAM chips and two 4KB ROM chips are interfaced with the 8086. The RAM chips are mapped to the lower addresses from 00000H to 01FFFH. The ROM chips are mapped to the higher addresses from FE000H to FFFFFH.

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Rocky Samrat
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8086 Memory Interfacing

8086 has 20 bits address line.

So, 2^20 = 1MB Memory.

00000 H

RAM

ROM

FFFFF H
• Interface two 4KX8 EPROM and two 4KX8 RAM chips with 8086.

Solution:

Capacity of 2 Chips = 4K X 8 X 2 = 8K X 8 = 8KB

Consider, EA of ROM = FFFFF H

Size = 8KB = 8 X 1KB = 2^3 X 2^10 = 2^13

0000 0001 1111 1111 1111 = 01FFF H

So, SA of ROM = FFFFF H – 01FFF H = FE000 H

Consider, SA of RAM = 00000 H

Now, 4KB = 2^2X2^10 = 2^12

So, Address Lines = A1 – A12

Ao = Bank Selection (Even/Odd)


The 8086 microprocessor uses a 20-bit address to access memory. With 20-bit address the
processor can generate 220 = 1 Mega address. The basic memory word size of the memories
used in the 8086 system is 8-bit or 1-byte (i.e., in one memory location an 8-bit binary
information can be stored). Hence, the physical memory space of the 8086 is 1Mb (1 Mega-
byte).

For the programmer, the 8086 memory address space is a sequence of one mega-byte in which
one location stores an 8-bit binary code/data and two consecutive locations store 16-bit binary
code/data. But physically (i.e., in the hardware), the 1Mb memory space is divided into two
banks of 512kb (512kb + 512kb = 1Mb). The two memory banks are called Even (or Lower)
bank and Odd (or Upper) bank.

The 8086-based system will have two sets of memory IC's. One set for even bank and another
set for odd bank. The data lines D0-D7 are connected to even bank and the data lines D8 -D15 are
connected to odd bank. The even memory bank is selected by the address line Ao and the odd
memory bank is selected by the control signal BHE. The memory banks are selected when these
signals are low(active low). Any memory location in the memory bank is selected by the address
line A1 to A19.
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

SA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RAM1

EA 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0

SA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RAM2

EA 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

SA 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
ROM1

EA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

SA 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1
ROM2

EA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Memory SA EA
RAM1 Even (Lower) Bank 00000 H 01FFE H
RAM2 Odd (Higher) Bank 00001 H 01FFF H
ROM1 Even (Lower) Bank FE000 H FFFFE H
ROM2 Odd (Higher) Bank FE001 H FFFFF H

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