Ingenic® JZ4770

Board Design Guide

Revision: 1.0
Date: July. 2011
Ingenic JZ4770
Board Design Guide

Copyright © Ingenic Semiconductor Co. Ltd 2011. All rights reserved.

Release history

Date Revision Change

July. 2011 1.0 First release

Disclaimer

This documentation is provided for use with Ingenic products. No license to Ingenic property rights is
granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to
the usage, or intellectual property right infringement except as provided for by Ingenic Terms and
Conditions of Sale.

Ingenic products are not designed for and should not be used in any medical or life sustaining or
supporting equipment.

All information in this document should be treated as preliminary. Ingenic may make changes to this
document without notice. Anyone relying on this documentation should contact Ingenic for the
current documentation and errata.

Ingenic Semiconductor Co., Ltd.

Room 108, Information Center Block A

Zhongguancun Software Park, 8 Dongbeiwang west Road,
Haidian District, Beijing China, 100193
Tel: 86-10-82826661
Fax: 86-10-82825845
Http: //www.ingenic.cn
 Content

Content

1 Overview............................................................................................ 1
1.1 Introduction ............................................................................................................................. 1
1.2 Reference Platform ................................................................................................................. 2

2 Platform Stack-Up and Placement ..................................................... 3

2.1 General Design Considerations.............................................................................................. 3
2.2 Nominal 6-Layer Board Stack-Up ........................................................................................... 3
2.3 PCB Technology Considerations ............................................................................................ 4

3 Static Memory Interface Design Guidelines....................................... 6

3.1 Overview ................................................................................................................................. 6
3.2 Boot Memory........................................................................................................................... 6
3.3 NAND Flash Connection......................................................................................................... 7

4 DDR2 SDRAM ................................................................................... 8

4.1 Overview ................................................................................................................................. 8
4.2 Connection to two 2Gb x 16 DDR2 SDRAM device ............................................................... 8
4.3 Layout Guideline ..................................................................................................................... 8

5 Audio Design Guidelines ..................................................................11

5.1 Overview ................................................................................................................................11
5.2 Audio Power...........................................................................................................................11
5.3 Headphone Out..................................................................................................................... 12
5.4 Mic In..................................................................................................................................... 12
5.5 Speaker................................................................................................................................. 13
5.6 Layout Guideline ................................................................................................................... 14

6 Video Design Guidelines ................................................................. 15

6.1 Overview ............................................................................................................................... 15
6.2 Video Power.......................................................................................................................... 15
6.3 TV Out................................................................................................................................... 15

7 USB and OTG Design Guidelines ................................................... 16

7.1 USB Overview....................................................................................................................... 16
7.1.1 USB Power.................................................................................................................... 16
7.2 OTG Overview ...................................................................................................................... 16
7.2.1 OTG Power ................................................................................................................... 16
7.3 The following are general guidelines for the USB and OTG interface:................................. 18

8 LCD ................................................................................................. 20
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Content

9 LVDS ................................................................................................22
9.1 Overview................................................................................................................................22

10 Camera.............................................................................................23

11 PS/2 and Keyboard ..........................................................................24

11.1 Overview................................................................................................................................24

12 SAR A/D Controller...........................................................................25

12.1 Overview................................................................................................................................25
12.2 Touch Screen.........................................................................................................................25
12.3 Battery Voltage Measurement ...............................................................................................26

13 OTP EFUSE .....................................................................................27

13.1 Overview................................................................................................................................27

14 Ethernet Design Guidelines..............................................................28

14.1 Overview................................................................................................................................28
14.2 JZ4770 Ethernet Controller Connection................................................................................28

15 RTC ..................................................................................................29
15.1 Overview................................................................................................................................29
15.2 RTC Clock .............................................................................................................................29
15.3 Power Control........................................................................................................................29

16 Miscellaneous Peripheral Design Guidelines ...................................31

16.1 SSI Design Guideline ............................................................................................................31
16.2 UART.....................................................................................................................................32
16.2.1 UART Implementation....................................................................................................32
16.3 I2C Bus..................................................................................................................................33
16.4 PWM......................................................................................................................................33
16.5 GPIO......................................................................................................................................33
16.6 JTAG/Debug Port ..................................................................................................................33

17 Platform Clock Guidelines ................................................................35

18 Platform Power Guidelines...............................................................36

18.1 Overview................................................................................................................................36
18.2 Power Delivery and Decoupling ............................................................................................36

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 Overview

1 Overview
JZ4770 is a mobile application processor targeting for multimedia rich and mobile devices like
smartphone, tablet computer, mobile digital TV, and GPS. This SOC introduces a kind of innovative
architecture to fulfill both high performance mobile computing and high quality video decoding
requirements addressed by mobile multimedia devices. JZ4770 provides high-speed CPU
computing power, good 3D experience and fluent 1080p video replay.
The memory interface supports a variety of memory types that allow flexible design requirements,
including glueless connection to SLC NAND flash memory or 4-bit/8-bit/12-bit/16-bit/24-bit ECC
MLC/TLC NAND flash memory for cost sensitive applications.JZ4770 also integrates DDR ( including
DDR, DDR2 and Mobile DDR) memory controller, LCD controller, LVDS interface, Audio Codec,
multi-channel SAR-ADC, AC97/I2S controller, Camera controller, PCM interface, TV encoder, TS
interface, MMC/ SD/SDIO host controller, high speed SPI, I2C, One-wire, PS2 interface, USB1.1 Host,
USB OTG, UART, GPIO and so on.

1.1 Introduction
This design guide provides recommendations for system designs based on the JZ4770 processor.
Design issues (e.g., thermal considerations) should be addressed using specific design guides or
application notes for the processor.
The design guidelines in this document are used to ensure maximum flexibility for board designers
while reducing the risk of board related issues. The design information provided in this document
falls into two categories:
• Design Recommendations: Items based on INGENIC’s simulations and lab experience to
date are strongly recommended, if not necessary, to meet the timing and signal quality
specifications.
• Design Considerations: Suggestions for platform design provide one way to meet the design
recommendations. Design considerations are based on the reference platforms designed by
INGENIC. They should be used as an example, but may not be applicable to particular
designs.
Note: In this manual, processor means the JZ4770 processor if not specified.
The guidelines recommended in this manual are based on experience and simulation work
completed by INGENIC while developing systems with JZ4770. This work is ongoing, and the
recommendations and considerations are subject to change.
Platform schematics can be obtained and are intended as a reference for board designers.
While the schematics may cover a specific design, the core schematics remain the same for
most platforms. The schematic set provides a reference schematic for each platform
component, and common system board options. Additional flexibility is possible through other
permutations of these options and components.
The document can help customer span doorstep, design product using existent software and
hardware resources. Your advice is the best encourage for us.

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Overview

1.2 Reference Platform

Figure 1-1 shows the JZ4770 Development Board Architecture.

EPD
LCD 5"

800*480 HDMI
HDMI
I2S chip
Touch Panel

LVDS
USB2.0 USB1.1

Touch Panel
USB USB
OTG HOST DDR2 DDR2

LCD
PS/2
EMI BUS

AUDIO
Jack NAND FLASH
MLC
MIC
JACK GPS
Line IN
AUDIO MIC IN
JACK TS SLAVE HEADER
HP OUT
AUDIO OUT SSI(0:1)
SPI WiFi Module
CVBS
8BIT JZ4770 SPI FLASH(SSI0)
SDIO MMC/SD CIM Expansion HEADER
WIFI SOCKET one wire bus
one wire chip
CAMERA
HEADER PCM
HEADER
SIM/SMC
SOCKET
UART RS232
3223 DB9,UART
JTAG
HEADER
12M 32.768K Reset I2C0 I2C1

RC EEPROM
CRY CRY reset AT24C16 FM PMU

Figure 1-1 JZ4770 Development Board Architecture

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 Platform Stack-Up and Placement

2 Platform Stack-Up and Placement

In this section, an example of a JZ4770 platform component placement and stack-up is presented
for a PMP product.

2.1 General Design Considerations

This section describes motherboard layout and routing guidelines for JZ4770 platforms. This section
does not describe the function of any bus, or the layout guidelines for an add-in device. If the
guidelines listed in this manual are not followed, it is very important that thorough signal integrity and
timing simulations are completed for each design. Even when the guidelines are followed, critical
signals are recommended to be simulated to ensure proper signal integrity and flight time. Any
deviation from the guidelines should be simulated.
The trace impedance typically noted (i.e., 50Ω ± 10%) is the nominal trace impedance for a 4-mil
wide trace. That is, the impedance of the trace when not subjected to the fields created by changing
current in neighboring traces. When calculating flight times, it is important to consider the minimum
and maximum impedance of a trace based on the switching of neighboring traces. Using wider
spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces
reduce settling time. Coupling between two traces is a function of the coupled length, the distance
separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance.
To minimize the effects of trace-to-trace coupling, the routing guidelines documented in this section
should be followed. Additionally, these routing guidelines are created using a PCB stack-up similar
to that illustrated in Figure 2-1.

2.2 Nominal 6-Layer Board Stack-Up

The JZ4770 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%.
Recommendations in this design guide are based on the following a 6-layer board stack-up:

Signal Layer 1
Prepreg Layer 2
Ground Layer 3

Core Layer 4

Signal Layer 5
Prepreg Layer 6
Power Layer 7

Core Layer 8
Ground Layer 9
Prepreg Layer 10
Signal Layer 11
-----------------------------------------------------
Figure 2-1 6-layer PCB Stack-Up Total Thickness 62 mils.

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Platform Stack-Up and Placement

Table 2-1 PCB Parameter

Description Nominal Value Tolerance Comments

Board Impedance Z0 50Ω ± 10% With nominal 4 mil trace width
Dielectric Thickness 4.3 mils ± 0.5 mils 1 x 2116 Pre-Preg
Micro-stripline Er 4.1 ± 0.4 @ 100 MHz
Trace Width 4.0 mils ± 0.5 mils Standard trace
Trace Thickness 2.1 mils ± 0.5 mils 0.5 oz foil + 1.0 oz plate
Soldermask Er 4.0 ± 0.5 @ 100 MHz
Soldermask Thickness 1.0 mils ± 0.5 mils From top of trace

2.3 PCB Technology Considerations

The following recommendation aids in the design of a JZ4770 based platform. Simulations and
reference platform are based on the following technology, and we recommend that designers
adhere to these guidelines.

L1 Signal

L2 Ground
Copper

L3 Signal

L4 Power

Copper

L5 Ground
Copper

L6 Signal

Figure 2-2 PCB Technologies – Stack-Up

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 Platform Stack-Up and Placement

Table 2-2 PCB Parameter for Vias

Number of Layers
Stack Up 6 Layer
Cu Thickness 0.5 oz Outer (before plating); 1 oz inner
Final Board Thickness 62 mils (- 5mils / +8mils)
Material Fiberglass made of FR4
Signal and Power Via Stack
Via Pad 13 mils
Via Anti-Pad 20 mils
Via Finished Hole 6 mils

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 Static Memory Interface Design Guidelines

3 Static Memory Interface Design

Guidelines
3.1 Overview
The External Memory Controller (EMC) divides the off-chip memory space and outputs control
signals complying with specifications of various types of memory and bus interfaces. It enables the
connection of static memory, NAND flash memory, etc., to this processor.
This section is the design guidelines for the external memory interface.
The static memory controller provides a glueless interface to ROM, Burst ROM, NOR Flash and
NAND Flash. It supports 6 chips selection CS6 ~1# and each bank can be configured separately.
JZ4770 supports most types of NAND flashes, including SLC and MLC/TLC, 8-bit and 16-bit bus
width, 512B, 2KB page size. It also support boot from NAND flash. The data bus width for each chip
select region may be programmed to be 8-bit, 16-bit.

3.2 Boot Memory

BOOT_SEL[2:0] pins define the boot time configurations as listed in the following table.

Table 3-1 Boot Configuration

BOOT_ BOOT_ BOOT_ Description

SEL[2] SEL[1] SEL[0]
1 1 1 NAND flash at CS1
1 0 0 SD card: MSC0
1 0 1 SPI: SPI0/CE0
0 1 1 NOR flash at CS4
1 1 0 USB2.0 OTG as device with EXCLK = 12MHz
0 0 0 iNAND: at MSC0
0 0 1 USB2.0 OTG as device with EXCLK = 26MHz
0 1 0 USB2.0 OTG as device with EXCLK = 19.2MHz

The boot procedure is showed in the following flow chart:

− In case of NAND/SDcard/iNAND/SPI boot, if it fails, enter USB boot.
− In case of USB boot, if it cannot connect to USB host within 10 seconds, restart the boot
procedure.
− In case of NOR boot, if it fails, restart the boot procedure.
− If the boot procedure has been repeated more than 10 times, enter hibernating mode.

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Static Memory Interface Design Guidelines

3.3 NAND Flash Connection

It supports on CS[6:1], sharing with static memory bank4~bank1.
The following Figure 3-1 is an example of 8-bit NAND Flash Interconnection, Figure3-2 is an
example of 16-bit NAND Flash Interconnection.

JZ4770 NAND Flash

CS[n]# CE#

SA0 CLE

SA1 ALE

FRE# RE#

FWE# WE#

FRB# R/B#

SD[7:0] I/O [7:0]

Figure 3-1 8-bit NAND Flash Interconnection Example

JZ4770 NAND Flash

CS[n]# CE#

SA0 CLE

SA1 ALE

FRE# RE#

FWE# WE#

FRB# R/B#

SD[15:0] I/O [15:0]

Figure 3-2 16-bit NAND Flash Interconnection Example

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 DDR2 SDRAM

4 DDR2 SDRAM
4.1 Overview
JZ4770 contain a DDR Controller which is a general IP that provide an interface to DDR2, DDR,
mobile DDR memory. The following figures give examples on the connection to external DDR2
SDRAM devices.

4.2 Connection to two 2Gb x 16 DDR2 SDRAM device

2Gb x 16
JZ4770
DDR2 SDRAM

CKE CKE
CS0_N CS#
BA[2:0] BA[2:0]
DA[13:0] A[13:0]

RAS_N RAS#
CAS_N CAS#
WE_N WE#
CK, CK_N CK, CK#

DQ[15:0] DQ[15:0]
DQS0, DQS0_N LDQS, LDQS#
DQS1, DQS1_N UDQS, UDQS#
DM0 LDM
DM1 UDM

CKE
CS#
BA[2:0]
A[13:0]

RAS#
CAS#
WE#
CK, CK#

DQ[31:16] DQ[15:0]
DQS2, DQS2_N LDQS, LDQS#
DQS3, DQS3_N UDQS, UDQS#
DM2 LDM
DM3 UDM

Figure 4-1 Two 16-bit DDR2 Interconnection Example

4.3 Layout Guideline

In the classical high-speed flow, to ensure the maximum performance of the DDR2, we should
observe the following guidelines. The questions we should be noticed are: Flight time delay and
skew, Signal integrity and impedance matching, Crosstalk, Power supply bypassing.
The basic recommendations are as follows:

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DDR2 SDRAM

• The minimum Stack-up required six layer stack. There must have a ground layer to
separated two signal layers. Just as describes in Figure 2-2.
• The fundamental high-speed PCB issues are flight time delay and skew. Controlling the
maximum placement of components. All of the shorter nets in a clock domain must be
match the longest one. Therefore, flight time delay and skew are controlled by the matching
of the trace.
• Signal integrity refers to controlling overshoot, ring back, and transition edges. These issues
are caused by the mismatch of impedance. Trace impedance is governed by the trace width
as well as the thickness and dielectric constant of the PCB insulating materials (usually
FR-4). So you should keep the impedance average in a trace, be sure the bending and via
as little as possible.
• Crosstalk is fundamentally controlled by the PCB stack-up and minimum trace spacing. The
best approach to avoiding a crosstalk problem is to ensure all the signals have high-quality
signal return paths and to spread the signal out. Each signal layer should have a nearby full
ground plane to provide the shortest return current path. The other aspect of crosstalk
control is signal separation, we should keep 3W space between two signals (‘W’ is the width
of trace). This method can reduce the crosstalk.
• Precise power supply bypassing is important for high-speed PCB. Control the power supply
high-frequency impedance means controlling power supply inductance. Power supply
high-frequency impedance is beaten down by many small capacitors connected between
the power and ground plane. Using many capacitors, rather than a large one, will reduce the
inductance. The inductance of a capacitor is dependant on its size. The capacitor need to be
placed very close to the device they are bypassing.
• VREF is used as a reference by the input buffers of the DDR2 memories. It is recommended
to be 1/2 of the DDR2 power supply voltage and should be created using a resistive divider
as shown in the schematic. Other methods are not recommended. Figure 4-2 shows the
layout guidelines for VREF.

VREF bypass
capacitor

DDR2

VREF nominal
minimum trace JZ4770
width is 20 mils

DDR2

Figure 4-2 VREF Routing and Topology

• The region of the PCB used for DDR2 circuitry must be isolated from other signals. Region
should be encompass all DDR2 circuitry and varies signals depending on placement.

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 DDR2 SDRAM

Non-DDR2 signals should not be routed on the DDR2 signal layer with in the DDR2 keep
out region. No breaks should be allowed in the reference ground layers in the region. In
addition, the +1.8V power plane should cover the entire keep out region.
• Bypassing capacitors should be close to the devices, or positioned for the shortest
connections to pins, with wide traces to reduce impedance.

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 Audio Design Guidelines

5 Audio Design Guidelines

5.1 Overview
The AIC(AC'97 and I2S Controller) included in this processor. The AIC supports the Audio Codec '97
Component Specification 2.3 for AC-link format and I2S or IIS (for inter-IC sound), a protocol defined
by Philips Semiconductor. Both normal I2S and the MSB-justified I2S formats are supported by AIC.

5.2 Audio Power

AVDHP25, AVDCDC25 should be connected to a cleaned +2.5V power.

For a correct working, it is required to connect decoupling capacitors (22μF and 100nF ceramic)
between the pins AVDCDC25,AVDHP25 and AVSCDC,AVSHP.

An electrolytic capacitor more than 10μF tantalum and a 100nF ceramic capacitor should be
attached from VCAP to AVSCDC to eliminate the effects of high frequency noise.

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Audio Design Guidelines

5.3 Headphone Out

The AOHPL and AOHPR pins are applied directly to the loads. The ground of the headphone is
connected to AOHPM. The DC value of the signal AOHPi equals to VREF/2.
The measurement ground reference corresponds to the physical interconnection of AOHPM and
AOHPMS. AOHPM and AOHPMS have to be connected together as close as possible of the
headphone connector. The measurement is done between AOHPL/R and the measurement ground
reference.
The ESD8 and ESD9 is an ESD transient voltage suppression component which provides a very
high level of protection for sensitive electronic components that may be subjected to electrostatic
discharge. The device provides protection for contact discharges to greater than +/-15KV.
HPSENSE and JD are used to implement the insert test. When the jack is inserted, the value of JD
will be high: HPSENSE and AOHPM are short circuit. Otherwise, JD will be low; HPSENSE and
AOHPM are open circuit.
The ANT pin is used as an antenna of FM module.

5.4 Mic In
Specific value of resistor (R127, R130, R136, R141, commonly from 2.2kOhm to 4.7kOhm) and
VMICBIAS (usually from 1V to 2V or more) depends on the selected EC (Electret Condenser)
microphone.
The 1nf decoupling capacitance removes high frequency noise of the chip.

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 Audio Design Guidelines

5.5 Speaker
The ESD1 and ESD2 is an ESD transient voltage suppression component which provides a very
high level of protection for sensitive electronic components that may be subjected to electrostatic
discharge. The device provides protection for contact discharges to greater than +/-15KV.

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Audio Design Guidelines

5.6 Layout Guideline

To ensure the maximum performance of the Audio, proper component placement and routing
techniques are required. These techniques include properly isolating associated audio circuitry,
analog power supplies, and analog ground planes, from the rest of the motherboard. This includes
plane splits and proper routing of signals not associated with the audio section.

The basic recommendations are as follows:

• Special consideration must be given for the ground return paths for the analog signals.
• Digital signals routed in the vicinity of the analog audio signals must not cross the power
plane split lines. Analog and digital signals should be located as far as possible from each
other.
• Partition the board with all analog components grouped together in one area and all digital
components in another.
• Separate analog and digital ground planes should be provided, with the digital components
over the digital ground plane, and the analog components, including the analog power
regulators, over the analog ground plane. The split between planes must be a minimum of
0.05 inch wide.
• Keep digital signal traces, especially the clock, as far as possible from the analog input and
voltage reference pins.
• Do not completely isolate the analog/audio ground plane from the rest of the board ground
plane. There should be a single point (0.25 inch to 0.5 inch wide) where the analog/isolated
ground plane connects to the main ground plane. The split between planes must be a
minimum of 0.05 inch wide.
• Any signals entering or leaving the analog area must not cross the ground split in the area
where the analog ground is attached to the main motherboard ground. That is, no signal
should cross the split/gap between the ground planes, which would cause a ground loop,
thereby greatly increasing EMI emissions and degrading the analog and digital signal
quality.
• Analog power and signal traces should be routed over the analog ground plane.
• Digital power and signal traces should be routed over the digital ground plane.
• Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the
shortest connections to pins, with wide traces to reduce impedance. It is especially for
VCAP.
• All resistors in the signal path or on the voltage reference should be metal film. Carbon
resistors can be used for DC voltages and the power supply path, where the voltage
coefficient, temperature coefficient, and noise are not factors.
• Regions between analog signal traces should be filled with copper, which should be
electrically attached to the analog ground plane. Regions between digital signal traces
should be filled with copper, which should be electrically attached to the digital ground
plane.

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 Video Design Guidelines

6 Video Design Guidelines

6.1 Overview
The TV Encoder enables the data for LCD panel showing in TV screen.

6.2 Video Power

AVDDA should be connected to a cleaned +3.3V power.
For a correct working, it is required to connect two decoupling capacitor (22μF and 100nF ceramic)
between the pins AVDDA and AVSDA.

6.3 TV Out
It is required a 75 Ohm 1% pull-down resistors for matching, a Ferrite Bead and a 10pF ceramic
capacitor for filtering.

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 USB and OTG Design Guidelines

7 USB and OTG Design Guidelines

7.1 USB Overview
JZ4770 integrates USB Host Controller (UHC) which is Open Host Controller Interface
(OHCI)-compatible and USB Revision 1.1-compatible. It supports both low-speed (1.5 Mbps) and
full-speed (12 Mbps) USB devices. Two downstream ports are provided.
Familiarity with the Universal Serial Bus Specification, Revision 1.1 and the OHCI specification are
necessary to fully understand the material.
It supports both low-speed and high-speed USB devices.

7.1.1 USB Power

For a correct working, it is required to connect two decoupling capacitor (22μF and 100nF ceramic)
between the pins AVDUSB and AVSUSB.

7.2 OTG Overview

The Universal Serial Bus (USB) supports serial data exchanges between a host computer and a
variety of simultaneously accessible portable peripherals. Many of these portable devices would
benefit a lot from being able to communicate to each other over the USB interface. And OTG make
this possible. An OTG device can plays the role of both host and device.
JZ4770 also integrates USB 2.0 OTG interface, which compliant with USB protocol Revision 2.0
OTG. It supports low-speed (1.5 Mbps), full-speed (12 Mbps) and high speed (480 Mbps). High
speed and full speed supported for device role, full speed and low speed supported for host role.

7.2.1 OTG Power

The power of AVDOTG is support for the USB OTG analog power. It is required to connect two
decoupling capacitor (22μF and 100nF ceramic) between the pins AVDOTG25 and AVSOTG.

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USB and OTG Design Guidelines

And we should have a pin of VBUS supply power OTG, it have to connect to an external charge. The
DRVVBUS is used to control whether to supply power for OTG.

To enable the OTG, the circuit should monitor the VBUS pin and can supply voltage for this pin and
ID pin need connect CPU’s ID pin and one GPIO pin for insert dection. Figure 7-1 shows the classic
design for OTG function.

Figure 7-1 Classic Design for USB 2.0 OTG

To achieve this function, DRVBUS control PMU’s 5VIN circuit whether supply voltage for VBUS or not.
DRVVBUS controlled by the processor. Via the state of USB_DETE and ID pins, the processor can
complete this task.

Figure 7-2 USB Power Switch for USB 2.0 OTG

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 USB and OTG Design Guidelines

7.3 The following are general guidelines for the USB and OTG interface:
• Unused USB ports should be terminated with 15 kΩ pull-down resistors on both DP1/DM1
data lines.
• 15 Ω series resistors should be placed as close as possible to the JZ4770. These series
resistors provide source termination of the reflected signal.
• 47-pF caps must be placed as close as possible to the JZ4770 as well as on the processor
side of the series resistors on the USB data lines (DP1, DM1). These caps are for signal
quality (rise/fall time) and to help minimize EMI radiation.
• 15 kΩ ± 5% pull-down resistors should be placed on the USB side of the series resistors on
the USB data lines (DP1, DM1). They provide the signal termination required by the USB
specification. The stub should be as short as possible.
• The trace impedance for the DP and DM signals should be 45 Ω (to ground) for each USB
signal DP or DM. This may be achieved with 9-mil-wide traces on the motherboard based
on the stack-up recommended in Figure 7-3 7-4. The impedance is 90 Ω between the
differential signal pairs DP and DM, to match the 90 Ω USB twisted-pair cable impedance.
Note that the twisted-pair characteristic impedance of 90 Ω is the series impedance of both
wires, which results in an individual wire presenting 45 Ω impedance. The trace impedance
can be controlled by carefully selecting the trace width, trace distance from power or ground
planes, and physical proximity of nearby traces.
• USB data lines should be routed as ‘critical signals’. (i.e., hand-routing preferred). The
DP/DM signal pair should be routed together and not parallel to other signal traces, to
minimize cross-talk. Doubling the space from the DP/DM signal pair to adjacent signal
traces will help to prevent cross-talk. The DP/DM signal traces should also be the same
length, which will minimize the effect of common mode current on EMI.

Driver Motherboard Trace

15 Ω
D+ 45 Ω

15 kΩ
47 pF
90 Ω
USB Connector

Driver Motherboard Trace

15 Ω
D- 45 Ω

47 pF 15 kΩ

JZ4770 Transmission Line USB Twisted-pair Cable

Figure 7-3 Recommend USB Host Schematic

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USB and OTG Design Guidelines

Driver Motherboard Trace

D+ 45 Ω

90 Ω

USB Connector
Driver Motherboard Trace
D- 45 Ω

JZ4770 Transmission Line USB Twisted-pair Cable

Figure 7-4 Recommend USB Device Schematic

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 LCD

8 LCD
The JZ4770 integrated LCD controller, which has the capabilities to driving the latest industry
standard STN and TFT LCD panels. It also supports some special TFT panels used in consuming
electronic products. The controller performs the basic memory based frame buffer and palette buffer
to LCD panel data transfer through use of a dedicated DMA controller. Temporal dithering (frame
rate modulation) is supported for STN LCD panels.

Table 8-1 TFT Pin Mapping

JZ4770 Pin 8-bit Serial 18-bit 24-bit Parallel Smart Smart LCD
RGB Parallel RGB RGB LCD Serial Parallel
LCD_PCLK/SLCD_CL CLK CLK CLK CLK
K
LCD_HSYNC/SLCD_ HSYNC HSYNC HSYNC RS RS
RS
LCD_VSYNC/SLCK_C VSYNC VSYNC VSYNC CS CS
S
LCD_R7 R5 R7 D17
LCD_R6 R4 R6 D16
LCD_R5 R3 R5 D15 D15
LCD_R4 R2 R4 D14 D14
LCD_R3 R1 R3 D13 D13
LCD_R2 R0 R2 D12 D12
LCD_G7 G5 G7 D11 D11
LCD_G6 G4 G6 D10 D10
LCD_G5 G3 G5 D9 D9
LCD_G4 G2 G4 D8 D8
LCD_G3 R7/G7/B7 G1 G3 D7 D7
LCD_G2 R6/G6/B6 G0 G2 D6 D6
LCD_B7 R5/G5/B5 B5 B7 D5 D5
LCD_B6 R4/G4/B4 B4 B6 D4 D4
LCD_B5 R3/G3/B3 B3 B5 D3 D3
LCD_B4 R2/G2/B2 B2 B4 D2 D2
LCD_B3 R1/G1/B1 B1 B3 D1 D1
LCD_B2 R0/G0/B0 B0 B2 D0 D0
LCD_DE DE DE DE
LCD_ R1 R1
LCD_CLS/LCD_ R0 R0
LCD_ G1 G1
LCD_SPL/LCD_ G0 G0

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LCD

LCD_PS/LCD_ B1 B1
LCD_REV/LCD_ B0 B0

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 LVDS

9 LVDS
9.1 Overview
This product is a single-Link high speed LVDS (Low-Voltage Differential Signaling) transmitter used
for digital flat panel display systems. It’s compatible with ANSI/TIA/EIA-644-A (LVDS) Standard. The
transmitter converts 28bits parallel TTL data into four LVDS data streams. An in-phase transmit
clock is transmitted in parallel with the data streams over a fifth LVDS link. It support full HDTV
display up to 1920x1080p @ 60 Hz.

The values of C165,C167,C172,C174 and R167,R171,R172,R173 are based on the datasheet

of LCD.

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 Camera

10 Camera
The CIM (Camera Interface Module) of JZ4770 connects to a CMOS or CCD type image sensor. The
CIM source the digital image stream through a common 8-bit parallel common digital protocol. The
CIM can directly connect to external CMOS image sensors and ITU656 standard video decoders.

JZ4770 Camera Module

MCLK MCLK

PCLK PCLK

VSYNC VSYNC

HSYNC HSYNC

Data [7:0] I/O [7:0]

Figure 10-1 Example of Camera Module Interconnection

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 PS/2 and Keyboard

11 PS/2 and Keyboard

11.1 Overview
The JZ4770 processor integrate PS/2 keyboard controller (KBC) to provide the functions to a keyboard
or to a PS/2 mouse. KBC receives serial data from the keyboard or mouse, checks the parity of the
data, and presents the data to the system as a byte of data in its output buffer. The KBC is compatible
with 8042.
The following figure is a typical design.

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Board Design Guide for JZ4770, Revision 1.0
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 SAR A/D Controller

12 SAR A/D Controller

12.1 Overview
The A/D in JZ4770 is COMS low-power dissipation 10bit SAR analog to digital converter. It operates
with +3.3/+1.2V power supply.
The SAR A/D Controller of JZ4770 can work at three different modes: Touch Screen (measure pen
position and pen down pressure), Battery (check the battery power), and SADCIN (external ADC
input).

Table 12-1 SAR ADC Pins Description

NAME I/O Description

XN AI Touch screen analog differential X- position input
YN AI Touch screen analog differential Y- position input
XP AI Touch screen analog differential X+ position input
YP AI Touch screen analog differential Y+ position input
VBAT AI VBAT direct input
WIPER AI Connection for 5 wire touch screen or auxiliary Input
AUX AI Auxiliary Input

12.2 Touch Screen

The JZ4770 can support 5-wire resistive touch screen.
There is needed a decouple capacitor for every channel to avoid the crosstalk from LCD. The value
is decided by the touch screen and can be from 100pF to 1000pF.

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 SAR A/D Controller

12.3 Battery Voltage Measurement

Users who already deployed divider resistors on board level can use VBAT to direct measure the
battery value. The following figure is the approach we recommend. Use the recommended
resistance, you can control the power consumption easier.

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Board Design Guide for JZ4770, Revision 1.0
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 OTP EFUSE

13 OTP EFUSE
13.1 Overview
Total 256 bits of EFUSE are provided, separated into lower 128bits segment and higher 128bits
segment. Each segment can be programmed separately or together. Each segment has a protect
bit.
Important:In program mode, supply AVDEFUSE with 2.5V. AVDEFUSE pin should be kept 0v
except during programming. Maximum accumulative time for AVDEFUSE pin exposed under
2.5V+/-10% should be less than 1 sec. In read mode, leave AVDEFUSE to 0V.

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 Ethernet Design Guidelines

14 Ethernet Design Guidelines

14.1 Overview
The JZ4770 processor contains one Ethernet media access controller (MAC), each capable of
supporting 10/100Mbps Ethernet. The MAC provides the interface between the host application and
the PHY layer through the media independent interface (MII) or the Reduced-MII (RMII). The PHY
layer device is external to the processor.
This section describes design guidelines for the LAN on board based JZ4770.

transceiver Magnetic connector

Connector
JZ4770
Module

Figure 14-1 LAN On Board Implementation

14.2 JZ4770 Ethernet Controller Connection

JZ4770 Ethernet controller interconnection example is shown as figure 14-2, the Ethernet
transceiver chip maybe varied for specific OEM design targets. JZ4770 NET_RESET_N drives the
RESET# input to reset the transceiver chip when power-up.

MII_RXD[0:3]
MII_TXD[0:3]
MII_RXCLK
TRANSCEIVER

MII_TXCLK
MII_RXER
JZ4770

MII_MDIO
MII_RXDV
MII_CRS
MII_COL
MII_MDC
MII_TXEN
NET_RESET_N

Figure 14-2 Controller Connection

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 RTC

15 RTC
15.1 Overview
The Real-Time Clock (RTC) unit can be operated in either chip main power is on or the main power
is down but the RTC power is still on. In this case, the RTC power domain consumes only a few
micro watts power.
The RTC contains a 32768Hz oscillator, a power-on-reset generator, the real time and alarm logic,
and the power down and wakeup control logic.
The external WAKEUP_N pin is with up to 2s glitch filter / alarm wakeup.

15.2 RTC Clock

Table 15-1 RTC Clock Routing Summary

Trace Routing Maximum Signal R55, C36, and C37 Signal
Impedance Requirements Trace Length Length Tolerances Referencing
To Crystal Matching
45 Ω to 69 5 mil trace 1 inch NA R77 = 10M ± 5% Ground
Ω, 60 Ω width (results in C51=C54=22pF±10
Target ~2pF per inch) %
The value of C51,
C54 and R77
should be referred
to the crystal’s
specification

15.3 Power Control

The following is the recommended circuit for the system power control.
PWRON is an active high signal from CPU. If the power circuit enable signal is active high signal,
you can use the PWRON directly. The resistance of R83 in the next figure is recommended to be
680K ohm, in this case ,you can consume less current when power down mode.

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RTC

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Miscellaneous Peripheral Design Guidelines

16 Miscellaneous Peripheral Design

Guidelines
16.1 SSI Design Guideline
The SSI is a full-duplex synchronous serial interface and can connect to a variety of external
analog-to-digital (A/D) converters, audio and telecom codecs, and other devices that use serial
protocols for transferring data. The SSI supports National’s Microwire, Texas Instruments
Synchronous Serial Protocol (SSP), and Motorola’s Serial Peripheral Interface (SPI) protocol.
The following figures show the connection example:

JZ4770 Microwire Device

SSI_CE# CS#

SSI_DR DO

SSI_DT DI

SSI_CLK SK

Figure 16-1 Microwire Interconnection

JZ4770 SSP Device

SSI_CE# CS#

SSI_DR DO

SSI_DT DI

SSI_CLK SCLK

Figure 16-2 SSP Interconnection

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 Miscellaneous Peripheral Design Guidelines

JZ4770 SPI Device

SSI_CE# SS#

SSI_DR MISO

SSI_DT MOSI

SSI_CLK SCLK

Figure 16-3 SPI Interconnection

16.2 UART
The JZ4770 processor has four UARTs: All UARTs use the same programming model. Each of the
serial ports can operate in interrupt based mode or DMA-based mode.
The Universal asynchronous receiver/transmitter (UART) is compatible with the 16550 industry
standard and can be used as slow infrared asynchronous interface that conforms to the Infrared
Data Association (IrDA) serial infrared specification 1.1.

16.2.1 UART Implementation

DB9-MALE

RS232 1
JZ4770 Transceiver 6
2
RXD R1_O R1_I
RTS# T1_I T1_O 7
3
TXD T2_I T2_O
8
CTS# R2_O R2_I
4

9
5
GND

Figure 16-4 RS232 Serial Port Interconnection

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Miscellaneous Peripheral Design Guidelines

16.3 I2C Bus

The I2C bus was created by the Phillips Corporation and is a serial bus with a two-pin interface. The
SDA data pin is used for input and output functions and the SCL clock pin is used to control and
reference the I2C bus. The I2C bus requires a minimum amount of hardware to relay status and
reliability information concerning the processor subsystem to an external device.
The I2C module supports I²C standard-mode and fast-mode up to 400 kHz. The interface example is
shown as following figure. The I2C bus serial operation uses an open-drain, wired-AND bus
structure, so the pull-up (R1, R2=2.2K) is required on SCL and SDA. Refer to The I2C-Bus
Specification for complete details on I2C bus operation.

JZ4770 I2C Device

SDA SDA

SCL SCL

R1 R2

VCC

Figure 16-5 I2C Interconnection

16.4 PWM
The Pulse Width Modulator (PWM) is used to control the back light inverter or adjust bright or
contrast of LCD panel and also can be used to generate tone. PWM consists of a simple
free-running counter with two compared registers, each compare register performs a particular task
when it matches the count value. The period comparator causes the output pin to be set and the
free-running counter to reset when it matches the period value. The width comparator causes the
output pin to reset when the counter value matches. JZ4770 contains eight pulse width modulators:
PWM0 ~ PWM7.

16.5 GPIO
The JZ4770 processor provides 180 multiplexed General Purpose I/O Ports (GPIO) for use in
generating and capturing application-specific input and output signals. Each port can be
programmed as an output, an input or function port that serves certain peripheral. As input, pull
up/down can be enabled/disabled for the port and the port also can be configured as level or edge
tripped interrupt source.

16.6 JTAG/Debug Port

JZ4770 has a built-in JTAG/Debug port. All JTAG pins are directly connected. The following figure
shows the connection of the JTAG port. Pin 11 RST_N should be connected to system reset circuit.
Pin 12 is a KEY. The header should be a 7X2(2.54mm Pitch) male header with coat.

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 Miscellaneous Peripheral Design Guidelines

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 Platform Clock Guidelines

17 Platform Clock Guidelines

The JZ4770 processor contains one PLL driven by the 12-MHz oscillator and a clock generator from
which the following are derived:
• CPU clock
• System bus clock
• Peripheral bus clock
• DDR2 bus clock
• Programmable clocks needed by certain peripherals

The following is the recommended circuit for main clock. When layout the board, you should keep
the distance between Y2 and JZ4770 as short as possible.

Table 17-1 Main Clock Routing Summary

Trace Routing Maximum Signal R52, C34, and C35 Signal

Impedance Requirements Trace Length Length Tolerances Referencing
To Crystal Matching
45 Ω to 69 5 mil trace 1 inch NA R78 = 1M ± 5% Ground
Ω, 60 Ω width (results in C52=C53=22pF±10
Target ~2pF per inch) % (Typical)
The value of C52,
C53 and R78
should be referred
to the crystal’s
specification

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 Platform Power Guidelines

18 Platform Power Guidelines

18.1 Overview
The JZ4770 processor needs four voltages: +3.3V, +1.8V for memory, +1.2V for core,+2.5V for
USB OTG and AUDIO. The following figure is a typical power circuit in the PMP application.

+1.2V

+1.8V

+3.3V

4.2V Li-ion +2.5V

Battery

+5V

PMU RTC3.3V
DC Plug

18.2 Power Delivery and Decoupling

The VDDIO (+3.3V), VMEM(+1.8V) and VDDCORE (+1.2V) of JZ4770 should be decoupled with
100nF, 10nF and 1nF capacitor.

The Power of PLL should be as the following circuit.

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Platform Power Guidelines

The power of USB should be as the following circuit.

The power of Audio should be as the following circuit.

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 Platform Power Guidelines

The power of DAC should be as the following circuit.

The power of ADC should be as the following circuit.

The power of RTC should be as the following circuit. The capacitors should be placed near the Pin
of power. The traces from capacitor to the Pin should be short and width.

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Platform Power Guidelines

The power of LVDS should be as the following circuit.

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Board Design Guide for JZ4770, Revision 1.0
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