Assignment # 3

Submitted to:
Ma’am Aimen Aakif

Submitted by:
Usama Jabbar

Course:
BETE 55 D

Date:
20th May,2020

MILITARY COLLEGE OF SIGNALS,NUST

 Question 1
Segmentation
Part(1)
Consider the statement MOV AX, WORD PTR [EBX+25]
EBX=4A679H; DS=0018H; GDTR=00000000H ;
The following table shows the……..?

Solution
EBX =4A679 H
Add 25 into EBX
We assumed 25 in hexadecimal system
4A679
00025
4A69E
As EBX gives offset to data segment, so
DS=0018
Convert into binary form
0000 0000 0001 1 000
Requested
selector privilege level
Table
indicator

There are 13 bits of selector. In order to make it 16, we append 3 zeros

0000 0000 0001 1000 {append 3 zeros}
It becomes: 0018
Now adding 0018 and GTDR

00000000
00000018
00000018

It represents the 4rth descriptor in the descriptor table

The descriptor table for above is given below:

0000001F 15
0000001E G= D=1 0 A=0
1
B
0000001D 93
0000001C 90
0000001B 0D
0000001A 2C
00000019 19
00000018 5A

From table we conclude following results:

Limit=B195A H
Base address=15900D2C H
Access right=93

Note:

As granularity bit is 1 so we append FFF in the limit

New limit=B195AFFF

Check whether segment is accessable or not:

OFFSET<=LIMIT
 4A69E<B195AFFF
As upper situation is true so we simply add offset int base address to get linear address
15900D2C
0004A69E
1594B3CA

LINEAR ADDRESS = 1594B3CAH

Part(2)
Write a format for Code descriptor of 80386 that describes a memory
segment that begins at location 030000H and ends at location
05FF00H

Solution
Given :

Base address = 030000H

Limit = 05FF00 – 030000
=02FF0

Access right byte

The access right byte is give by the following table

P DLP S E C R A
1 0 0 1 1 1 1 1
Now descriptor table becomes

4rth byte of base address 00

Granularity, limit, D-bit 12
etc
Access right byte 9F
3rd byte of base address 03
2nd byte of base address 00
1st byte of base address 00
2nd byte of limit FF
1st byte of limit 00

Part (3)
Solution

As we know that in case of other segments, addressable section starts from the base address
and ends on the limit but in case of stack segment, it is totally opposite, the limit field
determines that which area of the segment is not addressable.
As we know that there are 13 bits of selector so, 213=8KB

In case of data segment for example, the first addressable byte is at offset zero and last
addressable byte is at limit point 8KB, but in case of stack segment the first addressable byte is
at limit 8 KB and last addressable byte is at last limit of the segment
So 8KB of size starts from base address is addressable in other segment, but in in stack segment
we come from upper side of the segment,8KB size from base address of the segment is now
non-addressable
Now in stack segment offset will always be greater than the limit because after that limit
addressable section starts
Here is a diagram to show the changes occurs in stack segment
diagram

Base+FFFF
limit
Addressable
Addressable Bytes
bytes 56KB
base
limit
Data or any
other Nonaddressable
segment
bytes
8KB

base
Stack
segment

LIMIT OF STACK SEGMENT

In stack segment the lower limit is set by the limit field but for upper limit case ,there
are two cases

D=0
When D bit in the descriptor is 0, the upper limit will be the sum of base address and
constant value FFFF

D=1
When D bit is set, the lower limit will be the same but the upper limit will be equal to the
sum of base address and FFFFFFFF
Example :
Suppose we have a base address of 3400000000H and have a limit of 0001H
Then the top and bottom are given below

Top :
The top will be simply sum of base address and limit

34000000H + 0001H = 34000001H

BOTTOM:
When D=0:
Base address + FFFF=34000000+FFFF

=3400FFFF

When D=0:
Base address + FFFFFFFF = 34000000+FFFFFFF
=34FFFFFFF

Question # 2
Part (1)
What value is placed in page table to redirect linear address
20000000H to physical address 30000000H.

Solution

Given :
Linear address =20000000H
Required physical address=30000000H

Linear address into binary form

Converting linear address into binary form

0010 0000 0000 0000 0000 0000 0000 0000
Page directory page table offset

NOTE:

Here in this case we have to find the entry which is

present in the page table. This entry gives us the
linear address of the page. Means we add offset in
that page entry to reach physical address of page
which is given in the question (30000000)
The formula of physical address is given below
Physical Address = linear address + offset
And the offset is given in upper figure
Offset =00000000000 (last two are appended bits)
So linear address is given by

Linear address (page table entry) =30000000H - 00000000H

=30000000

So 30000000 is required page table value

 Part (2)
Each entry in page directory translates how much linear
address in to physical address
solution
Each entry in the page directory translates 10 bits of page table and 12 bits of offset into
physical address 22 bits of total is transferred into physical address
222=220*22=4MB
So total 4 MB is translated

Part (3)
(a)
Consider a paged virtual memory system with 32-bit virtual
addresses and 1 K-byte pages. Each page table entry requires
32 bit…….?

Solution

From question:
Virtual address=32 bits
So 232 bytes of memory
Page size= 1KB = 210
No of pages = 232/210 =222
So from above it is confirmed that we require 22 bits to access a page
From question: Page table size= 1 KB
 No of entries = (page table size)/(size of 1 entry)
=210/22 = 28
From above answer it is concluded that one page table can handle upto 8 bits
To complete 22 bits of required 1 page there will be 3 levels of page tables

(b)
What is the size of the page table at each level? Hint: One
page table size is smaller.
Solution
As we have to complete 22 bits so:
There should be upto 28 size of one level of page. So the two levels should be of sizes 28 each
and one level will be of the size 26.
Hence 8+8+6=22 (22 bits is completed)

(c)
The smaller page size could be used at the top level or the
bottom level of the page table hierarchy……?

Solution

We consider both cases

 When smaller table will be on top

When smaller page is on top the hierarchy becomes

26->28->28
The first level has 1 page with 26 entries. The second level has 26 pages with 28 entries each and
the bottom level has 26*28= 214 pages with 28 entries

Now add all of them it gives

1+26+214=16449
In this case 16449 pages will be consumed

This can be explained through diagram

diagram

1
 26
..
4 26
3
2
1 214
28
0
..
Level 1
4
3
2 28
1 ..
0 4
3
Level 2 2
1
0

Level 3

When smaller table will be on bottom

When smaller page is on bottom the hierarchy becomes
28->28->26
The first level has 1 page with 28 entries. The second level has 28 pages with 28 entries each and
the bottom level has 28*28= 216 pages with 26 entries
Now add all of them it gives
1+28+216=65793
In this case 65793 pages will be consumed
 diagram

28
..
4 28
3
2
1 216
28
0
..
Level 1 4
3
2 26
1 ..
0 4
3
Level 2 2
1
0

Level 3

So when smaller page table will be on top it consumed less pages so it is the
best case

Question # 3
solution
80386 micro processor has 32 bit data bus and have 4 memory banks. These banks are 8 bit
wide and have memory up to 1 GB
Word
When a word is transferred ,two consecutive memory banks are selected. If a word is placed at
an odd address, then it will consumed 2 consecutive memory banks and so word is transferred
in one bus cycle. When its address is located in bank 1, there will be no misalignment
When its on bank 3,now it will go on next bus cycle
Double word
When a double word is transferred, all four banks will be selected. There is a condition for
having no misalignment, if starting address is divisible by 4 then their will be no misalignment.
When the starting address is placed at an odd address, their will be a misalignment and 1 or 3
bytes according to their respective starting address will be transferred into next bus cycle.