SoC Testing

Jiun-Lang Huang
Graduate Institute of Electronics Engineering
National Taiwan University
 Outline

l SoC Test Challenges

l Test Access Mechanism
l Core Test Wrapper
l IEEE P1500
l Test Optimization

Fall 2003 2
 Technology Trend:
System-on-Board to System-on-Chip

Physical components System on Board

Virtual components System on Chip

Fall 2003 3
 Why System-on-Chip?
l Complex applications.
l Process technology allows it.
l High performance.
l Miniaturization.
l Battery life.
l Short market windows.
l Cost sensitivity.

Fall 2003 4
 Core-Based SoC Design
l Reuse of large modules.
– Examples: CPU, DSP, MPEG, JPEG,
communication modules, memories, analog
modules, …
– Reduced time-to-market, expertise import.
l ‘Divide-and-conquer’ design methodology
– Maximize core-level design tasks.
– Minimize SoC-level design tasks.
l Distributed design: core provider and user
– Intra-company and inter-company core use.

Fall 2003 5
 The Impact
l SoC components are only manufactured and tested in
the final system.

SoB Process SoC Process

IC Design ASIC Design Core Design UDL Design

IC Fab. ASIC Fab.

IC Test ASIC Test

SOB Design SOC Design

SOB Fab. SOC Fab.

SOB Test SOC Test

Fall 2003 6
 Separation of Responsibilities
l The core provider
– Test pattern generation for the cores.
– Core internal design-for-testability.
l The core user
– Test generation for the chip
• Reuse of core-level test patterns.
• Additional test patterns for non-core circuitry.
– Chip-level design-for-testability.

Fall 2003 7
 SoC Test Challenges
l Distributed design & test
l Test access
l Test optimization

Fall 2003 8
 Distributed Design & Test
l In general, the core provider develops the core
test including DfT & test patterns.
l However, the core provider does not know the
system chip environment
– Which test method to use?
– What type of faults to target?
– What level of fault coverage?
which may lead to
– inadequate test quality, or
– waste of resources.

Fall 2003 9
 l Need a set of standardized set of deliverables.
– Test methods
– Test modes and protocols
– Fault models and fault coverage
– Test pattern data
– Core-internal design-for-test
– Core-internal design-for-diagnosis
– Diagnostics and failure analysis information

Fall 2003 10
 Test Access
l Direct access to deeply embedded cores is
difficult.
l It’s not uncommon that
core’s I/O pin count > SoC’s I/O pin count
l To test each core, we need to provide
– core test access, and
– core isolation mechanism.

Fall 2003 11
 Test Optimization

l Test access infrastructure optimization

– Test quality vs. overhead

l Constrained test scheduling

– Overall test time
– Power consumption
– Test access bandwidth
– Available test resources
– Other considerations

Fall 2003 12
 Outline

l SoC Test Challenges

l Test Access Mechanism
l Core Test Wrapper
l IEEE P1500
l Test Optimization

Fall 2003 13
A Conceptual SoC Test Access Architecture

CUT
Source TAM TAM Sink
Wrapper

l Test pattern source and sink

– The source generates the test stimuli for the embedded core.
– The sink compares the responses to the expected responses.
l Test access mechanism (TAM)
– Test data transport from the test source to the CUT and from
the CUT to the test sink.
l Core test wrapper
– Connects the terminals of the core to the rest of the IC and the
TAM.
[Zorian, Marinissen, Dey – ITC98]
Fall 2003 14
 A Conceptual Test Architecture

DAC mP
SRAM

Wrapper
PCI TAM
CUT TAM
Source Sink

ROM DSP

Fall 2003 15
 On/Off-Chip Test Source/Sink

DAC mP
SRAM
On-chip Source/Sink
PCI • Closer to CUT
CUT
Source Sink • Less TAM area
• Less dependence on ATE
ROM DSP • BIST area overhead

Off-chip Source/Sink DAC mP

• Bandwidth limited by pin SRAM
count
• More TAM area PCI
src CUT
• More expensive ATE Src. snk Snk.

ROM DSP

Fall 2003 16
 TAM (Test Access Mechanism)
l Function
– Deliver test stimuli from the test source to the CUT.
– Transport test responses from the CUT to the test
sink.
l TAM design involves making trade-offs among
– data transport capacity,
– test time, and
– TAM overhead.

Fall 2003 17
 TAM Width
l Determines the test data transport bandwidth.
l Considerations
– A wider TAM shortens the test time, but consumes
more wiring area.
– The width of the test source and sink.
– Available IC pins if external test source/sink.
l Constraints to meet
– Test time
– Area overhead

Fall 2003 18
 TAM Length
l Physical distance
l Ways to reduce TAM length
– On-chip test sources and/or sinks.
– Sharing TAM among cores can shorten the total
TAM length.
• Reduced wiring area.
• Possibly reduced test concurrency.
– Reusing functional hardware as TAM.
• May not meet the desired test time constraint.

Fall 2003 19
 TAM Implementations
l Direct access scheme
– Immaneni, Raman – ITC90
l Bus-based scheme
– Varma, Bhatia – ITC98, Harrod – ITC99
l Transparency
– Beenker – D&T86, Beenker 95, Marinissen – TECS97,
Ghosh et al. – ITC97, CAC98
l Boundary-scan based
– Whetsel – ITC97, Bhattacharya – VTS98,
Touba, Pouya – D&T97, ITC97
l Test Rail
– Marinissen et al. – ITC98

Fall 2003 20
 Direct Access Scheme
l Map all core inputs, outputs, and I/O onto
package pins.
l In test mode, the I/Os of the selected core are
accessible through a group of package pins.
– Each core can be tested with its standard test
program.
l Test isolation provided and cores are tested
independently.

[Immaneni, Raman – ITC90]

Fall 2003 21
 Direct Access Scheme
l Modification to user logic block.

TSEL
Embedded
> Output
TMODE
Embedded
Bidirectional

User In Input Embedded

> Bidirectional
Test In User >
Dir Control
Logic Ctrl
Block <>
Bi-Dir
Primary Primary
> > Output
Input

Primary
<> Bidirectional
Output

Fall 2003 22
 Direct Access Scheme
l An implementation example

UIN Out Output

TIN TSEL1
TMODE TSEL Pad

User
Signal
Input UIN Out
TIN TSEL2
Pad TMODE TSEL Output
Pad

Input UIN Out

TIN TSEL3
Pad TMODE TSEL
TMODE
Input
Pad Test Control Logic

Fall 2003 23
 Remarks
l Advantages
– Embedded cores can be tested and debugged as a
stand-alone device.
– Transition from core-level test to chip level test is
simple.
– A slight increase in overall package pin count and
design complexity.
l Drawbacks
– Not scalable.
• The complexity of control logic and test circuitry grows
with the number of embedded cores.
– Long test time.
• Blocks are tested sequentially.
Fall 2003 24
 Bus-Based TAM
l Utilizing on-chip system bus or dedicated test bus for
test data transport.
– Varma, Bhatia – ITC98
– Harrod – ITC99

DAC mP SRAM
Src.

Sink
ROM DSP

Fall 2003 25
 AMBA Bus-Based Testing
l Test vectors produced for an AMBA-compliant
IP block can be reused in any AMBA-based
system.
l The AMBA Test Interface Controller (TIC) is
responsible for test application and response
capture.
l In test mode
– TIC becomes the AMBA bus master.
– The external bus interface (EBI) is reconfigured to
provide a high-speed, 32-bit, parallel vector
interface.
[Harrod – ITC99]
Fall 2003 26
 AMBA Bus-Based Testing
l Peripheral test harness
– Access to I/O’s not connected to the bus.
– Isolate the core under test from its environment.

Fall 2003 27
 AMBA Bus-Based Testing

Fall 2003 28
 Remarks
l Advantages
– Reusing system bus reduces TAM overhead.
– Transition from core-level test to chip-level test is
simple.
l Drawbacks
– Fixed bus width may be insufficient for some cores.
– Difficult to integrate full-scanned cores.

Fall 2003 29
 Transparency

DAC mP
SRAM

PCI
Source CUT Sink

ROM DSP

Fall 2003 30
 Transparency
l Transparent path
– A path from input to output which propagates data
without information loss.
l Examples
– Scan chains
– Arithmetic functions: + 0, x1
– Embedded memories
– Basic gates: AND, OR, INV, MUX
l Past techniques
– Beenker – D&T86, Beenker 95,
Marinissen – TECS97,
Ghosh et al. ITC97, CAC98

Fall 2003 31
 Remarks
l Advantages
– Low area overhead
l Drawbacks
– Transport latency through cores
– The desired transparency is not guaranteed.
• Too much transparency – waste.
• Too little transparency – TAM needed.
– Non-trivial transition of core-level test to chip-level
test.

Fall 2003 32
 Boundary Scan
l An IEEE 1149.1 compliant l 1149.1 board-level view.
chip.

TCK
TMS
TDI TDI

Digital TDO
circuit
TDI

TDO
TDI TAP TDO
TMS controller TCK TDI

TDO TDO
: Boundary scan cell
: Boundary scan path
Fall 2003 33
 Remarks
l Advantages
– Existing well-known, well-documented standard.
– Reuse IC level implementation.
l Drawbacks
– Fixed 1-bit TAM width.
– Complexity of test control and test data wiring
grows with the number of cores.
– Multiple TAP controllers.

Fall 2003 34
 Test Rail
l IC level view.

Core A
1
16 16

16
1 1 16
Core B Core C
16 16 16

Core E
1
8
Core D
1 Core F
1
12 12
4

[Marinissen et al. – ITC98]

Fall 2003 35
 Test Rail
l Core level view.

Decompression

Compression
Core Core

Serial
Parallel Compressed

Core

Fall 2003 36
 Test Rail
l An example.
– A: 4 scan chains.
– B: BIST
– C: Functional test

Decomp.

Comp.
A B C

Fall 2003 37
 Remarks
l Advantages
– Flexible
Enables integration of various core test techniques.
– Scalable
Allows trade-offs between area, quality, and test
time.
l Drawbacks
– Difficult to find optimal solution.

Fall 2003 38
 Multiplexing Architecture

Core A Core B Core C

[Aerts & Marinissen – ITC98]

Fall 2003 39
 Daisy Chain Architecture

Core A Core B Core C

[Aerts & Marinissen – ITC98]

Fall 2003 40
 Distributed Architecture

Core A Core B Core C

[Aerts & Marinissen – ITC98]

Fall 2003 41
 Remarks
l Different types of TAMs may coexist on a
single chip.
l Cores connected to different TAMs can be
tested concurrently.
l Cores connected to the same TAM cannot be
tested concurrently.

Fall 2003 42
 Outline

l SoC Test Challenges

l Test Access Mechanism
l Core Test Wrapper
l IEEE P1500
l Test Optimization

Fall 2003 43
 Core Test Wrapper
l Function
– Interface between the core and its environment.
• Width adaptation
– Provision of the following modes
• Normal: function mode
• InTest: inward-facing core test mode
• ExTest: outward-facing interconnect test mode
l Considerations
– Test time.
– Performance degradation.
– Area overhead.

Fall 2003 44
 Functional Only Connection

Scan Chain Scan Chain Scan Chain

Scan Chain Scan Chain Scan Chain

Core A Core B Core C

Fall 2003 45
 Wrapper & TAM

Bypass

Bypass
Bypass

Scan Chain Scan Chain Scan Chain

Scan Chain Scan Chain Scan Chain

Core A Core B Core C

Test Control Test Control Test Control

Fall 2003 46
 Normal Operation

Bypass

Bypass
Bypass

Scan Chain Scan Chain Scan Chain

Scan Chain Scan Chain Scan Chain

Core A Core B Core C

Test Control Test Control Test Control

Fall 2003 47
 InTest

Bypass

Bypass
Bypass

Scan Chain Scan Chain Scan Chain

Scan Chain Scan Chain Scan Chain

Core A Core B Core C

Test Control Test Control Test Control

Fall 2003 48
 ExTest

Bypass

Bypass
Bypass

Scan Chain Scan Chain Scan Chain

Scan Chain Scan Chain Scan Chain

Core A Core B Core C

Test Control Test Control Test Control

Fall 2003 49
 Bypass

Bypass

Bypass
Bypass

Scan Chain Scan Chain Scan Chain

Scan Chain Scan Chain Scan Chain

Core A Core B Core C

Test Control Test Control Test Control

Fall 2003 50
 Outline

l SoC Test Challenges

l Test Access Mechanism
l Core Test Wrapper
l IEEE P1500
l Test Optimization

Fall 2003 51
 Core-Based Test
l The core provider delivers
– the core design itself, and
– a set of tests for the core.
l The core user assembles a chip-level test
from
– the pre-defined tests for the various cores, and
– additional tests for non-core circuitry.
l A test as described above, in which cores are
tested as stand-alone units, is called a “core-
based test.”

Fall 2003 52
 IEEE P1500

l Standard for embedded core test (SECT).

l History
– Started in 1995 as a TAC of the TTTC of the IEEE
Computer Society.
– In June 1997, Project Authorization Request
approved by the IEEE Standards Activities Board.
– Current target
• A draft standard for non-merged digital logic and memory
cores.
– Future extensions
• Mergable cores and analog and mixed-signal cores.

Fall 2003 53
 Goals of IEEE P1500
l Standardize a core test architecture which
– Defines a core test interface between an
embedded core and the system chip,
– Facilitate test reuse for embedded cores through
core access and isolation mechanisms, and
provide testability for system chip interconnect and
logic, and
– Facilitates core test interoperability, with plug-and-
play protocols, in order to improve the efficiency of
test between core providers and core users.

Fall 2003 54
 Scope of IEEE P1500

l Yes.
– Standarize core test mechanisms, for core access
and isolation, including protocols and test mode
control.
l No.
– System chip test access mechanism.
• Defined by the system chip integrator.
– Core test method.
• Defined by the core provider.
• P1500 supports, and enables various different methods,
e.g., scan, BIST, Iddq, etc.

Fall 2003 55
 P1500 Task Forces
l Core test language
l Scaleable architecture
l Compliance definition
l Terminology / Glossary
l Documentation
l Mergeable cores test
l Benchmarking
l Industry & media relations

Fall 2003 56
 P1500 Core Test Wrapper Architecture
E. J. Marinissen, CTAG Working Group
in DATE’03

Fall 2003 57
 P1500 Core Wrapper Architecture

l Wrapper overview and applications

l Wrapper architecture and instructions

l Wrapper harness cells

Fall 2003 58
 Block Level Overview
l WPP
– Optional.
– User defined port for test
flexibility.
– Components:
• Wrapper Parallel In
• Wrapper Paralles Control
• Wrapper Parallel In
l WSC
– Required.
– Standardized port for plug-
and-play.
– Components:
• WSI, WSC, WSO

Fall 2003 59
 The P1500 Wrapper Boundary Cell

l Cell modes
– Normal, Inward facing, Outward facing, Safe (recommended)
l Cell events
– Shift, Capture, Apply, Update, Transfer

Fall 2003 60
 P1500 Wrapper Parameters
l Bandwidth
– Number and/or width of WPI-WPO pairs.
l Instructions
– Optional instructions
– User-defined instructions
– OpCodes of instructions
l WBR functionality
– Shared or dedicated wrapper cells
– Shift-only or Shift + Update cells
– Storage capacity (one or more bits)
– Ripple protection (w/ Update register or gate)
– “Safe State” output values
Fall 2003 61
 The P1500 Wrapper Architecture

Fall 2003 62
 Wrapper Configuration

Fall 2003 63
 Daisy-Chained Wrapper Configuration

Fall 2003 64
 Bussed Wrapper Configuration

Fall 2003 65
 Direct Access Wrapper Configuration

Fall 2003 66
 Wrapper Configuration w/
Local Controllers

Fall 2003 67
 P1500 Core Wrapper Architecture

l Wrapper overview and applications

l Wrapper architecture and instructions

l Wrapper harness cells

Fall 2003 68
 Required Wrapper Architecture

l WSC
– WRST, WCLK, SelectWR, Capture, Shift, Update, Transfer

Fall 2003 69
 P1500 Wrapper Test Instructions
l WS_BYPASS Required WSP
l WS_PRELOAD Optional WSP
l WP_PRELOAD Optional WPP
l WS_CLAMP Optional WSP
l WS_SAFE Optional WSP
l WS_INTEST_RING Optional WSP
l WS_INTEST_SCAN Optional WSP
l WP_INTEST_RING* Optional WPP
l WP_INTEST_SCAN* Optional WPP
l WH_INTEST Optional and/or
l WS_EXTEST Required WSP
l WP_EXTEST Optional or
l WH_EXTEST Optional and/or

1. At least one optional INTEST required.

2. *: Examples of user-defined instructions.

Fall 2003 70
 Instruction Fields Naming Conventions

[Field 1] [Field 2] _ [Field 3] _ [Field 4]

Wrapper Test Access Test Mode Configuration

W S:serial Bypass Ring

P:parallel Preload Scan
H:hybrid Clamp User
Safe
Intest
Extest
User

WS_Intest_Ring

Fall 2003 71
 WS_Bypass

Fall 2003 72
 WS_Preload

Fall 2003 73
 WP_Preload

Note: WPC signals are user defined.

Fall 2003 74
 WS_Clamp

1. Inputs may also be controlled

to preloaded states.
2. WS_Clamp is preceded by
WS/P_Preload.
Fall 2003 75
 WS_Safe

1. Inputs may also be controlled

to safe states.
2. WS_Safe does no require
WS/P_Preload.
Fall 2003 76
 WS_Intest_Ring

1. Test is applied via WSC

controlled WBR scan path.
Fall 2003 77
 WS_Intest_Scan

1. Test is applied via WSC

controlled WBR and internal
scan path.
Fall 2003 78
 WP_Intest_Ring

1. Test is applied via WPC * Under consideration as a

controlled WBR segments. standard instruction.
Fall 2003 79
 WP_Intest_Scan

1. Test is applied via WPC

controlled WBR and internal * Under consideration as a
scan segments. standard instruction.
Fall 2003 80
 WH_Intest

1. Test is applied via WSC and

WPC controlled WBR and
internal scan path.
Fall 2003 81
 WS_Extest

1. Test is applied via WSC

controlled WBR scan path.

Fall 2003 82
 WP_Extest

1. Test is applied via WSC

controlled WBR segments.

Fall 2003 83
 WP_Extest

1. Test is applied via WSC

controlled WBR segments.
Fall 2003 84
 WH_Extest

1. Test is applied via WSC &

WPC controlled WBR
segments.
Fall 2003 85
 P1500 Core Wrapper Architecture

l Wrapper overview and applications

l Wrapper architecture and instructions

l Wrapper harness cells

Fall 2003 86
 Applying Wrappers to Test Only I/O’s

Fall 2003 87
 Pass-Through Harness Cell

Fall 2003 88
 Scan-Through Harness Cell

Fall 2003 89
 Pass/Scan-Through Harness Cell

Fall 2003 90
 Pass-Through Harness Cell Example

Fall 2003 91
 Scan-Through Harness Cell Example

Fall 2003 92
 Pass/Scan-Through Cells: Pass Mode

1. Enables factory testing using

parallel access.
Fall 2003 93
 Pass/Scan-Through Cell: Scan Mode

1. Enables in-system testing

using serial access.
Fall 2003 94
 Outline

l SoC Test Challenges

l Test Access Mechanism
l Core Test Wrapper
l IEEE P1500
l Test Optimization

Fall 2003 95
 Problem Definition
l SoC test scheduling
– Given:
A set of cores, the associated test sets (maybe
more than one), and a set of constraints that must
be satisfied during testing.
– Find out:
The start time(s) of the test set(s) for each core
such that the total test time is minimum and none
of the constraints are violated.
– Note:
The test schedule should be identified efficiently,
and the results should be optimum or near
optimum.
Fall 2003 96
 SoC Test Constraints

l TAM width
l Power dissipation
l Resource sharing
l Precedence
l Multiple test sets

Fall 2003 97
 TAM Width Constraint
l Usually, the available TAM width for testing is limited
and fixed.
l TAM width for a core may be adjustable.

Fall 2003 98
 Power Dissipation Constraint
l The maximum power consumption is limited.
l Elevated power consumption during testing.

Fall 2003 99
 Test Scheduling Methodologies

l Graph based

l ILP based

l Bin-packing based

Fall 2003 100

 Graph-Based Scheduling Methodologies

l Developed in 80s’ and early 90s’.

l Aim at exploring parallelism in BIST.
l Test resource conflict is the major constraint.

Fall 2003 101

 Resource Allocation &
Test Compatibility Graphs
l Resource allocation graph (LHS)
– TI: test sets
– Ri: resources
l Test compatibility graph (RHS)
– Two tests are incompatible if they use the same resource.
– No edge between incompatible test sets.

Fall 2003 102

 Minimum Covering Table
l Tests in the same compatible set can be performed
concurrently.
l Cover all tests with minimum number of rows.

Fall 2003 103

 ILP Based Methodologies
l An example

Maximize
X +Y
subject to
6x - y £ 30
3x + 2y £ 30
x - 4 y ≥ -32
where
x, y ≥ 0

†
Fall 2003 104
 General Form
Maximize or minimize
Y = C1 X1 + C12 X 2 + L + Cn X n
subject to
A11 X1 + A12 X 2 + L + A1n X n ≥,=,£ B1
A21 X1 + A22 X 2 + L + A2n X n ≥,=,£ B2
M M M
Am1 X1 + Am 2 X 2 + L + Amn X n ≥,=,£ Bm
where
X j ≥ 0, j = 1,2,L,n
Aij ΠR, i = 1,2,L,m, j = 1,2,L,n
Bi ΠR, i = 1,2,L,m
Ci ΠR, i = 1,2,L,n

Fall 2003 105

 Mixed-Integer Linear Programming

l MILP
– Linear constraints and linear objective functions
– Combine integer in the model

l Allow the use of integer, real number, rational

numbers in the model.
l Integers can be used as decision variable and
indicator variable which are also called 0-1
variables.

Fall 2003 106

 Decision Variables
l Represent the possible decisions
– Example:

Ï1 if test set i is assigned to resource k

Rik = Ì
Ó0 otherwise

– Example for 2 test sets with 3 resources

R11 + R12 + R13 = 1
†
R21 + R22 + R23 = 1

†
Fall 2003 107
 Indicator Variables
l Used to link the logic condition between two
constraints.
l Indicate the state of the variable.
l Possible values are 0 and 1.
l Example:
– Logic condition:
x > 0 fi d = 1
– Constraint:
x - Md £ 0, d Œ {0,1}, M is x's upper bound.
†

†
Fall 2003 108
 Problem Formulation
l Linearize nonlinear item: xd.
– x is a non-negative real number.
– d is a 0-1 variable.
l Linearization procedure
1) y = dx
2) List logic condition
d = 0 fi y = 0
d = 1 fi y = x
† 3) Add extra constraints to represent
y - Md £ 0
† -x + y £ 0
x - y + Md £ M
y ≥ 0
M is the upper bound of x and y.

Fall 2003
† 109
 Problem Formulation - cont’d

l Additional constraints can be easily introduced

to model.
l The number of variables and constraints
increase incredibly fast as the number of
cores increase.
l ILP is computationally expensive for large
large SoC’s.

Fall 2003 110

 Bin Packing Based Methodologies

l Determine how to put the most objects in the

least number of fixed space bins.
l More formally, find a partition and assignment
of a set of objects such that a constraint is
satisfied or an object function is minimized (or
maximized).

Fall 2003 111

 One-Dimensional Bin Packing

l Given:
A list of objects with their associated values,
and a fixed bin size.
l Find:
The assignment of objects to bins such that
the least number of bins are needed.

Fall 2003 112

 A Best-Fit Algorithm Example
l Placing each package in the “best” place that can hold
it.
– The best bin is the one with the least amount of space left
after the package is added.

Fall 2003 113

 Two-Dimensional Bin Packing
l Given:
A set of orthogonal rectangles and a fixed-
width bin.
l Objective:
Pack the rectangles into the bin so as to
minimize the height of the bin.
l Remarks
– The rectangles do not overlap with each other or
the edges of the bin.
– The rectangles are packed with their sides parallel
to the sides of the bin. (Rotations disallowed.)

Fall 2003 114

 An Example

Fall 2003 115

 Multi-Dimensional Bin Packing

l 3D is complicated enough.
l When more constraints are considered, multi-
dimension problem will be extremely
complicated.
l Can be solved within reasonable time.

Fall 2003 116

 Dual Rectangle Bin Packing
l Each test set is represented by two rectangles
packed into two different open-ended 2-D
bins.

l Other constraints are considered when

packing the rectangles into the bins.

Fall 2003 117

 An Example

Fall 2003 118