What is FPGA?

• FPGA stands for Field Programmable Gate Array. It is an integrated circuit which can be
“field” programmed to work as per the intended design.
• The Microcontrollers have become dominant over FPGA because of their cheap cost, good support,
easy availability, large community, versatility, programming etc.
• But other than that microprocessors have some limitations such as the instructions set, sequential
execution of programs (sequential processing), lack of flexibility and reusability etc.
• However the FPGA can overcome these limitations as FPGAs have parallel execution of programs
and it is flexible & reusable means it can be reprogrammed over and over for different tasks.
• FPGA can work as a microprocessor, or as an encryption unit, or graphics card, or even all
these three at once. As implied by the name itself, the FPGA is field programmable. So, an
FPGA working as a microprocessor can be reprogrammed to function as the graphics card
in the field, as opposed to in the semiconductor foundries.
• The designs running on FPGAs are generally created using hardware description languages
such as VHDL and Verilog.

FPGA Microcontroller
A Field-Programmable Gate Array is an integrated microcontrollers cannot be programmed or
circuit silicon chip which has array of logic gates restructured in the field.
and this array can be programmed in the field.
the user can overwrite the existing configurations The user is neither allowed to overwrite its existing
with its new defined configurations and can create configurations nor can they create any digital
their own digital circuit on field. circuit on field.
The microcontrollers are easy to program and the
community is also wide.
FPGAs are only contains logic blocks that can again The microcontrollers are custom built mini
be rewired electrically computers which comes in IC form.
consumes more power. consumes less power
The FPGAs is known to be costly and it requires
more cost than microcontroller when it comes to
building any device.
FPGAs takes considerably much more time to set- microcontrollers are available readily built for
up specific applications.

FPGA Architecture

An FPGA has a regular structure of logic cells or modules and interlinks which is under the
developers and designers complete control. The FPGA is built with mainly three major blocks
such as Configurable Logic Block (CLB), I/O Blocks or Pads and Switch Matrix/
Interconnection Wires. Each block will be discussed below in brief.
• CLB (Configurable Logic Block): These are the basic cells of FPGA. The CLBs are primarily
made of Look-Up Tables (LUTs), Multiplexers and Flip-Flops. They can implement
complex logic functions. Each CLBs have I/Os on each side which makes them flexile for the
mapping and partitioning of logic.

• I/O Pads or Blocks: The Input/Output pads are used for the outside peripherals to access the
functions of FPGA and using the I/O pads it can also communicate with FPGA for different
applications using different peripherals.

• Switch Matrix/ Interconnection Wires: Switch Matrix is used in FPGA to connect the long and
short interconnection wires together in flexible combination. It also contains the transistors to
turn on/off connections between different lines.
Apart from CLBs, and routing interconnects, many FPGAs also contain dedicated hard-silicon
blocks for various functions such as Block RAM, DSP Blocks, External Memory Controllers, PLLs,
Multi-Gigabit Transceivers etc. A recent trend is providing a hard-silicon processor core (such as
ARM Cortex A9 in case of Xilinx Zynq) inside the same FPGA die itself so that the processor can
take care of mundane, non-critical tasks whereas FPGA can take care of high-speed acceleration
which cannot be done using processors. These dedicated hardware blocks are critical in
competing with ASICs.

FPGA Flow:

1. Design Entry: Design entry can be done using two ways. One is through schematic; another is
through Hardware Description Language (HDL). Generally, for a design that deals more with
complex systems, it is better to opt for HDL, a quicker, language-based process that rids you of
the need to design in lower level hardware, while schematics is a good choice for someone who
wishes to design hardware because it gives more visibility to the entire system. Schematic based
approach tends to work better for low level or smaller designs whereas for complex designs
better to go with HDL based approach.

2. Synthesis: As the design entered by us is in form of code, it needs to be converted into a

actual circuit what we intend to implement. This is done by the synthesis tools such as vivado
etc. It converts the behavior code into gate level netlist where the entire circuit will be
represented in form of gates, flip-flops and multipliers. The interconnections between them are
also shown in a netlist. The process begins with a syntax check once you feed in your HDL
based design. It is then optimized by the reduction of logic, elimination of redundant logic, and
the reduction of the size of the design while simultaneously making it faster to implement. The
last step is to map out the technology by connecting the design to the logic, estimating the
associated time, and churning out the design netlists which are subsequently saved.
3. Implementation: This phase is where the layout of your design will be determined and
consists of three steps: translate, map, and place & route. The tools used in this step are provided
by the FPGA vendors because they know best how to translate a synthesized netlist into an
FPGA. The first step for the tools is to gather all the constraints that are set by the user together
with the netlist files. These constraints can be regarding the assignment and position of the pins,
the requirements regarding timing such as the maximum delay or the input period of the clock.
Then the tool maps out the implementation by comparing the resource requirement specified in
the files to the resources actually available on the FPGA being used. The circuit is divided into
the logic blocks or elements in the form of sub blocks. As a result, your entire design is placed in
specific logic blocks and is ‘mapped out’ into the FPGA. The next step is to connect and route all
the signals accordance with the constraints set by the user between all the logic blocks and I/O
blocks.

4. Program FPGA: The last step in the process is to finally load the mapped out and completely
routed design into the FPGA. For that reason, you will need to generate a Bit-Stream file and this
bit stream file will be dumped onto your FPGA board using Flash programmer device. When you
run your FPGA the board mimics your design functionality. This is the entire process for FPGA
based design.

Also in FPGA there is simulation checks which are done at each level. Behavior simulation is
done at design entry level, Functional simulation is done post synthesis and Timing simulation is
done at Implementation level.

What is ASIC?
ASIC stands for Application Specific Integrated Circuit. As the name implies, ASICs are
application specific. They are designed for one sole purpose and they function the same their
whole operating life. For example, the CPU inside your phone is an ASIC. It is meant to function
as a CPU for its whole life. Its logic function cannot be changed to anything else because its
digital circuitry is made up of permanently connected gates and flip-flops in silicon. The logic
function of ASIC is specified in a similar way as in the case of FPGAs, using hardware description
languages such as Verilog or VHDL. The difference in case of ASIC is that the resultant circuit is
permanently drawn into silicon whereas in FPGAs the circuit is made by connecting a number of
configurable blocks.

ASIC FLOW:

1. Specification: The specification for the product is collected from the market or customer
requirements. The specification also consists of what all features the product should consist of
etc. These are generally collected by marketing people.

2. Architectural Design: The architectural design consists of what all blocks the design should
consist of and how they are connected in the design. They come up with a block diagram which
includes all the above based on the specification. This architecture team will estimate the block
area, how much power is required and cost for the design

3. RTL Design: The RTL design is developed using HDL. It is developed based on the
architecture design. It is written in Verilog or VHDL. This code describes how the data is
transferred between different components in the design.

4. RTL Verification: Verifying the developed design is done in this stage. Test cases will be
developed to check the functionality of the design and if found any bug in the design, it is
intimated to designer to modify it and release the new RTL. Verification itself takes 60 percent
of total lifecycle time of chip development. This stage is very important as the design is tested
for its functionality. Any bugs found post routing is difficult to correct and also post fabrication
we cannot correct the design. So this is very important part of a chip development cycle.
5. Synthesis: It is a process of converting the RTL code into gate level netlist. Up to RTL
verification the design is technology independent. In synthesis process the design is converted
into technology dependent. It is 3 stage process.

• Translation: RTL code is converted to Boolean expressions.

• Optimization: Boolean expression is optimized by SOP and POS optimization methods
• Mapping: In this the Boolean expression is converted into gates based on the technology
and generates a gate level netlist. The inputs for synthesis are RTL code, .SDC and .LIB
files. After the synthesis the generated outputs are gate level netlist and .SDC files.

6. Gate Level Simulations: Gate level simulation is used to boost the confidence regarding
implementation of a design and can help verify dynamic circuit behavior, which cannot be
verified accurately by static methods. It is run after RTL code is simulated and synthesized into
a gate-level netlist. Gate level simulation overcomes the limitations of static-timing analysis and
is increasing being used due to low power issues, complex timing checks at 40nm and below,
design for test (DFT) insertion at gate level and low power considerations. For DFT, scan chains
are inserted after the gate-level netlist is created; gate level simulation is often used to determine
whether scan chains are correct

7. Design for Testability: Design for testability (DFT) is a technique which facilitates a design
to become testable after production. In this stage we put extra logic along with the design logic
during implementation process which helps post production process. The DFT will make the
testing easy at post production process. At this stage an ATPG (automatic test pattern generator)
file will generate.

8. Floorplan: The floorplan is the process of determining the macro placement, power grid
generation and I/O placement. It is the process of placing blocks/macros in the chip/core area
there by determining routing areas between them. It determines the size of the die and
creates wire tracks for placement of standard cells. It creates power straps and specifies pg
connection. It also determines the I/O, pin/pad placement information.

9. Placement: Placement is the process of automatically assigning correct position to standard

cells on the chip with no overlapping. By global placement outside of standard cells will be
placed inside roughly. By the detailed placement the standard cells will place in site rows
(legalize placement).In placement stage we check the congestion value by GRC map.

10. Clock Tree Synthesis (CTS): In this stage we built the clock tree by using inverters and
buffers. In the chip clock signal is essential to the flip flops, to give the clock signal from clock
source we built the clock tree. It is the process of balancing the clock skew and minimizing
insertion delay in order to meet timing and power.

11. Routing: Before the routing stage the connection between the macros, standard cells, clock,
i/o port are logical connections. In this stage we connect all the cells physically with the metal
straps. Routing is divided as two parts 1) Global routing 2) Detailed routing. The global routing
will tell for which signal which metal layer is used. Before the detailed routing all are the logical
connections. In detailed routing the physical connections are done.
12. Signoff & Fabrication: After the routing the physical layout of chip is completed. In signoff
stage all the tests are done to check the quality and performance of the layout before tapeout.
After this the design is converted into GDS II file. By the GDS II file information we fabricate
the chip. The total design is converted into chip by the manufacturing process.

13. Post Silicon Validation: Post-silicon validation is used to detect and fix bugs in integrated
circuits and systems after manufacture. Post-silicon validation involves operating one or more
manufactured chips in actual application environments to validate correct behaviors over
specified operating conditions. The objective is to ensure that no bugs escape to the field. If there
is any fault in the design then we modifies the design by repeating the steps. If there are no faults
then chip will go to packaging.

14. Chip: Finally we get the required chip which will be manufactured in bulk. If we use this
process to produce only 1 chip, it costs a lot more than the actual chip cost after production. If
we produce the chips in bulk, we can save the silicon wafer for producing more chips with single
wafer and the cost of the production for each chip will be less than the cost for which it has been
sold.

FPGA vs ASIC comparison summary

No. FPGA ASIC
Reconfigurable circuit. FPGAs can be
reconfigured with a different design. They even Permanent circuitry. Once the application
have capability to reconfigure a part of chip specific circuit is taped-out into silicon, it
1
while remaining areas of chip are still working! cannot be changed. The circuit will work
This feature is widely used in accelerated same for its complete operating life.
computing in data centers.
Design is specified generally using hardware
Same as for FPGA. Design is specified
2 description languages (HDL) such as VHDL or
using HDL such as Verilog, VHDL etc.
Verilog.
Very high entry-barrier in terms of cost,
learning curve, liaising with semiconductor
Easier entry-barrier. One can get started with
3 foundry etc. Starting ASIC development
FPGA development for as low as USD $30.
from scratch can cost well into millions of
dollars.
Not suited for very high-volume mass Suited for very high-volume mass
4
production. production.
Less energy efficient, requires more power for Much more power efficient than FPGAs.
5 same function which ASIC can achieve at lower Power consumption of ASICs can be very
power. minutely controlled and optimized.
Limited in operating frequency compared to ASIC fabricated using the same process
6
ASIC of similar process node. The routing and node can run at much higher frequency
No. FPGA ASIC
configurable logic eat up timing margin in than FPGAs since its circuit is optimized
FPGAs. for its specific function.
Analog designs are not possible with FPGAs.
ASICs can have complete analog circuitry,
Although FPGAs may contain specific analog
for example WiFi transceiver, on the same
7 hardware such as PLLs, ADC etc, they are not
die along with microprocessor cores. This
much flexible to create for example RF
is the advantage which FPGAs lack.
transceivers.
FPGAs are highly suited for applications such
as Radars, Cell Phone Base Stations etc where
ASICs are definitely not suited for
the current design might need to be upgraded to
application areas where the design might
8 use better algorithm or to a better design. In
need to be upgraded frequently or once-in-
these applications, the high-cost of FPGAs is
a-while.
not the deciding factor. Instead,
programmability is the deciding factor.
Preferred for prototyping and validating a
design or concept. Many ASICs are prototyped It is not recommended to prototype a
using FPGAs themselves! Major processor design using ASICs unless it has been
9 manufacturers themselves use FPGAs to absolutely validated. Once the silicon has
validate their System-on-Chips (SoCs). It is been taped out, almost nothing can be done
easier to make sure design is working correctly to fix a design bug (exceptions apply).
as intended using FPGA prototyping.
ASIC designers need to care for everything
FPGA designers generally do not need to care
from RTL down to reset tree, clock tree,
for back-end design. Everything is handled by
physical layout and routing, process node,
synthesis and routing tools which make sure the
10 manufacturing constraints (DFM), testing
design works as described in the RTL code and
constraints (DFT) etc. Generally, each of
meets timing. So, designers can focus into
the mentioned area is handled by different
getting the RTL design done.
specialist person.

FPGA vs ASIC visual comparison

References:

https://numato.com/blog/differences-between-fpga-and-asics/

https://circuitdigest.com/tutorial/what-is-fpga-introduction-and-programming-tools

https://www.researchgate.net/figure/Fig-8-a-Structure-of-FPGA-b-Detailed-structure-of-Logic-
cell_fig4_320652259