Table of contents:

page

Objective of the project.............................................................................................4

The simple CPU design and the methodology...........................................................4
Parts of CPU.............................................................................................................4
Half Adder....................................................................................................................4
Full Adder.......................................................................................................................5
Parallel Adder.................................................................................................................5
8-bit left shift register........................................................................................................6
8-bit first complement.........................................................................................................6
1-bit register.........................................................................................................................7
Multiplexer........................................................................................................................7
Counter............................................................................................................................8
D-Flip Flop.......................................................................................................................9
ALU...................................................................................................................................9
CPU...................................................................................................................................10
Conclusion.........................................................................................................................12
Reference...

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ABSTRACT

This paper describes a sequence of designs, each building upon the next, and leading to a
working simulation of a simple 8-bit CPU (Central Processing Unit). The design features a
classic Von Neumann architecture comprising a simple data path with a few registers, a simple
ALU (Arithmetic Logic Unit. The first step involves the design of the ALU, which is capable of
three basic operations. The second step is construction of a data path complete with several 8-bit
registers. The third step involves the design and implementation of a control unit. All simulations
are performed using a free and open source simulator called Logism, which performs digital
logic simulations with the ability to build larger circuits from smaller sub circui

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Objective of the project
Computer architecture and organization form important parts of the computer science “body of
knowledge”. A professional in any field of computing should not regard the computer as just
black box that executes programs by magic. They need to understand computer architecture in
order to make best use of the software tools and computer languages they use to create programs.
One way to learn about this topic is to study existing CPU architectures. Many different CPU
architectures abound, and different textbooks have selected different processor architectures as
examples. Several commercial processors are used as an example to describe computer
architecture and organization concepts.

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THE SIMPLE CPU DESIGN AND METHODOLOGY
This paper will describe a series of designs using Logisim to provide a step-by-step design and
simulation of a simple CPU. The steps are broken down into several parts, each building upon
the next. These parts are
Half adder
Full adder
Binary parallel adder
8-bit left shift register
8-bit first complement
1-bit register
Multiplexer
D-Flip Flop
Counter
Half Adder
From the verbal explanation of a half adder, we find that this circuit needs two binary
inputs and two binary outputs. The input variables designate the augend and addend
bits; the output variables produce the sum and carry. The C output is 1 only when both inputs are
1. The S output
represents the least significant bit of the sum.
The simplified Boolean functions for the two outputs can be obtained directly from
the truth table. The simplified sum-of-products expressions are
S = x_y + xy_

Full Adder
Addition of n-bit binary numbers requires the use of a full adder, and the process of addition
proceeds on a bit-by-bit basis, right to left, beginning with the least significant bit. After
the least significant bit, addition at each position adds not only the respective bits of the
words, but must also consider a possible carry bit from addition at the previous position.
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It

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consists of three inputs and two outputs. Two of the input variables, denoted by x and y ,
represent the two significant bits to be added. The third input, z , represents the carry from
the previous lower significant position.

S = x_y_z + x_yz_ + xy_z_ + xyz

C = xy + xz + yz

Parallel Binary Adder

Parallel adders can be placed in to two categories based on the way in which the internal carries
from stage to stage are handled.
Ripple carry adder

Look-ahead carry adder

Externally, both types of adders are the same in terms of inputs and outputs.

The difference is the speed at which they can add numbers. The look-ahead carry adder is
much faster than ripple carry adder

8-bit left shift register

It has positive edge clock, serial in, and serial out .

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They will store a bit of data for each register.

A serial in, serial out shift register may be one to 64 bit in length, longer if register or

Package are cascaded

8 bit First complement

To inverting all the bit in the binary representation of the number(swapping 0s for 1s and vise
versa).

1s complement of the number behaves like the negative of the original number in some
arithmetic operation.

1 BIT REGISTER

An instruction set architecture for a processor that has datawidth and data register width

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Of 1-bit.

MULTIPLEXER
A multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. The selection of a particular input
line is controlled by a set of selection lines. Normally, there are 2n input lines and n selection
lines whose bit combinations determine which input is selected.

counter

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A register that goes through a prescribed sequence of states upon the application of input
pulses is called a counter . The input pulses may be clock pulses, or they may originate
from some external source and may occur at a fixed interval of time or at random. The
sequence of states may follow the binary number sequence or any other sequence of
states. A counter that follows the binary number sequence is called a binary counter . An
n ‐bit binary counter consists of n flip‐flops and can count in binary from 0 through 2n - 1.
Counters are available in two categories: ripple counters and synchronous counters.
In a ripple counter, a flip‐flop output transition serves as a source for triggering other
flip‐flops. In other words, the C input of some or all flip‐flops are triggered, not by the
common clock pulses, but rather by the transition that occurs in other flip‐flop outputs.
In a synchronous counter, the C inputs of all flip‐flops receive the common clock.
Synchronous counters are presented in the next two sections

D Flip-Flops
Once the state diagram has been derived, the rest of the design follows a straightforward
synthesis procedure. In fact, we can design the circuit by using an HDL
description of the state diagram and the proper HDL synthesis tools to obtain a
synthesized net list. (The HDL description of the state diagram will be similar to
HDL To design the circuit by hand, we need to assign
binary codes to the states and list the state table.
We choose two D flip-flops to represent the four states, and we label their outputs
A and B . There is one input x and one output y . The characteristic equation of the
D flip-flop is Q(t + 1) = DQ, which means that the next-state values in the state
table specify the D input condition for the flip-flop.

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steps to design Arithmetic logic unit(ALU)
Step 1: A simple ALU
The ALU is built with eight-bit adder, one bit-extender for subtracting, eight-bit multiplier, and
basic logic gates(OR, XOR,NOR, controlled buffer) for its operation. It is an 8-bit ALU using
the above-mentioned logic gates. The ALU have two 8-bit bus inputs (labelled a and b) and one
8-bit output as illustrated in Figure 2.2.The function of the ALU is selected using three ALU
control lines (F0, F1 and F2) which select one of eight operations in the ALU as indicated in
Table 2.1. The ALU is constructed in a straightforward manner by building the digital circuit for
each operation and using a 1-of-8 multiplexer to select which appears at the output.

Fig: Simple ALU

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 THE SUBCIRCUIT THAT BUILT-ON THE ALU ARE:
 Eight-bit adder-Subtracter
The eight-bit adder-subtracter is built from two four-bit adders-subtracter, which are built from
four full-adders(subtracters) individually.

Step 2: The CPU Data path

The next step in the process is to take the ALU sub circuit built in the previous step and place it
inside a data path using Logisim. The CPU includes MAR, MBR and data bus and address bus.

Step 3: The control Unit

The manual control of the data path highlights the need to manage the control signals. The
control lines help us with specifying which operation we are going to perform.

Op codes Output
000 SUB

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001 ADD
010 AND
011 OR
100 XOR
101 MUL
110 LOAD
111 STORE
summary of simple ALU operations

Step 4: Simulation result and discussion (Putting it all together)

Now it is time to put the ALU with the data paths and the control unit together. We can test using
some instructions if the CPU works properly.

CONCLUSION
 The design of processor Break down in to many parts Which are constructed individually
and represented in the process by only one simple block diagram
 Having built our own simple CPU has understanding value, which helps the description
of existing industrial CPU architectures. Logisim is a friendly and simple tool for
performing digital logic simulations, yet it is powerful enough to simulate a basic CPU.
This paper describes a sequence of step-by-step designs that gradually create simple CPU
simulation
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