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Verilog Sequential Modeling

1. Learn about sequential modeling concepts in Verilog including initial and always blocks, case statements, blocking/non-blocking assignments, and delays. 2. Implement several sequential designs in Verilog like priority encoders, counters, sequence detectors, and flip-flops. 3. Verify the designs through simulation using test benches and observing the outputs match the expected behavior. 4. Complete additional exercises to design a full adder, mod-8 counter, priority encoder, and other sequential circuits.

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R INI BHANDARI
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279 views

Verilog Sequential Modeling

1. Learn about sequential modeling concepts in Verilog including initial and always blocks, case statements, blocking/non-blocking assignments, and delays. 2. Implement several sequential designs in Verilog like priority encoders, counters, sequence detectors, and flip-flops. 3. Verify the designs through simulation using test benches and observing the outputs match the expected behavior. 4. Complete additional exercises to design a full adder, mod-8 counter, priority encoder, and other sequential circuits.

Uploaded by

R INI BHANDARI
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPT-4 (FIFTH WEEK LAB1 and LAB2)

Verilog Sequential Modeling

Please make note of the few topics of this experiment,

Structured procedures, initial and always, case statements, use of parameters, blocking and
nonblocking statements, delay control, generate statement, event control, conditional
statements, multiway branching, loops (while, repeat, forever), sequential and parallel blocks.

Note- Please go through the paper “Correct methods for adding delays to Verilog behavioral
models” attached with the previous email. If you had finished it in last week then fine,
otherwise finish it this week.

Objective:
To understand the concepts related to sequential modeling style and write Verilog programs
using the same.
Theory: To model the behavior of a digital description using sequential modeling the
following two statements are primarily used:
i) Initial statement
ii) Always statement
Initial statement: An initial statement executes only once. It begins its execution at the start of
simulation which is at time t = 0.
Syntax:
initial
[timing_control] procedural_statement
Always statement: An always statement executes repeatedly. Just like the initial statement, an
always statement also begins execution at time t = 0.
Syntax:
always
[timing_control] procedural_statement
Only a register data type can be assigned a value in either of these statements. Such a data
type retains its value until a new value is assigned. All initial and always statements begin
execution at time t = 0 concurrently. If no delays are specified in a procedural assignment,
zero delay is the default, that is, assignment occurs instantaneously.
Example-3.1: Write a sequential Verilog code for 8-to-3 priority encoder with active high
enable input and verify the design by simulation.
Solution:

8-to-3 priority encoder block with active high enable input


Truth Table of 8-to-3 priority encoder with active high enable input
Input Output
E D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 X X X X X X X X X X X
1 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 X 0 0 1
1 0 0 0 0 0 1 X X 0 1 0
1 0 0 0 0 1 X X X 0 1 1
1 0 0 0 1 X X X X 1 0 0
1 0 0 1 X X X X X 1 0 1
1 0 1 X X X X X X 1 1 0
1 1 X X X X X X X 1 1 1

`timescale 1ns / 1ps


// 8-to-3 priority encoder with active high enable input
module encoder(D,Q,E);
input [7:0] D;
input E;
output [2:0] Q;
reg [2:0] Q;
always @(D or E)
begin
if (E= = 1)
casez (D)
8'b00000001: Q=3'b000;
8'b0000001?: Q=3'b001;
8'b000001??: Q=3'b010;
8'b00001???: Q=3'b011;
8'b0001????: Q=3'b100;
8'b001?????: Q=3'b101;
8'b01??????: Q=3'b110;
8'b1???????: Q=3'b111;
endcase
else
Q=3'bX;
end
endmodule
Simulation Results:
Input: D [7:0] = 00100 010, E = 1
Output: Q [2:0] = 101

Example-3.2: Write a sequential Verilog code for 3-bit binary ripple up counter and verify
the design by simulation.
Solution:
Verilog Code:
`timescale 1ns / 1ps
module counter( clk, count );
input clk;
output [2:0] count;
reg [2:0] count;
wire clk;
initial
count = 3'b0;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
count[1] <= ~count[1];
always @( negedge count[1] )
count[2] <= ~count[2];
endmodule
Testbench:
module counter_tb;
reg clk;
wire [2:0] count;
counter cnter( .clk(clk), .count( count ) );
initial
begin
clk = 0;
#200 $finish;
end
always
begin
#2 clk = ~clk;
end
always @( posedge clk)
$display("Count = %b", count );
endmodule
Simulation Results:
Output: 000 - - 001 - - 010 - - 011 - - 100 - - 101 - - 110 - - 111

Example-3.3: Write a sequential Verilog code for 1010 overlapping sequence detector with
active low reset and positive edge triggered clock (use parameter declaration) and verify the
design by simulation.
Solution:

Overlapping 1010 sequence detector block and state diagram [Format: din/ y]

Verilog Code:
module melfsm(din, reset, clk, y);
input din;
input clk;
input reset;
output reg y;
reg [1:0] cst, nst;
parameter S0 = 2'b00, //all state
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;
always @(cst or din)
begin
case (cst)
S0: if (din == 1'b1)
begin
nst = S1;
y=1'b0;
end
else
begin
nst = cst;
y=1'b0;
end
S1: if (din = = 1'b0)
begin
nst = S2;
y=1'b0;
end
else
begin
y=1'b0;
nst = cst;
end
S2: if (din = = 1'b1)
begin
nst = S3;
y=1'b0;
end
else
begin
nst = S0;
y=1'b0;
end
S3: if (din = = 1'b0)
begin
nst = S2;
y=1'b1;
end
else
begin
nst = S1;
y=1'b0;
end
default: nst = S0;
endcase
end
always@(posedge clk)
begin
if (reset)
cst<= S0;
else
cst<= nst;
end
endmodule
Simulation Results:
Input: din :1010
Output: y : 0 0 0 1

Example-3.4: Write a sequential Verilog code for 4 bit ring counter and verify the design by
simulation and verify the design by simulation.
Solution:
Table showing output sequence of 4 bit ring counter
Count Sequence
Order
0 1000
1 0100
2 0010
3 0001
Verilog Code:
module Ringcounter(q,clk,clr);
input clk,clr;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
if(clr= =1)
q<=4'b1000;
else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule
Test Bench:
module ringtest;
// Inputs
reg clk;
reg clr;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
Ringcounter uut (
.q(q),
.clk(clk),
.clr(clr)
);
always
begin
#50 clk=1'b1;
#50 clk=1'b0;
end
initial begin
// Initialize Inputs
clk = 0;
clr = 0;
#50 clr = 1'b1;
#100 clr = 1'b0;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

Simulation Results:
Output: 1000 --- 0100 --- 0010 --- 0001--- 1000 ----

Exercise Problems
1. Write the sequential Verilog code for N bit full adder (assume N = 6 and use for-loop
statement) and verify the design by simulation.
2. Write the sequential Verilog code for synchronous mod 8 counter and verify the design by
simulation.
3. Write a sequential Verilog code for 8-bit priority encoder and verify the design by
simulation.
4. Write a Verilog code and test bench to model and simulate 4 bit synchronous up/ down
counter using Cadence tool.

5. Write a Verilog code and test bench to model and simulate the positive edge triggered SR flip-
flop using Cadence tool.

6. Write the sequential Verilog code for Master-Slave JK flip-flop and verify the design by
simulation.
7. Write sequential Verilog code for 4-bit universal shift register and verify the design by
simulation.
8. Write a sequential Verilog code for 1110 overlapping sequence detector with active low
reset and positive edge triggered clock and verify the design by simulation.

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