ATPG For Scan Chain Latches and Flip-Flops

Samy R. Makar* and Edward J. McCluskey

Center for Reliable Computing
Gates Hall 2A
Stanford University
Stanford, CA 94305

Abstract
A new approach for testing the bistable elements
(latches and flip-flops) in scan chain circuits is
presented. In this approach, we generate test pattems
that apply a checking experiment to each bistable
element in the circuit while checking their response.
Such tests guarantee the detection of all detectable
combinational defects inside the bistable elements. The
algorithm is implemented by modifying an existing
stuck-at combinational test pattern generator. The
z-
Figure 1-1 Three Bit Binary Counter.
number of test patterns generated by the new program is
comparable to the number of traditional stuck-at
patterns. This shows that this approach is practical for
large circuits.
1. Introduction
Scan was introduced to overcome the difficulties of
sequential test generation [I], [2]. The basic idea of
scan is to allow easy access to the flip-flops in the
design so that test patterns can be applied directly to the
inputs of the. internal combinational logic, and the
outputs of the internal combinational logic can be
"captured" by the bistable elements and scanned to the
primary output for comparison with expected values.
This makes it possible to use combinational circuit test -
o stuck-open
short

generation algorithms on sequential circuits.

A difficulty with scan based methods is that they do T

not address faults within the bistable elements. [3], [4]

and [5] showed that tests for stuck-at faults at flip-flop CK1 b-7
inputs and outputs miss many internal faults.
Simulation results presented in this paper confirm these
results. The three bit binary counter shown in Fig. 1-1
was used in our simulations. We found 37 faults that
were not detected by a traditional test (this test detected T
100% of input and output stuck-at faults on the Figure 1-2 Faults in First Flip-Flop of
combinational gates as well as the flip-flops, and Binary Counter Missed by 100% Stuck-
included a flush test of 01100 throughout the scan
At Test That Affect Normal Operation.
chain), but affect the normal operation of the counter.
Fig. 1-2 shows some of these faults. All these faults
are detected by our test.
Our test is based on checking experiments. A
checking experiment is a sequence of inputs that, when
* Samy is currently with Cirrus Logic Inc. applied to a circuit, gives different outputs than any

364
0-8186-7810-0/97 $10.00 0 1997 IEEE
other circuit with the same input, outputs, and same This may be very difficult or impossible to do. Also,
number of or fewer states [6]. The main advantage of a there are many possible checking experiments. Fig. 2-1
checkmg experiment approach over other methods (such shows a small circuit with three flip-flops. We will
as stuck-at ATPG) is that it is independent of the fault show how to generate a clhecking experiment for the
model, and will detect any defect that does not increase shaded MD flip-flop (F3) .
the number of states in the circuit. The main problem
with checking experiments is that the number of test
patterns can be very large, making it impractical for
large circuits. However, we use a checking experiment SDI -
only for the bistable elements. We show that such tests
are comparable in size to stuck-at tests, indicating that
they are practical for large circuits. We presented some
early results of this work in [ 7 ] . That paper described a
technique for finding tests for scan chain latches, but
cannot be used for flip-flops. The technique described
here applies to both flip-flops and latches. Another
important difference is that here we implemented our C L -
algorithm and generated tests fol- all the ISCAS-89
circuits [8]. The test lengths of our tests were Figure 2-1 Circuit Undler Test.
comparable with stuck-at test lengths. Instead of trying to apply a complete checking
The rest of this paper is divided as follows. In experiment directly from primary inputs, we use a
Section 2, we describe the basis of our algorithm, and divide-and-conquer approach. Every checking
in Section 3, we describe an implementation of our experiment must identify all the stable and unstable
algorithm. In Section 4, we present the fault states in its primitive flow table. For each of these
simulation results for a single MD flip-flop. The states a sequence of inpuls must be applied to the
simulations include test patterns for stuck-at faults and bistable element under test, and the output of the
checking experiment based test patterns. The results bistable must be observed at a primary output. An
indicate that there are many faults missed by the stuck- example of such an input sequence for an MD flip-flop
at test. In the same section, we present test generation is shown in Fig. 2-2. We can use the scan chain to
results for all the ISCAS-89 benchmark circuits [8]. supply a test pattern that would set the inputs and
The number of test patterns is compared with traditional output of the flip-flop under test to the initial values

r
stuck-at patterns. Results indicate that the number of (d=O, s=l, and q=1).
test patterns from our program increase at the same rate
as stuck-at patterns. This implies that they are practical
for large circuits.
2. Checking Experiments for Bistable
Elements ’
Flip-flops can have many flow tables, but there is Figure 2-2 A Required Input Sequence for an
only one primitive flow table (barring isomorphism) for MD Flip-Flop.
each flip-flop type [9]. Therefore we use primitive flow The method for finding a test pattern that would set
tables in our analysis. In a primitive $ow table, each d=O, s=l, and q=l is similar to combinational ATPG.
row contains only one stable state. A checking In our example, the test pattern would be Xi = 0 and y2
experiment for a primitive flow table will detect all = yg = 1 would set d, s and q to the desired values (see
defects that do not increase the number of states in any
column. Fig. 2-3). After applying C = 010, d and s will depend
on the new values in F1 and F2. Thus, the test pattern
Given the primitive flow table of a bistable element,
we can easily derive a checking experiment for the we use must preserve s = 0 and d = 0 after the clock
bistable element. However, if a bistable element is pulse. In our example, this can be done with the test
pattern Xi = 0 and y1 = y2 = yg = 1 (see Fig. 2-4). The
embedded inside a circuit, we need to find a way to get
the checking experiment from primary inputs to the difference between this and the earlier test pattern is that
bistable element, and to observe the output of the y1 is set to 1, so that after the clock pulse y2 is still 1.
bistable element under test from the primary output.

365
 L?
A2
I

I ame z- I tiemenrary uperarions

F3
Operation Description
SDI - SDO Single Cycle Determine bit values of a test pattern that
would set lines in the circuit to desired
values.
Single Cycle Determine bit values of a test pattern that

:fj Change would set lines in the circuit to desired

values, and by changing values only on
the primary inputs would change the value
of a line in the circuit.
Shift Determine bit values of a test pattern that
T=J Operation would set lines in the circuit to desired
values, and after the scan shifts by one,
Figure 2-3 Circuit Under Test With Test would again set some lines in the circuit to
Pattern.
desired values. The values on the lines
need not be the same for both cycles
This analysis is similar to sequential ATPG because Normal Determine bit values of a test pattern that
more than one time frame is considered, i.e. we consider Operation would set lines in the circuit to desired
the values on the flip-flop before and after the clock values, and after a normal cycle (bistable
pulse. Since we had only one pulse on C, we have to element input selected from combinational
logic), would again set some lines in the
deal with only two time frames. This makes the circuit to desired values. The values on the
problem much easier than sequential ATPG. In the lines need not be the same for both cycles.
above example, we had T = 1, and applying a pulse on lombinational Determine bit values of a test pattern that
C caused the scan chain to shift once. Thus the Logic would sensitize a line in the circuit to a
operation of generating a test pattern for such a sequence Sensitization primary output or an input of a bistable
element
is called a shift operation. Other required sequences need
other types of operations. These elementary operations Fig. 2-5. In this algorithm, we use elementary
are summarized in Table 2-1. The first two elementary operations to find a test pattern for each required
operations are used with sequences for which there is no sequence of each flip-flop in the circuit. The test
pulse on the clock. The third (the one we showed in the patterns are placed in pattern tables that are compacted
example) and fourth are used with sequences in which using standard test pattern compaction techniques.
there is a pulse on the clock. The last elementary There are four common scan chain architectures [9].
operation is used in conjunction with the other The architectures use different bistable elements for scan
elementary operations when the next flip-flop in the cells. Different bistable element types have different
scan chain cannot “capture” the output of the flip-flop required sequences, and thus even though their
under test. algorithms have the structure in Fig 2-5, each will have
Elementary operations can be used to generate test a different implementation.
patterns for all the required input sequences [ 101.
Therefore, we can define an algorithm for generating test for each bistable element {
patterns for the bistable elements using the algorithm in for each required sequence {
Apply Appropriate Elementary Operation
I A 2 I Add Test Pattern To Appropriate Table
1
1
1
Compact Tables
Print Tables
Figure 2-5 Algorithm for ATPG for Bistable
Elements.
3. Implementation

C
T=l U
Figure 2-4 Circuit Under Test With Test
We implemented our algorithm by modifying an
existing stuck-at ATPG program in SIS [ 111. This was
done by first creating elementary functions and then
using the elementary functions to write procedures for
the four different bistable element types used in the scan
Pattern. chain archtectures.

366
 As with most ATPG programs, this program reads a faults on the input and output of the MD flip-flop. The
gate level description of the circuit. However, unlike other two tests are a checking experiment for the MD
most ATPG programs, the output is not simply a file flip-flop and a checking experiment for the MD-latch in
with test patterns, but rather a set of files with test a scan chain [IO]. The flilp-flop implementation used
patterns. The number of test pattern files depends on for the simulation is shown in Fig. 4.1-1. This
the scan architecture used. Each file of patterns implementation is selected because it is a commonly
corresponds to a different type of sequence that has used structure.
different timing on the clock and control inputs.
Details can be found in [lo]. T T

4. ATPG Results
The effectiveness of a test can be measured by the
number of defects it can detect. Even though the stuck-
at models are often used for fault simulation, we use the
more accurate (for CMOS circuits) Crosscheck fault
models, [12] and [13], for our simulation. The fault
models comprise shorted interconnects (STI), open
interconnects (OPI), short-to-power (STP), short-to-
ground (STG), transistor stuck-on (SON), and transistor
stuck-open (SOP). In the simulations, faults are T c
injected by modifying a copy of the circuit description.
Figure 4.1-1 MD Flip-Flop Implementation
The faulty circuits were simulated using HSpice [14].
Used in Simulation.
In CMOS, there are some faults whose presence does
not change the functionality of the host circuit. Some The results of the simulations are shown in Table
of these cannot be detected (and thus are untestable or 4.1-1. From the table, there are 19 faults that were not
redundant). Others that cannot be detected by a Boolean detected by the checking experiment. These faults are
voltage test (since the circuit functionality is correct) shown graphically in Fig. 4.1-2. The table also shows
can, nevertheless, be discovered by a current test or a that the pin fault test misses ten faults that are detected
delay test [15]. The simulations reported here record by the checking experiment. These faults are shown in
whether tests caused excessive supply current (IDDQ) or
incorrect outputs. The current limit for IDDQ testing is Table 4.1-1 Number of Faults Detected in MD
often determined experimentally, by plotting the values Flip-Flop (Total Faults = 256).
of many good and bad die, and selecting an appropriate
I Boolean I Boolean Alone I Boolean Alone I IDDQ I
threshold that would detect as many faulty circuits as andIDDQ (100 ns and 10 msj (100 ns, 10 ms) I Alone
possible without discarding many good ones [I61 and !
(145,166) 155
[17]. For our simulations, the current limit is 227 I 184 I (162,183) I 161 I
determined by plotting the maximum observed current 207 I (186,204) I 182
for each fault, and selecting an appropriate threshold dl 237 I 206 I (184,204) I 181
from the graph. a = Traditional Test, b = Pin Fault Test, c = MD Flip-Flop
In Section 4.1, we present simulation results for an ,Checking Exp., d = Scan MD Flip-Flop Checking Exp.
MD flip-flop, comparing traditional tests with checking
experiment based tests. In Section 4.2, we present ostuck-open
ATPG results for all the ISCAS 89 circuits. We
- short
compare the length of our tests with the length of
T
traditional stuck-at tests. The test lengths increase at
the same rate, indicating that not many more test
patterns are needed for large circuits.
4.1 MD Flip-Flop Fault Simulation.
Four different tests for the MD flip-flop were
simulated using HSpice. The first test, a traditional
test, is based on scanning in and out the 01100 test
pattern, and test patterns that would detect stuck-at 0 and
T
T i'
stuck-at 1 faults on the D input of the flip-flop. The Figure 4.1-2 Faults Missed by Checking
second test is a pin fault test set, which targets stuck-at Experiment of MD Flip-Flop (19 of them).

367
Fig. 4.1-3. In these figures white ovals indicate stuck-
open or open-interconnect faults, black ovals indicate Table 4.2-4 Number of Test Patterns for
SON faults, and thick black lines indicate shorted- Different Tests.
interconnect faults. All short-to-power and short-to- I Circuit I MD- I LSSD I MD I Tp I Stuck- I
ground faults are detected by all tests. Latch Flip- Flip- At
Flop Flop
The faults missed by the checking experiment fall
S27 29 19 118 52 14
into two groups. The first group of faults missed by the ~~ ~

S298 71 47 356 162 66

checking experiment is the stuck-open faults on the s344 97 62 395 165 65
transmission gates. These faults, though undetectable, S349 91 61 375 158 66
could add a delay to the circuit, and will thus behave as
delay faults. A test pattern that would detect a path
delay fault to the input of the flip-flop may be able to
detect these faults. The other group of faults missed by
the chechng experiment, the stuck-ons and shorted-
interconnects, will turn the master or slave latch into a
dynamic latch. Since a dynamic latch cannot guarantee
holding its value for a very long time, then loading a
value and waiting a long time may change the value in
the flip-flop and the fault would bje detected. Thus a
very slow test (data retention test) is needed for these
faults. S1488 68 45 421 179 247
The traditional test and the pin fault tests miss many S1494 68 45 422 180 243

qk qKT2K1
faults (about 5 %) detected by the checking experiment.

o stuck-open
S5378 571 336 2139

Tab le 4.2-5 Number of Test Patterns Divided

by Stuck-At Test Length.
1023 700

T I I
Figure 4.1-3 Faults Missed by Pin Fault Test
Detected by Checking Experiment of MD ,5510 0.83 0.55 3.92 1.91 1.00

1 1 1 1 ::::I
Flip-Flop (10 of them). S526 0.76 0.49 4.12 1.85 1.00
S641 1.51 1.03 4.66 2.07 1.00
4.2 Circuits Using MD Flip-Flop S713 0.92 0.63 4.30 1.92 1.00
One practical concern with testing chips is the size of S820 0.34 0.23 2.15 0.89 1.00
the test being applied. To address this issue, we S832 0.32 0.22 2.04 0.87 1.00
generated test patterns for the ISCAS 89 benchmark SI196 y:fj; 0.40
~ 2.19 1.16 ~

S1423 0.99 7.52 3.47

circuits for all four architectures, and compared them to
S1488 0.28 0.18 1.70 0.72 1.00
the stuck-at test lengths. S1494 0.28 0.19 1.74 0.74 1.00
Table 4.2-4 shows the number of vectors for all the S5378 0.82 0.48 3.06 1.46
ISCAS 89 circuits for each architecture, and for the To compare our test size with the test size of the
stuck-at tests. The name of the ISCAS 89 circuits stuck-at test, we calculate the ratio of the size of our
indicates the number of lines in the circuit. This is
tests to the size of the stuck-at tests. These ratios are
directly related to the size of the circuit. The number of shown in Table 4.2-5. The numbers in this table were
test patterns for the LSSD architecture is always the calculated by dividing the number of test patterns for the
smallest of our tests, and the number of test patterns for bistable elements by the number of stuck-at test
the MD flip-flop architecture is always the largest.
patterns. We use the number of patterns instead of the

368
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369