LAB REPORT

ON

ADVANCED VLSI DESIGN LAB

EC-17203

SUBMITTED BY:

NAME: Huzaifa Ahmed

REG NO.: 20175151
GROUP: ECE-2
B. TECH: 7TH SEMESTER(2020-21)

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING MOTILAL

NEHRUNATIONALINSTITUTE OF TECHNOLOGY

ALLAHABAD-211004
 Index:

Exp. Experiment Exp. Sub. Remarks

No. Date Date

1 To design and simulate CMOS Inverter 2/9/20

2 To design and simulate XOR Gate 2/9/20 9/9/20
3 To design and simulate NAND & NOR 9/9/20 16/9/20
4 To design and simulate NAND gate using 16/9/20 23/9/20
Pseudo NMOS logic.
5 To design and simulate The ring oscillator 23/9/20 30/9/20
6 To design and simulate 6T RAM 30/9/20 7/10/120
7 To design and simulate 2x1 MUX 7/10/120 4/11/20
8 To design and simulate D-flip flop as Master- 4/11/20 11/11/20
slave Configuration
9 To design and simulate CS Amplifier and 11/11/20 18/11/20
Calculate Trans conductance
10 To design and simulate Current Mirror 18/11/20 25/11/20
11 To design and simulate Differential 25/11/20 2/12/20
Date:24/08/2020 AdvancedVLSIDesignLab
(EC17203)EXPERIMENTNO.1

AIM: To design and simulate CMOS inverter using SymicaDE tool.

Tools and Apparatus used: Symica 3.1.0.0209

THEORY: The inverter is universally accepted as the most basic logic gate doing
a Boolean operation on a single input variable. Image 1 depicts the symbol, truth
table and a general structure of a CMOS inverter. As shown, the simple
structure consists of a combination of an pMOS transistor at the top and a
nMOS transistor at the bottom. CMOS is also sometimes referred to as
complementary-symmetry metal–oxide–semiconductor. The words
"complementary-symmetry" refer to the fact that the typical digital design
style with CMOS uses complementary and symmetrical pairs of p-type and n-
type metal oxide semiconductor field effect transistors (MOSFETs) for logic
functions. Two important characteristics of CMOS devices are high noise
immunity and low static power consumption. Significant power is only drawn while
the transistors in the CMOS device are switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms
of logic, for example transistor-transistor logic (TTL) or NMOS logic, which
uses all n-channel devices without p-channel devices.

Image 1: CMOS Inverter Circuit

Image 2: Voltage vs Time graph of Ideal CMOS Inverter

Truth Table of CMOS inverter:

Table1.1

Design and simulation:

CIRCUIT DIAGRAM:
Design Parameters:
NMOS(L= 180nm, W=360nm) VDD = 1.8V
PMOS(L=180nm,W=720) CMOS technology: PTM 130nm

Image 3: CMOS inverter circuit has been successfully designed using SymicaDE

tool.

OBSERVATIONS:

INPUT SIGNAL PULSE-

V1= 1.8 V, V2= 0V
Period= 100nsec, Pulse Width=50nsec

Transient Analysis:
Delay Time Calculated: 6.02111e-009
 Image 4: Transient Analysis Input and Output

DC Analysis:

Image 5: DC analysis Output

RESULT:
• CMOS inverter circuit has been successfully designed using SymicaDE tool.
• Transient and DC analysis performed also delay time is also calculated.
Date: 2/08/2020

Advanced VLSI Design Lab (EC17203)

Experiment No. 2
Aim: To design and simulate XOR gate using Symica DE tool.

Tool & Apparatus Used: Symica DE3.1.0.0209

Theory:

XOR gate is a digital logic gate that gives a true (1 or HIGH) output when the number of true
inputs is odd. An XOR gate implements an exclusive or; that is, a true output results if one, and
only one, of the inputs to the gate is true. If both inputs are false (0 or LOW) or both are true, a
false output results. XOR represents the inequality function, i.e., the output is true if the inputs
are not alike otherwise the output is false.

Fig.2.1 Circuit diagram of XOR gate using CMOS

A B Y= A ⊕ B
0 0 0
0 1 1
1 0 1
1 1 0
Table 2.1 Truth Table of CMOS Inverter
Design and Simulation:

Figure 2.2 Schematic of connections of CMOS XOR-gate.

Figure 2.3 implementation of cmos XOR gate.

 Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal (Pulse) V1=1.8V, V2=0, Time
Period=100ns, Pulse Width=50ns
Table 2.2 Design specifications of CMOS Inverter

Observation:
INPUT SIGNAL PULSE-
V1= 1.8 V, V2= 0V
Period= 100nsec, Pulse Width=50nsec

Transient Analysis:
Delay Time Calculated: 5.03111e-009

Figure 2.4 Transient result of CMOS Inverter output

Result:

• XOR-gate circuit has been successfully designed using SymicaDE tool.

• Transient and DC analysis performed also delay time is also calculated.
Date: 08/09/2020

Advanced VLSI Design Lab (EC17203)

Experiment No. 3
Aim: To design and Simulate NAND and NOR gates using SymicaDE Tool .

Tool & Apparatus Used: SymicaDE 3.1.0.0209

Theory:

NAND: In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an
output which is false only if all its inputs are true; thus its output is complement to that of an
AND gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any input
is LOW (0), a HIGH (1) output results. A NAND gate is made using transistors and junction
diodes. By De Morgan's theorem, a two-input NAND gate's logic may be expressed as
AB=A+B, making a NAND gate equivalent to inverters followed by an OR gate.

NOR: The NOR gate is a digital logic gate that implements logical NOR - it behaves according
to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW
(0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation
of the OR operator. It can also in some senses be seen as the inverse of an AND gate. NOR is a
functionally complete operation—NOR gates can be combined to generate any other logical
function. It shares this property with the NAND gate. By contrast, the OR operator is monotonic
as it can only change LOW to HIGH but not vice versa.

Vin T1 T2 Vout
0 Off On 1
1 Off Off 0

Fig.3.1 Circuit diagram of CMOS Inverter Table 3.1 Truth Table of CMOS Inverter
 A B A NOR B A B A NAND B
0 0 1 0 0 1
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0

Table 3.2 Truth Table of NOR gate Table 3.3 Truth Table of NAND gate

Design and Simulation:

Table 3.4 Design specifications of CMOS Inverter

Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal (Pulse) V1=1.8V, V2=0, Time
Period=100ns, Pulse Width=50ns

Figure 3.2 Schematic of NAND gate

 Figure 3.3 Schematic of NOR gate

Observation:
INPUT SIGNAL PULSE-

V1= 1.8 V, V2= 0V

For A Period= 100nsec, Pulse Width=50nsec For B Period= 200nsec, Pulse Width=100nsec

Figure 3.4 Transient result of NAND gate output

Simulated propagation delay for NAND:

Delay Time Calculated: 5.6241e-008

Figure 3.5 Transient result of NOR GATE output

Simulated propagation delay for NOR gate:

Delay Time Calculated: 8.22571e-011

Result:

• NAND and NOR gates circuit has been successfully designed using SymicaDE tool.
• Transient analysis performed also delay time is also calculated.
Date: 16/08/2020

Advanced VLSI Design Lab (EC17203)

Experiment No. 4
Aim: To design and simulate NAND gate using Pseudo NMOS logic.

Tool & Apparatus Used: Symica DE3.1.0.0209

Theory:

A NAND gate (NOT-AND) is a logic gate which produces an output which is false only if all its inputs
are true; thus its output is complement to that of an AND gate. A NAND gate is made using
transistors and junction diodes. The NAND gate is significant because any Boolean function can be
implemented by using a combination of NAND gates. This property is called functional
completeness. It shares this property with the NOR gate. Digital systems employing certain logic
circuits take advantage of NAND's functional completeness.

Fig.4.1 Circuit diagram of CMOS inverter

A B Y= A ⊕ B
0 0 0
0 1 1
1 0 1
1 1 0

Table 4.1 Truth Table of CMOS Inverter

 A B A NAND B
0 0 1
0 1 1
1 0 1
1 1 0

Table 4.2 Truth Table of NAND gate

Design and Simulation:

Figure 4.2 Schematic of connections of pseudo NMOS logic NAND-gate.

Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal (Pulse) V1=1.8V, V2=0, Time
Period=100ns, Pulse Width=50ns
Table 4.3 Design specifications of CMOS Inverter
Observation:
INPUT SIGNAL PULSE-
V1= 1.8 V, V2= 0V
Period= 100nsec, Pulse Width=50nsec

Transient Analysis:
Delay Time Calculated: 5.03111e-011

Figure 4.3 Transient result of NAND-gate output

Result:

 NAND-gate circuit has been successfully designed using SymicaDE tool.

 Transient analysis is performed also delay time is also calculated.
Date:23/09/2020
AdvancedVLSIDesignLab(EC17203)
EXPERIMENT NO. 5

AIM: To design and Simulate The Ring Oscillator using SymicaDETool .

Tools and Apparatus used: Symica 3.1.0.0209

THEORY:
A ring oscillator is a device composed of an odd number of NOT gates in a ring, whose output
oscillates between two voltage levels, representing true and false. The NOT gates, or inverters, are
attached in a chain and the output of the last inverter is fed back into the first.

The main statement of the oscillator is that the oscillation is achieved through positive feedback
which generates the output signal without input signal

Fig.5.1 Circuit diagram of Ring Oscillator Fig.5.2: CMOS Inverter Circuit

Truth Table of CMOS inverter:

Vin T1 T2 Vout

0 off on 1

1 off off 0

Table5.1
Design and simulation:
CIRCUIT DIAGRAM:
Design Parameters:
NMOS(L= 180nm, W=360nm) VDD = 1.8V
PMOS(L=180nm,W=720) CMOS technology: PTM 130nm

Fig5.3: Ring oscillator circuit has been successfully designed using SymicaDE tool.

OBSERVATIONS:

INPUT SIGNAL PULSE-

V1= 1.8 V, V2= 0V Period= 100nsec

Transient Analysis:

Fig 5.4: Transient Analysis Input and Output

 From Simulation From Calculation

Propagation delay(from input 42.5 ns 36.12(=2*3*6.02) ns

to output)
Frequency of output 24.5 MHz 27.6 MHz
signal(=1/prop.delay)
Table 5.2 Simulated vs calculated results

RESULT:

• Ring oscillator circuit has been successfully designed using SymicaDE tool.
• Transient analysis performed also delay time is also calculated.
Date: 30/09/2020

AdvancedVLSIDesignLab(EC17203)
EXPERIMENT NO. 6

Aim: To design and Simulate 6-T SRAM using SymicaDETool .

Tool & Apparatus Used: SymicaDE

Theory: The structure of a 6 transistor SRAM cell, storing one bit of information, can be seen in
Figure 6.1 below. The core of the cell is formed by two CMOS inverters, where the output
potential of each inverter is fed as input into the other. . This feedback loop stabilizes the
inverters to their respective state.

CMOS devices have been scaled down in order to achieve higher speed, performance and lower
power consumption. SRAM means Static Random Access Memory. The SRAM cell that we
considered in this paper was 6T SRAM cell which consists of two crossly coupled inverters and
access transistors to read and write the data. In case of the SRAM cell the memory built is being
stored around the two cross coupled inverters. If we consider that, the input to the first inverter is
logic 1 then the output of this inverter will be logic 0. So, after one cycle the output of second
inverter will be logic 1.

Fig.6.1 Circuit diagram of 6T SRAM standard cell

Design and Simulation:

Fig.6.2 Schematic of 6T SRAM standard cell (for READ cycles)

Fig.6.3 Schematic of 6T SRAM standard cell (for WRITE cycles)

 Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V

Table 6.1 Design specifications used in the design

Observation:

Fig. 6.4 Transient simulation result of 6T SRAM standard cell (for READ cycles)
 Fig. 6.5 Transient simulation result of 6T SRAM standard cell (for WRITE cycles)

Result:

• The 6T (having 6 transistors per bit) SRAM standard cell (1 bit) has been successfully
designed using SymicaDE tool.
• Its transient simulation has been performed and the corresponding waveforms have been
obtained using SymSpice tool and SymProbe tool.
Date: 07/10/2020

Advanced VLSI Design Lab (EC17203)

Experiment No. 7
Aim: To design and Simulate 2x1 MUX using SymicaDE Tool .

Tool & Apparatus Used: SymicaDE 3.1.0.0209

Theory:

AND GATE: The AND gate is a basic digital logic gate that implements logical conjunction - it
behaves according to the truth table to the right. A HIGH output (1) results only if all the inputs
to the AND gate are HIGH (1). If none or not all inputs to the AND gate are HIGH, LOW output
results. The function can be extended to any number of inputs.

OR GATE: The OR gate is a digital logic gate that implements logical disjunction – it behaves
according to the adjacent truth table. A HIGH output (1) results if one or both the inputs to the
gate are HIGH (1). If neither input is high, a LOW output (0) results. In another sense, the
function of OR effectively finds the maximum between two binary digits, just as the
complementary AND function finds the minimum.

2X1 MUX: The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit
designed to switch one of several input lines through to a single common output line by the
application of a control signal. A 2-to-1 multiplexer consists of two inputs I0 and I1, one select
input S and one output Y. Depends on the select signal, the output is connected to either of the
inputs. Since there are two input signals only two ways are possible to connect the inputs to the
outputs, so one select is needed to do these operations.

A B A OR B A B A AND B
0 0 0 0 0 0
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1

Table 7.1 Truth Table of OR gate Table 7.2 Truth Table of AND gate
Design and Simulation:

Table 7.3 Design specifications of CMOS Inverter

Parameters Values
CMOS Technology PTM 130nm
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal (Pulse) V1=1.8V, V2=0, Time
Period=100ns, Pulse Width=50ns

Figure 7.1 Schematic of AND gate(by connecting an inverter to NAND)

Figure 7.2 Schematic of OR gate(by connecting an inverter to NOR)

FIG7.3 Schematic of 2x1 MUX using AND OR gates and inverter

FIG 7.4 Simulation of 2x1 MUX

Observation:
INPUT SIGNAL PULSE-

V1= 1.8 V, V2= 0V

For Period= 100nsec, Pulse Width=50nsec

Figure 1.3 Transient result of 2x1 MUX output

Result:

• 2X1 MUX circuit has been successfully designed using SymicaDE tool.
• Transient analysis is performed for the designed 2X1 MUX.
Date: 4/11/20

Advanced VLSI Design Lab (EC17203)

EXPERIMENT NO. 8
Aim: To design and simulate D-Flip Flop as master-slave configuration.

Tools used: SymicaDE 3.1.0.0209

Theory: A flip-flop is a device where output remains either low or high. The high state
is 1 called, SET state and Low state is 0 called, RESET state. The D-type flip-flop is a
modified Set-Reset flip-flop with the addition of an inverter to prevent the S and R
inputs from being at the same logic level. A Master Slave flip flop is the cascaded
combination of two flip-flops among which the first is designated as master flip-flop
while the next is called slave flip-flop. Those two flip-flops can be J-K, S-R or D flip-
flop. The master-slave configuration has the advantage of being edge-triggered,
making it easier to use in larger circuits, since the inputs to a flip-flop often depend on
the state of its output. The circuit consists of two D flip-flops connected together.
When the clock is high, the D input is stored in the first latch, but the second latch
cannot change state. When the clock is low, the first latch's output is stored in the
second latch, but the first latch cannot change state.

clk D Q Q’
0 0 Q Q’
0 1 Q Q’
1 0 0 1
1 1 1 0

Fig.8.1 Circuit diagram of Master Slave D-FF Table 8.1 Truth Table of D-FF
Circuit Diagram:

Figure 8.2 Schematic of D Flip-Flop

Figure 8.3 Schematic of Master Slave Configuration

Observation:

Figure 8.4 Output waveform of D-FF Master Slave

S. No. Parameters Value

1 CMOS Technology PTM 130nm
4 VDD 1.8V
5 Input Pulse V1 = 1.8V, V2 = 0V, per=200n, pw=60n
2 NMOS (W/L) 360nm/180nm
3 PMOS (W/L) 720nm/180nm

Table 8.2: Design specifications of CMOS Inverter:

Result:
• Master Slave configuration of D Flip-Flop has been successfully designed
using SymicaDE tool.
• The transient analysis was also obtained for the same
Date: 11/11/20

Advanced VLSI Design Lab (EC17203)

EXPERIMENT NO. 9
Aim: To design and simulate CS Amplifier with active and passive load and find the
transconductance.

Tools used: SymicaDE 3.1.0.0209

Theory:
In electronics , a common-source amplifier is one of three basic single-stage field-
effect transistor (FET) amplifier topologies , typically used as a voltage or trans-
conductance amplifier. The input being a voltage between the gate and ground, and
the output being a voltage between the drain and ground. A MOSFET can operate as
a resistor if its gate and drain terminals are shorted. In CMOS technology it is difficult
to fabricate resistors with tightly controlled values of physical size. Hence the load
resistor RD is replaced by the MOS transistor. In circuit design, an active load is a circuit
component made up of active devices, such as transistors, intended to present a high
small-signal impedance yet not requiring a large DC voltage drop, as would occur if a
large resistor were used instead. CS stage with resistive load con- verts the changes
in overdrive voltage, to a small signal drain current, which then passes through load
resistor, R d to produce an output voltage,
Here the gain of the amplifier is given by replacing the RD with the corresponding load
resistance of NMOS and PMOS diode connected loads.
For PMOS diode connected load,
An = - gm1

a) b)
Fig.9.1 Circuit diagram of CS amplifier with a)PMOS active load and b)resistive load
Circuit Diagram:

Figure 9.2 Schematic of CS amplifier with active load

Figure 9.3 Schematic of CS amplifier with resistive load.

Observation:

Figure 9.4 transient analysis of CS amplifier with resistive load.

Figure 9.5DC analysis of CS amplifier with resistive load

 Figure 9.6 DC analysis of CS amplifier with active load

CS amplifier With resistive load With active load

Transconductance(amp/v) 1.6m 399.4µ
Gain(v) -3 -5.9
Table9.1: observation

S. No. Parameters Value

1 CMOS Technology PTM 130nm
4 VDD 1.8V
5 Input Pulse V1 = .9V, V2 = 0V, per=500n, pw=60n
2 NMOS (W/L) 200nm/180nm
3 PMOS (W/L) 200nm/180nm

Table 9.2: Design specifications of CMOS Inverter:

Result:
• CS amplifier with active and resistive load were designed successfully and
simulated using symica DE.
• The transient analysis and DC analysis was also obtained for the same
Date: 18/11/20

Advanced VLSI Design Lab (EC17203)

EXPERIMENT NO. 10
Aim: To design and simulate Current Mirror for resistive and active load.

Tools used: SymicaDE 3.1.0.0209

Theory:
A current mirror is a circuit designed to copy a current through one active device by
controlling the current in another active device of a circuit, keeping the output current
constant regardless of loading. The current being "copied" can be, and sometimes is, a varying
signal current. Conceptually, an ideal current mirror is simply an ideal inverting current
amplifier that reverses the current direction as well. The current mirror is used to provide bias
currents and active loads to circuits. It can also be used to model a more
realistic current source. MOSFET device function like this, the drain current reflects the
function of the gate to source and drain to gate voltage. Due to this, the input current in
the MOSFET M1, is mirrored to the drain current, if the gate to source voltage of two
identical MOSFETs are equal then the drain current flowing through them is equal.

a) b)
Fig.10.1 Circuit diagram of current mirror with a) active load and b) resistive load
Circuit Diagram:

Figure 10.2 Schematic of Current mirror with resistive load.

Figure 10.3 Schematic of Current mirror with active load

Observation:

Figure 10.4 DC analysis of Current mirror with resistive load w.r.t current source

Figure 10.5 DC analysis of Current mirror with active load w.r.t voltage source
 Table 10.1: Design specifications of CMOS Inverter:
S. No. Parameters Value
1 CMOS Technology PTM 130nm
4 VDD 1.8V
5 Idc I = 100µ amperes
2 NMOS (W/L) 200nm/180nm ,400nm/180nm
3 PMOS (W/L) 200nm/180nm ,400nm/180nm

Result:
• Current mirror with active and resistive load were designed successfully and
simulated using symica DE.
• The DC analysis was also obtained for the same
• For active load the output and input currents are superimposed and for
resistive load with dc source output current saturates to a value near to input
current
Date:25/11/20
Advanced VLSI Design Lab (EC17203)

EXPERIMENT NO. 11

Aim: To design and simulate Differential Amplifier using Symica DE.

Tools used: SymicaDE 3.1.0.0209

Theory:
A differential amplifier is designed to give the difference between two input signals.
When a differential amplifier is driven at one of the inputs, the output appears at both
the collector outputs. Such a circuit is very useful in instrumentation systems.
Differential amplifiers have high common mode rejection ratio (CMRR) and high input
impedance.

Fig.11.1 Circuit diagram of Differential Amplifier

Table 11.1: Design specifications of CMOS Inverter:

S. No. Parameters Value

1. CMOS Technology PTM 130nm
2. VDC 1.8V
3. Differential nputs Idc=1mA, va=0.45V, freq=500MHz, r=1K
4. NMOS (W/L) 2000nm/180nm
5. PMOS (W/L) 2000nm/180nm
Circuit Diagram:

Fig 11.2 Schematic of Differential Amplifier

Observation:

Fig 11.3 Transient response of Differential Amplifier

 Fig 11.4 DC analysis of Differential Amplifier

Result:
• The schematic of Differential Amplifier was designed successfully
• It’s transient and DC analysis was obtained using Symica DE