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Experiment 3 PDF

This document describes an experiment to design and simulate CMOS NAND and NOR gates using the SymicaDE tool. It provides the theory of operation for NAND and NOR gates. The CMOS NAND and NOR circuits were successfully designed and their outputs were simulated. The delay times for the NAND gate was 3.20349e-009 seconds and for the NOR gate was 1.0008e-008 seconds. The experiment aimed to design and simulate the basic logic gates using a circuit design and simulation tool.

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951 views

Experiment 3 PDF

This document describes an experiment to design and simulate CMOS NAND and NOR gates using the SymicaDE tool. It provides the theory of operation for NAND and NOR gates. The CMOS NAND and NOR circuits were successfully designed and their outputs were simulated. The delay times for the NAND gate was 3.20349e-009 seconds and for the NOR gate was 1.0008e-008 seconds. The experiment aimed to design and simulate the basic logic gates using a circuit design and simulation tool.

Uploaded by

Vmosa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Date: 09/09/2020

EXPERIMENT NO. 3

AIM: To design and simulate CMOS NAND and NOR using SymicaDE tool.
TOOLS USED: SymicaDE
THEORY: NAND GATE- It consists of two series NMOS transistors between Y and Ground
and two parallel PMOS transistors between Y and VDD.If either input A or B is logic 0, at least
one of the NMOS transistors will be OFF, breaking the path from Y to Ground. But at least one
of the pMOS transistors will be ON, creating a path from Y to VDD.Hence, the output Y will be
high. If both inputs are high, both of the nMOS transistors will be ON and both of the pMOS
transistors will be OFF. Hence, the output will be logic low.

NOR GATE: A 2-input NOR gate is shown in the figure below. The NMOS transistors are in
parallel to pull the output low when either input is high. The PMOS transistors are in series to
pull the output high when both inputs are low, as given in below table. The output is never left
floating.

figure 3.1: CMOS NAND Circuit figure 3.2: CMOS NOR Circuit

A B A NOR B

0 0 0

0 1 0

1 0 0

1 1 1
CIRCUIT DIAGRAM:

figure 3.3: CMOS NAND circuit has been successfully designed using SymicaDE tool.

figure 3.4: CMOS NOR circuit has been successfully designed using SymicaDE tool.
Parameters Values
CMOS PTM 130nm
Technology
NMOS: W/L 360nm/180nm
PMOS: W/L 720nm/180nm
VDD 1.8V
Input signal V1=1.8V, V2=0, Time Period=100ns,
(Pulse) Pulse Width=50ns
A
Input signal V1=1.8V, V2=0, Time Period=20ns,
(Pulse) Pulse Width=100ns
B

Table 3.3:specifications of CMOS Inverter

OBSERVATIONS:
NAND
Simulated Delay Time: 3.20349e-009

figure 3.5: Output of NAND gate


NOR:
Simulated Delay Time: 1.0008e-008

figure 3.6: Output of NOR Gate

RESULT:
• CMOS NAND and NOR circuits have been successfully designed using SymicaDE tool.
• Delay time is also calculated for both.

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