12/19/2018 How does one learn AMBA bus protocols the best and easiest way?

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AMBA Communication Protocols VLSI System Design Digital Logic Design ASIC Verification Related Questions

System-on-Chip (SoC) ARM (architecture)

Is there any good book or website to learn AMBA
AXI protocol in details from scratch?
How does one learn AMBA bus protocols the best
and easiest way? What are ARM's APB, AHB, AXI, AHB-Lite, and
AXI-Lite protocols? Is there anything else I'm
2 Answers missing in AMBA (especially AMBA4)?

How does one learn common Bus and IO

Ramdas Mozhikunnath, Experienced microprocessor Verification Engineer - protocols used in SOC designs? What is the
x86, POWER, ARM approach to be followed?
Answered Nov 25 2016 · Author has 985 answers and 2m answer views
What is the AMBA and AHB bus in ARM?
The Advanced Micro controller Bus Architecture (AMBA) specification defines
Which I/O protocol (like USB, PCIe, or SATA) is
an onchip communications standard for building high performance SOC
currently the best to learn for SOC verification?
designs. These designs typically have one or more microcontrollers or
What is the difference between an AMBA AHB,
microprocessors along with several other components - memory, DSP, DMA,
AXI, or APB and peripheral buses like I2C, SPI,
and other peripherals like USB, UART, PCIE et etc and - having a standard etc., if both are on chip interconnects?

communications to build was the motivation. What is the operation of AMBA AHB so as to
implement it using Verilog?
1. Following diagram (Ref: AMBA spec) illustrates a typical AMBA based
In AMBA Protocol AXI, how do you connect
SOC that uses AHB/ASB for high bandwidth shared bus interconnect multiple masters with a slave device?
and an APB low bandwidth peripheral interconnects
What is the best way to learn arm architecture?
How can I understand the basics of any processor
and arm?

Why is the protocol needed in Soc?

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1. The second and 3rd diagrams (Reference: Google Images ) illustrates

the later AXI interconnect which is a point to point interconnect that
evolved in AMBA 4 specification for connecting more devices avoiding
shared bus limitations with AHB.

a. You can see that the processor is connected on an AXI interface to an

interconnect matrix that supports multiple slaves and this can be
used to connect a large number of components on chip in an
efficient manner. The peripherals on APB can still talk to the AXI
interconnect using a AXI2APB bridge.

b. The third diagram show a typical NOC (Network on Chip) that is

used in SOC designs having multiple masters needing to
communicate to multiple slaves.

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Now that hopefully you understand where these protocols fit in - here are few
basics and references to resources that you can use to learn more about each of
the protocol.

The first source to read would be AMBA details on wikipedia that talks about
how the protocols evolved from its introduction in 1996 till the latest revision 5
of AMBA protocols.

Following are the main AMBA protocols and all of them has a specification that
can be downloaded from the ARM website free by signing up.

1. APB : The Advanced Peripheral Bus (APB) is used for to connect to low
bandwidth peripherals. It is a simple non-pipelined protocol that can be
used to communicate from a bridge/master to a number of slaves
through the shared bus. The latest spec (APB 2.0) is available on ARM
website here .

2. AHB: The Advanced High-performance Bus (AHB) is used to connect

components that need higher bandwidth. These could be a internal
memory or an external memory interface, DMA etc. Similar to APB, this
is a shared bus but this supports higher bandwidth through burst data
transfers. The latest spec can be found on ARM website here

a. There is also a simplified version AHB-lite protocol which supports

only a single master design and that removes need for any
arbitration, retry, split transactions etc.

3. AXI: The Advanced Extensible interface (AXI) is useful for high

bandwidth and low latency interconnects. This is a point to point
interconnect unlike a shared bus and supports multiple outstanding
data transfers (pipelined), burst transfers, separate read and write
paths.
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a. AXI-lite
What is your protocol is a simplified version of AXI and the differenceAsk
question? is
that there is no support for burst data transfers.

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b. AXI-stream protocol
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questions, people, flavour of the AXI protocol that
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supports only streaming of data from a master to a slave. There is no
separate read/write in the stream protocol unlike a full AXI or AXI-
lite. Multiple streams of data can be transferred (even with
interleaving) across a mater and slave

c. The full AXI and AXI-lite specification can be downloaded on ARM

website here

d. The AXI-stream protocol has a different spec and is available here for
download.

4. ACE - AXI Coherence extension protocol is an extension to AXI4

protocol and evolved in the era of multiple cores along with coherent
caches were being integrated on a single chip. The ACE protocol
extends the AXI read and write data channels by introducing separate
snoop address, snoop data and snoop response channels. If you are new
to coherency, I think understanding that will be a pre-requisite before
learning ACE protocol. The spec is available for download from ARM
here as part of AXI4 spec

5. CHI - Coherent Hub Interface - The ACE protocol was developed as an

extension to AXI to support coherent interconnects. ACE uses signal
level communication between master/slave and interconnects needing
large number of wires with added channels. The ACE protocol works
well for small coherent clusters like the mobile systems. With
increasing coherent clusters on SOC (especially with more server class
SOC designs) CHI protocol was introduced in AMBA 5 as a complete re-
design of the ACE protocol. The CHI protocol uses a packet based
message (instead of signalling as in AXI/ACE) and implements
protocol/link/physical layer based communication, supports QoS based
flow control and retry mechanisms. I think CHI protocol spec is still not
freely available anywhere.

Hope this gives an overview. Now coming back to the learning part, I think best
is to read the specifications to understand the details of each protocol. The APB
and AHB are relatively easy and can be learned easily. AXI and ACE/CHI are
relatively complex and will need detailed reading along with other basics on
coherency.

If you are not actively working on any of these on any projects, but do have time,
you can develop a IP/VIP for a master or slave or both for any of these protocols,
simulate and understand the details in depth.

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What are ARM's APB, AHB, AXI, AHB-Lite, and AXI-Lite protocols? Is there anything else
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AMBA4)? Ask New Question Sign In

How does one learn common Bus and IO protocols used in SOC designs? What is the
approach to be followed?

What is the AMBA and AHB bus in ARM?

Which I/O protocol (like USB, PCIe, or SATA) is currently the best to learn for SOC
verification?

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Bhaskar Kakani, Working on several bus protocols for 9+ years

Answered Mar 25 2017 · Author has 135 answers and 242.2k answer views

To add to Ramdas answer,

1. First try to understand the role of particular Bus or IO protocol in SoC,

you can get that top level picture by watching some good videos on
youtube or reading some online blogs by SoC engineers.

2. Select a protocol which is the smallest and gradually move to bit more
complex protocols. For example it’s better you learn APB first then AHB
and finally AXI.

3. Before you start digging into protocol specification, have a quick glance
over presentations/lectures available on that particular protocol.

4. Once you are having basic overview of protocol, you can read
specification in detail.

5. And finally try to understand the use cases of the protocol in various
SoC’s.

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