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Conference Program Exhibition Guide: The Premier Conference For Design & Verification

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Conference Program Exhibition Guide: The Premier Conference For Design & Verification

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2017 TM

UNITED STATES

conference
program
- and -
exhibition
guide

The Premier Conference for Design & Verification

February 27 - March 2, 2017 • San Jose, California
Verification Continuum Platform

Virtualizer ZeBu
Verdi

VC
Formal

SpyGlass

Platform VCS
Architect
HAPS

VIP

VERIFICATION CONTINUUM

Debug, Planning & Coverage

• Fastest Engines
• Native Integrations
Virtual
Prototyping
Static
& Formal
Simulation Emulation Prototyping
• Uniﬁed Compile with VCS
• Uniﬁed Debug with Verdi
VIP, Models & Databases

Visit Synopsys at Booth #101

table of
contents

General Chair’s Welcome ..............................4 Wednesday Agenda .....................................25

General Information ...........................................6 Panel ...................................................................26

Voting Instructions ..............................................7 Sessions: 8 - 9 ....................................................27

Steering Committee ............................................8 Session 10: ........................................................28

Technical Program Committee..........................9 Sponsored Luncheon .......................................28

Conference Sponsor .........................................10 Panel ...................................................................29

Accellera Technical Excellence Award ............10 Session: 11 .........................................................29

Sessions: 12 - 13 ...............................................30

Monday Agenda ...........................................12 Best Paper & Poster Award .............................30

Tutorial Overview ..............................................13

Tutorial: 1 ..........................................................14 Thursday Agenda .........................................32

Tutorial: 2 ..........................................................15 Tutorial: 5 ..........................................................34

Tutorial: 3 ..........................................................16 Tutorial: 6 ..........................................................35

Tuesday Agenda ...........................................18 Tutorial: 7 ...........................................................36

Opening Session: .............................................19 Tutorial: 8 ...........................................................37

Sessions: 1 - 2 ....................................................19 Tutorial: 9 ..........................................................38

Session: 3 ..........................................................20

Session 4: Poster Session.................................20 DVCon Expo ...................................................40

Special Session: ................................................21 Exhibitor Listing.................................................42

Keynote Address ...............................................23 Exhibiting Companies .......................................44

Session: 5 ...........................................................23

Session: 6 - 7 ......................................................24
welcome
to dvcon

Dennis Brophy
General Chair -Mentor Graphics Corp

Welcome to DVCon U.S. 2017! It is hard to believe, but for that have culled the paper submissions to create this great,
almost 30 years, 29 to be precise, we have been gathering comprehensive program. We offer a balance to the technical
to explore advances in language-based design automation sessions with training, tutorials, poster sessions, panels and
methodologies and electronic system verification techniques. more. DVCon starts with Monday “Accellera Day” tutorials.
We trust you will get a lot out of the 29th DVCon that you can Accellera working groups use the Monday tutorials to highlight
apply to your daily design and verification activities. current and emerging standards from Accellera and their
The DVCon format is uniquely focused on the needs of application that you can use or plan to use shortly. DVCon
electronic design and verification teams and to those in the concludes on Thursday with a day of in-depth industry
electronic systems design automation industry who are focused sponsored tutorials. My thanks to Tutorial Chair, Aparna Dey,
on algorithmic advances, tool development and application for bringing this all together in conjunction with the Accellera
of standards. This conference is more than just a conference, Promotions Committee. Srivastava Vasudevan is the Poster
it is a community gathering that acts as an annual milestone Chair. I have always found conference poster sessions to be
in technology evolution and a means by which we can share a great way to hold a one-on-one conversation with a poster
best practices with each other and set the next technology presenter and the DVCon poster sessions are ready to delight
goalposts as we are challenged by ever increasing design you this year. Srivastava has a good lineup for the poster
complexity. session that will engage you. Vanessa Cooper is the Panel Chair
where she has put in place panels that will feature some back-
Accellera Systems Initiative hosts the conference but the and-forth discussions and debates certain to make us all think.
DVCon volunteers taking input from design and verification As always, we encourage you to get your questions ready
engineers around the world bring the conference to life. The because you are an active part of DVCon panels.
volunteers are DVCon’s life blood. As General Chair, I have
the honor and privilege to work with a dedicated team of You will find additional program elements interesting as well.
volunteers. While you enjoy DVCon, feel free to connect Keynote
with me and other conference volunteers if you would like to Anirudh Devgan, Senior Vice President and General Manager
explore an active volunteer role as well. We are always looking of the Digital & Signoff Group (DSG) and System & Verification
for additional passionate individuals to join us. Group (SVG) at Cadence is the conference keynote. Dr.
DVCon is a fixture in our industry to explore the most advanced Devgan’s keynote title is “Tomorrow’s Verification Today.”
technologies to help design and verify the most complex chips. He is going to review the latest trends which are redefining
Those collaborating with me as your General Chair include verification from IP to System-level with an increasingly
several of the past DVCon chairs, particularly Yatin Trivedi and application-specific set of demands for hardware and software
Stan Krolikoski who are full of insights and advice. I extend my development. I’m certain Dr. Devgan’s keynote will resonate
gratitude for their past service and willingness to help DVCon with all your challenges.
evolve by offering their continued counsel. If you don’t recall, Tutorials
Yatin and Stan are the last two immediate DVCon U.S. General
Chairs. They have been very involved to help make DVCon Tutorials will be on Monday and Thursday. On Monday,
a global event where local design verticals and technologies Accellera Day will have a set of tutorials and on Thursday
focused in certain geographies give each DVCon their own there will be a set of industry-sponsored tutorials. Accellera
flavor. has three half day tutorials. Monday morning starts with
one tutorial, “Creating Portable Stimulus Models with the
How do we bring DVCon to life? The Program Chair, Tom Upcoming Accellera Standard,” that will cover the emerging
Fitzpatrick, plays a pivotal role to create a compelling Portable Stimulus standard. This tutorial will help you prepare
technical program for you. He has a large team of reviewers to take advantage of this standard when it is approved by
• 4 •
Accellera. The tutorial will be delivered by Portable Stimulus an emerging standard, users are already using technology from
Working Group members so you will get the most current several companies that have helped drive the standardization
information on the status of the emerging standard. I effort. It will be great to add your voice from the floor as the
predict this emerging standard may well be one of the great panels are going to be open for audience questions too.
productivity boosters to design and verification of advanced The afternoon panel will explore the impact of SystemVerilog
systems in recent times. At the lunch break, we will have a on one’s career. Has it been good for you or has it “jinxed”
panel discussion that will give you the opportunity to interact it as the panel title says may have happened. Certainly,
with the Portable Stimulus presenters and those who are SystemVerilog has had many things emerge because of it.
working on IEEE P1800.2 (UVM) and the SystemC Design and Verification IP as a business standardized on the language has
Verification standard where you will learn about the pending flourished and we have all come to leverage it with UVM, the
IEEE approval of UVM and advances in abstraction above RTL Universal Verification Methodology. This leads me to ask, is
respectively. After lunch, tutorials on those two last topics will “jinxed” a “good” spell that has been cast on your career or
be held. something else?
The industry tutorials on Thursday bring solutions to issues in a Special Session
way that show the practical application of tools and technology.
The Big-3 EDA companies are your tutorial sponsors with topics From time-to-time DVCon will host some special sessions.
that include “Reinventing SoC Verification” from Cadence, to an This year, Harry Foster has been asked to present “Trends in
“Only Formal” answer from Mentor Graphics and “Managing Functional Verification: A 2016 Industry Study” based on the
Low Power Verification Complexity” from Synopsys. Those Wilson Research Group’s 2016 study. The findings from the
topics only scratch the surface as the afternoon industry- 2016 study provide invaluable insight into the state of today’s
sponsored sessions will cover more practical topics that I’m electronics industry.
certain you can apply to your current challenges. Exhibits and Show Floor
Technical Papers & Poster Sessions Coming together as a community is fostered by the DVCon
On Tuesday and Wednesday the conference technical sessions Expo. The bigger and better exposition will run from Monday
will be held and topics will rangefrom design verification evening to Wednesday evening. See the program for specific
language specifics, methodology application of UVM, Formal, opening and closing times. The Expo is a great place to catch
Analog/Mixed-Signal to system-level considerations with the up with commercial vendors and learn the latest in product
impact of software on the design of systems, not just hardware. developments. It is also great to connect with colleagues and
As with past years, the Technical Program Committee had exchange and share information and ideas. Join us for the
a hard task to select from so many great submissions. A DVCon U.S. 2017 “Booth Crawl” where after visiting select
conference will never have room for all papers submitted. As exhibitors you will be automatically entered for a lucky draw.
the TPC selected the best from the best, not all good papers All in all, there will be four days of learning, sharing, and
were able to make it into the conference. When we could, we industry interactions that will allow you to plan how to apply all
tried to make room in the poster sessions. There are almost this to your own design and verification environment in
twenty poster presentations scheduled for Tuesday morning. the months and years ahead. On behalf of all the volunteers
There will be awards for both best papers and best posters at and conference management staff we welcome you to
the end of the day on Wednesday. Please be sure to vote! DVCon U.S. 2017!
Panels
On Wednesday, there will be two panels. The morning panel
will be “User’s Talk Back on Portable Stimulus.” While this is General Chair, DVCon U.S. 2017
• 5 •
conference
details
Registration Hours
Location: Bayshore Foyer
Monday, February 27 .......................... 7:30am to 7:00pm Thank you to our Sponsor:
Tuesday, February 28 .......................... 7:30am to 6:00pm
Wednesday, March 1 ........................... 7:30am to 6:00pm
Thursday, March 2 ............................... 7:30am to 4:00pm

Expo Hours
Location: Bayshore Ballroom
CON
DV 2

Monday, February 27 ......... 5:00pm to 7:00pm

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Tuesday, February 1 ............................ 2:30pm to 6:00pm

Wednesday, March 2 ........................... 2:30pm to 6:00pm

Parking Instructions
Day/overnight self parking is $13.00 per day/per car with no in/out privileges.
Local attendees are to scan their parking ticket at the designated DVCon validation area (Bayshore Foyer).
The scanner will beep 3 times to notify the attendee has validated their tickets at the group discounted rate.
There are two pay stations inside the hotel. One is located near the convention entrance (Bayshore Foyer) side. This
machine accepts both cash and credit card. The second pay station is located near the guest elevators near the South
Parking Lot. This machine accepts only cash.

DVCon Tutorials & Proceedings Distribution

DVCon Conference Papers and Tutorial presenter slides will be delivered electronically online via a username
and password.
To access: http://proceedings.dvcon.org
Username = Email address
Password = Registration ID (on your badge)
Please refer to your registration receipt to access the files you are eligible to view.

Wireless Information
Enjoy free Wi-Fi at DVCon! Connect to the Conference Wi-Fi via:
Wi-Fi SSID: DVCon2017
No Password Required

Social Media At DVCon

Follow @DVCon on Twitter and get hourly conference announcements.
Also, tweet #DVCon about your experience and highlights at the conference!
Don’t miss DVCon on Facebook at facebook.com/DVCon.

• 6 •
Best Paper & Poster Voting Thank you to our sponsors:
All Access, Conference Only and One-Day only registrants are entitled to vote for
the “DVCon Best Paper and Poster” awards. The attendees are the judges!
Enjoy the convenience of voting from your PC and mobile device:
1. Go to http://vote.dvcon.org
2. Vote on the papers and posters you have attended

Awards Presentation
Wednesday, March 1 | Location: Bayshore Ballroom | 5:00pm
Join us on the Exhibit Floor for the announcement of the 2017 award recipients!

Expo Floor Plan

EMPLOYEE AREA

EXIT SERVICE CORRIDOR

905 805 705 605 505 405 305 205

1004 904 604 504 404 304

702
1002 902 602 502 402 302

1101 WOMEN MEN

101
1001 901 801 701 601 501 401 301

ENTRANCE PHONES
EXIT FOYER

REGISTRATION

UP TO
SECOND
FLOOR

• 7 •
steering
committee
General Chair Vice Chair
Dennis Brophy Ambar Sarkar, Ph.D.
Mentor Graphics Corp. eInfochips
8005 SW Boeckman Rd. 2025 Gateway Place, Suite #270,
Wilsonville, OR 97070 San Jose, CA 95110.
503-685-0893 508-292-1681
[email protected] [email protected]

Past Chair Program Chair

Yatin Trivedi Tom Fitzpatrick
Aricent, Inc. Mentor Graphics Corp.
2580, N. First Street 18 Whistle Post Ln.
San Jose, CA Groton, MA 01450
650-265-8031 978-448-8797
[email protected] [email protected]

Tutorial Co-Chair Poster Chair

Aparna Dey Srivatsa Vasudevan
Cadence Design Systems, Inc. Synopsys, Inc.
2655 Seely Ave., Bldg. 9 [email protected]
San Jose, CA, 95134
408-914-6503
[email protected]

Panel Chair Accellera Representative

Vanessa Cooper & Finance Chair
Verilab, Inc. Lynn Bannister-Garibaldi
609 Castle Ridge Rd., Ste. 210 Accellera Systems Initiative
Austin, TX 78746 8698 Elk Grove Blvd. Ste 1, #114
512-537-3136, ext. 7101 Elk Grove, CA 95624
[email protected] 916-670-1056
[email protected]

Publicity/Marketing Chair Conference Manager

Barbara Benjamin Nannette Jordan
HighPointe Communications MP Associates, Inc.
246 SE Spokane St. 1721 Boxelder St., Ste. 107
Portland, OR 97202 Louisville, CO 80027
503-209-2323 303-530-4562
[email protected] [email protected]

• 8 •
technical program
committee
Program Chair Poster Chair
Tom Fitzpatrick Srivatsa Vasudevan
Mentor Graphics Corp. Synopsys, Inc.
18 Whistle Post Ln. [email protected]
Groton, MA 01450
978-448-8797
[email protected]

Mark Azadpour Kaiming Ho Logie Ramachandran

Western Digital Corp. Independent VeriKwest Systems Inc.

Kamel Belhous Phu Huynh Josh Rensch

Teradyne, Inc. Cmma Inc. Superion Technology

Dan Benua Tor Jeremiassen Dave Rich

Cmma Inc. Texas Instruments, Inc. Mentor Graphics Corp.

Clifford Cummings Neyaz Khan Imtiyaz Ron

Sunburst Design, Inc. Cadence Design Systems, Inc. Broadcom Corp.

Stephen D’Onofrio Kelly Larson Ambar Sarkar

Paradigm Works Paradigm Works, Inc. eInfochips

Charles Dawson Kaowen Liu Erik Seligman

Cmma Inc. MediaTek, Inc. Intel Corp.

Joanne DeGroat Paul Marriott Amit Sharma

Ohio State University Verilab Synopsys, Inc.

John Dickol Don Mills Robert Troy

Samsung Austin R&D Center Microchip Technology, Inc. ON Semiconductor

Harry Foster Nagi Naganathan Greg Tumbush

Mentor Graphics Corp. Broadcom Corporation Tumbush Enterprises LLC

Manish Gajjar Karen Pieper Antonio Vaz

Light Microsemi Corp. Synopsys India Pvt. Ltd.

Ning Guo Mitchell Poplingher Srinivasan Venkataramanan

Advanced Micro Devices, Inc. Microsemi Corp. CVC Pvt., Ltd.

• 9 •
conference
sponsorS
About Accellera Systems Initiative
Accellera Systems Initiative is an • Collaborate with our community of companies, individuals,
independent, not-for profit organization and organizations to deliver standards that lower the cost of
dedicated to create, support, promote, and designing commercial IC and EDA products and embedded
TM
advance system-level design, modeling, system solutions, as well as increase the productivity of designers
and verification standards for use by the worldwide.
worldwide electronics industry. We are composed of a broad range • Encourage availability and adoption of next-generation EDA and
of members that fully support the work of our technical committee IP standards that encompass system-level, RT-level, and gate-level
to develop technology standards that are balanced, open, and design flows.
benefit the worldwide electronics industry. Leading companies
and semiconductor manufacturers around the world are using • Collaborate with the electronic design community to deliver
our electronic design automation (EDA) and intellectual property standards that increase designer productivity and lower the cost
(IP) standards in a wide range of projects in numerous application of product development.
areas to develop consumer, mobile, wireless, automotive, and • Provide mechanisms that enable the continued growth of the
other “smart” electronic devices. Through an ongoing partnership Accellera Systems Initiative user community including SystemC,
with the IEEE, standards and technical implementations developed Universal Verification Methodology (UVM), and IP-XACT.
by Accellera Systems Initiative are contributed to the IEEE for formal • Standardize technical implementations developed by Accellera
standardization and ongoing governance. Systems Initiative through the IEEE.
Our Mission
Membership
At Accellera our mission is to provide a platform in which the
Accellera members directly influence development of the most
electronics industry can collaborate to innovate and deliver global important and widely used standards in electronic design.
standards that improve design and verification productivity for Member companies protect and leverage their investment in
electronics products.
design languages through their funding of a proven, effective
The purposes of the organization include: and responsible organization. In addition, our members have a
• Provide design and verification standards required by systems, higher level of visibility in the EDA industry as active participants in
semiconductor, IP, and design tool companies to enhance a front- Accellera-sponsored activities and as contributors to its decisions,
end design automation process. which impact the EDA industry. For a full list of technical activities
that are supported by Accellera, and for information on how to join
us, please visit our website at www.accellera.org.

Accellera Systems Initiative Technical Excellence Award

Accellera wishes to recognize the outstanding achievements of its endorsed and selected by participants of the Accellera Technical
Working Group members by selecting outstanding contributors to Excellence Award Committee, which is a subcommittee of the
our standards development process as recipients of the Accellera Technical Committee.
Systems Initiative Technical Excellence Award. Past Recipients:
This annual award recognizes major contributions to the 2016: Erwin de Kock
development of Accellera standards. Examples of such 2015: Justin Refice
contributions may include leadership in standardization of new 2014: Andrew Goodrich
technologies, assuring achievement of standards development 2013: Janick Bergeron
goals, and identifying opportunities to better serve the needs of the 2012: John Aynsley
community through standards.
For more information about Accellera awards
Any member of an Accellera Working Group is eligible for the award. programs and to find out how to submit a nomination,
Candidates can be nominated by Working Group chairs and are visit accellera.org/about/awards.

Thank you to our Luncheon Sponsors

• 11 •
monday’s
agenda
8:00am - Coffee Break
11:00am Room: Gateway Foyer

9:00am - Tutorial 1
Creating Portable Stimulus Models
12:00pm with the Upcoming Accellera Standard
Room: Oak
MON DAY, F E B R UARY 2 7

Sponsored Luncheon
12:00pm - Accellera Lunch Featuring the 2017 Technical Excellence Award and
1:30pm an Update on Accellera Standards, Including a Town Hall Discussion
Room: Pine/Cedar

Tutorial 2
Introducing IEEE 1800.2 –The Next Step for UVM
2:00pm - Room: Oak

5:00pm
Tutorial 3
SystemC Design and Verification – Solidifying the Abstraction Above RTL
Room: Fir

Monday Tutorials and Luncheon Sponsored by

3:00pm - Coffee Break

4:00pm Room: Gateway Foyer

CON
DV

DVCon Expo & Booth Crawl

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Room: Bayshore Ballroom

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DVCon is doing it again! You won’t want to miss the annual DVCon Booth
Crawl on the exhibit floor.
5:00pm - Cocktails and conversations in a casual environment with the DVCon
exhibitors.
7:00pm
By attending the Booth Crawl you’ll be automatically entered into a drawing
for a $500 VISA gift card. The winner must be present to win and will be
announced Monday night.
Mingle from booth to booth while enjoying food and drinks.
Look for the flag to find a participating company!

• 12 •
tutorial
overview
Monday, February 27
Tutorial 1: Creating Portable Stimulus Models with the
Upcoming Accellera Standard ...........................................................................14

Tutorial 2: Introducing IEEE 1800.2 – The Next Step for UVM ..........................................15

MONDAY + Th ur sday t ut o ri a ls
Tutorial 3: SystemC Design and Verification – Solidifying the Abstraction Above RTL ...16

Thursday, March 2
Tutorial 4: Reinventing SoC Verification – It Is about Time ..............................................33

Tutorial 5: Stuck on a Desert Island without Simulation – Only Formal!

How Do I Verify My Rescue Drone’s RTL? .........................................................34

Tutorial 6: Practical Applications for Managing Low Power Verification

Complexity and Debug of Advanced SoCs .......................................................35

Tutorial 7: Optimizing IP Verification – Which Engine? .....................................................36

Tutorial 8: Testbench Automation : How to Create a Complex

Testbench in a Couple of Hours ........................................................................37

Tutorial 9: Formal Verification Methodology: Maximizing Productivity

and Achieving Formal Closure with Confidence .............................................38

Special Thanks to Our Tutorial Sponsors

TM
Tutorial 1 - Creating Portable Stimulus Models with the
Upcoming Accellera Standard
Time: 9:00am - 12:00pm | Room: Oak
Organizer:
Barbara Benjamin - Accellera Systems Initiative

Portability of reusable test cases has long been a Attendees will learn how to:
goal for semiconductor verification and validation
teams. No one wants to “reinvent the wheel” by • Understand and develop abstract, portable test
having to rewrite similar tests again and again. and stimulus models for their chip designs
While the widely accepted, Accellera Universal
Verification Methodology (UVM) standard, enabled • Use PSS constraints to guide randomization of
reuse of testbench components and constrained- both data and control flow to describe a legal
random tests at the IP and block level, limitations scenario space to be verified
in terms of reuse at subsystem and full-chip level,
and lack of portability across execution platforms • Target use of existing low-level sequences or
required a fresh look at addressing the portable drivers in the generation of tests
MON DAY, F E B R UARY 27

stimulus and test challenge. Accellera Systems

Initiative formed the Portable Stimulus Working • Execute generated tests across platforms from
Group (PSWG) in early 2015 to do just that. The simulation, emulation, FPGA prototype, and
group’s charter is to define a portable test and post-silicon to verify a complete chip or
stimulus standard specification to permit the multi-chip system
creation of a single representation/model, usable
by a variety of users across different levels of • Specify and gather coverage metrics at every step
integration under different configurations, enabling to assess verification completeness
the generation of different implementations
that run on a variety of execution platforms, Speakers:
including, but not limited to, simulation, emulation, David Brownell - Analog Devices, Inc.
FPGA prototyping, and post-silicon. With such a Sharon Rosenberg - Cadence Design Systems, Inc.
specification in place, EDA vendors can produce Tom Fitzpatrick - Mentor Graphics Corp.
tools that automatically generate stimulus, Adnan Hamid - Breker Verification Systems, Inc.
results checks, and coverage metrics tuned for a Srivatsa Vasudevan - Synopsys, Inc.
particular target. The first version of the Accellera Karthick Gururaj - Vayavya Labs Pvt., Ltd.
Portable Test and Stimulus Standard (PSS) is Faris Khundakjie - Intel Corp.
nearing completion. This timely tutorial presents
an introduction to the standard’s main features
leveraging a series of usage examples defined
by PSWG members that represent many of the
Thank you to our Sponsor:
common challenges faced in today’s multi-core
designs. The tutorial will show with actual coding TM

examples how the verification and portability

challenges of these examples are met using
the standard.

• 14 •
Accellera Lunch Featuring the 2017 Technical Excellence
Award and an Update on Accellera Standards, Including a
Town Hall Discussion
Thank you to our Sponsor:
Time: 12:00pm - 1:30pm | Room: Pine/Cedar TM

Organizer:
Adam Sherer - Accellera Systems Initiative

Accellera Day 2017 at DVCon will be filled with • Follow up questions from the Portable Stimulus
exciting technical insights you’ll be able to apply morning tutorial
immediately to your projects. In the middle of the • Future directions for the UVM Working Group
day we’ll take a break and gather for lunch where
we will have a presentation by Accellera that will • SystemC working groups activity including
include the 2017 Technical Excellence award, a what’s new
look forward to the worldwide DVCon events, latest Speakers:
news, and working group activities. After that, Mark Glasser - NVIDIA Corporation
we will have a town hall meeting covering Trevor Weiman - Intel Corp.

MON DAY, F E B R UARY 27

topics including: David Brownell - Analog Devices, Inc.

Tutorial 2 - Introducing IEEE 1800.2 - The Next Step for UVM

Time: 2:00pm - 5:00pm | Room: Oak
Organizer:
Adam Sherer - Accellera Systems Initiative

By all measures, UVM is the most successful review those changes, we will also examine the
verification standard ever created in the EDA impact it will have on your existing verification
community. And that’s no boast. From inception environments including how to debug and regold
to today, it has swept through project teams those environments improving your ability to share
worldwide which makes it ready for the next verification IP among globalized teams.
step with the IEEE. The IEEE 1800 committee
is completing the work on UVM as the 1800.2 Speakers:
standard. This rigorous review of the Accellera Tom Alsop - Intel Corp.
work has resulted in some changes that improve Srivatsa Vasudevan - Synopsys, Inc.
UVM as a standard for interoperability. The Mark Glasser - NVIDIA Corp.
tutorial will focus on those changes and how you Srinivasan Venkataramanan - CVC Pvt., Ltd.
can prepare for the IEEE standard today. As we Krishna Thottempudi - Qualcomm, Inc.

Thank you to our Sponsor:

• 15 •
Tutorial 3 - SystemC Design and Verification - Solidifying the
Abstraction Above RTL
Time: 2:00pm - 5:00pm | Room: Fir
Organizer:
Adam Sherer - Accellera Systems Initiative

Each year the EDA community makes critical that can be reused at RTL so we’ll discuss how to
advances in SystemC. As we do, the momentum apply the emerging UVM-SystemC standard. We’ll
toward SystemC as the primary point of entry above complete the tutorial with a Q/A session with all
RTL becomes more tantalizing. Will this be the of our presenters focusing on the remaining work
year your team makes the leap? This tutorial could they see to help you make the leap to the SystemC
answer that question for you. abstraction.
We will focus on three key components that could Speakers:
help you make that decision: design, modeling, Trevor Wieman - Intel Corp.
and testbench. We’ll start by examining the latest Peter Frey - Mentor Graphics Corp.
advances in the SystemC language including the
MON DAY, F E B R UARY 2 7

synthesizable subset and CCI configuration. A

discussion of modeling for high-performance
simulation will follow to complete our view of the
Thank you to our Sponsor:
overall design. Of course, we need to verify this
fast-running design with a testbench approach TM

• 16 •
DVCon 2017
join us in China, April 19, 2017

2017
Join us at the Parkyard Hotel
TM

china Shanghai for DVCon China

专家级的学习平台
DVCon-China.org
tuesday’s
agenda
7:30am - Coffee Break
11:00am Room: Gateway Foyer

8:15am - Opening Session

8:45am Room: Oak

9:00am - Session 1 Session 2 Session 3

UVM Stimulus Optimizing Verification Power Optimization
10:30am Room: Oak Room: Fir Room: Monterey/Carmel
t u esday, F e b r uary 28

10:30am - Special Session

Trends in Functional Verification: A 2016 Industry Study
11:00am Room: Fir

10:30am - Poster Session

12:00pm Room: Gateway Foyer

Sponsored Luncheon
12:00pm - Application Specific Verification From Edge Nodes Through Hubs, Networks
1:15pm And Servers – Are The Requirements All The Same?
Thank you to
Room: Pine/Cedar our Sponsor:

Keynote Address: Tomorrow’s Verification Today

1:30pm - Anirudh Devgan - Senior Vice President and General Manager
2:30pm of the Digital & Signoff Group (DSG) and System & Verification Group (SVG)
Room: Oak/Fir

2:30pm - Coffee Break

3:00pm Room: Gateway Foyer

2:30pm - dvcon DVCon Expo

6:00pm expo Room: Bayshore Ballroom

Session 5 Session 6 Session 7

3:00pm - UVM Register Layer Exploring Coverage Optimization
4:30pm Applications SystemVerilog Room: Monterey/Carmel
Room: Oak Room: Fir

5:00pm - DVCon Reception

6:00pm Room: Bayshore Ballroom

• 18 •
Opening Session
Time: 8:15am - 8:45am | Room: Oak
Join us as we set the stage for the 2017 DVCon Conference and Exhibition. DVCon’s Steering Committee will
highlight the conferences events.

Session 1 - UVM Stimulus

Time: 9:00am - 10:30am | Room: Oak
Session Chair:
Clifford Cummings - Sunburst Design, Inc.

tue sday, F e b r uary 2 8

How to use UVM to Generate Interesting Stimulus.

1.1 Error Injection: When Good Input Goes Bad 1.3 Keeping Your Sequences Relevant
Kurt Schwartz - Aletheia Design Services & Nicholas Zicha, Eric Combes
Willamette HDL - Accedian Networks
Tim Corcoran - Willamette HDL
1.2 A Simplified Approach Using UVM Sequence
Items for Layering Protocol Verification
Haiqian Yu, Christine Thomson
- Microsoft Corp.

Session 2 - Optimizing Verification

Time: 9:00am - 10:30am | Room: Fir
Session Chair:
Erik Seligman - Intel Corp.

Interesting Approaches to Optimizing Various

Aspects of Verification.

2.1 DPI Redux. Functionality. Speed. 2.3 New Constrained Random and Metric-

Optimization. Driven Verification Methodology
Rich Edelman, Rohit K. Jain, Hui Yin using Python
- Mentor Graphics Corp. Marek Cieplucha, Witold Pleskacz - Warsaw
Univ. of Technology
2.2 Efficient SCE-MI Usage to Accelerate TBA
Performance
Ponnambalam Lakshmanan - Analog Devices,
Inc., Prashantkumar Ravindra, Rajarathinam
Susaimanickam - Aceic Design Technologies

• 19 •
Session 3 - Power Optimization
Time: 9:00am - 10:30am | Room: Monterey/Carmel
Session Chair:
Charles Dawson - Cadence Design Systems, Inc.

Low Power Verification Applications.

3.1 Random Directed Low-Power Coverage 3.3 Automatic Investigation of Power

Methodology: A Smart Approach to Power Inefficiencies
Aware Verification Closure Kuo-Kai Hsieh - Univ. of California,
Awashesh Kumar, Madhur Bhargava - Mentor Santa Barbara
Graphics Corp. Wen Chen, Monica Farkash, Jayanta Bhadra -
3.2 Emulation Based Full Chip Level Low Power NXP Semiconductors
Validation at Pre-Silicon Stage Li-C. Wang - Univ. of California, Santa Barbara
Kyoungmin Park, Jaegeun Song, Hyundon
Kim, Seonil Brian Choi, Suk Won Kim -
Samsung Electronics Co., Ltd.
t u esday, F e b r uary 28

Session 4 - Poster Session

Time: 10:30am - 12:00pm | Room: Gateway Foyer
Session Chair:
Srivatsa Vasudevan - Synopsys, Inc.

4P.1 System Responsiveness Verification of 4P.5 Assertion based Verification for Analog
large Multi-Processor System and Mixed Signal Designs.
Configurations using Micro-Benchmarks Srinivas R. Aluri - Texas Instruments, Inc.
and a Multi-Level Analysis
4P.6 End to End Formal Verification Strategies
Ralf Winkelmann - IBM Deutschland Research
for IP Verification
& Development GmbH
Jacob R. Maas, Nirabh R. Regmi, Ashish
Edward Chencinski - IBM Corp.
Kulkarni, Krishnan Palaniswami - Microsoft
Hanno Eichelberger - IBM Deutschland
Corp.
Research & Development GmbH
Michael Fee - IBM Corp. 4P.7 Systematic Speedup Techniques for
Carsten Otte, Christoph Raisch - IBM Functional CDC Verification Closure
Deutschland Research & Development GmbH Author order is Sulabh K. Khare, Ashish Hari,
Anwesha Choudhary - Mentor Graphics (India)
4P.2 Functional Coverage of Register Access via Pvt. Ltd.
Serial Bus Interface using UVM
Darko M. Tomusilovic 4P.8 Coverage Models for Formal Verification
Xiushan Feng - Oracle Labs
4P.3 Novel Test Case Design Techniques for
Xiaolin Chen, Abhishek Muchandikar -
Logical Specifications of Safety Critical
Synopsys, Inc.
Systems Software in Aerial Vehicle
Lakshmi Kvns, Sanjeev Kumar - Advanced 4P.9 Use of Portable Stimulus to Verify Task
Systems Laboratory Dispatching Functions in an LTE Design
Adnan Hamid - Breker Verification Systems, Inc.
4P.4 A Dyadic Transformation Based
Methodology to Achieve Coverage Driven 4P.10 Debug APIs - Next Wave of Innovation in
Verification Goal DV Space
Swapnajit Mitra - Broadcom Corp. Srinivasan Venkataramanan,
Ajeetha Kumari - VerifWorks & CVC Pvt., Ltd.

• 20 •
Session 4 - Poster Session
Time: 10:30am - 12:00pm | Room: Gateway Foyer
4P.11 System Level Fault Injection Simulation 4P.16 A Novel Approach to Create Multiple
Using Simulink Domain Based DV Architecture to Address
Wai Tang, Marcelo Mizuki, Fengying Qiao, Typical Verification Challenges, for the DUT
Mitch Norcross - Melexis with Mutual Exclusive Functionalities,
Using UVM Domains
4P.12 Transparent SystemC Model Factory for
Subham Banerjee - Xilinx Inc.
Scripting Languages
Keshava Krishna Raja Sooryambail - Cisco
Rolf Meyer, Bastian Farkas, Mladen Berekovic,
Systems, Inc.
Syed Abbas Ali Shah - Technische Univ.
Braunschweig 4P.17 Automatic Debug Down to the Line of Code
Daniel Hansson, Patrik Granath - Verifyter AB
4P.13 Free Yourself from the Tyranny of Power
State Table with Incrementally Refinable 4P.18 A New Approach for Generating View
UPF Generators
Progyna Khondkar, Ping Yeung, Gabriel Johannes Schreiner, Felix Willgerodt,
Chidolue, Joe Hupcey III, Rick Koster - Mentor Wolfgang Ecker -Infineon Technologies AG &

tue sday, F e b r uary 2 8

Graphics Corp. Technische Univ. München
Madhur Bhargava - Mentor Graphics (India) Pvt. Ltd. 4P.19 Power Aware CDC Analysis at Top Level
4P.14 Increased Regression Efficiency with Using SOC Abstract Flow
Jenkins Continuous Integration Before You Pramod Rajan K S, Venkatesh Ranga - NXP
Finish Your Morning Coffee Semiconductors
Thomas Ellis - Mentor Graphics Corp.
4P.15 Mixed-Signal Verification Methodology to
Verify Type-C USB
Varun R, Vinayak Hegde,
Somasunder Kattepura Sreenath - Cadence
Design Systems, Inc.

Special Session: Trends in Functional

Verification: A 2016 Industry Study
Time: 10:30am - 11:00am | Room: Fir
Speaker
Harry Foster - Mentor Graphics Corp.

In 2002 and 2004, Collett International Research, new studies were commissioned in 2014 and 2016.
Inc. conducted its well-known ASIC/IC functional The 2014 study was a world-wide, double-blind,
verification studies, which provided invaluable functional verification study covering all electronic
insight into design and verification trends at that industry market segments. The findings from this
point in time. study were published in the proceedings of the
However, after the 2004 study, no additional Collett 2015 Design Automation Conference. The 2016
studies were conducted. Three private functional study followed the format of the 2014 study and is
verification studies were commissioned in 2007, the focus of this invited talk. The findings from the
2010, and 2012. Although the data from these 2016 functional verification study provide invaluable
studies has been referenced in various publications insight into the state of today’s electronics industry.
and blogs, these studies were never officially
published. To address this dearth of knowledge, two

• 21 •
Sponsored Luncheon - Application Specific Verification from
Edge Nodes through Hubs, Networks and Servers – Are the
Requirements all the Same?
Time: 12:00pm - 1:15pm | Room: Pine/Cedar
Moderator:
Ed Sperling - Semiconductor Engineering
Organizer:
Frank Schirrmeister - Cadence Design Systems, Inc.

With the “Internet of Things” (IoT) connecting some designs than it is in others? Are the design
billions of “things”, all of them aggregating data cycles forcing early software development and
through hubs and sending them through networks different forms of prototyping in some application
to cloud servers for big data analytics across areas more than in others? Are safety critical
different application domains, how does that design flows as important in IoT edge nodes as in
change verification of the different components automotive?
involved? Do the same flows and development
t u esday, F e b r uary 28

requirements apply to designs that enable the Panelists:

cloud, networks, hubs and edge nodes? With the IoT James Hogan - Vista Ventures
spanning across a variety of application domains, Christopher Lawless - Intel Corp.
how do those requirements play into verification? David Lacey - Hewlett Packard Enterprise
Frank Schirrmeister - Cadence Design Systems, Inc.
After an introduction of the different application
domains and how they relate to the IoT, the
panel will discuss application specific aspects for
verification of the different designs at the IP, Sub-
system, Chip and System-level. Are the key drivers Thank you to our Sponsor:
different? Is power optimization more critical in

• 22 •
Keynote: Tomorrow’s Verification Today
Time: 1:30pm - 2:30pm | Room: Oak/Fir

Speaker
Anirudh Devgan - Senior Vice President and General Manager of the Digital &
Signoff Group (DSG) and System & Verification Group (SVG)

Over the past decade, verification complexity and with Palladium®and Protium™ platforms, formal
demands on engineering teams have continued to and automated verification with
raise rapidly. However, the supporting automation JasperGold®Apps, system-level design, and system
tools and flows have been only improving verification solutions.
incrementally, resulting in a verification gap. It Prior to joining Cadence in 2012, Devgan spent
is time to redefine how verification should be seven years at Magma Design Automation as
approached to accelerate innovation in the General Manager and Corporate Vice President of
next decade. Magma’s Custom Design Business Unit, leading the
In his presentation, Dr. Devgan will review the development and introduction of several successful
latest trends which are redefining verification from products. Prior to his tenure at Magma, he spent 12

tue sday, F e b r uary 2 8

IP to System-level, with an increasingly application- years at IBM in various management and technical
specific set of demands changing the landscape for positions at the IBM Thomas J. Watson Research
hardware and software development. Center, IBM Server Division, IBM Microelectronics
Biography: Anirudh Devgan serves as the Senior Division, and IBM Austin Research Lab, where
Vice President and General Manager of the Digital he received numerous awards including the IBM
& Signoff Group (DSG) and System & Verification Outstanding Innovation Award and IBM Outstanding
Group (SVG). As the leader of DSG, he is responsible Research Accomplishment. In 2003, he was awarded
for the core digital design, implementation, and the IEEE/ACM William J. McCalla Award and in
silicon signoff business, which encompasses 2005, the ACM Design Automation Conference
logic synthesis, formal verification, test, physical Best Paper Award. He was named an IEEE Fellow in
synthesis, place and route, electrical signoff, 2006. Devgan has published more than 90 research
physical signoff, and design for manufacturing papers and holds 27 U.S. patents.
(DFM) technologies. In his role as leader of Devgan received a bachelor of technology degree
SVG, he is responsible for delivering the System in electrical engineering from the Indian Institute
Development Suite, including technologies from of Technology, Delhi, and M.S. and Ph.D. degrees in
Advanced Verification Solutions featuring the electrical and computer engineering from Carnegie
Incisive® platform, hardware system verification Mellon University.

Session 5 - UVM Register Layer Applications

Time: 3:00pm - 4:30pm | Room: Oak
Session Chair:
Stephen D’Onfrio - Paradigm Works, Inc.

Tips and Tricks for Using the UVM Register Layer.

5.1 Flexible Indirect Registers with UVM 5.3 Doing Funny Stuff with the UVM Register
Uwe Simm - Cadence Design Systems, Inc. Layer: Experiences Using Front Door
Sequences, Predictors, and Callbacks
5.2 Modeling a Hierarchical Register Scheme
John Aynsley - Doulos
with UVM
Joshua Hardy - Pensar Development

• 23 •
Session 6 - Exploring SystemVerilog
Time: 3:00pm - 4:30pm | Room: Fir
Session Chair:
Dave Rich - Mentor Graphics Corp.

Looking at Interesting Aspects of the SystemVerilog Language.

6.1 Architecting “Checker IP” for AMBA 6.3 Statically Dynamic or Dynamically
protocols Static? Exploring the Power of Classes and
Ajeetha Kumari, Srinivasan Venkataramanan Enumerations in SystemVerilog Assertions
- VerifWorks & CVC Pvt., Ltd. for Reusability and Scalability
6.2 Is the Simulator Behavior Wrong for my Sachin Scaria, Sreenu Yerabolu - Intel Corp
SystemVerilog Code? Don Mills - Microchip Technology, Inc.
Weihua Han - Synopsys, Inc.
t u esday, F e b r uary 28

Session 7 - Coverage Optimization

Time: 3:00pm - 4:30pm | Room: Monterey/Carmel
Session Chair:
Harry Foster - Mentor Graphics Corp.

Using Coverage to Optimize Verification.

7.1 Improving Constrained Random Testing by 7.2 Optimizing Random Test Constraints Using
Achieving Simulation Verification Goals Machine Learning Algorithms
through Objective Functions, Rewinding Stan Sokorac - ARM, Inc.
and Dynamic Seed Manipulation
7.3 Dynamic Regression Suite Generation
Eldon G. Nelson - Intel Corp.
Using Coverage-Based Clustering
Shahid Ikram, Jim Ellis - Cavium, Inc.

• 24 •
wednesday’s
agenda
8:00am - Coffee Break
10:00am Room: Gateway Foyer

8:30am - Panel
Users Talk Back on Portable Stimulus
9:30am Room: Oak/Fir

Session 8 Session 9 Session 10

10:00am - Virtual Platforms and Formal Verification Case AMS Verification

w e dn e sday, m ar ch 1
12:00pm High-Level Languages Studies Room: Monterey/Carmel
Room: Oak Room: Fir

2:30pm - Coffee Break

3:30pm Room: Gateway Foyer

2:30pm - dvcon DVCon Expo

6:00pm expo Room: Bayshore Ballroom

Session 11 Session 12 Session 13

3:00pm - UVM Registers at the Formal Verification Verification Reuse and
4:30pm System Level Applications Debug
Room: Oak Room: Fir Room: Monterey/Carmel

4:45pm - Best Paper & Poster Awards Presentation

5:00pm Room: Bayshore Ballroom

5:00pm - DVCon Reception

6:00pm Room: Bayshore Ballroom
• 25 •
Panel: Users Talk Back on Portable Stimulus
Time: 8:30am - 9:30am | Room: Oak/Fir
Moderator:
Adnan Hamid - Breker Verification Systems, Inc.
Organizer:
Nanette Collins - Nanette V. Collins Marketing and Public Relations

DVCon is a global event for verification engineers • Is Portable Stimulus evolving in a way that will suit
to exchange ideas, identify new solutions or their needs?
clever ways to better utilize existing tools in • How urgent is the finalization of a Portable
the design flow and, sometimes, commiserate. Stimulus standard?
One of the more exciting areas in verification is
Portable Stimulus, a standard means to specify While the format will include a panel moderated by
verification intent and behaviors reusable across user advocate Adnan Hamid of Breker Verification
target platforms. It’s real, growing in adoption and Systems, audience participation will be encouraged.
promoted by Accellera’s Portable Stimulus Working The audience should bring questions, concerns and
Group (PSWG), an active group of users and EDA gripes for a lively exchange of what is working in
the verification space. Panelists will describe some
w e dn e sday, m ar ch 1

vendors. DVCon will be a showcase for PSWG’s

efforts. Vendors will exhibit the latest Portable of their biggest headaches related to tools, vendor
Stimulus software. A tutorial will summarize how support, standards efforts or budget. The goal is
portable stimulus is evolving technologically. Equally to provide constructive feedback to tool vendors,
important is giving users a forum to share their DVCon exhibitors and Accellera to ensure Portable
perspectives on Portable Stimulus, many of whom Stimulus meets the needs of the verification
are not represented on PSWG. community.

Topics include: Panelists:

• What do users expect? Asad Khan - Cavium
Dave Brownell - Analog Devices, Inc.
• What impact could Portable Stimulus have on chip Mark Glasser - NVIDIA Corp.
design verification? Wolfgang Roesner - IBM Corp.
Sanjay Gupta - Qualcomm, Inc.

• 26 •
Session 8 - Virtual Platforms and High-Level Languages
Time: 10:00am - 12:00pm | Room: Oak
Session Chair:
Robert Troy - Cadence Design Systems, Inc.

Moving Beyond SystemVerilog.

8.1 Automatic Exploration of Hardware/ 8.3 Micro-processor Verification Using a C++11

Software Partitioning Sequence-Based Stimulus Engine
Syed Abbas Ali Shah, Sven A. Horsinka, Stephan Bourduas, Chris Mikulis - Cavium, Inc.
Bastian Farkas, Rolf Meyer, Mladen Berekovic - 8.4 Early Software Development and
Technische Univ. Braunschweig Verification Methodology Using Hybrid
8.2 Accelerated Simulation through Design Emulation Platform
Partition and HDL to C++ Compilation Woojoo Kim, Haemin Park, Hyundon Kim,
Theta Yang, Sga Sun - Advanced Micro Devices, Inc. Seonil Brian Choi, Sukwon Kim - Samsung
Electronics Co., Ltd.

w e dn e sday, m ar ch 1
Session 9 - Formal Verification Case Studies
Time: 10:00am - 12:00pm | Room: Fir
Session Chair:
Dan Benua - Cadence Design Systems, Inc.

User Experiences with Formal Verification.

9.1 Making Formal Property 9.3 Formal Proof for GPU

Verification Mainstream: Resource Management
An Intel® Graphics Experience. Jia Zhu, Chuanqing Yan, Nigel Wang -
Achutha Kiran Kumar V. Madhunapantula, Advanced Micro Devices, Inc.
Aarti Gupta, Bindumadhava S. Singanamalli,
9.4 Efficient and Exhaustive Floating
Abhijith A. Bharadwaj, Erik Seligman - Point Verification Using Sequential
Intel Corp. Equivalence Checking
9.2 Using Formal-based Applications to Make Travis Pouarz - Mentor Graphics Corp.
Pristine IPs Vaibhav Agrawal - ARM, Inc.
David Crutchfield, Lee Burns,
Bob Metzler, Hithesh Reddy Velkooru -
Cypress Semiconductor Corp.

• 27 •
Session 10 - AMS Verification
Time: 10:00am - 12:00pm | Room: Monterey/Carmel
Session Chair:
Neyaz Khan - Maxim Integrated

Analog & Mixed-Signal Verification Using UVM (or not).

10.1 Machine Learning based PVT Space 10.3 Real Number Modeling of RF Circuits
Coverage and Worst Case Exploration In Jakub Dudek, Joshua Nekl, Keith O’Donogue -
Analog and Mixed-Signal Design Analog Devices, Inc.
Verification
10.4 Connecting UVM with Mixed-Signal Design
Honghuang Lin, Zhipeng Ye, Asad Khan -
Ivica B. Ignjic - Elsys Eastern Europe d.o.o.
Texas Instruments, Inc.
10.2 Advances in RF Transceiver SoC
Verification – A Walk-Through over a
2.4 GHz Multi-Modal Integrated Transceiver
Verification Cycle
Charul Agrawal, Ashwin Vijayan, Jakub Dudek
w e dn e sday, m ar ch 1

- Analog Devices, Inc.

Session 11 - UVM Registers at the System Level

Time: 3:00pm - 4:30pm | Room: Oak
Session Chair:
John Dickol - Samsung Austin R&D Center

Interesting UVM Register Applications.

11.1 One Stop Solution for DFT Register

Modelling in UVM
Rui Huang - Advanced Micro Devices, Inc.
11.2 Yet Another Memory Manager (YAMM)
Andrei Vintila, Ionut Tolea, Teodor C.
Vasilache - AMIQ srl
Because this paper was previously presented
at DVCon Europe, it is ineligible for the
Best Paper award.

11.3 Tackling Register Aliasing Verification

Challenges in Complex ASIC Design
Shan Yan, Jie Wu, Jing Li - Broadcom Corp.

• 29 •
Session 12 - Formal Verification Applications
Time: 3:00pm - 4:30pm | Room: Fir
Session Chair:
Ambar Sarkar - eInfochips

Formal Verification Applications.

12.1 Comprehensive and Automated Static 12.3 Accelerating CDC Verification Closure on
Tool Based Strategies for the Detection and Gate-Level Designs
Resolution of Reset Domain Crossings Anwesha Choudhury, Ashish Hari - Mentor
Yossi Mirsky - Intel Corp. Graphics (India) Pvt. Ltd.
12.2 Ironic But Effective: How Formal Analysis
Can Perfect Your Simulation Constraints
Penny Yang - MediaTek, Inc.
Jin Hou - Mentor Graphics Corp.
Yuya Kao, Nan-Sheng Huang - MediaTek, Inc.
Ping Yeung, Joe Hupcey - Mentor Graphics Corp.
w e dn e sday, m ar ch 1

Session 13 - Verification Reuse and Debug

Time: 3:00pm - 4:30pm | Room: Monterey/Carmel
Session Chair:
Josh Rensch - Superion Technology

Optimizing Verification Through Reuse and Debug.

13.1 UVM Interactive Debug Library – Speedup 13.3 Practical Schemes to Enhance Vertical,
the Debug Turnaround Time Horizontal and Platform Reusability of
Horace Chan - Microsemi Corp. Verification Components in AMBA Based
SoC Design.
13.2 Making Legacy Portable with the Portable
Ieryung Park, Nara Cho, Yonghee Im
Stimulus Specification
- SK hynix Inc.
Matthew Ballance - Mentor Graphics Corp.

Best Paper & Poster Awards Presentation

Time: 4:45pm - 5:00pm | Room: Bayshore Ballroom
2017 Recipients of the Best Paper and Poster are announced by Technical Program Chair, Tom Fitzpatrick.

Thank you to our sponsors:

• 30 •
DVCon India

2017 TM

Join us in Bangalore for DVCon India!

September 14-15, 2017 | DVCon-India.org

Leela Palace, Bangalore India
THURSDAY’s
agenda
8:00am - Coffee Break
11:00am Room: Gateway Foyer

Tutorial 4
Reinventing SoC Verification – It Is about Time
Room: Donne Thank you to our Sponsor:

Tutorial 5
Stuck on a Desert Island without Simulation – Only Formal! How Do I Verify
Th ur sday, m ar ch 2

8:30am - My Rescue Drone’s RTL?

Room: Siskiyou Thank you to our Sponsor:
12:00pm
Tutorial 6
Practical Applications for Managing Low Power Verification Complexity and
Debug of Advanced SoCs
Room: Cascade Thank you to our Sponsor:

12:15pm - Sponsored Luncheon

Enterprise Verification Platform Required
1:45pm Room: Sierra/Cascade Thank you to our Sponsor:

Tutorial 7
Optimizing IP Verification – Which Engine?
Room: Donner Thank you to our Sponsor:

Tutorial 8
2:00pm - Testbench Automation : How to Create a Complex Testbench in a Couple
5:30pm of Hours
Thank you to our Sponsor:
Room: Siskiyou

Tutorial 9
Formal Verification Methodology: Maximizing Productivity and Achieving
Formal Closure With Confidence
Room: Cascade Thank you to our Sponsor:

3:00pm - Coffee Break

4:00pm Room: Gateway Foyer

• 32 •
Tutorial 4 - Reinventing SoC Verification - It Is about Time
Time: 8:30am - 12:00pm | Room: Donner
Organizers:
Larry Melling - Cadence Design Systems, Inc.
Tom Anderson - Cadence Design Systems, Inc.

Let’s face it, at the end of the day projects are ruled • Attaching project based metrics management to
by time and one of the leading stresses on project your test and coverage driven flow
time is verification. It is time to take a fresh look at • Utilizing formal technology at IP level and system-
how we do verification, how we measure progress, on-chip (SoC) level, beyond connectivity
and how we manage throughput. In this tutorial
we will examine how to reinvent verification to
best achieve end-to-end productivity, performance, Who should attend:
and throughput using a goal-driven approach.
• Developers of SoC designs
This tutorial will introduce a metric-driven design
flow for SoC development, spanning from proper • Verification engineers/leads responsible for IP,
definition of project goals, through the creation of block, subsystem and system-level verification
portable stimulus that can be used for software- • Verification managers and design managers

Th ur sday, m ar ch 2
driven SoC verification across the various dynamic responsible for delivering quality SoCs on time
engines, formal verification, and planning and
management automation.
What you will learn: Speakers:
Lawrence Loh - Cadence Design Systems, Inc.
• New methodologies to drive throughput –
Larry Melling - Cadence Design Systems, Inc.
software-driven testing, formal
Sharon Rosenberg - Cadence Design Systems, Inc.
optimization techniques
Frank Schirrmeister - Cadence Design Systems, Inc.
• New planning and management optimizations to Uri Tal - Cadence Design Systems, Inc.
improve server farm utilization John Brennan - Cadence Design Systems, Inc.

Thank you to our Sponsor:

• 33 •
Tutorial 5 - Stuck on a Desert Island without Simulation -
Only Formal! How Do I Verify My Rescue Drone’s RTL?
Time: 8:30am - 12:00pm | Room: Siskiyou
Organizer:
Rebecca Granquist - Mentor Graphics Corp.

It could happen to any of us: your plane is stricken • Setup a formal testbench and related
by mechanical failure and is forced on a desert verification methodology efficient property
island. Your only hope of rescue is to verify the RTL checking and analysis. This includes how
for a solar powered drone that will fly to the nearest to translate your requirements into SVA
civilization with your message. All you have for your assertions, constraints, and “covers” that will
EDA usage is a solar powered Linux laptop, your be optimized for formal analysis. Not all formal
DUT’s RTL, some planning & management tools, and runs get a complete proof on the first pass, so
formal & CDC apps -- no simulation! The questions we will also share methodologies for dealing
before you include: with “inconclusives” and how to leverage
How do you translate verification requirements into “bounded proofs” to meet your verification
a machine-readable verification plan and related objectives even if a formal proof isn’t obtained.
Th ur sday, m ar ch 2

coverage goals? • Use formal-based CDC analysis to make

• How do I create the corresponding “formal sure none of the inter-clock domain signals
testbench”? go metastable

• Are there any formal apps that can expedite or • Use formal to check your drone’s sensitivity to
expand the scope my verification? logic faults so it will endure its trip to civilization

• The drone’s FPGA design will call for multiple • Close the verification loop by electronically
asynchronous clocks – will this be a problem? mapping all your progress back to your
original plan
• Is my drone’s RTL sensitive to any logic
faults, and how can I verify that the internal
safety mechanism handles them to avoid a Save yourselves and come to this tutorial!
catastrophic failure?
• How can I be confident that my verification is
complete, and it is safe to launch the drone? Speakers:
Joe Hupcey III - Mentor Graphics Corp.
In this tutorial you will learn how to: Mark Eslinger - Mentor Graphics Corp.
• Map your verification requirements to a human Mitchell Poplingher- Microsemi Corp.
and machine readable verification plan Kartik Raju - Knowles Corp.
• Select & run automated formal apps to
expedite your verification effort without writing
any SVA code Thank you to our Sponsor:

• 34 •
Tutorial 6 - Practical Applications for Managing Low Power
Verification Complexity and Debug of Advanced SoCs
Time: 8:30am - 12:00pm | Room: Cascade
Organizer:
Kiran Vittal - Synopsys, Inc.

With the explosion in design complexity of The following will be discussed in the tutorial, using
advanced SoC designs, power management has real life examples:
become a key issue. Each new generation of • Accurately capturing power intent with IEEE1801
consumer electronic devices is expected to have a for design implementation & verification
longer battery life than before, and even compute
servers now focus on reduced power consumption • SoC integration challenges with respect to
to lower cooling costs. In order to address the need Power State Tables (PST)
for power optimization, SoC teams have adopted • Static checks for targeted verification at RTL,
advanced low power design techniques for power post synthesis and post-layout stages
management. However, these low power design
• Advances in power aware RTL simulation
techniques including: power gating, isolation,
addressing new challenges
retention, standby etc., bring with them a unique set

Th ur sday, m ar ch 2
of challenges. • Effective debug of low power violations with
industry leading solutions
In this session, users will learn the latest
advancements in power architecture specification, • Methodology for IP to SoC validation
specifically complex power states, leveraging • Risks in hierarchical waiver management for low
existing UPF standards and emerging low-power power verification
design methodologies. Users will also learn the
• Practical applications and industry best
recommended methodology and best practices
practices for low power design/verification
for use at different stages in the design flow.
Additionally, a panel of leading-edge SoC companies Speakers:
and Synopsys low power experts will discuss the Satya Ayyagari - Intel Corp.
new trends in next generation verification solutions. Vikas Gupta - Samsung Electronics America, Inc.
These solutions address the static and functional YC Wong - Broadcom Corp.
verification along with seamless debug of power Amol Herlekar - Synopsys, Inc.
managed designs, to enable advanced performance Ankush Bagotra - Synopsys, Inc.
and accelerated turnaround times.
Thank you to our Sponsor:

Thank you to our Sponsor:

• 35 •
Tutorial 7 - Optimizing IP Verification - Which Engine?
Time: 2:00pm - 5:30pm | Room: Donner
Organizer:
Pete Hardee - Cadence Design Systems, Inc.

IP verification is too-often mistakenly tagged as a regressions, maximizing compute-farm resources,

solved problem. The reality is that IP verification is and applying innovative bug-hunting techniques to
plagued with a wide variation in effectiveness – the attain greater confidence that IP is bug-free.
ability to confirm that new IP fulfils function, is of What you will learn:
high quality, and is bug-free; and efficiency – the
ability to assure IP quality in reasonable project • Best practices for rigorous reusable UVM-based
timescales, and to be able to repeat easily when dynamic verification for IPs
the IP is reconfigured for use in derivative designs. • Practical methodologies to select and fully verify
All of this is exacerbated by the fact that today, IPs with formal verification
we’re dealing with IPs and subsystems as big as • New planning and management optimizations to
yesterday’s chips, and tomorrow’s IPs will be as big improve farm utilization
as today’s chips. In short, the barrier to realizing
true IP reuse is verification, not design. This tutorial • How to apply formal and simulation
Th ur sday, m ar ch 2

shares best practices and gives real actionable coverage results in a coherent metric-driven
guidelines for how and where to apply UVM-based verification flow
dynamic and formal verification engines, within a
common metric-driven framework, to optimize IP Who should attend:
verification efficiency and effectiveness.
• IP Developers
Choosing the Appropriate Engine
• Verification engineers/leads responsible for IP,
We can optimize verification by knowing which Block, and Subsystem level verification
IP blocks are best verified with formal and which
• Verification managers and design managers
are best done using UVM; based on design type,
responsible for delivering quality IPs and SOCs
sequential depth and interface type to reduce the
on time
number of dynamic verification cycles needed.
We offer practical guidelines for choosing the Speakers:
appropriate engine, and best practices for Chris Komar - Cadence Design Systems, Inc.
verification reuse based on that method. We Meir Solomon - Cadence Design Systems, Inc.
also highlight verification IPs that can be used
by multiple engines to streamline verification of
common interface protocols. Further guidelines Thank you to our Sponsor:
are given for optimizing dynamic and formal

• 36 •
Tutorial 8 - Testbench Automation : How to Create a
Complex Testbench in a Couple of Hours
Time: 2:00pm - 5:30pm | Room: Siskiyou
Organizer:
Rebecca Granquist - Mentor Graphics Corp.

In 2014, the semiconductor industry passed an improves the efficiency of the whole testbench
important milestone. For the first time, the average creation process. In this tutorial, you will learn how
engineering team had more verification engineers to create a complex testbench that can be targeted
than designers. This means that any improvement at simulation or emulation in a couple of hours. •
in the efficiency of verifications teams has a You will learn:
significant impact on overall project costs and time
to market. In the past two decades, the industry • How to use the UVM-Framework code generation
has converged on two complementary strategies to rapidly build reusable testbench infrastructure
to verify increasingly complex SoCs : the reuse of • How to use a VIP Configurator to shorten the bring
testbenches from subsystem level to SoC level, and up time for industry standard protocols
the use of advanced verification techniques such
• How Portable Stimulus shortens the time to create
constrained random, assertions, and verification

Th ur sday, m ar ch 2
efficient, systematic scenario-level stimulus
management. The key technology that enables
these two strategies is the UVM. Despite its You will also hear from industry experts who have
success and proliferation, experience shows us that successfully used this testbench automation flow
there are two main problems with this approach. on their projects.
The first is that there is a learning curve associated This tutorial is intended for verification engineers,
with the adoption of UVM, and the second is that architects and managers who are interested in
even for UVM experts, creating the necessary making significant improvements to the overall
infrastructure, getting it up and running, and efficiency of their verification process.
achieving coverage closure is a time consuming and
Speakers:
error prone process. This tutorial introduces three
new technologies which significantly reduce the Matthew Ballance - Mentor Graphics Corp.
time to create a reusable testbench infrastructure. Hans van der Schoot - Mentor Graphics Corp.
These three technologies are integrated into Bob Oden - Mentor Graphics Corp.
a single comprehensive flow that significantly

Thank you to our Sponsor:

• 37 •
Tutorial 9 - Formal Verification Methodology: Maximizing
Productivity and Achieving Formal Closure With Confidence
Time: 2:00pm - 5:30pm | Room: Cascade
Organizer:
Prapanna Tiwari - Synopsys, Inc.

Rapidly growing design functionality has an design types and sizes (including SoC’s). In addition,
explosive impact on verification complexity. As the tutorial will provide guidance on a methodology
a result of this growing complexity, verification for users to define and metrics to provide insight
teams are looking for innovative technologies that on coverage and provide confidence on formal
complement and accelerate their flows. The latest verification closure and assess the completeness
advances in formal verification are a powerful driver of their formal environment. Applications such as
for this. In this tutorial, we will discuss how to use the Formal Testbench Analyzer and Formal Core
formal technologies for faster verification flows and provide the visibility and confidence needed for
the methodology for how to measure and achieve functional sign-off.
formal verification closure.
Industry experts from Qualcomm, Oski and
Speakers:
Th ur sday, m ar ch 2

Synopsys will use real world design scenarios to

showcase how certain verification problems are Mandar Munishwar - Qualcomm, Inc.
extremely well suited to be solved with formal Vigyan Singhal - Oski Technology, Inc.
verification. These include applications such as Sean Safarpour - Synopsys, Inc.
Connectivity Checking, Register Validation, and Pratik Mahajan - Synopsys, Inc.
Design Navigator. With these apps, users save
significant time, effort and resources across all Thank you to our Sponsor:

• 38 •
2017 TM

join us in europe!
EUROPE October 16-17, 2017

Holiday Inn Munich City Centre

Munich, Germany
DVCon-Europe.org
Welcome to the
DVCon 2017 Expo!

Collaborate with vendors at the pinnacle of innovation!

Learn about new, cutting-edge technology and network with vendors well-tuned to today’s
verification needs, and see how collaboration can take your design to the next level.
4th Annual

BOOTH CRAWL

WIN $500!
O
VC N 2
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01
7

& C
C ock
on t a il s s
v e r s a ti o n

• Attend the Booth Crawl

• Get automatically entered into a drawing for a $500 Visa gift card
• Winner announced Monday at 6:45pm on the exhibit floor!
(Must be present to win)

Join us for the 4th Annual

C
C
&

o
o n ckt
v e a il s
r s a tion s

Booth Crawl! Wednesday, March 1:

2:30pm - 6:00pm

DVCon 2017 Exhibitors

Agnisys, Inc. .................................................. 805 Oski Technology, Inc. ................................... 205

Aldec, Inc. ...................................................... 904 ProDesign Electronics.................................. 905

AMIQ EDA ...................................................... 405 Real Intent, Inc. ............................................ 605

Avery Design Systems, Inc. ......................... 304 Runtime Design Automation* .................... 404

Blue Pearl Software ................................... 1001 S2C Inc. .......................................................... 402

Breker Verification Systems ....................... 504 Sandstrom Engineering* ............................. 401

Cadence Design Systems, Inc. .................... 702 Semifore, Inc................................................. 502

DINI Group .................................................... 604 Sigasi*............................................................ 601

Doulos ........................................................... 501 SmartDV Technologies ................................ 302

EDACafe.com ................................................ 801 Synopsys, Inc. ............................................... 101

HyperSilicon Co., Ltd.* .............................. 1004 Test and Verification Solutions LLC ........... 901

InnovativeLogic, Inc. .................................... 505 Truechip Solutions Pvt. Ltd. ........................ 902

Magillem Design Services* ......................... 602 VeriFast* ....................................................... 301

MathWorks ................................................. 1002 Verific Design Automation .......................... 705

Mentor Graphics Corp. .............................. 1101 Verifyter ........................................................ 305

OneSpin Solutions ....................................... 701

* Denotes First-time Exhibitor

• 42 •
Dvcon expo
Exhibitor Floor Plan
EMPLOYEE AREA

EXIT SERVICE CORRIDOR

905 805 705 605 505 405 305 205

1004 904 604 504 404 304

702
1002 902 602 502 402 302

1101 WOMEN MEN

101
1001 901 801 701 601 501 401 301

ENTRANCE PHONES
EXIT FOYER

REGISTRATION

UP TO
SECOND
FLOOR

Networking Receptions
One of the main reasons you came to DVCon: NETWORKING!
Introduce yourself and leave DVCon with a deeper professional network!

DV
CON
Monday, February 27: Tuesday, February 28:
5:00 - 7:00pm 5:00 - 6:00pm
2
01
7

C
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Join us for the 4th Annual Networking Reception
&

o
o n ckt
v e a il s
r s a tion s

Booth Crawl!
Wednesday, March 1:
5:00 - 6:00pm
Networking Reception

• 43 •
Dvcon expo
Exhibitor Listing
Agnisys, Inc. Blue Pearl Software
Booth: 805 Booth: 1001
www.agnisys.com www.bluepearlsoftware.com
Agnisys has products to take customers from Specification Blue Pearl Software, Inc., an industry leading provider of
to Realization with certainty of functionality and time to design automation software for ASIC, FPGA and IP RTL
market. IDesignSpec generates RTL, UVM, C/C++ API from verification, offers Linting, debug, and CDC solutions
registers/sequence specification. DVinsight is a smart proven to improve quality of results, accelerate RTL error
editor purposefully built for SV/UVM based verification. find/fix rates while ensuring uniform coding styles. Blue
Agnisys is now offering its Consulting and Training Services Pearl provides out-of-the-box consistent results, easy
in SV/UVM/SystemC for SoC, ASIC, IP and FPGA in Design setup, SDC generation, management dashboard views and
and Verification space. runs on Linux and Windows.

Aldec, Inc. Breker Verification Systems

Booth: 904 Booth: 504
www.aldec.com www.brekersystems.com
Established in 1984, Aldec is an industry leader in Breker Verification Systems is the Portable Stimulus
Electronic Design Verification and offers a patented leader, adding GPS to your verification. Compliant with the
technology suite including: RTL Design and Mixed- upcoming Accellera Portable Stimulus standard, Breker
Language Simulation (VHDL, Verilog, SystemVerilog/UVM), automates the generation of target-specific, multi-threaded
FPGA-based Hardware-Assisted Verification, SoC and tests cases, by taking as inputs a single, executable Graph-
ASIC Prototyping, Emulation, Design Rule Checking, Clock based, Portable stimulus or spec of your verification intent,
Domain Crossing, VIP Transactors, Requirements Lifecycle Shareable across platforms and projects.
Management, Embedded Development Kits, High-
Performance Computing/Acceleration, DO-254 Functional Cadence Design Systems, Inc.
Verification and Military/Aerospace solutions. Booth: 702
www.cadence.com
AMIQ EDA Cadence enables global electronic design innovation and
Booth: 405 plays an essential role in the creation of today’s integrated
www.amiq.com circuits and electronics. Customers use Cadence software,
AMIQ EDA provides worldwide adopted software tools hardware, IP and services to design and verify advanced
for hardware design and verification. Its solutions, DVT semiconductors, consumer electronics, networking and
Eclipse IDE, DVT Debugger Add-On, Verissimo Linter, and telecommunications equipment, and computer systems.
Specador Documentation Generator, enable design and For more information, visit www.cadence.com.
verification engineers to increase the speed and quality of
new code development, simplify legacy code maintenance, DINI Group
accelerate language and methodology learning, improve
testbench reliability, extract automatically accurate Booth: 604
documentation, and implement best coding practices. For www.dinigroup.com
further information visit: www.dvteclipse.com Located in La Jolla, California, Dini Group is a professional
hardware and software engineering firm specializing in
FPGA-based high performance digital circuit design and
Avery Design Systems, Inc. application development. We have products targeted
Booth: 304 to ASIC prototyping, High Performance Computing,
www.avery-design.com Algorithmic Acceleration (including Data Center), and Low
Latency Networking.

• 44 •
Dvcon expo
Exhibitor Listing
Doulos Magillem Design Services
Booth: 501 Booth: 602
www.doulos.com www.magillem.com
Doulos has set the industry standard for high quality Magillem is a leading EDA software provider. Internationally
training and KnowHow for over 25 years in design and renowned, we are present in 12 countries. 90% of our
verification languages and methodologies for system, turnover is realized in the export. Our innovative solution,
hardware, and embedded software designers. The introducing a XLM-based collaborative platform, supports
essential choice for 3500+ companies across 60+ countries, our customers’ R&D from specification of their product
Doulos provides scheduled classes across North America to the documentation, and connects all business experts,
and Europe, and delivers on-site and live online training especially in IoT and embedded systems’ domain.
worldwide. Find out more: www.doulos.com
MathWorks
EDACafe.com Booth: 1002
Booth: 801 www.mathworks.com
www.edacafe.com MathWorks is the leading developer of mathematical
EDACafe.Com is the #1 EDA web portal. Thousands of IC, computing software. Engineers and scientists worldwide
SoC, FPGA, PCB, System designers and top level decision- rely on its products to accelerate the pace of discovery,
makers visit EDACafe.Com daily to learn about the latest innovation, and development. MATLAB and Simulink
industry trends, design tools and services. Sign up for the are used throughout the automotive, aerospace,
industry’s best daily newsletter at communications, electronics, and industrial automation
www10.edacafe.com/nl/newsletter_subscribe.php. industries as fundamental tools for research and
development. They are also used for modeling and
HyperSilicon Co., Ltd. simulation in increasingly technical fields, such as financial
Booth: 1004 services and computational biology. For more information
www.hypersilicon.com visit www.mathworks.com
HyperSilicon is one of the leading suppliers of FPGA based
rapid system prototype and desktop emulator for SoC Mentor Graphics Corp.
design industry. We provide flexible, reliable SoC/ASIC Booth: 1101
verification platform, fastest desktop emulator and FPGA www.mentor.com
based customizing design services. With over 10 years in Mentor Graphics delivers the most comprehensive
SoC/ASIC verification market, we have built excellent long Enterprise Verification Platform™ (EVP), delivering
term partnership with an impressive number of customers performance and productivity improvements ranging from
worldwide, like Huawei, AMD and Fujitsu etc. 400X to 10,000X. Tightly integrated combining Questa® for
high performance simulation, verification management and
InnovativeLogic, Inc. coverage closure, low-power, CDC & Formal Verification,
Booth: 505 Veloce® for hardware emulation and HW/SW system
www.inno-logic.com verification, Catapult® for High-Level Synthesis,
Innovative Logic is the leading provider of ASIC, FPGA, PowerPro® for RTL Low-Power unified with the Visualizer™
Firmware, Software & IT services and Soft IP. We have debug environment.
very flexible model to offer on-site, offsite or turnkey
solutions to our customers. We also provide complete
soft IP solution that includes source code, verification
environment, firmware, documentation, prototyping and
extensive support to ensure that you have successful
product. We are in business of offering the best quality
services and soft IP to many Fortune 500 companies for
last 10 years.

• 45 •
Dvcon expo
Exhibitor Listing
OneSpin Solutions Runtime Design Automation
Booth: 701 Booth: 404
www.onespin-solutions.com www.rtda.com
OneSpin Solutions, a leader in formal verification, is Runtime, headquartered in Santa Clara, California, is
creating the industry’s most advanced formal platform, the leading supplier of high-performance computing
encompassing agile design evaluation, coverage-driven infrastructure and workflow optimization solutions,
ABV, and automated DV apps. The world’s leading dramatically improving resource utilization and efficiency,
electronics companies partner with us to pursue design enabling faster time to market for our customers. Our
perfection in areas where reliability really counts: safety- family of high-performance schedulers offer optimum
critical verification, SystemC/C++ HLS code analysis, and performance for all aspects of design verification including
FPGA equivalence checking. OneSpin: Making Electronics simulations (NetworkComputer), full-chip regressions
Reliable (WorkloadXelerator) and hardware emulation (HERO). For
more information, visit www.rtda.com.
Oski Technology, Inc.
Booth: 205 S2C Inc.
www.oskitechnology.com Booth: 402
Oski Technology has established itself as the unsurpassed www.s2cinc.com
global leader in the domain of formal verification S2C has been successfully delivering rapid SoC prototyping
methodology and services. Founded in 2005, Oski serves solutions since 2003. Our portfolio includes prototyping
six out of the top seven semiconductor design companies, hardware and automation software, IP, and system-level
yielding accelerated verification schedules and higher design verification and acceleration tools. With over 200
quality designs than what is possible through simulation customers and more than 800 systems installed, S2C
alone. Visit us at DVCon and discover how we can help with systems have been deployed by leaders in consumer
your design. electronics, communications, computing, image
processing, data storage, research, defense, education,
ProDesign Electronics automotive, medical, design services, and silicon IP. For
Booth: 905 more information, visit www.s2cinc.com.
www.profpga.com
ProDesign Electronics products and services include the Sandstrom Engineering
proFPGA family of ASIC Prototyping and FPGA systems. Booth: 401
The proFPGA system is a complete, scalable and modular www.sandstrom.org
multi FPGA solution, which fulfills highest needs in the UVM doesn’t need to be drinking-from-a-firehose
area of FPGA based Prototyping. It addresses customers complicated. I’ve developed techniques to simplify
who need a scalable and most flexible high performance the UVM bloatware while still being UVM compliant. I
ASIC Prototyping solution for early software development demystify the entire UVM environment and development.
and real time system verification.
Semifore, Inc.
Real Intent, Inc. Booth: 502
Booth: 605 www.semifore.com
www.realintent.com Semifore Inc. provides the CSRSpec language and the
Real Intent is the leading provider of EDA software to CSRCompiler, a complete register design solution for
accelerate Early Functional Verification and Advanced hardware, software, verification, and documentation.
Sign-off of digital designs. It provides comprehensive Collaboratively manage your design from a single
clock-domain crossing verification, advanced RTL analysis source specification. CSRSpec, SystemRDL, IP-XACT, or
and sign-off solutions to eliminate complex failure modes Spreadsheet inputs generate: Verilog and VHDL RTL;
of SoCs. The Meridian and Ascent product families lead Verilog, or C headers; Perl, IEEE IP-XACT, UVM, HTML web
the market in performance, capacity, accuracy and pages, and Word or Framemaker documentation.
completeness.

• 46 •
Dvcon expo
Exhibitor Listing
Sigasi TRUECHIP
Booth: 601 Booth: 902
www.sigasi.com www.truechip.net
Sigasi radically redefines digital design. Our design entry Truechip is a leading provider of Verification IP Solutions.
tool, Sigasi Studio, drastically improves hardware designer Truechip has enabled its customers to bring superior
productivity by helping to write, inspect and modify digital products to market with reduced cost and time-to-market.
circuit designs in the most intuitive way. Advanced features All Truechip VIPs come with Spec-tagged features and
such as intelligent autocompletes and code refactoring, Testplan for the robust Verification of Design. Truechip’s
make VHDL and SystemVerilog design easier, more efficient. portfolio of Verification IPs includes USB, PCIe, Ethernet,
Sigasi was founded in 2008 and has customers worldwide in Memory, Display, AMBA, MIPI VIPs. For more details visit us
all fields of industry. at www.truechip.net.

SmartDV Technologies VeriFast

Booth: 302 Booth: 301
www.smart-dv.com www.verifasttech.com
SmartDV creates standard and custom verification VeriFast Technologies is a Design Verification company
intellectual property (VIP), memory models and simulation specializing in Training and Consulting with a focus on the
acceleration VIPs designed to work with coverage-driven latest technologies such as SystemVerilog and UVM. Our
verification flows. All SmartDV VIPs ship with compliance training courses are offered in an online learn-as-you-go
test-suite and comprehensive functional coverage models. format complete with state of the art Questa tools from
All VIPs are native UVM or language of customer choice. For Mentor Graphics. Add horsepower to your project by
more information on SmartDV’s products, see adding our DV engineers to your team.
www.smart-dv.com/products.html
Verific Design Automation
Synopsys, Inc. Booth: 705
Booth: 101 www.verific.com
www.synopsys.com Support your own RTL tools with Verific’s industry standard
Synopsys delivers comprehensive verification solutions (System)Verilog, VHDL, and UPF parsers ! Verific Design
spanning the complete design cycle, including simulation, Automation has provided (System)Verilog and VHDL front-
emulation, advanced debug, static/formal verification, ends to EDA, FPGA, and semiconductor computers for
FPGA-based prototyping and virtual prototyping. Synopsys’ many years. With more than 60 active licensees worldwide,
Verification Continuum combines best-in-class technology, Verific’s parsers are found everywhere. And all our APIs are
verification IP, and advanced methodologies enabling available in Python, Perl, and C++.
users to address rapidly escalating SoC complexity,
accelerate time-to-market, and bring innovative products Verifyter
to market sooner. Booth: 305
www.verifyter.com
Test and Verification Solutions LLC Verifyter was founded 2010 with the mission to transform
Booth: 901 the development process by automating debug of
www.testandverification.com regression test failures, especially targeting the ASIC
T&VS provides hardware verification and software testing market. PinDown, Verifyter’s automatic debugger, is
products and services to the worldwide semiconductor currently used by both ASIC and ASIC IP companies and has
and embedded systems industries to help improve their proven to speed-up the bug fixing cycle by up to 400% and
product time-to-market and quality. T&VS applies well bring in the project release date by as much as 10%.
proven methodologies, tools and processes to ensure the
thoroughness of the verification, generating metrics to track
progress and enable a go-to-market decision thus enabling
our customers to focus their R&D resources on feature
development rather than QA.
*Note Exhibitor Listing as of January 30, 2017
• 47 •
Dvcon expo
Thank You to Our Event Sponsors