IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO.

11, NOVEMBER 2017 4165

A 30-GHz Power-Efficient PLL Frequency

Synthesizer for 60-GHz Applications
Nagarajan Mahalingam, Member, IEEE, Yisheng Wang, Bharatha Kumar Thangarasu, Member, IEEE,
Kaixue Ma, Senior Member, IEEE, and Kiat Seng Yeo, Fellow, IEEE

Abstract— This paper presents the design and verification of synthesizers reported in [1]–[3] are not large enough to cover
a proposed 30-GHz power-efficient phase-locked loop (PLL) fre- all channels in the 60-GHz band allocated across different
quency synthesizer for 60-GHz applications. Fabricated by a com- regions. Also, the phase noise of synthesizers in [2]–[5] is
mercial 0.18-µm SiGe BiCMOS process, the synthesizer employs
coupled LC tank voltage-controlled oscillator, high power-added not good. Moreover, the synthesizer reported in [1] has large
efficiency amplifier, reconfigurable divider realizing fractional power consumption, limiting its integration into the low-power
division ratios for choice of multiple reference frequencies and transceiver. The possible reasons for the above-mentioned
low operation power, a programmable charge pump, an internal practical design challenges in the synthesizer are low quality of
loop filter, and an integrated slave serial peripheral interface. The varactors used for high tuning range in the voltage-controlled
PLL synthesizer (PLLS ) provides output frequency from 29.5 to
33.4 GHz with phase noise of −97 dBc/Hz at 1-MHz offset. The oscillator (VCO), unpredictability of frequency shift due to the
integrated phase noise over the frequency of 10 kHz–10 MHz is parasitic capacitance, and transistor modeling [7].
2.05° rms at a frequency of 30.24 GHz. Operating with a single To overcome the design challenges, integrated synthesizers
1.8-V supply voltage, the PLLS consumes a low power of 63 mW are designed at lower frequencies and several synthesizer
and occupies an area of 2.8 mm × 1.86 mm. designs have been reported in [8]–[15]. To achieve a wide
Index Terms— Coupled LC tanks (CLCTs), fractional-N, fre- tuning range, push–push VCO is employed in [8] and [9].
quency synthesizer, low phase noise, low power, multimode, Also in [11], a Wilkinson’s power combiner is employed
phase-locked loop (PLL), silicon–germanium (SiGe), 60 GHz, following the VCO. Although the tuning range and phase
30 GHz, voltage-controlled oscillator (VCO).
noise of the VCO are improved with push–push topology,
I. I NTRODUCTION the push–push VCO output is typically single ended and has
relatively poor drive capability. Differential push–push output
O VER the years, the increased usage of handheld and
smart devices and appetite for seamless wireless con-
nectivity has led to the need for high data-rate communication
can be realized with quadrature VCO as in [8]. However,
the power hungry buffer amplifiers are required to improve
the power level of push–push output prior to the mixer stages.
systems. More recently, the presence of up to 9 GHz of unli-
This additional power consumption in the LO path increases
censed band around 60 GHz for wireless communication has
the overall power consumption of the transceiver. In [10],
drawn much attention of researchers and industry worldwide.
the phase-locked loop (PLL) synthesizer (PLLS ) requires extra
The bandwidth of 2.16 GHz for each channel has enabled the
multiplier and divider circuits with large power consumption to
realization of applications with gigabits per second data rates.
complement for IEEE 802.15.3c standard. Sigma-delta-based
In order to support these high data-rate applications with low
fractional synthesizer for 60-GHz application with comparable
cost, it is important to develop a high-performance integrated
performance is presented in [12]. However, the phase noise
synthesizer, generally used as local oscillator (LO) source in
is poor because of the ring-oscillator-based injection-locked
the transceiver.
frequency divider in the LO path. In [13], the presented PLLS
Recent advances in silicon (Si)-based CMOS and silicon–
requires a variable reference frequency.
germanium (SiGe) BiCMOS technologies have made it possi-
In this paper, we present a power-efficient PLLS includ-
ble to design integrated synthesizers at 60 GHz [1]–[5] with
ing proposed reconfigurable power saving architecture and
performance comparable to high-electron mobility transistor-
building blocks for 60-GHz applications. First, the VCO in
based synthesizer [6]. However, there are several practical
the PLLS is optimized by using coupled LC tanks (CLCTs)
design challenges. For example, the frequency range of the
achieving a wide tuning range and low phase noise but
Manuscript received December 11, 2016; revised March 20, 2017; accepted with low power consumption. Second, a high power-added
April 19, 2017. Date of publication May 17, 2017; date of current version efficiency (PAE) amplifier is implemented in the LO path to
November 3, 2017. (Corresponding author: Nagarajan Mahalingam.)
N. Mahalingam, Y. Wang, B. K. Thangarasu, and K. S. Yeo are with increase the power efficiency. Also, the divider chain is imple-
Engineering Product Development (EPD), Singapore University of Tech- mented with continuously scaled emitter-coupled logic (ECL)
nology and Design, Singapore 138682 (e-mail: [email protected]; dividers for high frequency and CMOS for low frequency.
[email protected]).
K. Ma is with the School of Physical Electronics, University of Elec- In addition, the proposed PLLS architecture provides a good
tronic Science and Technology of China, Chengdu 610054, China (e-mail: tradeoff among phase noise, tunable frequency range, and
[email protected]). power consumption of only 63 mW.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. This paper is extended based on [15] and is organized as
Digital Object Identifier 10.1109/TMTT.2017.2699671 follows. In Section II, the architecture of the proposed PLLS
0018-9480 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 4166 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 11, NOVEMBER 2017

is presented. Section III provides the description and design

implementation of individual building blocks in the PLLS .
Experimental results of the PLLS are presented in Section IV,
and conclusion is presented in Section V.

II. PLLS A RCHITECTURE

In general, the performance requirement and architectural
selection of the PLLS is largely dependent on the transceiver
architecture. Several transceiver architectures for the 60-GHz
applications are reported in [16]–[19]. The PLLS presented in
this paper is based on the one-time conversion architecture
requiring an LO center frequency of 30-GHz supporting the
IEEE 802.11ad wireless standards. Employing a PLLS at half
the frequency for 60-GHz applications simplifies the LO chain
and reduces both the LO and transceiver power consumption. Fig. 1. Block diagram of proposed PLLS .
The architectural choice of the PLLS in this paper is
influenced by the need to provide a good tradeoff among
performance and to reduce the overall area and power con- A. Coupled LC Tank VCO
sumption of the PLLS and the transceiver. Based on the
one-time conversion architecture, the required LO frequencies VCO design based on cross-coupled and Colpitts topology
corresponding to the RF center frequency in the 60-GHz have remained the most popular choice due to their simple
band are 29.16, 30.24, 31.32, and 32.4 GHz, respectively, for design and adequate performance. The motivation for VCO in
channels 1–4. Also, the heterodyne approach requires only a this work stems from the requirement of wide tuning range,
single-phase 30-GHz VCO, while the I/Q signals are generated low phase noise, and low power consumption for the LO
by passive I/Q generators reducing the complexity of the in Fig. 1. Also, to reduce the overall power consumption
synthesizer. With this approach, the power consumption of the of the transceiver, the LO must have a high output power
transceiver can be reduced. with minimum variation over the entire LO range to drive the
In the PLLS , there is lot of choice for reference fre- subsequent stages.
quency (Fref ) which is typically from an external crystal The simple way to obtain the required frequency tuning
oscillator. However, the reference frequency for the PLLS range in the VCO is to use a single large varactor. Using
must be chosen based on the application, integration capability a single large varactor in LC tank to cover the whole LO
and cost. For the 60-GHz high-speed wireless application, frequency range would result in large variation of LO per-
the coexistence of 60 GHz with the existing Wi-Fi standards formance due to: 1) change in quality factor of the varactor
is an important criterion. Also, the PLLS in this paper is used in the resonator; 2) nonlinear K VCO values increasing
designed to be part of 60-GHz transceiver supporting IEEE the AM–PM noise conversion [20]; and 3) conversion of 1/ f
802.11ad wireless standard. Therefore, the reference frequency noise into 1/ f 3 phase noise due to varactor nonlinearity [21].
is chosen to be 120 MHz, which is an integer multiple Also, when employed in a PLLS , the large K VCO results in
of 40 MHz commonly used for Wi-Fi applications. The choice large up-conversion of noise from the CP and the loop filter.
of 120 MHz as reference frequency can improve the in-band Therefore, the standard approach to minimize these effects is
phase noise in comparison to the 40-MHz reference due to to employ either discrete tuning of capacitor [22] or oscilla-
smaller division ratio. However, the integration capability and tor elements [23] in combination with continuous tuning of
cost is traded-off with performance. varactors in the VCO. Though this approach works well at
The block diagram of the proposed PLLS is shown in Fig. 1. RF frequencies, in the frequency range of K -band and above,
The high-frequency blocks of the synthesizer consist of CLCT the loss from switching elements and interconnect parasitic
VCO, high PAE variable gain amplifier, and high-frequency contribute a significant portion degrading the tuning range and
ECL divide-by-2. The remaining divider chain in the PLLS is quality factor of the resonator.
composed of ECL-based divide-by-8, a dual modulus divide- To address these problems, Colpitts VCO based on CLCTs
by-3/4 prescaler, and multistage noise shaping (MASH) 1-1- as shown in Fig. 2 is used in this paper. The primary inductor
1 sigma-delta modulator (SDM). A CMOS phase frequency L p is connected to the base of transistors Q 1 and Q 2 , and the
detector (PFD), a CMOS variable current charge pump (CP), secondary coils L s1 and L s2 are connected to MOS varactors
and an internal second-order loop filter completes the PLLS . Cv1 and Cv2 , respectively, for continuous frequency tuning
The proposed PLLS is fully integrated with a bandgap refer- and discrete band switching. The negative resistance of the
ence and serial peripheral interface (SPI) slave for control of VCO is generated by the fixed capacitor C1 , transistor base–
digital tuning bits. emitter parasitic capacitance Cπ and coarse tuning varactors
in the emitter (Ce0 –Ce3 ). The varactors in the emitter form
III. C IRCUIT D ESIGN a capacitor bank to overcome the issue of noise sensitivity
The circuit design details of the key building blocks in the due to the varactor gain and are used for coarse tuning of the
proposed PLLS are described in this section. VCO frequency. The degeneration inductor L e acts as a RF

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 MAHALINGAM et al.: 30-GHz POWER-EFFICIENT PLL FREQUENCY SYNTHESIZER 4167

Fig. 3. Choice of capacitance tuning (a) switch and (b) varactor.

Fig. 2. Schematic of CLCT VCO.

choke improving the VCO signal feedback. The combination

of L c and C M in the collector improves the negative resis-
tance in the frequency band of interest reducing the power
consumption [24].
In the CLCT, the change in the currents in the primary
and the secondary coils based on the coupling can achieve a
change in the oscillation frequency due to the variation of the
effective inductance. The corresponding impedance matrix of
the CLCT in the VCO across points A and B in Fig. 2 is given
by
⎡ ⎤
V1
⎢V ⎥
⎣ 2⎦
V3
⎡ ⎤
R p + j ωL p − j ωM12 − j ωM13
⎢ 1 ⎥
⎢ − j ωM ⎥
=⎢ 21 Rs1 + j ωL s1 + − j ωM23 ⎥
⎢ j ωCv1 ⎥
⎣ 1 ⎦
− j ωM31 − j ωM32 Rs2 + j ωL s2 +
j ωCv2
⎡ ⎤
ii Fig. 4. Comparison of capacitive tuning. (a) Capacitance. (b) Q-factor.
⎢ ⎥
× ⎣ i2 ⎦ (1)
i3 where
RCLCT

where R p , Rs1 , and Rs2 represent the losses in the primary


2 + M 4ωL 3
Rs M1 L 4sc + L 2sc ω2 M23
and secondary coils. Also, the mutual inductance Mi j = = Rp +
2 sc
2 + L2
K i j (L i L j )1/2 . Rdr dr
Assuming Mi j = M j i , Rs = Rs1 = Rs2 , and Cs = = [R p + Reff ] (3)
Cs1 = Cs2 and L sc = L s1 = L s2 due to symmetry, L CLCT
⎡ ⎤
the impedance of the CLCT can be simplified and represented L 2sc 2 2

3 
ω ω M23 L sc M1 +2ωM2 − L sc M1 +2ωM2 L sc ⎦
2
as [24] = ⎣L p + 2 + L2
Rdr dr
Z CLCT = RCLCT + j ωL CLCT (2) = [L p + L eff ] (4)

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 4168 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 11, NOVEMBER 2017

Fig. 8. Simulated matching of LO distribution network.

Fig. 5. EM simulation model of VCO emitter components.

Fig. 9. Simulated loss of LO distribution network.

Fig. 6. Circuit schematic of high PAE amplifier.

by strong coupling between the coils and reducing resistive
losses in the primary and secondary coils.
The layout of CLCT in the VCO is shown in Fig. 2. The
primary coil consists of a single turn inductor drawn on top
metal (metal 6) with a width of 6 μm. The secondary coil
connected to the continuous tuning varactor is drawn with
identical metal width as the primary coil with a spacing of
2 μm (process dependent) to increase the coupling between
the coils. However, to reduce the area and further improve the
coupling current, the discrete band switching secondary coil is
stacked to the primary and secondary coil. Also, to reduce the
resistive losses due to the use of lower metal layer, the width
increased to 10 μm.
Design of Capacitor Tuning: In the CLCT VCO, capac-
Fig. 7. LO distribution transmission line. itive tuning is employed in the core and in the secondary
of CLCTs to achieve a wide tuning range with low VCO
sensitivity. The different choice of capacitive tuning tech-
where Rdr = Rs3 −3Rs L 2sc +ω2 M23 2 R , L
s dr = 3Rs L sc − L sc +
2 3 niques is shown in Fig. 3. In Fig. 3(a), a switch capacitor
ω2 M232 L , M = ω2 (M 2 + M 2 ), M = (ω2 M M M ),
sc 1 12 13 2 12 13 23 with a switch and capacitor generally implemented as metal-
and L sc = (ωL s ) − (ωCs )−1 . insulator-metal capacitors is shown. Based on the control
Intuitively, from (4), the inductance is dominated by L 3sc M1 voltage of MSW , the switch is in the either ON-state or OFF-
term and the effective inductance is tuned by M1 when the state. In Fig. 3(b), varactor-based capacitance tuning is shown.
coupling between the primary and secondary coil is increased. The accumulation-mode MOS varactors are preferred and
Also, since Q eff = ω · L CLCT · (RCLCT )−1 , a higher quality implemented over p-n junction varactors for better tunability
factor in the presence of wide tuning range can be achieved and high quality factor.

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 MAHALINGAM et al.: 30-GHz POWER-EFFICIENT PLL FREQUENCY SYNTHESIZER 4169

Fig. 12. Schematic of CP.

Fig. 10. Logic structure of SDM.

Fig. 11. SDM noise spectrum.

In frequencies of K -band and above, the implementation

of the switch in Fig. 3(a) becomes a dominant factor. In the
OFF -state, the capacitance of the switch (C OFF ) degrades the Fig. 13. Measured VCO frequency tuning range.
tuning range by lowering the achievable Cmax /Cmin ratio.
In the ON-state, the switch ON resistance (RON ) degrades the
in the secondary coils. The value of coarse tuning varactor
achievable quality factor for the capacitor bank. In Fig. 3(b), connected to the emitter of transistors Q 1 and Q 2 is a tradeoff
the digital signal is applied directly to varactor. Typically, between negative resistance, tuning range, and phase noise.
the quality factor of the switch capacitor or varactor is given
Therefore, to carefully characterize the parasitic effects due to
by layout, the electromagnetic (EM) simulation is performed in
1 ADS momentum for the components connected to the emitter
Q cap,var = (5)
ωCcap,var Rcap,var of transistors Q 1 and Q 2 and the 3-D model is shown in Fig. 5.
Also, to save on die area, the ac biasing of varactors through
where Ccap,var and Rcap,var represent the overall capacitance large capacitors is not used in this work.
and resistive loss. The comparison of Cmax /Cmin and quality The phase noise is one of the most critical specifications
factor for a unit capacitance of 100-fF based on the switch and in the VCO. Based on the Leeson’s model, the close-in phase
varactor capacitive tuning is shown in Fig. 4. It can be seen noise of the VCO is given by [25]
that the varactor-based tuning achieves a higher Cmax /Cmin   2  
ratio and a better overall quality factor. 2FKTReq ωo ω1/ f 3
L(ω) = 10 log · 1+
All the varactors in this paper are based on accumulation- A2o 2Qω |ω|
mode MOS varactors, and the device length of the varac- (6)
tors is kept to minimum to maximize their quality factor.
To maximize the tuning range and quality factor for the given where K is Boltzmann’s constant, T is the absolute temper-
varactor size, the bias point is controlled by the center-tap ature, A0 is the amplitude of oscillation, Q is the resonator

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 4170 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 11, NOVEMBER 2017

Fig. 15. Measured VCO phase noise.

where Rtank is the parallel equivalent of resonator tank quality

factor and ηcolp = (C1 + Cπ )/(C1 + Cπ + Cei,i=0 ). From (9),
it can be seen that, the phase noise is influenced by the quality
factor of tank circuit and effect on capacitor ratio formed
Fig. 14. Measured VCO output power.
by C1 , base–emitter capacitance Cπ and total capacitance
connected to the emitter of transistors Q 1 and Q 2 .
In the CLCT VCO, the capacitance connected between the
loaded quality factor, ω1/ f 3 is the corner frequency, and F
emitter of transistor Q 1 and Q 2 is part of frequency tuning
is the excess noise factor. For the Colpitts oscillator, the phase
to achieve a wide tuning range in the VCO. The equivalent
noise based on Leeson’s model can be given by [26]
capacitance is varied by using the digital tuning bits and this
2   result in a small change of C in the capacitance for each
|In |   A0  1
Sout = 2 · (7)
|Vtan k |2  C I  ω2
tuning step. Therefore, the normalized output amplitude of the
Colpitts oscillator is given by
where Sout denotes the phase noise spectral density, |In |  is
2  

 C1 + Cπ
the average input white noise power of the transistor, Vtank is Vo  ≈ 2Ic Rtan k 1 − ηcolp

· 1+ (10)
Cei,i=0
the tank swing, A0 is the element A of the ABCD matrix, C I

where, ηcolp = (Cei,i=0 + C)/(C1 + Cπ + (Cei,i=0 + C)) .
is the imaginary part of the capacitive element in the matrix,
and ω is the offset from the carrier angular frequency. The From [26], A0 and C I is given by
output amplitude of the Colpitts oscillator is given by [27] Cei,i=0
A0 = − (11)
2Ic (C1 + Cπ )
Vo = (8) C I = −2(C1 + Cπ + Cei,i=0 ). (12)
gmc
where gmc is the minimum required transconductance for the Substituting (10)–(12) into (7), the phase noise of the
oscillator startup. In the Colpitts oscillator, the equivalent Colpitts oscillator can be obtained as shown in (13) at the
base–emitter capacitance (C1 +Cπ ) and equivalent capacitance bottom of this page.
connected between the emitter terminals of transistors Q 1
and Q 2 (Cei,i=0 ) generate the required negative resistance B. High PAE Amplifier and LO Distribution
to sustain the oscillation. Due to the operation of active
transistors of the Colpitts oscillator in Class-C mode [27] and From the PLLS perspective, the VCO output is shared
loading of the capacitive element on the VCO tank circuit, between the transmitter, receiver, and PLL blocks. Therefore,
the oscillation amplitude of the Colpitts oscillator can be the VCO is followed by a low power high PAE variable gain
expressed as amplifier to generate sufficient power level to drive signals
for the LO chain and transceiver portion with low power
Vo = 2Ic Rtan k (1 − ηcolp ) (9) consumption. The use of amplifier in the LO path also reduces

2 2
1 |In |  Cei,eq 1
Sout = 
  2 · (13)
2  C 1 +C π (C1 + Cπ )2 · (C1 + Cπ + Cei,eq )2 ω2
2Ic Rtan k 1 − ηcolp · 1+ C ei,eq

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 MAHALINGAM et al.: 30-GHz POWER-EFFICIENT PLL FREQUENCY SYNTHESIZER 4171

Fig. 16. Die microphotograph of high PAE amplifier.

Fig. 18. Amplifier PAE versus input power. (a) VSW = 00 and
(b) VSW = 11.

Fig. 17. Measured performance of high PAE amplifier.

the design complexity and output power requirement of

the VCO.
The schematic of the fully differential two-stage amplifier
is implemented in stacked current reuse topology as shown
in Fig. 6 [28]. To optimize for the gain control in different
channels, 4-bit digitally controlled variable current and 2-bit
transformer-based LC tank tuning is employed in the first
and second stage of the amplifier, respectively. In comparison
with the stand-alone inductive load, the transformer-based
frequency tunable load in the second stage improves the Fig. 19. Die microphotograph of PLLS .
effective quality factor of the tank circuit. This increase in the
tank quality factor improves the amplifier’s overall peak gain,
PAE and linearity due to reduced losses in the tank circuit. always biased in active region and only the bottom stage
In the high PAE amplifier, the P1dB is determined by the transistors Q 1,2 moves earlier toward saturation that results
VCE voltage of the bottom stage differential pair transistors, in compression. The circuit operation is illustrated in detail
Q 1,2 as shown in Fig. 6. The top stage transistors Q 3,4 are in [28].

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 4172 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 11, NOVEMBER 2017

Fig. 20. PLLS measurement setup.

To reduce the overall power consumption of the PLLS and

the transceiver, the LO distribution is an important aspect
in the PLLS design. The transmission line LO distribution
network in the proposed PLLS is shown in Fig. 7. To improve
the matching and reduce the transmission line losses, the dis-
tribution network to the transmitter and receiver portion are
implemented in the top metal layer with a width of 10 μm.
The output of the amplifier to the divider is implemented in
Metal 5 with a width of 10 μm. The simulated matching and
loss of the LO distribution network is shown in Figs. 8 and 9,
respectively. Since the blocks in the transmitter and receiver
Fig. 21. Measured PLLS phase noise.
chain are designed for 50  to enable design reusability,
the transmission lines in the LO distribution network are
also matched to 50 . Also, the loss in the PLLS divider cost of increased chip area and power consumption. To reduce
chain is increased to ensure linearity of the high-frequency the power consumption with reduced hardware, it is possible
divider. to increase the word length of the first stage by 1-bit and
reduce the word length in other stages [31]. Therefore, in this
C. Divider Chain paper, after careful optimization, word length of 20, 15, and 10
The divider chain of the PLLS is composed of high are chosen for the first, second, and third stage, respectively.
frequency divide-by-2, fixed divide-by-8, and multimodulus This choice can provide the same performance as word length
divider. The multimodulus divider (MMD) is comprised of a of 19 for all the three stages but the power consumption can
divide-by-3/4 dual modulus prescaler (DMP), MMD control be reduced up to 25% MHz. The simulation spectrum of the
(MMDC) and SDM. The implementation detail of the circuit SDM is shown in Fig. 11.
blocks in the divider chain is presented in this section.
In the PLLS , the high frequency divider chain consists of D. PFD, Charge Pump, and Loop Filter
four static ECL divide-by-two. The ECL divider chain in the As shown in Fig. 1, the reference frequencies are supplied
proposed PLLS is optimized for low power consumption by from an external reference source. The output of the frequency
scaling the load resistor in the latch of cascaded ECL divider reference is fed to the PFD, which is implemented in standard
stages. tri-state topology. The delay select in the PFD is used to
As shown in Fig. 1, the MMD comprising of a divide-by- control the delay of the reset path in the PFD, to overcome
3/4 DMP, MMDC, and SDM implemented in CMOS logic is the dead-zone due to the nonideal characteristic of the CP
the last stage in the divider chain. switches resulting from finite transistor resistance.
The logic structural schematic of SDM is shown in Fig. 10. The schematic of the CP circuit used in this paper is shown
In order to achieve high-speed operation and low power in Fig. 12. The CP core is current steering CP with wide swing
consumption, seven-stage pipeline architecture is chosen in cascode current mirror for high-speed operation and increased
this paper. The maximum delay for each stage is optimized linearity. One of the drawbacks in the current steering CP is
to achieve high speed operation [29]. For the accumulator, leakage current due to the use of current switches in the output
5-bit ripple carry adder is chosen due to its small area and node. Therefore, a unity gain buffer is employed to maintain
low power consumption. The accumulator is one of the key the same voltage at the output node and the current steering
components in the SDM where a better frequency resolution node. Also, to compensate for the change in VCO gain and to
can be achieved with increased word length [30] but at the maintain loop filter parameters, a variable current control using

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 MAHALINGAM et al.: 30-GHz POWER-EFFICIENT PLL FREQUENCY SYNTHESIZER 4173

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON OF PLL S

digital control bits is used in the CP. To reduce the overall chip, The stand-alone die microphotograph and measurement
only second-order loop filter is used in this work. result of the high PAE amplifier is shown in Figs. 16–18,
respectively. The amplifier achieves a gain range of 20 dB with
a peak gain of 15 dB. The peak gain variation in comparison
IV. E XPERIMENTAL R ESULTS
with the simulation is around 3.8 and 5.2 dB for the maximum
The PLLS , shown in Fig. 1, has been fabricated in Tower and minimum gain, respectively. The maximum output P1dB
Jazz 0.18-μm SiGe BiCMOS with six metal layers and f T at the frequency of 32.5 GHz is 11 dBm. Also, the amplifier
of 200 GHz. An on-chip slave SPI controls the digital bits achieves a PAE of 40% to 60% in the interested frequency
used for current control, frequency tuning, power down logic, range of 28 to 32 GHz.
and various other control lines. A PTAT current reference is
used to provide accurate current bias for the different blocks
in the PLLS . The inductors and transformer in the circuit B. Measurement of PLLS
blocks are implemented in the 2.81-μm-thick top metal layer. The PLLS in this work is intended to be integrated in the
All the circuit blocks in the PLLS are powered with a single 60-GHz transceiver, and the die microphotograph is shown in
supply voltage of 1.8 V. The individual circuit blocks and the Fig. 19. The chip area of the proposed PLLS with internal loop
integrated PLLS performance is measured on-wafer and the filter and on-wafer probing pads is 2.8 ×1.86 mm2 . Excluding
corresponding measured result is presented in this section. the loop filter, the PLLS occupies an area of 1.1 × 1.6 mm2 .
The on-wafer measurement setup is shown in Fig. 20. The ref-
erence frequency input is provided by Agilent MXG N5183A
A. Measurement of VCO and High PAE Amplifier signal generator and the SPI slave to control the digital tuning
The measured frequency tuning range of the VCO is shown bits in the PLLS is controlled using a self-programmed SPI
in Fig. 13. The VCO achieves a tuning range from 29.5 to software. The PLLS is powered by from a single 1.8-V supply
33.4 GHz with a K VCO of 550 MHz/V, in the linear region and the power consumption is 63 mW, of which 9.6, 5.4, 22.5,
of the tuning curve. The measured average single-end output 24, and 1.2 mW are consumed by the CLCT VCO, buffer, high
power of VCO and buffer across the frequency tuning range PAE amplifier, divider chain, and other blocks, respectively.
is shown in Fig. 14. The measured output power is −5 to The measured PLL phase noise is shown in Fig. 21. The phase
−12 dBm including the simulated buffer loss of 3.1 dB. The noise at 10 kHz, 100 kHz, 1 MHz, and 10 MHz offset from
measured VCO phase noise across frequency tuning range the carrier is −80, −91, −97, −118 dBc/Hz, respectively. The
is shown in Fig. 15. In comparison with the simulation, measured reference spur level is −40 dBc. The integrated rms
a frequency variation of 3% to 6% is observed across the noise from 10 kHz to 10 MHz is 2.05° rms, 2.01° rms, and
VCO frequency tuning range. 3.36° rms at the frequency of 30.24, 31.32, and 32.4 GHz,

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 4174 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 11, NOVEMBER 2017

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in 45 nm CMOS for mm-wave communication applications,” IEEE
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 MAHALINGAM et al.: 30-GHz POWER-EFFICIENT PLL FREQUENCY SYNTHESIZER 4175

Nagarajan Mahalingam (S’12–M’16) received Kaixue Ma (M’05–SM’09) received the B.E. and
the B.E. degree in electronics and communication M.E. degrees from Northwestern Polytechnolgical
engineering from Bharathidasan University, University, Xi’an, China, and the Ph.D. degree from
Tiruchirappalli, India, in 2001, the M.S. degree Nanyang Technological University, Singapore.
in electrical engineering from The University of From 1997 to 2002, he was with the China Acad-
Texas at Arlington, Arlington, TX, USA, in 2005, emy of Space Technology, Xi’an, where he was a
and the Ph.D. degree from Nanyang Technological Group Leader of the Millimeter-Wave Group for
University (NTU), Singapore, in 2016. space-borne microwave and millimeter-wave com-
In 2006, he joined Advanced RFIC (S) Private ponents and subsystems of satellite payload and
Limited, Singapore, as an IC Design Engineer, VSAT ground stations. From 2005 to 2007, he was
where he was involved in frequency synthesizers a Research and Development Manager and Project
for portable wireless and data converter applications. In 2008, he joined Leader with MEDs Technologies, Singapore, where he was involved in design
the Circuits and Systems Division, School of Electrical and Electronic services and product development. From 2007 to 2010, he was a Research
Engineering, NTU, as a Research Associate, where he was involved in low and Development Manager, Project Leader, and Technique Management
power designs for wireless and biomedical applications. Since 2010, he has Committee with ST Electronics (Satcom & Sensor Systems), Singapore. From
been an Integral Member of the 60 GHz Team at NTU, which has developed 2010 to 2013, he was a Senior Research Fellow and Millimeter-Wave IC
the VIRTUS chipset. He is currently a Post-Doctoral Research Fellow with Team Leader of 60-GHz flagship chipset project and successfully developed
the Singapore University of Technology and Design, Singapore. His current the reconfigurable 60-GHz system-on-chip and demo system. Since 2013,
research interests include radio and millimeter-wave integrated circuit design he has been a Full Professor with the University of Electronic Science
with focus on oscillators and frequency synthesizers. and Technology of China, Chengdu, China. He holds 16 patents and has
authored or co-authored over 180 international journal and conference papers.
His current research interests include RFIC design, satellite communication,
software-defined radio, microwave/ millimeter-wave circuits and systems
Yisheng Wang received the B.E. degree in elec- using CMOS, MEMS, MMICs, and LTCC.
tronic engineering from the Huazhong University of Dr. Ma was a recipient of the Best Paper Award from the IEEE SOCC2011,
Science and technology, Wuhan, China, in 2001, the IEEK SOC Design Group Award, the Excellent Paper Award from the
and the M.S. degree in electrical engineering International Conference on HSCD2010, the Chip Design Competition Bronze
from Nanyang Technological University, Singapore, Award from ISIC2011, the Special Mention Award of Emerging Technology,
in 2013. Since 2016, he has been pursuing the Ph.D. Singapore Inforcomm Technology Federation for the development of the
degree at the Singapore University of Technology Singapore next generation Wi-Fi Chipset 2012, and named in the “China
and Design, Singapore. Thousand Young Talent Program” in 2012. He was named in “The National
From 2001 to 2003, he was a full-time Trainee Distinguished Young Scholar Program” in 2016. He is on the Review Board
with the Institute of Microelectronics (IME), for several international journals. He has given invited talks and keynote
Singapore. He was working within the industry in addresses over 20 times.
Singapore, where he was involved in the field of digital integrated circuit (IC)
design, field-programmable gate arrays, and embedded system design. When
he joined IME as a Research Engineer in 2007, he was involved in low-power
digital IC design for wireless communication. In 2010, he joined Nanyang
Technological University, as a Research Associate to focus on the 60-GHz
chipset development. His current research interest includes low-power and
high-speed digital IC design.

Bharatha Kumar Thangarasu (S’12–M’16)

received the B.E. degree in electronics and
communication engineering from the Ratreeya
Vidyalaya College of Engineering, Bangalore,
India, which is affiliated to the Visvesvaraya
Technological University, Belagavi, India, in 2002,
the M.Sc. degree from the German Institute
of Science and Technology, Singapore (a joint
master’s degree program by Nanyang Technological
University (NTU), Singapore, and Technische Kiat Seng Yeo (M’00–SM’09–F’16) was an Asso-
Universitaet Muenchen, Munich, Germany), in ciate Chair (Research), the Head of circuits and
2010, and the Ph.D. degree in electrical engineering from NTU, in 2015. systems, and the Director of VIRTUS with Nanyang
From 2010 to 2015, he was with VIRTUS, IC Design Center for Excellence, Technological University, Singapore. He possesses
NTU, as a Research Associate, where he was involved in SiGe-, HBT-, and 25 years of experience in industry, academia, and
CMOS-based reconfigurable amplifiers for microwave and millimeter-wave consultancy. He is currently an Associate Provost
RF integrated circuit design. He is currently a Researcher with the Singapore with the Singapore University of Technology and
University of Technology and Design, Singapore. His current research Design, Singapore. He is a member of the Board
interests include RF and millimeter-wave reconfigurable integrated circuit of Advisors of the Singapore Semiconductor Indus-
design. He has authored or co-authored over 25 journals and conference try Association and a world-renowned authority on
papers. low-power RF/millimeter-wave IC design. He has
Dr. Thangarasu was a recipient of DAAD scholarship during his M.Sc. authored 6 books, 5 book chapters, and over 500 top-tier refereed journal
study. and conference papers in his area of research. He holds 35 patents.

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