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To Describe The Procedures For Using Qsys Software and Design of Basic Nios II Based Embedded System

This document provides an overview of the objectives and procedures for a lab on real-time embedded systems using the Qsys software and Nios II processor. The goals of the lab are to design digital systems using HDL modeling, manipulate basic building blocks of Nios II systems using software and hardware platforms, and write effective lab reports. The document introduces Nios II, describes Qsys and its advantages for system integration, and explains the hardware generation and software creation processes used to develop Nios II systems. It provides details on defining a sample system in Qsys using components like the Nios II processor, on-chip memory, JTAG UART, ALTPLL, and a system ID peripheral.

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37 views

To Describe The Procedures For Using Qsys Software and Design of Basic Nios II Based Embedded System

This document provides an overview of the objectives and procedures for a lab on real-time embedded systems using the Qsys software and Nios II processor. The goals of the lab are to design digital systems using HDL modeling, manipulate basic building blocks of Nios II systems using software and hardware platforms, and write effective lab reports. The document introduces Nios II, describes Qsys and its advantages for system integration, and explains the hardware generation and software creation processes used to develop Nios II systems. It provides details on defining a sample system in Qsys using components like the Nios II processor, on-chip memory, JTAG UART, ALTPLL, and a system ID peripheral.

Uploaded by

Muhammad Moin
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EEE-446 Real Time Embedded Systems Lab

To describe the procedures for using Qsys software and


design of basic Nios II based embedded system
Table of Contents

❑ Lab CLO’s
❑ Objectives of Lab
❑ Nios II System
❑ Qsys
❑ Advantages of using Qsys
❑ Development Processes
Lab CLO’s

❑ To design the digital systems based on HDL modelling techniques using the knowledge of VHDL.
(PLO3-C5)
❑ To manipulate the basic building blocks of a Nios II based embedded systems using Software and
Hardware Platforms. (PLO5-P5)
❑ To explain and write effective lab reports of experiments performed during lab. (PLO10-A3)
Objectives of Lab

❑ Introduction to Nios II System


❑ To Recognize the Qsys
❑ To Create a system Using Qsys
Nios II System

❑ Nios II is a 32-bit embedded-processor architecture designed specifically for

the Altera family of field-programmable gate array (FPGA) integrated circuits.

❑ Nios II architecture is a RISC soft-core architecture which is implemented entirely in

the programmable logic and memory blocks of Altera FPGAs.

❑ Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios.

❑ The Nios II processor can be used with a variety of other components to form a

complete system.
Qsys

❑ Qsys is a powerful system integration tool which is included as part of the


Quartus II software
❑ Simplifies Complex System Design
❑ Qsys captures system level hardware designs at a relatively high level of
abstraction and also automates the task of defining and integrating customized
HDL components
❑ You can implement an entire design using components from the Altera
component library
❑ Qsys automatically creates high-performance interconnect logic from the
connectivity options you specify, eliminating the error- prone and time
consuming task of writing HDL to specify the system-level connections.
Advantages of using Qsys

Qsys provides the following advantages for hardware system design:

❑ Automates the process of customizing and integrating components

❑ Supports modular system design

❑ Supports visualization of large systems

❑ Supports optimization of interconnect fabric and pipelining within the system

❑ Fully integrated with the Quartus II software


Development Processes
The development for Nios II consists of two separate steps: hardware generation and software
creation.

Hardware and Software generation process

Nios II hardware designers use the Qsys system integration tool, a component of the Quartus-II
package, to configure and generate a Nios system.
Defining and Generating the System in Qsys
The design you build in this lab is a small NIOS II system consist of the
following components.

❑ Nios II/s processor core

❑ On-chip memory

❑ JTAG UART

❑ ALTPLL

❑ System ID peripheral
System ID Peripheral
❑ System ID is for systems involving multiple processors.

❑ System ID also prevents you from having a mismatch between your hardware and software configurations.

When you compile the software, it stores the system ID of the SOPC Builder/QSYS project at the time of

the compile.
In case of any query email at [email protected]

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