UNIT – III

8086 INTERRUPTS:

An interrupt is the method of processing the microprocessor by peripheral device. An

interrupt is used to cause a temporary halt in the execution of program. Microprocessor
responds to the interrupt with an interrupt service routine, which is short program or
subroutine that instructs the microprocessor on how to handle the interrupt.

There are two basic type of interrupt, maskable and non-maskable, nonmaskable
interrupt requires an immediate response by microprocessor, it usually used for serious
circumstances like power failure. A maskable interrupt is an interrupt that the
microprocessor can ignore depending upon some predetermined upon some predetermined
condition defined by status register.

Interrupt can divide to five groups: 1. hardware interrupt

2. Non-maskable interrupts

3. Software interrupt

4. Internal interrupt

5. Reset

Hardware, software and internal interrupt are service on priority basis. Each interrupt
is given a different priority level by assign it a type number. Type 0 identifies the highest-
priority and type 255 identifies the lowest- priority interrupts. The 80x86 chips allow up to
256 vectored interrupts. This means that you can have up to 256 different sources for an
interrupt and the 80x86 will directly call the service routine for that interrupt without any
software processing. This is in contrast to no vectored interrupts that transfer control
directly to a single interrupt service routine, regardless of the interrupt source.

The 80x86 provides a 256 entry interrupt vector table beginning at address 0:0 in
memory. This is a 1K table containing 256 4-byte entries. Each entry in this table contains a
segmented address that points at the interrupt service routine in memory. The lowest five
types are dedicated to specific interrupts such as the divide by zero interrupt and the non
maskable interrupt. The next 27 interrupt types, from 5 to 31 are High priority 3 reserved by
Intel for use in future microprocessors. The upper 224 interrupt types, from32 to 255, are
available to use for hardware and software interrupts.
 When an interrupt occurs (shown in figure 1), regardless of source, the 80x86 does
the following:

1. The CPU pushes the flags register onto the stack.

2. The CPU pushes a far return address (segment: offset) onto the stack, segment value first.

3. The CPU determines the cause of the interrupt (i.e., the interrupt number) and fetches
the four byte interrupt vector from address 0: vector*4.

4. The CPU transfers control to the routine specified by the interrupt vector table entry

PROCESSING OF AN INTERRUPT:
Hardware and Software Interrupts:

Hardware interrupts:

 The nonmaskable interrupt is generated by en external device, trough a rising edge on

the NMI pin
 An external device, trough a high logic level on the INTR pin (the external device has to
specify the interrupt number).
Software interrupts: Software interrupts (exceptions) using the INT instruction (followed by
the interrupt number (type)).
Interrupt Vector Table:

An "interrupt vector table" (IVT) is a data structure that associates a list of interrupt
handlers with a list of interrupt requests in a table of interrupt vectors. An entry in the
interrupt vector is the address of the interrupt handler. While the concept is common across
processor architectures, each IVT may be implemented in an architecture-specific fashion.
For example, a dispatch table is one method of implementing an interrupt vector table.

The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing the
starting addresses of Interrupt Service Procedures (ISP). Since 4-bytes are required for
storing starting addresses of ISPs, the table can hold 256 Interrupt procedures. The starting
address of an ISP is often called the Interrupt Vector or Interrupt Pointer. Therefore the table
is referred as Interrupt Vector Table. In this table, IP value is put in as low word of the vector
& CS is put in high vector.

Dedicated interrupts of 8086:

The following are the various types of interrupts:

- Type 0 interrupts: This interrupt is also known as the divide by zero interrupt. For cases
where the quotient becomes particularly large to be placed / adjusted an error might occur.
- Type 1 interrupts: This is also known as the single step interrupt. This type of interrupt is
primarily used for debugging purposes in assembly language.
- Type 2 interrupts: also known as the non-maskable NMI interrupts. These type of
interrupts are used for emergency scenarios such as power failure.
- Type 3 interrupts: These type of interrupts are also known as breakpoint interrupts. When
this interrupt occurs a program would execute up to its break point.

-Type 4 interrupts: Also known as overflow interrupts is generally existent after an arithmetic
operation was performed.

Interrupt Priority Structure

Bios interrupts:

BIOS interrupt calls are a facility that operating systems and application programs use
to invoke the facilities of the Basic Input/Output System on IBM PC compatible computers.
Traditionally, BIOS calls are mainly used by MS-DOS programs and some other software such
as boot loaders (including, mostly historically, relatively simple application software that
boots directly and runs without an operating system—especially game software.) BIOS only
runs in the real address mode (Real Mode) of the x86 CPU, so programs that call BIOS either
must also run in real mode or must switch from protected mode to real mode before calling
BIOS and then switch back again. For this reason, modern operating systems that use the
CPU in Protected Mode generally do not use the BIOS to support system functions, although
some of them use the BIOS to probe and initialize hardware resources during their early
stages of booting.
In all computers, software instructions control the physical hardware (screen, disk,
keyboard, etc.) from the moment the power is switched on. In a PC, the BIOS, preloaded in
ROM on the main board, takes control immediately after the processor is reset, including
during power-up or when a hardware reset button is pressed. The BIOS initializes the
hardware, finds, loads and runs the boot program (usually, but not necessarily, an OS
loader), and provides basic hardware control to the operating system running on the
machine, which is usually an operating system but may be a directly booting single software
application.
For IBM's part, they provided all the information needed to use their BIOS fully or to
directly utilize the hardware and avoid BIOS completely, when programming the early IBM
PC models (prior to the PS/2). From the beginning, programmers had the choice of using
BIOS or not, on a per-hardware-peripheral basis. Today, the BIOS in a new PC still supports
most, if not all, of the BIOS interrupt function calls defined by IBM for the IBM
AT (introduced in 1984), along with many more newer ones, plus extensions to some of the
originals (e.g. expanded parameter ranges). This, combined with a similar degree of
hardware compatibility, means that most programs written for an IBM AT can still run
correctly on a new PC today, assuming that the faster speed of execution is acceptable
(which it typically is for all but games that use CPU-based timing). Despite the considerable
limitations of the services accessed through the BIOS interrupts, they have proven extremely
useful and durable to technological change.

Interrupt
Description
vector

Executed when Shift-Print screen is pressed, as well as when

05h
the BOUND instruction detects a bound failure.

10h Video Services

AH Description

00h Set Video Mode

01h Set Cursor Shape

02h Set Cursor Position

03h Get Cursor Position And Shape

04h Get Light Pen Position

05h Set Display Page

06h Clear/Scroll Screen Up

07h Clear/Scroll Screen Down

08h Read Character and Attribute at Cursor

09h Write Character and Attribute at Cursor

 0Ah Write Character at Cursor

0Bh Set Border Color

0Ch Write Graphics Pixel

0D
Read Graphics Pixel
h

0Eh Write Character in TTY Mode

0Fh Get Video Mode

10h Set Palette Registers (EGA, VGA, SVGA)

11h Character Generator (EGA, VGA, SVGA)

12h Alternate Select Functions (EGA, VGA, SVGA)

13h Write String

1Ah Get or Set Display Combination Code (VGA, SVGA)

1Bh Get Functionality Information (VGA, SVGA)

1Ch Save or Restore Video State (VGA, SVGA)

4Fh VESA BIOS Extension Functions (SVGA)

11h Returns equipment list

12h Return conventional memory size

 Low Level Disk Services

AH Description

00h Reset Disk Drives

01h Check Drive Status

02h Read Sectors

03h Write Sectors

04h Verify Sectors

05h Format Track

13h
08h Get Drive Parameters

09h Init Fixed Drive Parameters

0Ch Seek To Specified Track

0D
Reset Fixed Disk Controller
h

15h Get Drive Type

16h Get Floppy Drive Media Change Status

17h Set Disk Type

18h Set Floppy Drive Media Type

 41h Extended Disk Drive (EDD) Installation Check

42h Extended Read Sectors

43h Extended Write Sectors

44h Extended Verify Sectors

45h Lock/Unlock Drive

46h Eject Media

47h Extended Seek

48h Extended Get Drive Parameters

49h Extended Get Media Change Status

4Eh Extended Set Hardware Configuration

14h Serial port services

AH Description

00
Serial Port Initialization
h

01
Transmit Character
h

02
Receive Character
h

03 Status
 h

15h Miscellaneous system services

AH AL Description

00h Turn on cassette drive motor

01h Turn off cassette drive motor

02h Read data blocks from cassette

03h Write data blocks to cassette

4Fh Keyboard Intercept

83h Event Wait

84h Read Joystick

85h Sysreq Key Callout

86h Wait

87h Move Block

88h Get Extended Memory Size

89h Switch to Protected Mode

C0h Get System Parameters

C1h Get Extended BIOS Data Area Segment

 C2h Pointing Device Functions

C3h Watchdog Timer Functions - PS/2 systems only

C4h Programmable Option Select - MCA bus PS/2 systems only

D8
EISA System Functions - EISA bus systems only
h

Get Extended Memory Size (Newer function, since 1994). Gives

E8h 01h
results for memory size above 64 Mb.

Query System Address Map. The information returned

E8h 20h from E820 supersedes what is returned from the
older AX=E801h and AH=88hinterfaces.

Keyboard services

AH Description

00
Read Character
h

01
Read Input Status
h

16h
02
Read Keyboard Shift Status
h

05
Store Keystroke in Keyboard Buffer
h

10
Read Character Extended
h

11 Read Input Status Extended

 h

12
Read Keyboard Shift Status Extended
h

Printer services

AH Description

00
Print Character to Printer
h
17h

01
Initialize Printer
h

02
Check Printer Status
h

Execute Cassette BASIC: Very early true IBM computers contain Microsoft
Cassette BASIC in the ROM, to be started by this routine in the event of a failure
18h to boot from disk (called by the BIOS). On virtually all clones and later models in
the PC line from IBM, which lack BASIC in ROM, this interrupt typically displays a
message such as "No ROM BASIC" and halts.

After POST this interrupt is used by BIOS to load the operating system. A
program can call this interrupt to reboot the computer (but must ensure that
19h hardware interrupts or DMA operations will not cause the system to hang or
crash during either the reinitialization of the system by BIOS or the boot
process).

1Ah Real Time Clock Services

AH Description

00
Read RTC
h
 01
Set RTC
h

02
Read RTC Time
h

03
Set RTC Time
h

04
Read RTC Date
h

05
Set RTC Date
h

06
Set RTC Alarm
h

07
Reset RTC Alarm
h

PCI Services - implemented by BIOSes supporting PCI 2.0 or later

AX Description

B101h PCI Installation Check

1Ah B102h Find PCI Device

B103h Find PCI Class Code

B106h PCI Bus-Specific Operations

B108h Read Configuration Byte

 B109h Read Configuration Word

B10Ah Read Configuration Dword

B10Bh Write Configuration Byte

B10Ch Write Configuration Word

B10Dh Write Configuration Dword

B10Eh Get IRQ Routine Information

B10Fh Set PCI IRQ

1Bh Ctrl-Break handler - called by INT 09 when Ctrl-Break has been pressed

1Ch Timer tick handler - called by INT 08

Not to be called; simply a pointer to the VPT (Video Parameter Table), which
1Dh
contains data on video modes

Not to be called; simply a pointer to the DPT (Diskette Parameter Table),

1Eh
containing a variety of information concerning the diskette drives

Not to be called; simply a pointer to the VGCT (Video Graphics Character Table),
1Fh
which contains the data for ASCII characters 80h to FFh

41h Address pointer: FDPT = Fixed Disk Parameter Table (1st hard drive)

46h Address pointer: FDPT = Fixed Disk Parameter Table (2nd hard drive)

4Ah Called by RTC for alarm

MEMORY AND I/O INTERFACING:

I/O Interface
Introduction:
Any application of a microprocessor based system requires the transfer of data
between external circuitry to the microprocessor and microprocessor to the external
circuitry. User can give information to the microprocessor based system using keyboard and
user can see the result or output information from the microprocessor based system with
the help of display device. The transfer of data between keyboard and microprocessor, and
microprocessor and display device is called input/output data transfer or I/O data transfer.
This data transfer is done with the help of I/O ports.
Input port:
It is used to read data from the input device such as keyboard. The simplest form of
input port is a buffer. The input device is connected to the microprocessor through buffer, as
shown in the fig.1. This buffer is a tri-state buffer and its output is available only when
enable signal is active. When microprocessor wants to read data from the input device
(keyboard), the control signals from the microprocessor activates the buffer by asserting
enable input of the buffer. Once the buffer is enabled, data from the input device is available
on the data bus. Microprocessor reads this data by initiating read command.

It is used to read data from the input device such as keyboard. The simplest form of
input port is a buffer. The input device is connected to the microprocessor through buffer, as
shown in the fig.1. This buffer is a tri-state buffer and its output is available only when
enable signal is active. When microprocessor wants to read data from the input device
(keyboard), the control signals from the microprocessor activates the buffer by asserting
enable input of the buffer. Once the buffer is enabled, data from the input device is available
on the data bus. Microprocessor reads this data by initiating read command.

Output port:
It is used to send data to the output device such as display from the microprocessor.
The simplest form of output port is a latch. The output device is connected to the
microprocessor through latch, as shown in the fig.2. When microprocessor wants to send
data to the output device is puts the data on the data bus and activates the clock signal of
the latch, latching the data from the data bus at the output of latch. It is then available at the
output of latch for the output device.

There are three different ways that the data transfer can take place. They are
(1) Program controlled I/O
(2) Interrupt Program Controlled I/O
(3) Hardware controlled I/O
In program controlled I/O data transfer scheme the transfer of data is completely
under the control of the microprocessor program. In this case an I/O operation takes place
only when an I/O transfer instruction is executed. In an interrupt program controlled I/O an
external device indicates directly to the microprocessor its readiness to transfer data by a
signal at an interrupt input of the microprocessor. When microprocessor receives this signal
the control is transferred to ISS (Interrupt service subroutine) which performs the data
transfer. Hardware controlled I/O is also known as direct memory access DMA. In this case
the data transfer takes place directly between an I/O device and memory but not through
microprocessors. Microprocessor only initializes the process of data transfer by indicating
the starting address and the number of words to be transferred. The instruction .set of any
microprocessor contains instructions that transfer information to an I/O device and to read
information from an I/O device.
In 8086 we have IN, OUT instructions for this purpose. OUT instruction transfers
information to an I/O device whereas IN instruction is used to read information from an I/O
device. Both the instructions perform the data transfer using accumulator AL or AX. The I/O
address is stored in register DX. The port number is specified along with IN or OUT
instruction. The external I/O interface decodes to find the address of the I/O device. The 8
bit fixed port number appears on address bus A0 - A7 with A8 - A15 all zeros. The address
connections above A15 are undefined for an I/O instruction. The 16 bit variable port number
appears on address connections A0 - A15. The above notation indicates that first 256 I/O
port addresses 00 to FF are accessed by both the fixed and variable I/O instructions. The I/O
addresses from 0000 to FFFF are accessed by the variable I/O address.
I/O devices can be interfaced to the microprocessors using two methods. They are
I/O mapped I/O and memory mapped I/O. The I/O mapped I/O is also known as isolated I/O
or direct I/O. In I/O mapped I/O the IN and OUT instructions transfer data between the
accumulator or memory and I/O device. In memory mapped I/O the instruction that refers
memory can perform the data transfer.

I/O mapped I/O is the most commonly used I/O transfer technique. In this method
I/O locations are placed separately from memory. The addresses for isolated I/O devices are
separate from memory. Using this method user can use the entire memory. This method
allows data transfer only by using instructions IN, OUT. The pins M/ IO and W/R are used to
indicate I/O read or an I/O write operations. The signals on these lines indicate that the
address on the address bus is for I/O devices. Memory mapped I/O does not use the IN, OUT
instruction it uses only the instruction that transfers data between microprocessor and
memory.
A memory mapped I/O device is treated as memory location. The disadvantage in
this system is the overall memory is reduced. The advantage of this system is that any
memory transfer instruction can be used for data transfer and control signals like I/O read
and I/O write are not necessary which simplify the hardware.
Memory interfacing
Memory is an integral part of a microcomputer system. There are two main types of
memory.
(i) Read only memory (ROM): As the name indicates this memory is available only
for reading purpose. The various types available under this category are PROM,
EPROM, EEPROM which contain system software and permanent system data.
(ii) (ii) Random Access memory (RAM): This is also known as Read Write Memory. It
is a volatile memory. RAM contains temporary data and software programs
generally for different applications.
While executing particular task it is necessary to access memory to get instruction codes
and data stored in memory. Microprocessor initiates the necessary signals when read or
write operation is to be performed. Memory device also requires some signals to perform
read and write operations using various registers. To do the above job it is necessary to have
a device and a circuit, which performs this task is known as interfacing device and as this is
involved with memory it-is known as memory interfacing device. The basic concepts of
memory interfacing involve three different tasks. The microprocessor should be able to read
from or write into the specified register. To do this it must be able to select the required
chip, identify the required register and it must enable the appropriate buffers.
 Any memory device must contain address lines and Input, output lines, selection input,
control input to perform read or write operation. All memory devices have address inputs
that select memory location within the memory device. These lines are labeled as AO ......
AN. The number of address lines indicates the total memory capacity of the memory device.
A 1K memory requires 10 address lines A0-A9. Similarly a 1MB requires 20 lines A0-A19 (in
the case of 8086). The memory devices may have separate I/O lines or a common set of
bidirectional I/O lines.
Using these lines data can be transferred in either direction. Whenever output buffer is
activated the operation is read whenever input buffers are activated the operation is write.
These lines are labeled as I/O,......... I/On or DO .............Dn. The size of a memory location is
dependent upon the number of data bits. If the number of data lines is eight D0 - D7 then 8
bits or 1 byte of data can be stored in
each location. Similarly if numbers of data bits are 16 (D0 - D15) then the memory size is 2
bytes. For
Example 2K x 8 indicates there are 2048 memory locations and each memory location can
store 8 bits
of data.
Memory devices may contain one or more inputs which are used to select the
memory device or to enable the memory device. This pin is denoted by CS (Chip select) or
CE (Chip enable). When this pin is at logic '0' then only the memory device performs a read
or a write operation. If this pin is at logic ‘1’ the memory chip is disabled. If there are more
than one CS input then all these pins must be activated to perform read or write operation.
All memory devices will have one or more control inputs. When ROM is used we find
OE output enable pin which allows data to flow out of the output data pins. To perform this
task both CS and OE must be active. A RAM contains one or two control inputs. They are
R /W or RD and WR. If there is only one input R/W then it performs read operation when
R/W pin is at logic 1. If it is at logic 0 it performs write operation. Note that this is possible
only when CS is also active.
Memory Interface using RAMS, EPROMS and EEPROMS:
Semiconductor Memory Interfacing:
Semiconductor memories are of two types, viz. RAM (Random Access Memory) and
ROM (Read Only Memory).
Static RAM Interfacing:
The semiconductor RAMs are of broadly two types-static RAM and dynamic RAM.
The semiconductor memories are organised as two dimensional arrays of memory locations.
For example, 4K x 8 or 4K byte memory contains 4096 locations, where each location
contains 8-bit data and only one of the 4096 locations can be selected at a time. Obviously,
for addressing 4K bytes of memory, twelve address lines are required. In general, to address
a memory location out of N memory locations , we will require at least n bits of address, i.e.
n address lines where n = Log2 N. Thus if the microprocessor has n address lines, then it is
able to address at the most N locations of memory, where 2n = N. However, if out of N
locations only P memory locations are to be interfaced, then the least significant p address
lines out of the available n lines can be directly connected from the microprocessor to the
memory chip while the remaining (n-p) higher order address lines may be used for address
decoding (as inputs to the chip selection logic). The memory address depends upon the
hardware circuit used for decoding the chip select ( CS ).
The output of the decoding circuit is connected with the CS pin of the memory chip.
The general procedure of static memory interfacing with 8086 is briefly described as follows:
1. Arrange the available memory chips so as to obtain 16-bit data bus width. The
upper 8-bit bank is called ‘odd address memory bank’ and the lower 8-bit bank is called
‘even address memory bank’.
2. Connect available memory address lines of memory chips with those of the
microprocessor and also connect the memory RD and WR inputs to the corresponding
processor control signals. Connect the 16-bit data bus of the memory bank with that of the
microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and A0 are used for
decoding the required chip select signals for the odd and even memory banks. CS of
memory is derived from the O/P of the decoding circuit.
As a good and efficient interfacing practice, the address map of the system should be
continuous as far as possible, i.e. there should be no windows in the map. A memory
location should have a single address corresponding to it, i.e. absolute decoding should be
preferred, and minimum hardware should be used for decoding. In a number of cases, linear
decoding may be used to minimize the required hardware. Let us now consider a few
example problems on memory interfacing with 8086.
UNIT-IV

8255 PPI: