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Introduction To VHDL: Boumerdes University

This document describes Lab Work #6 on designing combinational digital circuits using VHDL. The objectives are to enhance familiarity with Altera Quartus II and writing VHDL codes. Problem 1 involves designing a majority gate circuit. Problem 2 designs a bar graph LED display. Problem 3 displays different shapes using a 2-input 7-output logic circuit. Problem 4 outputs a '1' only when the corresponding input is '1'. Problem 5 is a hexadecimal to 7-segment display converter. The conclusion is that this lab increased familiarity with VHDL statements to solve various problems.

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Ti Na
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52 views

Introduction To VHDL: Boumerdes University

This document describes Lab Work #6 on designing combinational digital circuits using VHDL. The objectives are to enhance familiarity with Altera Quartus II and writing VHDL codes. Problem 1 involves designing a majority gate circuit. Problem 2 designs a bar graph LED display. Problem 3 displays different shapes using a 2-input 7-output logic circuit. Problem 4 outputs a '1' only when the corresponding input is '1'. Problem 5 is a hexadecimal to 7-segment display converter. The conclusion is that this lab increased familiarity with VHDL statements to solve various problems.

Uploaded by

Ti Na
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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BOUMERDES UNIVERSITY

INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERING

I.G.E.E ( ex- INELEC)

(EE-221)

Lab Work # 6

Introduction to VHDL
Design, Simulation and Implementation of Combinational
Digital Circuits using VHDL Design Entry

Written by:
 Cylia LEBAZ

Parteners’ name:
 Lisa KEZMANE
 Rayane GHERNAOUT

Groupe : 08
Lab Instructor: Mrs.AZZOUGUI
Objectives:
The objective of this laboratory experiment is to enhance our familiarity with
Altera Quartus II Schematic and VHDL design and also to practice writing VHDL
codes for basic combinational circuits using concurrent statements.

Getting Started:
We launch Quartus II → File → New Project Wizard → we set working
directory, project name ad Top-Level Design→ We choose Cyclone II as target
Device Family and from the list of available devices we choose the
EP2C35F672C6.

We set Pin Count to 672 and Speed Grade to 6 in order to limit the device
selection.

To create a VHDL source code file we select from Quartus II window


File → New → VHD File → OK

Problem 01 : Majority
T .T a b c d M F=
0 0 0 0 0 K-map
0 0 0 1 0
0 0 1 0 0
0 0 0 0
0 0 1 1 0
0 0 1 0
0 1 0 0 0
1 1 1 1
0 1 0 1 0
0 1 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1 F = AB + AC + AD + BCD
1 0 1 0 1
1 0 1 1 1 F = A(B + C + D) + BCD
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

i. VHDL code using direct signal assignment statement


ii. The function simulation :

iii. After assigning the input and output pins, we downloaded our design
onto the EPGA of the DE2 board in order to test its functionality.
Everything was corrected and worked good.
iv. Circuit synthesized
Tools → Netlist Viewer → RTL Viewer
Problem 02 : Bar-Graph LED
T .T a b c LED0 LED1 LED2 LED3 LED4 LED5 LED6
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0
0 1 0 1 1 0 0 0 0 0
0 1 1 1 1 1 0 0 0 0
1 0 0 1 1 1 1 0 0 0
1 0 1 1 1 1 1 1 0 0
1 1 0 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1

The VHDL Code using with-select statement

Problem 03 : Displays
In this part, we are asked to design a 2-input 7-output logic circuit , using
when-else statement, to display the different shapes given in the handout
We assigned pins to inputs and outputs and then we download our code to the
DE2 board to test its functionality and it was succefull.

Problem 04 :
For this problem, we wrote a VHDL code for a combinational circuit that has six
inputs W and six outputs Y where an input Yk is to be ‘1’ if and only if Wk is ‘1’
and each Wi = ‘O’ for all i>j.
Problem 05 : Hexadecimal to 7-Segment Display Converter
For the last problem, we wrote a VHDL code of a 7-segment driver for a circuit
that takes 4-bit input and drives the 7-segment display on the DE2 board , using
with-select statement .

Unfortunately we didn’t have enough time during the lab session to download
the 2 last circuits on the DE2 board and test them

Conclusion :
By the end of this lab, which was well conducted, we get become more familiar
with the use of VHDL, with its different statements, to solve a variety of
problems.

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