_ SECOND EDITION

Insights on
MICROPROCESSORS
-~;:::;
B.E. [TU, PU, PoU, KU], BEIT,
B~cnll, BIM, BIT, BCA
 CONTENTS

Ciidhirii
INTRODUCTION
1. 1 Introduction to Microprocessor ........ ... .................. .................. ..... .. 1
1.2 Microprocessor as a CPU (MPU) ..... ... ..... ..... .. .. .. ....... .......... .. .... .... I
1.3 Organization of a Microprocessor-Based System ...... ......... .... ..... ...4
1.4 Bus Organization .................................................... ............ .... ... .... . 6
1.5 Historical Background of the Development of Computers ...... ....... 7
1.6 Stored-Program Concept and Von-Neumann Machine ... ..... ... ..... 10
I. 7 Harvard Architecture .......... .......... .. ... ................................ ... ..... ... 11
1.8 Evolution of Microprocessors (Intel Series) .... .. .......... .. ... ...... ..... . 13
1.9 Processing Cycle of a Stored-Program Computer ...... .. ........ .... .. .. 15
1. IO Micro-Operations and Microinstructions ............................ .... ...... 17
1.1 1 Control Unit... ...... ........... .. ................. .. ......................... ......... ....... I 9
1.12 Register Transfer Language (RTL) .. .......... ....... ...... ..................... 20
I. 13 Applications of Microprocessors ................ ..... ... ... ... ........ ..... ....... 30
tlihhh44
PROGRAMMING WITH 8085 MICROPROCESSOR
2.1 Internal Architecture of 8085 Microprocessor .... ....... ................... 32
2.2 Characteristics (Features) of 8085 Microprocessor ................ .. .... 36
2.3 Instruction Description and Format .. .. .. ............. ........................... 39
2.4 Classification of an Instruction .................... .................. .. ... ... ..... .. 41
2.5 Addressing Modes ...... ............. ....... ........................ :...................... 70
2.6 Time Delay and Counter.. ................ ...... ............ ...... .. .... ... .... ........ 72
2.7 Number Conversion ................................ ................................ ..... . 74
2.8 Multiplication and Division ................................... ... .. ... ......... ...... 82
ADDITIONA!, QUESTIONS...................................................... 84
tlifihhiii
PROGRAMMING WITH 8086 MICROPROCESSOR
3.1 Introduction ........................... ... ... ....................... ............. .. ......... 100
3.2 Internal Architecture of 8086 Microprocessor ............................ 100
3.·3 Instructions in 8086 .......................... .. ...... ... ................... ............ 107
3.4 Operators in 8086 .............................................. ....... ........... .. .. ... 113
3.5 Coding in Assembly Language .. .. .. .. ........... ............................. ... 115
3.6 Assembling, Linking, and Executing .......................................... 123
3. 7 .COM Programs and .EXE Programs ......................................... 126
ADDITIONAL QUESTIONS.................................................... 150
 j§j@I! MICROPROCESSOR SYSTEM
· o£8085 .... ..... ...... .. .... .. ................ ........ .. ..... .. .. 189
-=== Chapter-I!
p· Configuration
4.1
4.2
m
Pin Configuration o
£8086 ........ ........ ................ .............. . 194
·:::::::::: ............................ .. ..... ..... ....... 198
INTRODUCTION
1:~ :sc~t:c;;l~~·~~d·B;~·Timing.~'.~~~~~~..~:..~.~~.~................... 201
Microprocessor .. ......................... .
1.1 Introduction to Microprocessor
4.5 Read and Wnte Bus Timing of 8086 Microprocessor ................ 209 A microprocessor is a multipurpose, programmable, clock-
driven, register-based electronic device that reads binary
4.6 Memory Devi~~sg........................... :·::::::::::::::::::::::::::::::::::::::::::: ~~~
4. 7 Address Oeco ID ......................... • instn;ctions from a storage device called memory, accepts binary
8 Input/Output Devices ............... •.. •• .. ·· .... ·.. ···· .. ·.. ····· .. ··· .. · .. ·· ···.. •••• 226 data as input and processes data according to those instructions,
44. 9 Bit and Baud rate .......................................... .............. ........ ........ 246 and provides results as output.
· Standards in Serial I/O ....................... ·.... ·.. · ·.. · · .... ·· · · .... · · · · · · · · · · · · ·· · 24 7
44.10 Introduction to Direct Memory Access (DMA) & DMA A typical programmable machine can be represented with
.l I Controllers ..................................................... ··· ················ ·········· 253 four components: microprocessor, memory, input, and output as
AJJDITIONAL QUESTIONS.................................................... 257 showh in Figure 1.1. These four components work together or
[•Mfu&i interact with each other to perform a given task; thus, they
INTERRUPT OPERATIONS comprise a system. The physical components of this system are
5.1 Introduction ................................................ ... .............. ............... 270 called hardware. A set of instructions written for the microprocessor
52 Polling versus Interrupt ............................... ............................... 27 I to perform a task is called a program, and a group of programs is
5.3 Interrupt Structures ......................................... ...... .......... ............ 272 called software. The fact that the microprocessor is programmable
5.4 Interrupt Processing Sequence ........................................ ............ 274
means it can be instructed to perform given tasks within its
5.5 Multiple Interrupts and Priorities .......................... .................. .... 276 capability.
5.6 Interrupts Types ................................................................ .......... 278
5. 7 Interrupts in 8085 ...... ....... ... .... ... ...... .. ....... ......... ... ..................... 280
5.8 Interrupts in 8b86 ................................. .................. .................... 287 i -- - Memory
5.9 Priority Interrupt Controller (PIC) .............. ................................ 292
Giitifu&I Microprocessor i -- - , Input
ADVANCED TOPICS
6. 1
6.2 Multiprocessing Systems ........................................................... 295
6.3 :ta! and Pseudo-Parallelism ...................................................... 297 Output
6.4 1 Ynn's Classification ........................................ .............. ........... 298
Pnstrullctlmn Level, Thread Level, and Process Level
ara e ism ......... ..
Figure 1.1 A programmable machine
6.5 Inter-Process Co ....... :... ··:··--·•· .. ·····--···· --·--··········· ····················· 301
Deadlock mmumcation, Resource Allocation, and 1.2 Microprocessor as a CPU (MPU)

!~~
6.6
6.7 Traditionally, the computer is represented with four
~r;:;:i;tg~·;~;~~·::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::~::::
6.8 components: memory, input, output, and central processing unit
RISC and C~~r~pArrocessor Architectures ..................................... 313
6.9 . ch1tectures 314 (CPU), which consists of the arithmetic logic unit (ALU) and the
The Digital Signal Processor (D·s·p·--•--....................................... 31 7
APPENDIX ) .......................................... . control unit (CU). The CPU contains various registers to store data,
Bib/iograph; .................. .. ........... ........ ...... .. ................................ 319
322
INn"ROOUCTION 11
 . an d Jo<Tical operations, . instruction With the advancement in technology, manufacturers were
rithmebc o-
able to place memory and 1/0 interfacing circuits along with MPU
h A LU to perfo rm a i·nes The CPU reads mstructions
t c d contro I 1 ·
on a single chip; this is known as a microcontroller or microcontroller
d..xodl'rs, counters, ~n d performs the tasks specified. It
from the memor~ . an/ tput devices (I/0 devices) either to unit (MCU) . Figure 1.4 shows the block diagram of a
nth inpu t ou microcontroller.
wrnmunicates \ _ he I/0 devices are also known as
acc,•pl or to send da ta, t
Microcontroller
pcnp/icru l<
.. ...CPU MPU
Arithmetic/
Logic Unit
(ALU)
Memory I/0

Input
Output
Peripheral Devices
• AID Converter
• Timer
Figure J.2 Trnditionnl block diagram of ri computer. • Serial 1/0
The advent of integrated circuit technology made possible to Figure 1.4 Block diagram of a microcontroller
build the CPU on a single chip; this was coined microprocessor. A
Differences Between Microprocessor and Microcontroller
computer with a microprocessor as its CPU is known as a
microcomputer The terms microprocessor and microprocessor unit The differences between microprocessor and microcontroller
('v1PU) are often used synonymously. MPU implies a complete
are·
processing unit with the necessary control signals. Because of the Microprocessor Microcontroller
li mited number of available pins on a microprocessor package, ·
A microprocessor is a silicon A microcontroller is an integrated
some of the signals (such as control and multiplexed signals) need
chip representing a central chip that contains a CPU,
to be generated by using discrete devices to make the
microprocessor a complete functional unit or MPU. processing unit (CPU), which is scratchpad RAM, special and
capable of performing general purpose resister arrays, on
arithmetic, as well as logical chip ROM/FLASH memory for
operations according to a program storage, timer and
Jnput Microprocessor as predefined set of instructions. interrupt contirol units, and
CPU Output dedicated 1/0 ports.
It is a dependent unit. It It is a self-contained unit and it
requires the combination of doesn't require external interrupt
other chips like timers, controller, timer, UART, etc, for its
Memory
program and data memory functioning,
Figure 1.3 Block d,u m .,
0
gro 1 11 cvmputer with the microprocessor as CPU chips, interrupt controllers, etc.
for functioning.
2
INSIGHTS ON MICROPROCESSORS

INTRODUCTION 3
 Microcontroller
Microprocessor a. Arithmetic/logic unit: It performs arithmetic operations
of Microcontrollers are mostly such as addition and subtraction, and logic operations
:Microprocessors are mo st
the time general purpose in application-oriented or domain- such as AND, OR, and XOR.
design and operation. specific.
b. Register array: 1bis part consists of various registers
It does not contain a built in Most of the processors contain identified by letters such as B, C, D, E, H , and L. These
I/ O port. The I/0 port multiple built-in 1/0 ports which registers are primarily used to store data temporarily
functiona lity needs to be can be operated as a single 8- or during the execution of a program and are accessible to
implemented with the help of 16- or 32-bit port or as individual the user through instructions.
external programmable port pins. c. Control unit: It provides the necessary timing and
peripheral interface chips like control signals to all the operations in the
8255. microcomputer. It controls the flow of data between the
microprocessor and memory and peripherals.
1.3 Organization of a Microprocessor-Based System
ii. Memory
Microprocessor-based system includes three components:
microprocessor, inpuVoutput, and memory (read-only memory Memory stores binary information such as instructions and
and read/write memory) . Figure 1.5 shows a simplified structure data, and provides that information to the microprocessor
of a microprocessor-based system. whenever necessary. To execute programs, the
microprocessor reads instructions and data from memory
Microprocessor
and performs the computing operations in its ALU section.
1/0 Results are either transferred to the output section for
Input/Output
display or stored in memory for later use. The memory block
ALU Register has two sections:
Array
a. Read-only memory (ROM): The ROM is used to store
programs that do not need alterations. Programs stored
in ROM can only be read; they cannot be altered.
Memory
Control b. Read/write memory or random-access memory
~B
Figure 1.5 Micraprocessor-based system with bus architecture
(RAM): It is also known as user memory which is used to
store user programs and data. The information stored
i. Microprocessor in this memory can be easily read and altered.

It is a clock driven semico d . iii. Input/Output (1/0)

electronic lotMc . . n uctor device consisting of
b. circU1ts manufactur d b .
large-scale integration LS e Y using either a 1/0 includes two types of devices: input and output; these
(VLSI) technique It ~ I) or very-large-scale integration I/ 0 devices are also known as peripherals. The input devices
· 1s capable of f . such as keyboard, switches, and an analog to digital (A/ D)
computing functio d . per ormmg various
ns an makmg d · · converter transfer binary information (data and instructions)
sequence of a p ec1s1ons to change the
segments: rogram execution. It consists of three from the outside world to the microprocessor. The output
devices transfer data from the microprocessor to the outside
INSIGHTS ON
MICROPROCESSORS
4 \
INTRODUCTION 5
 world . They include the devices such as LED, CRT, digital to
analog (D/ A) converter, printer etc.
• The data lines provide a path for moving data between
iv. System Bus system modules. These lines are collectively called data bus.

It is a communication path between the microprocessor anct • The address lines are used . to designate the source/
destination of data on data bus.
peripherals; it is nothing but a group of wires to carry bits.
• The control lines are used to control the access to and the use
1.4 Bus Organization of the data and address lines. Because data and address lines
are shared by all components, there must be a means of
Bus is a group of lines used to transfer bits between the
controlling their use. Control signals transmit both
microprocessor and other components of the computer system. It is
command and timing signals. Timing signals indicate the
a common channel through which bits from any sources can be
· validity of data and address information. Command signals
transferred to the destination. A typical digital computer has many
specify operations to be performed. Control lines include
registers, and paths must be provided to transfer instructions from
memory read/ write, I/ 0 read/ write, bus request/ grant,
one register to another. The number of wires will be excessive if
clock, reset, interrupt request/ acknowledge etc.
separate lines are used between each register and all other registers
in the system. A more efficient scheme for transferring information 1.5 Historical Background of the Development of
between registers in a multiple register configuration is a common Computers
bus system. A bus structure consists of a set of common lines, one
For understanding the historical background of the
for each bit of a register, through which binary information is
development of computers, it is a wise decision to classify
transferred one at a time. Control signals determine which register
computers under mechanical and electronic era.
is selected by the bus during each particular register transfer.
1. Mechanical Era
The mechanical computer namely difference engine and
analytical engine developed by Charles Babbage, the father of
Microprocessor computer can be considered as the forerunners of modern digital
computers.
The difference engine was a mechanical device that could add
and subtract, and could only run a single algorithm. It's output
Figu're 1.6 Bus organization system was incompatible to write on punched cards and early
A very easy way of constr . optical disks. The analytical engine provided more advanced
with multiplexers The . uctmg a common bus system is features. It consisted mainly four components: the store (memory),
1 1
whose binary info;matio 1:1uhtip exers select the source register the mill (computation unit), input section (punched card reader),
n is t en placed on the bus.
and output section (punched and printed output). The store
A. system bus consists of about 5
each assigned a Particular . 0 to 100 of separate lines consisted of 1000s of words of 50 decimal digits used to hold
-
many different bus des·1mearung or funcrion. A!though there are variables and results. The mill could accept operands from the
. d into
class if1e . three furt gners,
. on any bus, th e lines can be
store; add, subtract, multiply, or divide them; and return a result to
lines. In addition, there m~tiyobnaI group~: data, address and control the store.
e power d1str·b · .
6 INSIGHTS ON MIC l Uhon lines as well.
ROPROCESSORS

INTRODUCTION 7
2. Electronic Era
the prov1s10n of system software with the computer. In 1957,
The First Generation: Vacuum Tubes Digital Equipment Corporation (DEC) was founded, and in that
The ENIAC (Electronic Numerical Integrator And year, delivered its first computer, the PDP-1. IBM developed 7090
Calculator), designed and constructed at the University of in 1960, 7094 I in 1962, and 7094 II in 1964 (successive products had
Pennsylvania, was the world's first general-purpose electronic increased performance, capacity, and/ or low cost).
digital computer. The ENIAC was a decimal rather than a binary
machine. That is, numbers were represented in decimal form, and
The Third Generation: Integrated Circuits
arithmetic was performed in the decimal system. It's memory Throughout the 1950s and early 1960s, electronic equipment
consisted of 20 accumulators, each capable of holding a IO-digit was composed largely of discrete components - transistors,
decimal number. A ring of 10 vacuum tubes represented each resistors, capacitors, and so on. Discrete components were
digit. manufactured separately, packaged in their own containers, and
soldered or wired together onto masonite-like circuit boards,
In 1947, Eckert and Mauchly formed the Eckert-Mauchly \
which were then installed in computers, oscilloscopes, and other
Computer Corporation. Their first successful machine was the electronic equipment. Whenever an electronic device called for a
UNIVAC I (Universal Automatic Computer). It was the first transistor,' transistor had to be soldered to a circuit board. T.he
successful commercial computer. It was intended for both scientific entire manufacturing process, from transistor to circuit board, was
and commercial applications. This computer was thought to expensive and cumbersome.
perform matrix algebraic computations, statistical problems,
The use of the integrated circuit defines the third generation
premium billings for a life• insurance company, and logistical
of computers. The entire circuit was fabricated in a tiny piece of
problems. The UNIVAC II, which had greater memory capacity
silicon. Initially, only a few gates or memory cells could be reliably
and higher performance than the UNIV AC I, was delivered in the
late 1950s. manufactured and packaged together. These early integrated
circuits are referred to as small-scale integration (SSI) The most
Later in 1953, IBM introduced its first electronic stored- important members of the third generation are: IBM System/360
program computer, the 701, and was intended primarily for and the DEC PDP-8. These computers were small enough that it
sc1entif1c applica_tions. In 1955, IBM delivered the companion 702 could be placed on top of a lab bench or be built into other
product that suited for business applications Th equipment.
. ese computers
establis h ed IBM as the overwhelmin 1 d .
manufacturer. gY 0 rrunant computer Later Generations
The Second Generation: Transistors . Beyond the third generation, there is less general agreement
on defining generations of computers. Based on advances in
The first major change in the electr .
the replacement of th . onic computer came with integrated circuit technology, there have been a number of later
transistor is smaller he vacuum tube by the transistor. The generations. With the introduction of large-scale integration (LSI),
' c eaper and diss· t 1 more than 1000 components can be placed on a chip. Very-large-
vacuum tube. The f ' ipa es ess heat than a
use o the transistor d f" scale integration (VLSI) achieved more than 10,000 components per
generation of compute Th e mes the second
· rs. e second chip, while current ultra-large-scale integration (ULSI) chips can
introduction of more co 1 . generation saw the
mp ex anthmeti d contain more than one billion components.
control units, the use of high-I I c an logic Units and
eve progra .
mrrung languages, and
8 INSIGHTS .ON MICROPROCESSORS

INTRODUCTION 9
l.6 Stored-Program Concept and Von-Neumann
of control unit and ALU are called registers and the various models
Machine: of registers are:
.
Accor d mg to this concept' instructions . are stored in
ory to enable it to perform. a variety of • MAR (memory address register) - contains the address in
computer mem . tasks in
· termittently The idea was mtroduced m the late memory of the word to be wriUen into or read from the
sequence or m · MBR.
1940s by John Von-Neumann, who proposed_ that a program be
electronically stored in binary-number format m a memory device • MBR (memory buffer register) - consists of a word to be
so that instructions could be modified by the computer as stored in memory or sent to the I/0 unit, or is used to
determined by intermediate computational results. Other receive a word from memory or from the I/0 unit.
engineers, notably John W. Mauchly and J. Presper Eckert, • IR (instruction register) - contains the 8-bit op-code
contributed to this idea, which enabled digital computers to instruction being executed.
become much more flexible and powerful.
• IBR (instruction buffer register) - used to temporarily hold
The task of entering and altering the programs for the the instruction from a word in memory.
ENIAC was extremely tedious. The programming process could be
• PC (program counter) - contains the address of the next
facilitated if the program could be represented in a form suitable instruction to be fetched from memory.
for storing in memory alongside the data. Then, the computer
could get its instructions by reading them fx:om memory, and a • AC & MQ (accumulator and multiplier quotient) -
program could be set or altered by setting the values of a portion of employed tq hold temporarily operands and results of ALU
memory. This approach is known as stored-program concept, and operations. For example, the result of multiplying two 40-bit
I
such architecture is named as Von-Neumann architecture. numbers is an 80-bit number; the most significant 40 bits are
; . : stored in the AC and the least sigriificant in the MQ.

Arithmetic/Logic 1. 7 Harvard Architecture

Unit (ALU)
Memory VO In Von-Neumann architecture, the same memory is used for
Equipments storing instructions and data. Similarly, a single bus called data
Program Corttrol bus or address bus is used for reading data and instructions from
Unit (CU)
or writing to memory. This architecture limits the processing speed
'• ····•··· . ···········•··•·····• ·•··· of computers.
Figure 1.7 Von-Neumann architecture The Harvard architecture based computer consists of separate
memory spaces for the programs (instructions) and data. Each
. ~e main ~emory is used to store both data and
ins tructions. The arithmetic and lo . . . space has its own address and data buses. So, instructions and data
arithmetic and lo · . gic urut is capable of performing can be fetched from memory concurrently and provides
gica1 operation on binar d
control unit interprets th . . . Y ata. The program sigriificance processing speed improvement.
e mstruchon in me d
to be executed. The I/O ·t mory an causes them
uru gets operated from the control unit. In Figure 1.8, there are two data and two address buses
The Von-Neu . multiplexed for data bus and address bus. Hence, there are two
mann architecture · th
the architecture of mod d' . IS e fundamental basis for blocks of RAM chips: one for program memory and another for
ern igital comput
ers. The storage location data memory addresses.
10 INSIGHTS ON MICROPROCESSORS

INTRODUCTION

I"
Address Program Memory Address Bus Harvard architecture Von-Neumann architecture
Bus
2t========~~~~;=;;~;;;;;;c=======
v Data Memory Address Bus 2. Easier to pipeline, so high 2. Low performance
, . , ~---~-,---=-------:.:----r----.- performance can be achieved compared to Harvard
architecture
Control PC Data
Bus Control Central Related Memory Progra Data 3. Comparatively high cost 3. Cheaper
+ - - - + Unit ALU Hardware Address Memo Memory
AU 4. No memory alignment 4. Allows self modifying
problems. codes
Program Memory Data Bus 5. Since data memory and 5. Since data memory and
program memory are stored program memory are
Data Memory Data Bus
physically in different locations, stored physically in the
no changes for accidental same chip, chances for
Figure 1.8 Haroard architecture corruption of program memory. accidental corruption of
TI1e control unit controls the sequence of operations. Central program memory.
ALU consists of ALU, multiplier, accumulator, and scaling chief
register. The PC is used to address program memory and always 1.8 Evolution of Microprocessors (Intel Series)
contains the address of next instruction to be executed. Here, data The evolution of microprocessor is dependent on the
and control buses are bidirectional and address bus is development of integrated circuit technology from single scale
unidirectional.
integration (SSI) to giga scale integration (GSI).
Differences Between Harvard and Von-Neumann Table 11 Evolution of microprocessors (Intel series)
Architecture
Date Microprocessor Data Bus Address Bus Memory
Figure 1.9 differentiates the Harvard concept with Von- 1971 4004 4 bit 10 bit 640 Bytes
Neumarm concept.
1972 8008 8 bit 14 bit 16K
1974 8080 8 bit 16 bit 64K
Program
Memory CPU Data
Memory 1976 8085 8 bit 16 bit 64K
Single shared bus
(a)
1978 8086 16 bit 20 bit lM
Figure 1. 9 Harvard V N (b)
1979 8 bit 20 bit
vs on- eumann architecture (a) Von-Neumann 8088 lM
h
arc llecture (b) Harvard architecture
1982 80286 16 bit 24 bit 16M
The differences between H
architecture are· arvard and Von-Neumann 1985 80386 32 bit 32 bit 4G
Harvard architecture 1989 80486 32 bit 32 bit 4G
1. Separate buses for Von-Neumann architecture
instruction 1993 Pentium· 32/64 bit 32 bit 4G
and data fetching 1. Single shared bus
for
instruction and 1995 Pentium pro 32/64 bit 36 bit 64G
data
fetching
12 INSIGHTso

I"
N MICROPROCESSORS -----------
INTRODUCTION
 Date Microprocessor Data Bus Address Bus
Memory
Pentium II 64 bit 36 bit
1997 61c • 80486: The 80486 introduced the use of much m ore
1998 Celeron 64 bit 36 bit sophisticated and powerful cache technology and
61c
sophisticated instruction pipelining, and offered a built-in
1999 Pentium III 64 bit 36 bit 64G---- math coprocessor.
2000 Pentium IV 64 bit 36 bit 64G----- • Pentium: This processor introduced the use of superscalar
2001 Itanium 128 bit 64 bit 64G ~ teclmiques, that is, ability to execute multiple instructions in
2002 Itanium 2 128 bit parallel.
64 bit 64G -
2003 Pentium M/ Centrino (wireless capability) for Mobil~ • Pentium Pro: Along with the-features of Pentium, Pentium
version e.g. Laptop Pro enabled use of register renaming, branch prediction,
2006 Dual Core (32-bit or 64-bit processor) - data flow analysis, and speculative execution.
2006 Core 2 Series (64-bit processor)- Dual and Quad Core • Pentium II: The Pentium II incorporated Intel MMX
Processor technology, which\is designed specifically to process video,
2008 audio, and graphics data efficiently. ~
Atom (32-bit or64-bit processor) - Single or Dual
Core Processor • Pentium III: This version offered additional floating-poirtt
2010 Core i3 (Dual Core Processor) irtstrw;:tions to support 3D graphics software.
2009 • Core: This is the first Intel x86 microprocessor with a dual
Core iS (Dual and Quad Core Processor)
2008 core, that is, two processors on a sirtgle chip
Core i7 (Dual and Quad Core Processor)
2011 Core i7 Extreme Edition • Core 2: The Core 2 is a 64-bit architecture. The Core 2 Quad
2017 Core i9 X-series provides four processors on a single chip.

. So'.1'e of the highlights of the evolution of the Intel product 1.9 Processing Cycle of a Stored-Program Computer
hne are listed below:
The basic function performed by a computer is execution of
• 8080: The world's first g 1 . a program, which consists of a set of irtstructions stored irt
. enera -purpose microprocessor. This
was an 8-b1t machin •h memory. Each instruction has two parts: one is the task to be
Th 8080 . e, wit an 8-bit data path to memory.
e was used m the f t performed, called the operation code (op-code) field, and the
rrs personal computer, the Altair.
• 8086: A far more po f 1 . second is the data to be operated on, called the operand or address
addressing a 1 MB fwer u, 16-bit machine which enabled field. The processor does the actual work by executing instructions
o memory and · th f1
the x86 architectu A . ' is e rst appearance of specified in the program. In its simplest from, instruction processing
re. vanant of thi 8
was used in IBM' fir processor, the 8088, consists of two steps: The processor reads (fetches) instructions
s st personal computer
• 80286· Thi · from memory one at a time and executes each irtshuction. Program
. s ts an extension of 8086 w . execution consists of repeating the process of instruction fetch and
a 16 MB memory. hich enabled addressing
instruction execution. The irtstruction execution may involve
• 80386: Intel's first 32-bit . several operations and depends on the nature of the irtstruction.
multitasking microprocessor that d
_ :___ supporte The processing required for a single instruction is called an
14\'~ R _ _ _ _ _ _
I 0CESSORS - ---

INTRODUCTION I
instruction cycle. Program execution halts only if the machine is
turned off, some sort of umecoverable error occurs, or a progr¾\
instruction that halts the computer is encountered. Fetch
Fetch Cycle Exceute Cycle

Fetch Next Execute Next

Instruction Instruction Halt

Figure 1.10 Basic instruction cycle Execute

In fact, the processor has to do the following things:
F~gure 1.11 The instruction cycle (elaborated) .
• Fetch instruction: The processor reads an instruction from
memory (register, cache, main memory) . 1.10 Micro-Operations and Microinstructions
• Interpret instruction: The instruction is decoded to Micro-Operations
determine what action is required. A computer executes a program consisting sequence of
• instructions. Each instruction is made up of shorter sub-cycles
Fetch data: The execution of an instruction may require
(machine cycles): fetch, indirect, execute cycle (read, write), and
reading data from memory or an I/0 module. interrupt. Performance of each cycle has a number of shorter
• Process _data: The ~xecuti~n of an instruction may require operations called micro-operations. Micro-operations are functional
perfonrung some anthmetic or logical operation on data. atomic operations of CPU. Events of any instruction cycle can be
described as a sequence of micro-operations. The prefix "micro" in
• Write data· The result Of . · ,micro-operations ref~rs to the fact that each step is very simple and
d · s an execution may require writing
ata to memory or an 1/0 module .. accomplishes very little.
To elaborate instruction c cl .
Thus an instruction c I . y e, we include two more stages. Program Execution
' ye e consists of:
• Fetch: Read the next .
processor. instruction from memory into the
• Execute: Interpret the opcode
operation. and perform the indicated ,
• Interrupt: If interrupts are
occurred, enabled and an
save the current interrupt has
interrupt. process state
and service the
• Indirect· If .
. : any indirect addres . .
instruction is fetched, the requ •s:g is involved after an Figure 1.12 Constituent elements of a program execution
using indirect addressing. ire operands are fetched
Microinstructions
Each instruction is characterized with many machine cycles
16 and each cycle is characterized with many T-states; one complete

INTRODUCTION
I,
 cvcle of clock is caJJed as I-state. The lower i~struction level
patterns which are the numerous_sequences for a sm~le instruction
are known as micromstructwns. We can visualize th
• Control unit issues READ command .

m icroinstruction with the help of any machine cycle. Here e • Result (data from memory) appears on data bus.
We
consider the fetch cycle. • D~ta from data bus is copied into MBR.
CPU • PC is incremented by 1
• Data (instruction) is moved from MBR to IR.
• MBR is now free for further data fetches.
Memory
Symbolically, fetch sequence is completed in 3 clock cycles.
T1: MAR f-- PC
T2: MBR f-- [MARJ
T3: PC f-- PC +1
IRf--MBR
Address Data Control where T; = time unit or clock cycle.
Bus Bus Bus
Figure 1.13 Data flow in fetch cycle. 1.11 Control Unit
Various registers involved in fetch cycle are: The control unit is the heart of CPU. It gets instruction from
• Memory Address Register (MAR) memory. The control unit decides what the instructions mecll). and
connected to address bus directs the necessary data to be moved from memory to ALU. It
must comr:tmnicate with both ALU and main memory. It
specifies address for read or write op-code
coordinates all activities of processor unit, peripheral devices, and
• Memory Buffer Register (MBR) storage devices.
connected to data bus The functions of control unit include:
holds data to write • Sequencing
• Program Counter (PC) Causing the CPU to step through a series of micro-
operations
holds address of next instru ti
. c on to be fetched • Execution
• Instruction Register (IR) Causing the performance of each micro-operations
holds last instruction fetched
Two types of control unit can be implemented in computing
The fetch sequence can be explained as follow . systems: hardwired control unit and micro-programmed control unit.
• Address of · s. 1. Hardwired Control Unit
next mstruction . .
to memo dd is m PC. This dd .
ry a ress register (MAR a ress 1s moved This control unit is essentially a combinational circuit. In
• Address from MAR . ). hardwired control unit, for each control signal, Boolean
is placed on add
ress bus. expression has to be derived for that signal as a function of
18
INSIGHTS ON MICRQp _
RocessoRs --: - - - - _ the inputs. Hardwired control unit has faster mode of

INTRODUCTION I"
 .
opera hon. A hardwired control unit needs rewiring if design
has to be modified.
i. The program counter contains the address of the next
2. Micro-Programmed Control Unit
instruction to be executed. If the next instruction to be
In a modem complex processor, the number of Boolean executed is MOV A, B; the program counter contains the
equations needed to define the control uni~ is very large. The address of the memory location where the instruction code
task of implementing a hardwired control unit that satisfies for MOV A, B resides.
all of these equations becomes extremely difficult. The result In the first operation of fetch cycle, the contents of program
is to opt for a far simpler control unit, known as micro- counter will be transferred to the memory address register
programmed con trol unit. (MAR). The memory address register then uses the address bus
to transmit its contents that specifies the address of memory
In micro-programmed control unit, the logic of the control unit
location from where that instruction code of MOV A, B is to be
is specified by a microprogram. A microprogram consists of a
fetched. Let T1 indicates the period of first operation
sequence of instructions in a microprogramming language.
These are very simple instructions that specify micro-- T1 : MARf-PC
operations. Modifications in micro-programmed control unit ii. When the control unit issues the memory read signal, the
can be done by changing the microinstructions. contents of the address memory location specified by MAR
will be transferred to the memory buffer register (MBR).
1.12 Register Transfer Language (RTL) Suppose T2 is the time period for this operation.

The symbolic notation used to describe the micro-operation T2: MBR f- [MAR]
transfers amongst registers is called register transf~r language (RTL). iii. Finally the contents of MBR will be transferred to the
It is one of the forrns of hardware description language (HDL). The instruction register and then the program counter gets
t~rm _"register transfer" implies the availability of hardware logic incremented. Let T3 be the time required by the CPU ·to
circmts that can perform a stated micro-operation and transfer the complete these operations.
result of the operation to the same or another register. The term T3: IRf-MBR
"language" i~ borrowed from programmers, who apply this term PCf-PC+ 1
to programming languages.
Execute Cycle
_RTL is the convenient tool for describing the internal
organization of digital computers in concise and precise manner. It After the fetch cycle is completed, the execution starts. The
can also be used to facilitate th d • execute cycle steps are described as follows:
such as microprocessors.
• e esign process of digital systems
i. At the start of execution cycle, the instruction register (IR)
An Example of RTL consists of instruction code for instruction MOV A, B. The
address field of instructions specifies the addresses of the
Consider the execution of instructio .
of two machine cycles name] fi n MOVA, B that consists two memory locations A & B. The first step needed is to
y etch cycle and execution cycle. obtain the data from the location B. For this, the address
Fetch Cycle
field of IR indicating the address of memory location will be
Within the fetch cycle th transferred to address bus through the MAR. Let T1 be this
' e operations performed are: time taken.
20
INSIGHTS ON r•mtROPROCESSORS T1 : MAR f- (IR(Address of B))

INTRODUCTION
 ii. When the control unit issues a mem~ry read signaJ, the
contents of location B will be output (wntten) to t~e :rne:rnory 3. MOVR,M
buffer register (MBR). Now t~e conte:11t of_ B which is to be
written to memory location A 1s contained m MBR. Let be r ~ T1 : MAR +-PC
the time taken for that operation. 2
~~ T2 : MBR +-[MARJ
T2 : MBR f- (B) ~ "'
"<:: <.)
;:,-,
T3 :
Q:;' ou
<..)
IR +- MBR, PC+-PC + 1,
iii. Now, we need the memory !~cation of A _because it is being
;::..
8- T4: Unspecified
written with the data of location B. For this the address field ~ "<::
of IR indicating the address of memory location A Will be 's- Cl
Ts: MAR
"' +-HL
transferred to MAR in time T3. ~ Q:;
i:' <a
"'
T6: MBR
Q:; Q ;:,-, +- [MARJ
T3 : MAR f- (IR(Address of A)) £: u T7: R +-MBR
~
"'
iv. When the control unit issues the memory write signal, the
contents of MBR will be written to the memory location 4. ,
MOV MR
indicated by the contents of MAR in time T4.
ii
.... T1: MAR +-PC
T4: A f- MBR or T4 : [MARJ f- MBR ~~ T2: MBR +-[MARJ
Note: [MAR] = A i:i::: "' <..)

i la'
<..)
T3, IR +- MBR, PC+-PC + 1,
Program consists of instructions which contains different ;::..
8- T4: Unspecified
cycles like fetch and execute. These cycles in turn are made up of
the smaller operations called micro-operations.
~ ~
's- i:' Ts: MAR f-HL
Some RTL Examples ~ Q a,
<..)

T6:
i:i::: £: "' MBR +-R
1. MOVRd, Rs ~ ·i:: T1: [MARJ +-MBR
~
"'
i::i:: ~ T1:
~":!' ~cu ~ MAR +-PC 5. MVIM, 8 - b"1t D aa
t
<.) T2:
I:;~ ~0' MBR +-[MARJ .i:::
i::i:: 0 <.) T3: ~ T1 : MAR +-PC
IR ~~
~ ~ Tc +- MBR, PCf-PC+l T2: MBR +- [MARJ
Unspecified "'
"<:: <..)
;:,-, '--
2. ou T3: IR +-MBR, PC+-PC+l
MVI R, 8-b1t Data <..)
;:... T4: Unspecified
~
~ T1 : Cl 0
~~ T2 : MAR +-Pc 0
-l:!
<::t ~ <.) MBR ~-"t:: i:' u"' Ts: MAR +-PC
c::i at T3: +-[MARJ O,::i
Q 0'
~] IR ~ ob !-.:: T6: MBR +-[MARJ
I:; ~ C' Tc +- MBR, PC+-PC+l
Unspecified i:i:::i ~ ~
i:i:::
T1: z +- MBR, PC +-PC + 1

~
i::i:: e::' ~
~ t' -~ Ts: MAR +-Pc
~
~ (.,) T6: Ta: MAR +-HL
~~~ MBR i:' ·i::"' <a"'
+- [MARJ 0 T9: MBR f-Z
Cl:: T7:
- R i~a' Tio:

---
22 +- MBR, Pc +-Pc + l [MARJ f-MBR
INSIGHTso

INTRODUCTION I"
6. LXI RP, 16-bit Data
~

T1: MAR f---PC 8. STA 16-bit Address

"'
"'
i:i
~0 T2 : MBR f---[MAR] . ...i:: T1 : MARf-PC
.;:l
.... 0t-5....
<:,t
<:,t
T3 : IR f--- MBR, PCf---PC + 1
~ .!!: T2: MBR f--- [MARJ
Q ...."' T4 : Unspecified "'C <J
....
;g -
"<:I
<J
G' T3 : IR f--- MBR, PCf-PC + 1

....'
1,0
C
i:' i:i"'
(J
Ts: MAR f---PC t T4 : Unspecified
Q' E'l:I T6: MBR f--- [MARJ
"' <:,t
>< :E"' T1: RPL f--- MBR, PC f---PC + 1 "'~"' i:' C,"'
Ts: MARf-PC
...i r:i:: "<:I C cJ' T6 : MBRf-[MAR]
~ . "<:I
'et: E "<:I
~ i:' 1"' Ts: MAR f---PC
·-'
..... ~ ~ Ti : z f--- MBR, PC f-PC + 1
R::: C <J
,.Q i:r::
E 'I:! T9: MBR f---(MAR] l,C)
T--1
"' <:,t "<:I
:E R:::"' Tio: RPtt f---MBR,PCf---PC + 1 ~
V)
...
<:,t Ts: MARf-PC
i:r:: ...
~ i:' C, T9: MBRf-[MARJ
7. LOA 16-bit Address ,..:i
h C cJ'
~ T1: MARf---PC i:r:: j Tio : W f- MBR, PC f---PC + 1
...
"'
"' ;:,,
<J
~ T2: MBRf---[MAR]
'IS .!!: Tn: MARf---WZ
3u T3: IR f--- MBR, PCf-PC + 1 i:' <J

0
!:l..
T4: U~pecified
C cJ' T12: MBRf---A
£ ...
~ ·i: T13: [MARJ f--- MBR
'I:!
<:,t Ts: ~
\
<I)
"' MAR f-PC
j r:i::
t' i:i
C
"'
G'
T6:
MBRf-[MAR]
9. LDAXRp
~ I

,)
I ....
~
....'
1,0
I T1: z f- MBR, PC f-PC + 1
...i::
.;:l
~ .!!:
... <J
T1 :
T2:
MARf-PC
MBR f-[MAR]
'IS
~ <:,t
"'
Ts:
MARf-PC
l G'
<J
T3 : IR · f--- MBR, PCf-PC + 1
~
>-.1
~
~"'
t' i:i T9: t T4: Unspecified
~
R:::
I
C G'
Tio:
MBR f- [MARJ
~
'-l .!!:
<J
W f- MBR, PC f-PC + 1 'c;--
"<:I
G' Ts: MARf-Rp
"<:I
Tn: E=l
<:,t
"' MARf-WZ i:r:: ...
<:,t
T6: MBRf-[MAR]
~"' i:r::
t'
C '°e, T12:
MBRf-[MAR]
i:'
0 T1: A f-MBR
I Tn:
A f-MBR
£
~
24 INSIGHTS ON Ml _._
CROPRocessoRs

I"
INTRODUCTION
11. STAX RP
..:: T1:
- 13. SHLD 16-bit Address
MAR f- PC ..:::
.l:: ~ T1 : MJ\Rf-PC
0..
i::i:::
.
~~
',:t;:,,,
IJ
T2:
T3:
MBRf-[MAR]
IR f- MBR, PCf-PC + 1
~~
.. IJ
T2 : MBRf-[MAR]
><
CU
IJ
1:1. Unspecified
1 G'
IJ
T3: IR f- MBR, PO--PC + 1
~ 0 T4:
~ T4 : Unspecified
V}

"c- . Ts :
MAR f- Rp i:' u
. Ts: MARf-PC
~ t'], Ca'
C U T6:
i::i::: E ., MBRf-A "'"' T6: MBRf-[MAR]
......
~ ·i:: [MARJ f-MBR
~
;: "<:lt
~ ~
~
T7: ~ ~ T7 : z f- MBR, PC f-PC + 1

12. LHLD 16-bit Address

~
....
:sI
.
i:' u Ts : MARf-PC
. ,..,
1.0
Ca'
.cu"
',:: ::r,
T1:
T2:
MARf-PC
MBRf-[MAR]
Cl
~ 11 ~
T9:
T10:
MBRf-[MAR]
W f- MBR, PC f-PC + 1
~ 'ti
V}
T3: IR f- MBR, PCf-PC + 1 'B-
0 .... ~
~ T4: Unspecified i:' ;i, Tu: MARf-WZ
~ cu
-~
C'~ Ts: MARf-PC ~
!~·i:: T12: MBRf-L
C ::r,
.E '" T6: MBRf-(MAR] s: T13: [MARJ f-MBR
"'"'
~
',:t ~ ~
',::
T7: z f- MBR, PC f-PC + 1 .
i:'], T14: MARf-WZ+l
.
',::
~
' cu
.....
:s C"" Ts: MARf-PC ~
!~·i:: Tis: MBRf-H
1.0
I
,..,
C

~~
;:,,,
T9: MBRf-[MAR] s: T16: [MARJ f-MBR
Q ~ ~ T10: W f- MBR, PC f-PC + 1 14. IN 8-bit Address
~
~
i::i:::
~ T1: MAR f-PC
"c-
~
.
',::
<::t
i::i::: .. Tu : MARf-WZ
"' IJ
"<:lt;:.,,
cu
IJ ..:::
T2: MBR f- [MARJ
i::i::: C' " T12: MBRf-[MAR] "'"' ~~ T3: IR f- MBR, PCf-PC + 1
C cJ'
E Tn: L f-MBR ~
~
~ T4 : Unspecified
~ ~

C'
. cl T14: MARf-WZ + 1
·-....
.Q
00
I
i:'
!~
u"'
C ;:.,,
Ts :
T6:
MAR f-PC
MBR f- [MARJ
-
C
E
cJ' Tis: ~ ~ ~ T7: z f- MBR, PC f-PC + 1
MBRf-[MAR]
~] T16: H f-MBR
'B- ~
R:;
~ ~
·i:: "'
Ts: IOAR f-Z
~
s:], T9 : IOBR f-A
ou T10: A f-lOAR
~

I"
INTRODUCTION
15. OUT 8-bit A ddress

. .
- 19. ADCR
~ T1 :
MAR
MBR
f- PC
f- [MAR]
. T1 : MAR f--PC
"I:$
C U
~..::
;:,-.
T2:
IR f-MBR, PCf-PC+l
~i:::.:::
I=: u
i~
"'..s::
T2 : MBR f--[MAR]
0~
~
T3 :
T4: Unspecified i:::.::: ~ t~ ~
T3:
T4:
IR f-- MBR, PCf--PC+l
Unspecified
::i::
,...
C
h
C'],
. T1 : MAR f-PC 20. ACI 8 -bit Data
:::s
0 C U
¼: T2: MBR f- [MAR] . "' ~ T1: MAR f--PC
~
~
..
~ .
"I:$
i::s

A:.
T3: z f- MBR, PC f-PC + 1
·t
i::s
"I:$
cu
t~. "'..s::
;:,-.
T2:
T3:
MBR f-- [MAR]
IR f-- MBR, PCf--PC+l
i:::.:::
.
.... ~o.... r..., T4: Unspecified
·t
s
~
~
T1:
T2:
!OAR f-Z
IOBR f-A
!,ol · -
h .I;'
i:::.::: 00 C'~
. Ts:
MAR f--PC
au
~ T3: [!OAR] f- IOBR, SC f- 0 u
~
C cJ" T6:
MBR f--[MAR]
~] T7:
A f-- MBR + A + CY, PC
f-PC + 1
16. XCHG i:::.:::

~\.!)
..
"I:$;:.,
C
~
U
T1:
T2 :
MAR f-PC
MBR f-[MAR]
21. ADDM
..s:: T1: MAR ~PC
::i:: ~
~ u "' ..s:: T3: IR
i:::.::: ><
;:,._"'
0 .....
~ T4:
f-MBR, PCf-PC+l
Unspecified ~ . "'
~~
',:s
au
;:,-.
T2:
T3:
MBR
IR
f--[MAR]
f-- MBR, PCf--PC + 1,
17. ADDR
§ T4:
~ <3- Unspecified
. ~
"'
T1: MAR f-PC ~
Ts: MAR f--HL
~
~A:. "I:$;:,.,
CU T2 : MBR <-- [MAR] C'-,:stS ~"'
t:: § 0
t~.:= T3: IR <-- MBR, PCf--PC+l
0
ij "' ;:,-. T6: MBR f- [MAR]
A:. ~
~ T4:
~ i:::.::: u T7: A f--MBR+A
Unspecified
18. ADI 8-bit Data 22. ADCM

16'
. ~
"' T1:
T2:
MAR <-PC ..s::
~
. T1: MAR f--PC
.s "'..s::
MBR <-[MAR] ~~ T2: MBR f-- [MAR]
0i::..."' T3: ~~
~::
i::s IR
.....
~
<-- MBR, PCf--PC+l ~ au T3: IR f-- MBR, PCf--PC + 1,
T4: Unspecified u ~
t::A::.(l()~ ., 0 0 T4: Unspecified
c><3 ~
Ts: MAR
cS ct3'
~
<-PC ~
i:' ~"'
~ T6: Ts: MAR f--HL
MBR
~]Ct:: T7: A
<-[MAR] I=:
i:::.::: Q 0' T6: MBR f--[MAR]
f--MBR + A, PC f--PC+l ~ ',:s

~ ~ T7: A f--MBR+A+CY
i:::.:::

2B \ '""GHT~ROPR
OCESSORS
INTRODUCTION
23. INRM
,.:: T1 : MAR f-PC
....I.) • Industry
~.., ~I.) T2: MBR f- [MARJ
It is used in data monitoring system, autom a tic weigh ting,
"I:!~ T3: IR f- MBR, PCf--PC + 1, batching systems, etc .
oU
I.)
~ • Security systems
0 T4: Unspecified
~ MAR f-HL
It is used in smart cameras, CCTV, smart doors, etc.
Ts :
~ i:' "I:!
E.., ~
..,
C l::t ~ T6: MBR f- [MARJ
•
•
Automatic system
Robotics
"o-- .., ~ u
~ T1: z f-MBR
•
~ Communication system
~
......, • Games machine
·c Ts : MAR f-HL
3: ~ • Accounting system
i:'
ou
~ T9: MBR f-Z+l • Complex industrial controllers
E Tio: [MARJ f-MBR • Data acquisition system
i • Military applications system

1.13 Applications of Microprocessors

Microprocessors are applicable to a wide range of
information processing tasks, ranging from general computing to
real-time monitoring systems. Most electronic systems - including
everything from personal computers, laptops, remote controls,
washing machines, microwave ovens to mobile phones, complex
military and space systems, and industrial automation contain a
built-in microprocessor in it. These applications are listed below:
• Microcomputer
Microprocessor is the CPU of the microcomputer.
• Embedded system
It is used in microcontrollers.
• Measurements and 'testing equipment
It is used in signal ge t .
voltmeters x-ray anal nera ors, oscilloscopes,
bl counters, digital
yzer, . oodd group analyzers, baby
.mcu bator, 'frequency synth
spectrum analyzers, etc. esizers, ata acquisition systems,
• Scientific and e · .
ngmeermg research

30 INSIGHTS ON MICROPR
ESSORS

INTRODUCTION
I,
 temporary register is used to hold data during an
arithmetic/logic operation. The result is stored in the
-.... accumulator; the flags (flip-flops) are set or reset according
PROGRAMMING WITH 8085 to the result of the operation.
2. Accumulator (Register A): It is an 8-bit register that is the
MICROPROCESSOR part of ALU. This register is used to store the 8-bit data and
to perform arithmetic and logic operations. 8085
2.1 Internal Architecture of 8085 Microprocessor microprocessor is called accumulator based microprocessor.
When data is read from input port, it is first moved to
The Intel 8085A is a complete 8-bit parallel central
accumulator and when data is sent to output port, it must be
processing unit. The main components of 8085A are array of
first placed in accumulator.
registers, the arithmetic logic unit, the encoder/ decoder, and
timing and control circuits linked by an internal data bus. 3. Temporary Registers (W and Z): They are 8-bit registers not
accessible to the programmer. During program execution,
SIO SOD
8085A places the data into it for a brief period.
4. Instruction Register (IR): It is an 8-bit register not accessible
t~ the programmer. It receives the operation codes of
instruction from internal data bus and passes to the
instruction decoder which decodes so that microprocessor
knows which type of operation is to be performed.
5. Register Array (Scratch Pad Registers B, C, D, E): Each one
(B, C, D, E) is an 8-bit register accessible to the programmers.
Data can be stored upon it during program execution. These
r"c'c--ccc-+-=-=---1 f
i----=--,'-='---.j 1 can be used individually as 8-bit registers or in pair BC, DE
as 16-bit registers. The data can be directly added or
transferred from one to another. Their contents may be
incremented or decremented and combined logically with
the content of the accumulator.
6. Register H & L: They are 8-bit registers that can be used in
same manner as scratch pad registers.
. .,,.... Allr"'I,
Figure2.1:TheBOBSAm' - .... _ _ .._. 7. Stack Pointer (SP): It is a 16-bit register used as a memory
rcraprocessor function,,/ bl k d.
So oc lllgram pointer. It points to a memory location in R/W memory,
urce: lntel Corporation. Embedd rl M
a
e tcroprocessors (Santn
ara Calif: Author 1994), pp 1-11 called the stack. The beginning of the stack is defined by
1. ALU: The arith . loading a 16-bit address in the stack pointer.
. mettc logic unit f
functions. It includ h per orms the computing
· esteaccu I 8. Program Counter (PC): Microprocessor uses the PC register
register, the aritluneti mu ator, the temporary
c and logi · . to sequence the execution of the instructions. The function of
c crrcuits and five flags. The
32 INSIGHTS ON MICROPRocessoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 33
 PC is to point to the memory address from which the ne
byte is to be fetched. When a byte is being fetched, the
incremented by one to point to the next memory location.
Pc: WR signals are sync pulses indicating the availability of
data on the data bus.
9. Flags:
D1 11. Interrupt Controls: The various interrupt controls signals
Do
(INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP) are used to
I s I z I X AC X p X I CY] interrupt a microprocessor.
Register consists of five flip flops, each holding the status of 12. Serial J/O Controls: Two serial 1/0 control signals (SID and
different states separately is known as flag register and each SOD) are used to implement the serial data transmission.
flip flop are called flags . 8085A can set or reset one or rnore
Programmer's Model of an 8085 Microprocessor
of the fla~s. The flags are sign (S), Zero (Z), Auxiliary Carry
(AC), Parity (P), and Carry (CY) . The state of flags indicates
the result of arithmetic and logical operations, which in turn
can be used for decision making processes. The different A 8 Flag 8
flags are described as:
B 8 C 8
• Carry: It stores the carry or borrow frorn one byte to
another. . If the last operation generates a carry or D 8 E 8
borrow, its status will be 1 otherwise 0.
• Zero: If the result of last operation is zero, its status will
H 8 L 8
be 1 o~erwise 0. It is often used in loop control and in SP 16
searching for particular data value.
• PC 16
Shignl: If the ~ost significant bit (MSB) of the result of
t e ast operation is 1 ( • Data bus
. O. negative), then its status will be 1 Address bus
o therwise
• ,.
Parity: If the result of the 1
number of 1' ( ast operation has even 8 lines 16 lines
otherwise 0. s even parity), its status will be 1
'✓ ' 7
'
• Auxiliary Carry· If h
· t e last operaf
Bidirectional Unididrectional
from the lower half word (lo i~n generates a carry Figure 2.2 Programmer's model of an 8085 microprocessor
be 1 otherwise o. Wer rubble), its status will
The programmer's model of an 8085 microprocessor consists
10.
Ti_m ing and Control Unit: This . of:
microprocessor operations With thurut synchronizes all the
control signals e clock and Accumulator
. necessary for generates the
microprocessor and peri h conunUnication betwee th It is an 8-bit register accessible to programmer. Almost all
• . P erals. Th n e
sirrular to the sync pul . e control signals are arithmetic, logical, and 1/0 operations are performed on the
se m an oscilloscope Th -R accumulator.
· e D and
34
INSIGHTS ON MICRO
PRocessoRs

PROGRAMMING WITH 8085 MICROPROCESSOR 35

 Flags
Flags are 8-bit register that shows the status of last
(IO/ M , S1 and So) to identify the nature of the operation,
operations. There are five flip flops, each flip flop is called All)
each holding the status of different states separately. flag, and one special signal (ALE) to indicate the beginning of the
operation.
D1 D6 Ds D4 D3 D2 D1 Do
• ALE (Address Latch Enable): This is a positive going
I s I z I I AC I I p I I CY I
X X X pulse generated every time 8085 begins an operation
(machine cycle) . It indicates that the bits AD7-AD0 are
Stack pointer (SP)
address bits. This signal is used primarily to latch the
It is a 16-bit register used as a memory pointer It · low-order address from the multiplexed bus and
. . · points toa
memory loca~on 11: R/W memory, called the stack. The beginnin generate a separate set of eight address lines A7-Ao.
of the stack 1s defined by loading a 16-bit address in th g
pointer. e stack • RD (Read): This is a read control signal (active low).
This signal indicates that the selected I/O or memory
Program counter (PC) device is to be read and data are available on the data
bus.
. It is a 16-bit register that holds the address of next
mstruction to be executed. • WR (Write): This is a write control signal (active
low) . This signal indicates that the data on the data bus
B, C, D, E, H, L
are to be written into a selected memory or I/O
. These are six general purpose 8-bit reoisters location.
parrs (B-C, D-E, H-L) can handle 16-bit of data. c,· • The register
• IO/ M : This is a status signal used to differentiate
2.2 Characteristics (Features) , between I/ 0 and memory operations. When it is high ,
. of 8 085 Microprocessor it indicates an I/O operation; when it is low, indicates a
The 8085A (commonly kn memory operation. This signal is combined with RD
.
Purpose microprocessor own as 8085) · b'
capabl f is an 8 - it general
The device has 40 pins . e o addressing 64K of memory. (Read} and WR (Write) to generate I/O and memory
, requires a +SV · l
can operate with a 3-MHz . smg e power supply, and signals.
, smg1e phase clock
1. Address Bus: The 8085 h
16
. . • S1 and So : Tkese status signals, similar to IO/ M , can
the address bus· ho as signal lines that are used as
, Wever, these ]' identify various operations, but they are rarely used in
se~ents_ A1s-As and AD1-AD 11:es are split into two small systems.
urudrrectional and used as hi ~- The eight signals A1s-As are
2.
4. Power Supply and Clock Frequency:
Data Bus· The . g er order bus.
serve . signal lines AD7- AD . • V cc: +5V power supply
b a dual purpose. They are o are bidirectional, they
us as well as data bus. used as lower order address • V ss: Ground reference
3.
Control and Status s·1 • X1 and X2: A crystal (RC or LC network) is connected at
gnals: Thi these two pins for frequency.
two control signals ( RD~ u p of signals includes .
and WR ) thr • CLK OUT: It can be used as the system clock for other
~~ ' ee status signals devices.
\ MICROPRocessoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 37
5. Externally Initiated Signals:

• INTR (Input): Interrupt request, used as a g 2.3 Instruction Description and Format
purpose interrupt. enera1
The computer can be used to perform a specific task, only by
specifying the necessary steps to complete the task. The collection
• INTA (Output): This is used to acknowledge an of such ordered steps forms a 'program' of a computer. These
interrupt. ordered steps are known as instructions. Computer instructions are
• RST 7.5, 6.5, 5.5 (Inputs): These are vectored inte stored in central memory locations and are executed sequentially,
rrupts one at a time. The control reads an instruction from a specific
that _transfer the program control to specific memo
address in memory and executes it. It then continues by reading
locations. They have higher priorities than INTry
. R the next instruction in sequence and executes it until the
mterrupt. Among these three, the priority order is 7
completion of the program.
6.5, and 5.5. .5'

• ~ (In~u~): This is a non-maskable interrupt with

Instruction Cycle
highest pnonty. Instruction contained in the program is pointed by the
• HOLD (Input): This signal indicates that a peripheral
program counter. Instruction is first moved to the instruction
such as a DMA (D· t M register and is decoded in binary form and stored as an instruction
. rrec emory Access) controller is in the memory. The computer takes a certain period to complete
requesting use of address and data bus.
this task i.e., instruction fetching, decoding and executing on the
• H~D~ (Output): HLDA stands for Hold Acknowled e basis of clock speed. Such time period is called 'instruction cycle'
This signal acknowledges the HOLD g . and consists two cycles namely fetch and decode, and execute
, request
• READY (Input) . Thi . cycle.
microprocessor R;ad :rs0~1 is used to delay the
In the fetch cycle, the central processing unit obtains the
responding periph al . n e cycles until a slow-
er 1s ready to d instruction code from the memory for its execution. Once the
When this signal sen or accept data.
goes Iow the mi instruction code is fetched from memory, it is then executed. The
an integral number of 1 ' q:oprocessor waits for
execution cycle consists the calculating the address of the
c ock cycles until it goes high.
• RESETIN ·Wh operands, fetching them, performing operations on them and
. en the signal on thi . finally outputting the result to a specified location.
program count . s pm go~s low, the
er is set to zero th b
and MPU is reset. ' e uses are tri-stated, Clock Cycle

• RESET OUT· Thi . .. I •

be . . s signal ind'
~g reset. The signal can belCates that the MPU is
devices. used to reset other
• Serial J/O Ports· Th 8
the serial tr . . e 085 has two si 1 .
SOD (S . ansnussion: SID (S . gna s to Implement Fetch Cycle . Execution Cycle
I
. enaI Output Da ena1 Input Data) and
bits are sent ta). In serial tr . , Instruction Cycle
the trans,.,.,, ~Ver a single line on b' ansnussion, data
«uss1on O ' e It at a ti
38 ver telephone !in Ine, such as Figure 1.3 Instruction cycle
INSIGHTS ON MIC es.
ROPRocessoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 39
Instruction Format
An instruction manipulates the data and a sequence of 2.4 Classification of an Instruction
instructions constitutes a program. Generally, each instruction has An instruction is a binary pattern designed inside a
two parts: one is the task to be performed, called the operation code microprocessor to perform a specific function (task) . The entire
(op-code) field, and the second is the data to be operated on, called group of instructions called the instruction set. The 8085
the operand or address field. The operand (or data) can be specified instruction set can be classified into five different groups:
in various ways . It may include 8-bit (or 16-bit) data, an internal • Data Transfer Group: The instructions which are used to
register, a memory location, or an 8-bit (or 16-bit) address. The op- transfer data from one register to another register or register
code field specifies how data is to be manipulated and address to memory fall in this category.
field indicates the address of a data item. For example,
• Arithmetic Group: The instructions which perform
ADD R1, Ro arithmetic operations such as addition, subtraction,
op-code address increment, decrement, etc. are categorized in this group.
H ere, Ro is the source register and R1 is the destination • Logical Group: The · instructions which perform logical
register. The instruction adds the contents of Ro with the content of operations such as AND, OR, XOR, etc. comes under this
R1 and stores result in R1. group.
8085A can handle at the maximum of 256 (=28) instructions; • Branching Group: The instructions which are used for
however, only 246 instructions are used in 8085A. The sheet which looping and branching such as jump, call, etc. are
contains all these instructions with their hex code, mnemonics, categorized in this group.
descriptions and function is called an instruction sheet. Depending • Miscellaneous Group: The instructions relating to stack
on the number of address specified in instruction sheet, the operation, controlling purposes such as interrupt operations
instruction format can be classified into the categories. including machine control instructions like HLT, NOP, etc.
• One address format (1 byte instruction): Here, 1 byte will fall under miscellaneous group.
be op-code and operand will be default.
2.4.1 Data Transfer Group Instructions
E.g., A DD B; MOV A,B
It is the longest group of instructions in 8085. This group of
• T~o address format (2 byte instruction): Here, first byte instructions copy data from a source location to destination
will be op-code and second byte will b th location without modifying the contents of the source. The transfer
e e operand/ data.
E.g., IN 40H; MVI A, 8-bit data of data may be between the registers or between register and
• Three address format (3 b t . memory or between an 1/0 device and accumulator. None of these
will be op-code y e 10struction): Here, first byte instructions changes the flag. The instructions of this group are:
' second and thi d
operands/ data. That is, r byte will be 1. MOV Rd, Rs (Move Register to Register)
2nd byte- lower order data.
• 1-byte instruction
3,d byte - higher order data
E.g., LXI B, 4050 H
• Copies data from source register to destination register .
• ~ & Rs may be A, B, C, D, E, H, and L
E.g., MOV A, B; A +- B
40 INSIGHTS ON MICRO
ROCESSORS
PROGRAMMING WITH 8085 MICROPROCESSOR 41
2. MVI R, B-bit Data (Move Immediate Data to Register)

2-byte instruction 7. LOA 16-bit Address (Load Accumulator D irect)

•
Loads the second byte ( 8-bit immediate data) into the • 3-byte instruction
•
register specified. ·• Loads the accumulator w ith the contents of m emory
location whose address is specified by 16 bit ad dress.
• R may be A, B, C, D, E, H, and L
E.g., LDA 4035H; A f- [4035H]
E.g., MVI C, 53H ; C f- 53H
8. LDAX Rr (Load Accumulator Indirect)
3. MOV M, R (Move to Memory from Register)
• 1-byte instruction
• 1-byte instruction
• Loads the contents of memory location pointed by the
• Copies the contents of the specified register to memory. contents of register pair to accumulator.
Here, memory is the location specified by the contents E.g., LDAX B; [A] f- [[BC]]
of HL register pair. LXI B, 9000H; B= 90, C= 00
LDAX B; A f- [9000]
E.g., MOV M, B
9. STA 16-bit Address (Store Accumulator Conten t D irect)
4. MOV R, M (Move to Register from Memory)
• 3-byte instruction
• 1-byte instruction • Stores the contents of accumulator to specified address
• Copies the contents of memory location as specified by E.g., STA FA00H; [FA00] f - [A]
HL register pair to a register. 10. STAX Rr (Store Accumulator Content Indirect)
E.g., MOV B, M • 1-byte instruction
5. LXI Rp, 16-bit Data (L oa d Register
· • Stores the contents of accumulator to memory location
Pair with Immediate
Data) specified by the contents of register pair.
• 3-byte instruction E.g., STAX B ; [BC] f-A
• Load immediate 16-bit data to register pair 11 . IN 8-bit Address (Input Data from Input Port)
Register pair may be BC, DE, HL, and SP • 2-byte instruction
• First it loads lower 8-bit d . • Reads data from the input port address specified in the
and th ata into lower order register
1 second byte and loads data into the accumulator i.e.,
. en oads higher 8-bit data into higher order
register. input port to accumulator.
E.g., LXI B, 4532H- B ~ C E.g., IN 40H; A f- [40H]
. ' 45, ~32H
6.
MVI M, Data (Load Memo . 12. OUT 8-bit Address (Output Data to Output Port)
. ry Wtth Immediate Data)
• 2-byte instruction • 2-byte instruction
•
Loads the 8-bit data to th • Copies the contents of the accumulator to the output
address is specified b e memory location whose port address specified in the 2nd byte i.e., accumulator
E y the contents of HL . to output port.
.g., MVI .M: 358· [HLJ pair.
' ' ~35H E.g., OUT 40H; [40] f-A
--:-:42:-.----
INSIGHTS ON MICROPROCESSoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 43
13. LHLD 16 _bit Address ( Load HL Pair Direct)

• 3 byte instruction MOVA,M

• Loads the contents of specified ~emory location to l- HLT
register and contents of next higher location to I-I- UsingLDAX
register.
LXI B, 2050H
E.g., LXI H, 9500H
LDAXB
MVIM,32H;
MVIL, 0lH;
MVIM, 7AH
LHLD9500H;
9500
9501

H=7A, L=32
88 A
HLT
Using LOA
LDA2050H
HLT
14. SHLD 16-bit Address (Store HL Pair Direct) 2. Register B contains 32H, Use MOV and STAX to copy the
• 1-byte instruction contents of register B in memory location 8000H.
UsingMOV
• It is opposite to LHLD instruction
LXIH, 8000H
• Store_s the contents of L-register to specified memory
location and contents of H-register to next higher MOVM,B
memory location. HLT
E.g., LXI H, 9500H UsingSTAX
SHLD 8500H; (8500] = 00, (850{] = 95 LXI D,8000H
15. XCHG (Exchange)
MOVA, B
• 1-byte instruction
STAXD
• Exchanges DE pair with HL pair.
.
HLT
E.g., LXI H, 7500H; H= 75, L=00
3. The accumulator contains F2H, Copy A into memory
LXI D, 9532H; D=95. E=32 8000H. Also copy F2H directly into 8000H.
XCHG;
Examples H= 9s, L=32; D=75, E=OO STA8000H
LXIH, 8000H
1. !he memory location 20SOH
instructions to trans{ th holds the data byte F7H. Write MVIM,F2H
diff er e data b t
erent op-codes: Moy L Y e to accumulator using
Using MQy ' DAX and LDA.
HLT
4. The data 20H and 30H are stored in 2050H and 2051H.
LXI H,2050H
WAP to transfer the data to 3000H and 3001H using LHLD
and SHLD instructions.
44

PROGRAMMING WITH 8085 MICROPROCESSOR 45

 MVIA, 20H
STA 2050H
1. ADD R/M (Addition)
MVIA, 30H
• 1-byte instruction
STA2051H
• Adds the contents of register/memory to the contents
LHLD2050H of the accumulator and stores the result in accumulator.
SHLD3000H E.g., Add B; A~ [A) + [BJ
HLT • All flags are affected
5. Register B contains 45H and register D contains C2H W 2. ADI 8-bit Data (Addition Immediate)
· AP
to swap the contents of register B and D . • 2-byte instruction
MVI B, 45H • Adds the 8-bit data with the contents of accumulator
MVID,C2H and stores result in accumulator.

MOVA, B E.g., ADI 9BH; A~ A+9BH

MOV B, D • All flags are affected

MOV D, A 3. SUB R/M (Subtraction)

HLT • 1-byte instruction

6. Pair B contains 1122H and air f • • Subtracts the contents of specified register/ memory
exchange the contents of pB ,p contain~ 3~H. WAP to with the contents of accumulator and stores the result
instruction. and D pair usmg XCHG in accumulator.
LXI B, 1122H E.g., SUB D; A ~ A- Q
B=11,C=22
LXID, 3344H • All flags are affected
D=33, E=44
MOV H, B 4. SUI 8-bit Data (Subtraction Immediate)
MOVL,C • 2-byte immediate instruction
XCHG • Subtracts the 8-bit data from the contents of
Exchange DE pair with HL pair accumulator stores result in accumulator.
MOV B, H
E.g., SUI D3H; A ~ A - D3H
Move, L
HLT • All flags are affected
5. INR R/M (Increment)
2.4.2 Arithmetic G
roup lnstructi OCR R/M (Decrement)
The 8085 . ons
· nucroproces • 1-byte instructions
operations as actct·ti
I
sor performs .
These arithm ti on, subtraction . Vanous arithmetic
e c operati , increment d • INR R/M and DCR R/M increases and decreases the
-:-:--r-- - ons have the followin an decrement. contents of R (register) or M (memory) by 1
46 INSIGHTS ON g mnemonics
MICROPRocessoRS . respectively.

PROGRAMMING WITH 8085 MICROPROCESSOR 47

 E.g., DCRB ; B=B-1
DCRM ; [HL] = [HL]-1
10. SBI 8-bit Data (Subtraction with Borrow Immediate)
!NRA ;A=A+l
INRM ; [HL] +1 • 2-byte instruction
• All flags are affected except carry. • It subtracts the 8-bit data from the content of
accumulator using previous borrow. It is 2 byte
6. INX Rp (Increment Register Pair)
instruction.
DCX Rr (Decrement Register Pair)
E.g., SBI 70H ; A +-A - 70 - Borrow
• 1-byte instructions
• All flags are affected
• Increases and decreases the content of register pair by 1. DAD Rp (Double Addition)
9.
• Acts as 16-bit counter in looping
• 1-byte instruction
E.g., INX B ; BC=BC+l
• Adds the content of register pair with the content of HL
DCXD ;DE=DE+l pair and stores the 16-bit result in HL pair.
• No flags are affected E.g., LXI H, 7320H
7. ADC R/M (Addition with Carry) LXI B, 4220H
• 1-byte instruction DAD B; HL +- HL + BC (7320 + 4220 = B540)
It adds the contents of register/memory with the • Only carry flag is affected if the result is greater than 16
cont~nt of accumulator using previous carry. It is 1 bit.
byte instruction.
E.g., ADC B ; A +-A + B + CY
10.
•
.
DAA (Decimal Adjustment Accumulator)
1-byte instruction
• All flags are affected
8.
ACI 8-bit Data (Addition with C I .
• Used only after addition
arry mmed1ate) • The content of accumulator is changed from binary to
• 2-byte instruction
two 4-bit BCD digits.
• It adds the 8-bit data 1. h
using previous ca "". t the content of accumulator E.g., MVI A, 78H ; A=78
rry. 1t is 2 byte instruction. MVI B,42H ; B=42
E.g., ACI 70H . A LA
' .,_ + 7O+cy ADDB ;A=A+B =BA
• All flags are affected
9. DAA ; A=20, CY=l
SBB R/M (Subtraction With Borrow)
• l-byte instruction • All flags are affected
• It subtracts the contents . Examples
content of accumul t o_f register/ memory from the 1. WAP to add two 4-digit BCD numbers equals 7342 and
byte instruction. a or using previous borrow. It is 1
1989 and store result in BC register.
E.g., SBB D
• ;A+-A-D B LXI H, 7342H
All flags are ff - orrow
a ected
48 LXI B, 1989H
INSIGHTS ON :::::--__

- - ------
r
MICROPROCEss~- - -
PROGRAMMING WITH 8085 MICROPROCESSOR
 MOVA, L
ADDC Features of Arithmetic Instructions
DAA The arithmetic operations, add and subtract are performed
in relation to the contents of accumulator. The features of these
MOVC,A
instructions are:
MOVA, H
1. They assume implicitly that the accumulator is one of the
ADCB operands.
DAA 2. They modify all the flags according to the data conditions of
the result.
MOVB,A
3. They place the result in the accumulator.
HLT
2. 4. They do not affect the contents of operand register or
Register BC contain 2793H and register DE contain 3182H memory.
Write instruction to add these two 16 bit numbers and
place the sum in memory locations 2050H and 2051H. But the INR and DCR operations can be performed in any
register or memory. These instructions
MOVA,C
1. affect the contents of specified register or memory.
ADDE
2. affect the flag except carry flag.
MOVL,A
MOVA,B Addition Operation in 8085
ADCD 8085 performs addition with 8-bit binary numbers and stores
MOVH,A the result in accumulator. If the sum is greater than 8-bits (FFH), it
sets the carry flag.
SHLD2050H E.g. MVI A, 93H B7H: 1011 0111
HLT MVIC,B7H
ADDC + 93H: "'"l-'-0"""'0_1_0'-0-'--1_1
3. R . [D 4A [DO 1 00 l O 1 0
egister BC contains 8538H
62ASH. Write instru ti and register DE contain CY 4AH---~
CY'--
from the contents of ;Cons to subtract the contents of DE
MOV A, C and place the result in BC. Subtraction Operation in 8085
SUBE 8085 performs subtraction operation by using 2' s
complement and the steps used are:
MOVC,A
1. Converts the subtrahend (the number to be subtracted) into
MOVA,B
its l's complement.
SBBD
2. Adds 1 to 1's complement to obtain 2' s complement of the
MOVB,A subtrahend.
HLT 3. Adds 2' s complement to the minuend (the contents of the
accumulator).

PROGRAMMING WITH 8085 MICROPROCESSOR 51

4. Complements the carry flag.

2.4.3 Logical Group Instructions

e.g MVI A, 97 H: 0110 0101
10 0 1 l Ol 0 A microprocessor is basically a programmable logic chip. It
MVI B,65 H:
can perform all the logic functions of the hardwired logic through
SUB B 2's comp.: 100 1 10 1 l
its instruction set. The 8085 instruction set includes such logic
97 : + 1 0 0 1 0 1 1 1 functions as AND, OR, XO~ and NOT (complement).
[00011 0010
The following features hold true for all logic instructions:
Complement carry = 0 1. The instructions implicitly assume that the accumulator
Accumulator= 32 H is one of the operands.
2. All instructions reset (clear) carry flag except for
BCD Addition complement where flag remain unchanged.
1n many applications, data are presented in decimal numbe 3. They modify Z, P, and S flags according to the data
r.
1n such applications, it may be convenient to perform arithmetic conditions of the result.
operations directly in BCD numbers. 4. Place the result in the accumulator.
The microprocessor cannot recognize BCD numbers; it adds 5. They do not affect the contents of the operand register.
any two numbers in binary. 1n BCD addition, any number larger The logical operations have the following instructions.
than 9 (from A to F) is invalid and needs to be adjusted by addin
6 in binary. g 1. ANA R/M (Logical AND)
E.g., A: 0000 1010 • 1-byte instruction.
+ 0000 0110
• Logically AND the contents of register/memory with
0001 0000 ➔ 10aco
the contents of accumulator and stores result into
A special instruction called DAA f . accumulator.
adjusting a BCD . per orms the function of
8
value of the least~:m. O~S. It uses the AC flag to sense that the • CY flag is reset, AC is set and others as per result.
BCD value Simil . bits is larger than 9 and adjusts the bits to
· ar1y, 1t uses CY flag t 0 d' E.g., ANA C; A +- A && C
four bits. a Just the most significant
2. ANI 8-bit Data (Logical AND with Immediate Data)
E.g., Add BCD 77 and 48
• 2-byte instruction .
77H 0 111 0111 • Logically AND 8-bit immediate data with the contents
+48H
+o100 1000 of accumulator and stores result into accumulator.
125H
1011 1111
• CY flag is reset, AC is set and others as per result .
+ 0 1 1O
E.g., ANI 85H; A +- A && 85H
01
1 01
ORA R/M (Logical OR)
~
3.
+0110
---.:. • 1-byte instruction.
...L ~
1 2 • Logically OR the contents of register/memory with the
contents of accumulator and stores result into
10010 0101
52 ~125seo accumulator.
INSIGHTS ON MICR
OPRocessoRS

I"
PROGRAMMING WITH 8085 MICROPROCESSOR
 • CY and AC are reset and others as per result.
E.g.,ORAC;A+-A 11 C CPI 8-bit Data (Compare Immediate with Accumulator)

4. ORI 8-bit Data (Logical OR with Immediate Data) • 2-byte instruction

, • All flags are modified.
• 2-byte instruction .
These instructions compare the content of register/memory
• Logically OR 8-bit immediate data with the cont
the accumulator and stores result into accumulatoents 0f or 8-bit data with the content of accumulator by subtracting
r. the data from accumulator. However, the content of
• CY and AC are reset and others as per result. operands are not modified. It is used -to compare the data
E.g., ORI 54H; A+- A I I 54H which can be used to indicate end of data. The status of
5. XRA R/M (Logical XOR) comparison is shown by flags as illustrated below.

• 1-byte instruction Case CY z

• [A]<[R/M] or 8-bit data 1 0
Logically exclusive OR the contents of reo-ister mem
.h h o· ory [A]=[R/M] or 8-bit data
wit t e contents of accumulator and stores result into 0 1
accumulator.
[A]>[R/M] or 8-bit data 0 0
• CY and AC are reset and others as per result.
E.g., CMP C; compares register C with accumulator
E.g., XRA M; A+- A EB [HL]
6. CPI 76H; compares 76H with accumulator
XRI 8-bit Data (Logical XOR with Immediate Data)
9. Logically Rotate Instructions
• 2-byte instruction
RLC (Rotate Accumulator Left)
• Logically exclusive OR 8-bit data immediate with the
• 1-byte instruction
content of accumulator and sto result tom·
accumulator. res
• Each bit is shifted to the adjacent left position. Bit D7
• CY and AC are reset d th becomes Do.
an °
ers as per result.
E.g., XRI 28H; A +- A EB 28H • The carry flag is modified according to D7.
7.
CMA (Complement Accumulator)
1
•
•
l-byte instruction
Complements the contents of th
~Dz
CY fffffff D ~

• No fl e accumulator. CY= D7, D7= D6, D6=Ds, ...... ,D1=Do, Do=D7

ags are affected.
E.g., CMA; A +- A' RAL (Rotate Accumulator Left through Carry)
8. Lo . all
gic y Compare Instructi • 1-byte instruction
CMpon.. ons
..,,n (Compare With • Each bit is shifted to the adjacent left position. Bit D7
• 1-byte · . Accumulator) becomes the carry bit and the carry bit is shifted into Do.
instruction
• Ali fla • The carry flag is modified according to D7.
--,..__ gs are modified
54 IIIISIGHTs 0111 MICROPRocessoRS
PROGRAMMING WITH 8085 MICROPROCESSOR
 Ldi:H tff f f £SJ
0

10. CMC (Complement Carry)

• 1-byte instruction
CY= D7, D7= D6, D6=Ds, ..... .,D1=Do, Do=cY
• It complements the carry flag.
RRC (Rotate Accumulator Right)
• No other flags are affected.
• 1-byte instruction 11. STC (Set Carry Flag)
• Each bit is shifted right to the adjacent position. B • 1-byte instruction
becomes D7. it Do
• It sets the carry flag to 1
• The carry flag is modified according to D 0 • • No other flags are affected
12. CMA (Complement Accumulator)

§-LiD±f f f ff f)J •
•
1-byte instruction
It complements the content of accumulator.

CY= Do, D7= Do, ... .. .,Do=D1 • No flags are affected

RAR (Rotate Accumulator Right throu gh Carry) Data Masking (Setting and Resetting Specific Bits)
• 1-byte instruction In various situations, we need to set or reset a specific bit
without affecting the other bits. This process is referred to as data
• Each bit is shifted right to the adjacent position. Bit Do masking.
becomes the carry bit and the carry bit is shifted into Di.
Setting bits
• The carry flag is modified according to Do.
Logical OR instructions are used to set particular bits

LiiH-°¥ff ff f +\J
without affecting other bits. This is done by ORing the particular
bits with logic 1 and other bits with logic 0. This is known as OR
masking.
CY= Do' Do= D1, ........ D7 = CY
For example, if the accumulator has data 1100 1000 = C8H
The rotate instructions
divide operations and f are ~sed in arithmetic multiply and • By ORing C8H with 03H (0000 0011) using instruction
or senal data transfer. ORI 03H, accumulator will have 1100 1011 = CBH, that
For example, if the ace
• umulator has data 00001000 = 8 is, Do and D1 of accumulator are both set to 1, and other
By rotating 08H left bits are unchanged.
0000 = 16 whi h . , accumulator will have 0001
c is equivale t t Resetting bits
• B .
y rotating 08H ri t
n °multiplying by 2.
0100 = 4 hi . gh , accumulator will h OOOo Logical AND instructions are used to reset particular bits
w ch 1s equ· al ave without affecting other bits. This is done by ANDing the particular
However, these . iv ent to dividing by 2.
D, to D0 are invalid When 1 . bits with logic O and other bits with logic 1. This is known as AND
and rotated right fr ogic 1 is rotate d left from masking.
om Doto D7.
56 INSIGHTS For example, if the accumulator has data 11001000 = CBH
ON IIIIICROPRocesso-~RS_ __
PROGRAMMING WITH 8085 MICROPROCESSOR 57
 By ANDing C8H with 3FH (0011 1111) Usii)
instruction ANI 3FH, accumulator will have OOOQ ~
10 LDAC020H
= OSH that is D7 and D6 of accumulator are both
, , reset RLC
to 0, and other bits are unchanged.
RLC
Complementing bits RLC
Logical XOR instructions are used to complement particul RLC
bits without affecting other bits. This is done by XORing t: STAC020H
particular bits with logic 1 and other bits with logic 0. This is' HLT
known as XOR masking.
4. Register C contains 95H. Write instructions to unpack
For example, if the accumulator has data 1100 1000 = C8H this data to 09H and 05H, and store into memory
locations 9050H and 9051H.
• By XORing C8H with OCH (0000 1100) using instruction
MVIC,95H
XRI OCH, accumulator will have 1100 0100 = C4H, that
MOVA,C ;Af--95H
is, 03 is complemented to 0 and D2 is complemented to
1, and other bits are unchanged. ANIF0H ; A f--90l-I
Examples RLC
1. Write a program to AND the content of memory location
RLC
COSOH and the content of register C, and store the result RLC
into location COSIH. RLC ; A f--09H
LDAC0S0H STA9050H
ANAC MOVA,C ;Af--95H
STAC0SlH ANI0FH ; A f--05H
HLT STA9051H
2. Write a program to 1 HLT
. . comp ement the content of register D
using instructions XRI and CMA. 5. Register B contains A6H. Write instructions to set D 6 and
Usin~ XRI to reset D2.
MOV A, D Using Masking
XRIFFH
MVIB,A6H
HLT
MOVA,B
Usin~CMA
ORI40H ; Sets D6 [OR 0100 0000 : A f-- 1110 0110]
MOVA, D
CMA ANI FBH ; Resets D2 [AND 11111011: A~ 1110 0010]
HLT MOVB,A

3. Write a program t h
HLT
o c ange th 1
the data stored in Joe ti e ower and upper nibble of
a onco20R.
S588T-;,;NS~IG;;;H~T;;S-;:
O-;::
N-M-IC_R_O_PR- - - -----------
0CESSORS
PROGRAMMING WITH 8085 MICROPROCESSOR 59
 Using Rotation
1. Jump Instructions
MVI B, A6H
MOVA,B ; CY r X, Ar 1010 0110 The jump instructions specify the memory location
; CY r 1, A r 0100 110x explicitly. They are 3-byte instructions, one byte for the
RAL operation code follow ed by a 2-byte (16-bits) memory
RAL ; CY r O, A r 1001 lOxl
address. Jump instructions can be used to create loops and
STC ;CYrl are classified into unconditional and conditional jump.

RAR ; CY r 1, Ar 1100 ll0x a. Unconditional Jump

RAR ; CY..- x, Ar 1110 0110: Sets D 6 8085 includes unconditional jump instructions to enable
RAR ; CY r 0, Ar xlll 0011 the programmer to set up continuous loop without
depending on any type of conditions.
RAR ; CY r 1, A r 0xll 1001
; CY ..--1, Ar lOxl 1100 JMP 16-bit Address
RAR
STC ;CYrl • 3-byte instruction

CMC ;CY..--0 • It loads the program counter by 16-bit address and

program execution transfers to that m em ory
RAL ; CY ..--1, Ar 0xll 1000
location.
RAL ; CY r 0, A..- xlll 0001
E.g., JMP 4000H
RAL ; CY..- x, A f- 1110 0010 : Resets D 2
The jump location can also be specified using a label (or
HLT
name). However, we should not specify both a label
2.4.4 Branching Group Instructions and its 16-bit address in a jump instruction.
Furthermore, we carmot use the same label for different
The microprocessor is a sequential machine· it executes
memory locations.
•
machine codes from one memory location to t~e next. The
branching
. instructio ns ms
· truct th e microprocessor to go to a Example
different
. memory. locati on and th e microprocessor
. continues Using 16-bit Address
executing machine codes from that new location.
Address Mnemonics
The branching inst ti
instructio b rue ons are the most powerful CO00H MVIA,00H
ns ecause they allow th .
sequence of a progr .h e microprocessor to change the C002H OUT40H
am, e1t er uncond.1r 11 I
conditions. The b hin . Iona Y or under certain tes
ranc g mstructi · C004H !NRA
follow ing three groups: ons can be categorized U1
CO0SH JMPC002H
• Jump Instructions
• Call and Return Instruction C008H HLT
• Restart Instruction

60
INSIGHTS ON MICROPROCESSORS
PROGRAMMING WITH 8085 MICROPROCESSOR 61
 Using Label Examples
MVIA,00H 1. WAP to move 10 by tes of data from starting address
Ll: OUT40H 9500 H to 9600H.

!NRA 9500H~=====~~t====:{_-=--=--=--=--=--=--=i9600H
JMPL1
HLT
Using Name
MVIA,00H 9509H 9609H
NEXT: OUT 40H MVIB,0AH
INRA LXIH,9500H
JMPNEXT LXID,9600H

HLT NEXI': MOVA,M

b. Conditional Jump STAXD

The conditional jump instructions allow the INXH

microprocessor to make decisions based on certain INXD
conditions indicated by the flags. After logic and DCRB
arithmetic operations, flags are set or reset to reflect the
conditions of data. These instructions check the flag JNZNEXT
conditions and make decisions to change or not to HLT
change the sequence of program. The four flags namely Write a program to transfer 30 bytes of data starting from
2.
carry,. zero, sign, and parity are used by the conditional 8500H to 9500H if data is odd else store OOH.
]Ump mstructwns.
MVI C, lEH ; Counter 30D = lEH
Mnemonics
Description
LXIH,8500H ; Source
JC 16-bit address/label Jump on carry (if CY=l)
JNC 16-bit address/label Jump on if no carry (if CY==O) LXID,9500H ; Destination
JZ 16-bit address/label Ju . NEXT: MOV A,M
JNZ 16 b" mp on zero (if Z=l)
P 16-b~t itdaddress/Jabel Jump on if no zero (if Z=O) RRC
J I a dress/label J
JM 16-bit dd ump on positive (if S=O) JCLl ; If data is odd, then go to Ll.
a ress/labe! J
JPE 16-b't1
d ump on negative (if S=l) MVIA,00B
a dress/ label J
JPO 16-b"t d ump on parity even (if P=l) JMPL3
\
I a dress/Jab I J
e ump on parity odd (if P=O)
62 INSIGHTS ON
MICROPROCESSORS PROGRAMMING WITH 8085 MICROPROCESSOR 63
 U: RLC
L3: STAXD RET
INX D • 1-byte instruction

INXH • Returns from the subroutine unconditionally

• t er to program
Inserts the contents of stac k pom . counter
to
DCRC •
and program control transfers into mam program
JNZNEXT execute it.
HLT E.g., RET
b. Conditional Subroutine Instructions
2. Call and Return Instructions (Subroutine)
CC/CNC/CZ/CNZ/CP/CM/CPF/CPO 16-bit Address /Label
Call and return instructions are associated with subroutine
• 3-byte instructions .
technique. A subroutine is a group of instructions that
perform a subtask. A subroutine is written as a separate unit • Call subroutine conditionally .
apart from the main program and the microprocessor • Same as CALL except that it executes on the basis of
transfers the program execution sequence from main flag conditions.
program to subroutine whenever it is called to perform a E.g., CC COS0H
task. After tJ:\e completion of subroutine task, 4. RCjRNCJRZ/RNZ/RPfRM/RPF/RPO
microprocessor returns to main program. The subroutine
• I-byte instructions.
technique eliminates the need to write a subtask repeatedly,
• Return subroutine conditionally .
thus it uses memory efficiently. Before implementing the
subroutine, the stack must be defined; the stack is used to • Same as RET except that if executes on the basis of flag
store the memory address of the instruction in the main conditions.
program that follows the subroutine call. E.g.,RZ
Subroutine instructions are classified into conditional and Examples .
unconditional.
1. Write an ALP to add two numbers using subroutines.
a.
Unconditional Subroutine Instructions MVIB,4AH
8000
CALL 16-bit Address /Label
8002 MVIC,A0H
• 3-byte instruction
8004 CALL9000H ; SP f- 8007H (PC), PC ~ 9000H
•
It calls subroutine unconditionally 8007 MOVB,A
• It saves the content of
stack pointer (SP) 1 program counter (PC) on the 8008 HLT
address), progra ' oads the PC by jump address (16-bit 9000 MOVA,B
m control transf .
execute subroutine. ers mto that location to ADDC
9001
E.g., CALL C040H ; PC ~ 8007H (SP)
9002 RET
64 IIIISIGHTso111
MICROPROCESSORS 65
PROGRAMMING WITH 8085 MICROPROCESSOR
2. wAP to sort in ascending order for 10 bytes from 9
OCJol{
START: LXI H, 9000H ; source · RST4 E7 0020H
MVID,00H ; notification RSTS EF 0028H
MVI C,09H ; counter RST6 F7 0030H
L2: MOVA,M RST7 FF 0038H

INXH When RST instruction is executed, the 8085 stores the

contents of PC on SP and transfers the program to the restart
CMPM
location. Actually these restart instructions are inserted through
JCLl ;ifA<M additional hardware. These instructions are part of interrupt
MOVB,M process.

MOV M,A 2.4.5 Miscellaneous Group Instructions

DCXH STACK
MOVM,B The stack is defined · as a set of memory location in R/W
memory, specified by a programmer in a main program. These
INXH
memory locations are used to store binary information tem porarily
MVID,0lH during the execution of a program.
Ll: DCRC The beginning of the stack is defined in the program by
using the instruction LXI SP, 16-bit address. Once the stack location
JNZL2
is defined, storing of data bytes begins at the memory address that
MOVA,D is one less than the address in the stack pointer register.
RRC For example if the stack is defined as LXI SP, 2099H, the location
JC START 2099H is useless and starts storing of data bytes from location
2098H and continuous in reverse order (decreasing memory
HLT address such as 2098H, 2097H etc.). Therefore, the stack is
3. Restart Instruction initialized at the highest available memory location to prevent the
8085 ms
· tru ction
. program from being destroyed by the stack information. The stack
set incl
These are 1 b te . udes 8 restart ins . instructions are:
executi y mstructions d tructions (RST).
on to a specific locati an transfer the program PUSH R.p /PSW (Store Register Pair on Stack)
Restart instru ti on.
con 0 • 1-byte instruction
RSTo p-code
Call location in hex
C7 • Copies the contents of specified register pair or program
RST1 000OH status word (PSW : pair of accumulator and flag register)
CF on the stack.
RSr2 0008H
D7 • Stack pointer is decremented by one, and content of high
RST3 0010H
DF order register is copied to that location. Then SP is again

I
66 INSIGHTS ON 0018H
MICROPROCESSORS
PROGRAMIIING vmtl 8085 ""'ROPROCESSOR &7
 decremented by one and content of low order re .
.
copied into that location. 8Istet .~
DI - disable interrupt
POP Rp /PSW (Retrieve Register Pair from Stack) El - enable interrupt

• 1-byte instruction SIM _ set interrupt mask

RIM _ read interrupt mask
• Copies the contents of the top two memory locations of
NOP - no operation
.
stack mto spec if'1ed regis
. t er pair
. or program status ,.. the
" otd HLT- halt
(PSW).
Examples
• The content of top of stack location indicated by SP ~
Execute the program below and illustrate the content of all
copied into low order register and SP is incremented b l. registers before and after using PUSH and POP
one. Then the content of top of stack is ·copied into hig~ instructions.
order register and SP is incremented by one.
LXI SP, 8FFFH
PUSH H
LXIH, 9320H
LXI B,4732H
H 20 10 L
LXID,ABCDH
SP=1997 MVIA,34H
SP=1999
PUSHH
PUSHB

10 PUSHD
1997 10
PUSHPSW
20
1998 20
POPH
X
1999 X POPB
POPD

H POPPSW
20 1O L
HLT
Before PUSH
SP::1999
H=93 L= 20
Some Other Instru ti
c ons C=32
B=47
X1BL - exchanges to O
f
stack (TOS) With BL
SPHL _ move HL to Sp
p D=AB E=CD
----.--P_CHL - move HL to PC A=34 F= lO
68
INSIGHTS ON MICROPRocessoRs
PROGRAMMING WITH 8085 MICROPROCESSOR
 After POP
H = 34 L=lO 1. Direct Addressing Mode:The instruction using this mode
C=CD specifies the effectiv e address as part of instruction. The
B=AB
instruction size is either 2-bytes or 3-bytes with first byte op-
D= 47 E=32 code followed by 1 or 2 bytes of address of data. Some
A =93 F=20 examples are:
LDA9500H
Note: STACK· works in LIFO (Last In First Out) m anner.
SHLDCOS0H
2. Write a program to set carry flag, reset sign fla IN80H
other flags as it is. g and keep
This type of addressing is also called absolute addressing.
LXI SP, CFFFH
2. Register Direct Addressing Mode: This mode specifies the
PUSHPSW ; Push flag into stack register or register pair that contains the data rather than
POPH address. That means the operand is in general purpose
; Retrieve flag into L recnster
o~
[HL t-A+F]
register. Some examples are:
MOV A,L
MOVA, B
ORI01H ; Set carry flag
ADDD
ANI7FH ; Reset sign flag
ORAC
MOVL,A
XCHG
PUSHH
; Push HL into stack Register · Indirect Addressing Mode: In this mode, the
3.
POPPSW operand part of the instruction specifies the register pair
; Retrieve
. upda t e d fl ag into
. flag register
HLT whose contents are the address of the operand. That means
the address of operand is specified by a register pair. So, in
2.5 Addressing Modes this type of addressing mode, it is the address of the address
Instructions are rather than address itself. Some examples are:
micropr ocessor. The instr command
. to p erform a certain task in
STAXB
[data or address] Th uction consists of op d d
onl · e•operand b -co e and operan LDAXD
reJst:: !oth of them. In thesen:~ t~e source only, destination MOVA,M
recnste/ amemory, or an input port s ·milc_ons, the source can be a
o· , memory I · 1 arl d 4. Immediate Addressing Mode: In this mode, the operand
which th dd ocation, or an Y, estination can be a position is the immediate data. That means, the operand is
ea ress of output
result is given in so~rce of data or the port. The methods by specified within the instruction itself. For 8-bit data,
other words th th e Instruction ar address of destination of
' e Vario f e called dd instruction size is 2 bytes and for 16-bit data, instruction size
are called addr . us ormats (way ) a ressing modes. In is 3 bytes. Some examples are:
th essmg mod s of spe uy·
e operands are es. So, addre . c mg the operands
1 MVIA,32H
addressing mod ocated rather than ths~mg mode specifies where
es. eu nat LXI B, 4567H
70 ure. The 8085 has five
INSIGHTS ON M
ICROPROcEssoRS
PROGRAMMING WITH 8085 MICROPROCESSOR 71
 SUI95H
XRI55H conditions are satisfied. These loops usu ally include
5. Implied or Inherent Addressing Mode: The m
· ..__ counting and indexing.
S., ~Cti
0
this mode do not have operands. If address of s 0 11s . The looping in 8085 microprocessor is performed by
urce '
as well as address of destination of result is fixed of d,~ following steps:
· d · ,then ,l1
1s no nee to give any operand along with the ins " !11 • Counter is set up by loading an appropriate cou nt in a
Some examples are: trucn0~
register.
NOP • Counting is performed by either incrementing or
HLT decrementing the counter.

CMA • Loop is set up by conditional jump instruction.

EI • End of counting is indicated by a flag.

Time Delay
2 ·6 Time Delay and Counter
When we use loop by counter, the loop causes the delay.
Counter Depending upon the clock period of the system, the time delay
occurs during looping. The instructions within the loop use their
It is designed simply by loadin an a .
one of the registers and . th g ppropnate number into own T-states. So, they need certain time to execute resulting delay.
. using e INR or OCR . tru .
1s established to updat ms ctions. A loop Suppose, we have an 8085 microprocessor with 2 MHz clock
e a count and each ·
d etennine whether i·t h h , count is checked to frequency.
as reac ed th f al
is repeated. e m number, if not the loop
Clock frequency of system (f) = 2 MHz
Loop 1 1
Clock period (T) = f = 2 xlQ--6 = 0.5 µs
. The programming techni
~croprocessor to repeat t ks . que used to instruct the
instructing th . as 1s called lo · Time delay example:
;n d e rrucroprocessor t0 h oping. A loop is set by
p~rform the task again Th. c ange the sequence of execution
ump instructions. . Is process is accomplished by using
Instructions T-Sates
MVIC,FFH 7
Loops can be classified . LOOP: DCRC 4
mto two t .
• Continuous loop ca egones:
JNZLOOP 10/7
It is set up by .
progr usmg the uncond · · Here, register C is loaded with count FFH (25510) by using
tasks am _With a continuous loo Itional Jump instruction. A MVI which takes 7 I-states. Time to execute. MVI instruction
until the system is reset p does not stop repeating the (outside loop)= 7 T-states x 0.5 = 3.5 µs
• Conditional loop .
Next, 2 instructions DCR and JNZ form a loop with a total of
It is set up b .
. Yusmgth 14 ( = 4+10) T-states. The loop is repeated 255 times until C=0. The
mstructions h e conditional J
---,.__ c eek flags and re ump instructions. These time delay in loop (TC) with 2 MHz frequency is
72 1NSIGHrs ON Mtc
peat the ..
specified tasks if the

I"
ROPRocessoRs PROGRAMMING WITH 8085 MICROPROCESSOR
 T1 = ( T x I-states of loop x count)

Where, instrumentation laboratory, readings such as v oltage and current

T1 = time delay in loop are maintained in decimal num bers, and data are entered through
decimal keyboard. The system m onitors program of the
T= system clock period instrument, converts each key into an equiv alent 4-bit binary
Count = decimal value for counter number, and stores two BCD numbers in an 8-bit register or a
memory location. These numbers are called packed BCD.
T1= 0.5 X 10-6 X 14 X 255 = 1785 µs
Conversion of BCD number into binary nu mber employs the
But JNZ takes only 7 I-states when exited from lo . principle of positional weighting in a given num ber.
loop delay is calculated as op. AdJuste/
E.g., 7210 = 7 X 10 + 2
T1. = T1 - (3 I-states)= 1785 µs - 3 x 0.5 µs = 1783.5 µs
Converting an 8-bit BCD number into its b inary equivalent
Total delay loop of program is expressed as
requires the following steps:
To= Time to execute outside loop + Tia inside loop • Separate an 8- bit packed BCD number into two 4-bit
= 3.5 µs + 1783.5 µs = 1787 µs = 1.8 ms unpacked BCD digits i.e., BCD1 and BCD2.
. To increase the time delay beyond 1 8 f 0111 0010 ➔ 0000 0010 (02H) Unpacked BCD1
rmcroprocessor we need t . ms or 2 MHz
within a loop. ' o use counter for register pair or loop ➔ 0000 0111 (07H) Unpacked BCD2
• Convert each digit into its binary value according to its
T-States Clocks position.
MVI B, 40H; 64 7 7xl BCD1=02H
L2: MVI C, 80H; 128
7 7x64
Ll: DCRC Multiply BCD2 by 10 = 7xlO = 70 = 46H
4 4x128x64 • Add both binary numbers to obtain the binary
JNZLl
10/7 (10x127+7xl) x64 equivalent of the"BCD number.
DCRB
4 02H + 46H = 48H
4x64
JNZL2
10/7 10x63+7xl Example
RET
10 1. WAP to read BCD number (Suppose 7010: 0111 0000BCD)
lOxl
store'd at memory location 2020H and converts it into
For 2 MHz micr Total clocks =115854 binary equivalent and finally stores that binary pattern
oprocessor total tim into memory location 2030H.
subroutine = 11 ' e taken to execute above
58 xo.s µs = 57.927 ms
LXIH, 2020H
2.7 Number Conversion MVIE,OAH
2.7.1 BCD toe · --- ; 01110010
•nary Conversion - - - - - - - - - - MOVA,M
In
most micro ANIFOH ; 01110000
and displayed . processor-based
74
111 decimal products data
numbers F , are
en-d
.... ~ RRC
INSIGHTS ON MICRQp . or example, in att
ROCEssoRs PROGRAMMING WITH 8085 MICROPROCESSOR 75
 RRC
RRC
LXI SP, 199?H
RRC
LXI H, 2020H; Source
MOVB,A
MOVA,M
XRAA CALLPWRTEN
Ll: ADDB ; 7x 10+2 HLT
DCRE PWRTEN:
JNZLl LXI H, 2030H; Destination
MOVC,A MVIB,64H
MOVA,M CALLBINBCD

ANI0FH MVIB,0AH

ADDC CALLBINBCD

STA2030H MOVM,A

HLT RET
BINBCD:
2.7.2 Binary to BCD Conversion
MVIM,FFH
If we need to convert a b. . .
BCD number, followin t mary number mto its equivalent NEXT:
g s eps can be sought·
Step 1· If b. · INRM
· mary number < 100 (64H), goo t step 2
Else subtract 100 (64H) .. SUBB
. repetitively.
Quotient is BCD1 (Divide by 100) JNCNEXT
Step 2: If
remainder from step 1 < 10 0 ADDB
Else subtract (0 ( AH), goto step 3
. 10 AH) repetitive! INXH
Quotient is BCD (D' . y. RET
Step 3: Rema. 2 IVIde by 10)
mder from step 2 is BCD 2.7.3 Binary to ASCII Conversion
E.g., 111111112 (FFH - 3 .
Example ) - 25510"' 0010 0101 0101aco A computer is a binary machine, to communicate with the
l. Ab' computer in alphanumeric letters and decimal numbers,
inary numb translation codes are necessary. The commonly used code is
memory 1 . er (Suppose FFH
and stor ocatton 2020}! Co : llll 11112) is stored ill known as ASCII (American Standard Codes for Information
e each BCD . nvert the CV
memory loca . as two number into B Interchange). It is a 7-bit code with 128 combinations and each
tion from 2030H unpacked BCD digits ill combination from 0lH to 7FH is organized to a letter, decimal
INSIGHTS ON M .
ICROPRocessoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 77
number, symbol or machine command. For example,
30
represents 0 to 9, 41H to SAH represents A to z, lf-iIi to 3~,
,~
2
represents various symbols, and 61H to 7AH represent to ~ CALL ASCII
s a to
General Letters /Numbers ASCII (Hex) ASCII (D . z. STAXD
ec11nill)
0-9 30-39 HLT
48-57
A-Z 41 - SA ASCII: CPI 0AH
65-90
JC BELOW
a-z 61-7A 97 -122 ADI07H
The following simple algorithm can be implem
BELOW: ADI 30H
need to convert 8-bit binary number to ASCII ented if II",
RET
If number < 10, then add 30H
Else add 37H (30H + 07H) 2. 7 .4 ASCII to Binary Conversion
For example: A= A+ 30H + 07H = 41H The following algorithm can be implemented for converting
Example
a number from ASCII to 8-bit binary.
Step 1: Subtract 30H
1. An 8-bit binary number is stored in memo . I .
Step 2: If < 0AH, then binary as it is
1120H. WAP to store the ASCII d _ry ocation
• . • co es of the binary di 'b Else subtract 07H
m 1ocation 1160H and 1161H. gi
E.g., if ASCII is 41H, then 41H - 30H = llH; llH - 07H =
LXI SP, 1999H 0AH
LXI H, 1120H ; Source Example
1. WAP to convert ASCII code stored at memory location
LXI D, 1160H ; Destination
1040H to binary equivalent and store the result at location
MOVA,M 1050H. LXI SP, 1999H
ANIF0H LXI H, 1040H; Source
RRC LXI D, 1050H; Destination
RRc MOVA,M
RRc CALLASCBIN
RRc STAXD
CALLAScu HLT
STAXo ASCBIN: SUI 30H
INXH CPI0AH
M:ov A,M: RC
•
ANI OFH SUI07H
INSIGHTS ON RET
MICROPRocessoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 79
z.7.5 BCD to 7-Segment LED Code Conversion
Each segment in a seven-segment display is identif
. h .. . . t· led bs number and select an appropriate seven segment code for
an index from O to 6, with t e positions given m 1gure. For ,, each digit. Th e cod es should be stored in output buffer
conversion, table lookup technique (TL T) is used. In TLT, the coct this memory.
digits to be displayed are stored sequentially in memory so es of LXI SP, 1999H
these codes can be used effectively and efficiently. tha1
LXI H, 1150H
0 MVID,03H
LXI B, 1190H
NEXT: MOVA, M
ANIFOH
RRC
RRC
RRC
RRC

BCD Number CALL CODE

7-Segment Code
INXB
0 3FH
MOVA,M
1 06H ANIOFH
2 SBH CALL CODE
3
4FH INXB
4
66H INXH
5 DCRD
6DH
6 JNZNEXT
7DH
7 HLT
07H
8 CODE: PUSHH
7FH
9 LXIH, 1170H
6FH
Invalid ADDL
OOH
Example MOVL,A
1. A set of three pack MOVA,M

t;
locations t . ed BCD numb
digits 0 arting at 1150H. The ers are stored in memor)'
memory I 9 for a common thseven segment codes of
STAXB
POPH
memory isocatton
r 8 . at ca ode LED are stored ill
starting ·
117011 RET
eserved at 1190H W and the output buffet
INSIGt-trs ON • AP to unpack the BCV
MICROPRocessoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 81
2 _8 Multiplication and Division
Multiplication
Example
Multiplicatwn can be performed by repeated addi .
However it is inefficient technique for a large multiplier. A. tio~ 1. Write a program to divide 16-bit number stored in memory
locations 8800H and 8801H by the 8-bit number stored at
efficient technique can be devised ·by following the ~ 011
memory location 8802H. Store the quotient in memory
multiplication of decimal numbers. Each bit of multiplier is t ~~
.. aken locations 8900H and 8901H and remainder in memory
one-by-one and it is chec kd e w hh et er It IS 1 or 0. If the bit locations 8902H and 8903H.
multiplier is 1, the multiplicand is added to the product anct of
product is shifted to left. When the bit of multiplier is o, ~
I
LHLD8800H ; Dividend in HL
product is simply shifted to left by one bit.
LDA8802H
Example MOVC,A ; Divisor in C
1. Write a program to multiply two 8-bit numbers stored a LXID,OO00H ; Quotient = 0
COSOH where multiplicand at C0S0H and multiplier a:
NEXT: MOVA, L
C051H; store 16-bit result at memory location C052H.
SUBC ; Subtract divisor
MVID,00H MOVL,A ; Save partial result
LDAC0S0H JNCSKIP ; ifCYljump
MOVE,A ; Multiplicand in DE DCR H ; Subtract borrow of previous subtraction
LOA C051H ; Multiplier in A SKIP: INXD ; Increment quotient
LXIH,00OOH
MVIC,08H ' ; Counter MOVA,H
LOOPl:DADH CPI OOH ; Check if dividend < divisor
RAL ; Left shift partial product by 1 bit
; Rotate multiplier by 1 bit JNZNEXT ; if no repeat
JNCNExr
MOVA,L
DADD · Prod -
NEXT: DCR c ' uct - Product + Multiplicand CMPC
JNZLOOPt JNCNEXT
SHLDC052H
HLT SHLD8902H ; Store the remainder
Division
XCHG
Division can be SHLD8900H ; Store the quotient
d· · · performed b
IVISor is s~b_tracted from the di . y repetitive subtraction. The HLT
~han the divisor. After s V1dend until dividend will be less
mcremented by 1. Fin I uccessful subtraction ti. t 'II be
remainder a Value of muI . . ' quo en W1
· tiplicand registers will be the

82

I"
INSIGHTS ON 1111
ICROPRocEssoRs
PIIOGRAMIING WITH BOBS MK:ROPROCESSOR
1. Write a program for 8085 to change the bit => LXI H, 9000H ;Let 16 bit number starts from 9000H
0
numbers stored at address 7600H if the number 5 of le1 MVI C, 09H ;set counter
s are I
than or equal to 80H. [2061 A h . ilrg~ MVI B, OOH ;to save carry over 16 bits
s Wzn]
⇒ LXIH, 7600H MOV E, M ;get LS byte of 16 bits data to E
IN X H ;increment the memory pointer
MVI C,0AH ;COUNTER MOV D, M ;get MS byte of the 16 bit data to D
LOOPl: MOVA,M ; A<-[H L] REPEAT: INX H ;increment the memory pointer
CPI80H MOV A,M ;get LS Byte of NEXT data to A
ADD E ;add it with PREVIOUS data in E
JC NEXT DAA
XRI20H MOVE,A
MOVM,A INXH ;increment the memory pointer
NEXT: MOVA,M ;get MS Byte of NEXT data to A
INXH
ADCD ;add it with PREVIOUS data in D
DCR C DAA
JNZLOOPl MOVD,A
HLT JNCPASS
2. MOVA,B
Registers BC contain 2793H . ADI0lH
3182H. Write instru ti and registers DE contain ;incremen t the carry by 1
and place the sum t ons to add these two 16 bit numbers
n memory location s 2050H and 2051H. PASS:
DAA
DCR C ;update counter
JNZ REPEAT ;continue for 10 w ords
⇒ [2062 Baishakh]
LXIB, 2793H INX H ;24 bit results in B, D, E respectiv ely
LXID,3I82H MOV M,E ;storing final 24 bit sum at end of
MOVA,C ;table
ADDE INXH
MOVM,D
MOVL,A
INXH
MOVA,B
MOVM,B
ADco HLT
MOVH,A 4. Write a program for 8085 to convert and copy the lowercase
SHLD2osoH ASCII codes to uppercase from memory location 9050H if
HLT any, otherwise copy as they are. Assume there are fifty
3. Write a program f codes in the source memory. [Note: ASCII Code for
and store 24-b. or 8085 to add t A=65 ....Z=90, a=97 ....z=122] [2062 Bhadra]
numbers. it Ben result at th:n 16-bit PCD numbers
end of the ten given LXI H, 9050H ; loads memory in HL
[2062 Bhadra] MVIC,32H ; counter for 50 codes.

PROGRAMMING WITH 8085 MICROPROCESSOR

 NEXT: MOVA, M
CPI61H ; compares with Asen v
alu_e Of'q 6. There are two tables TI, T2 in memory having ten eight bit
JCNOC data in each. Write a program for 8085 to find the difference
CPI7BH ; compare with ASCII valu of corresponding element of these two tables. Store the result
eof '..,
JNCNOC G 'I of each operation on the corresponding element of the third
table. Remember that the result should not be negative; it
SUI20H ; convert uppercase Asen to
should be I TI - T2 I. [2064 Poush]
; lowercase ASCII
⇒ A ssume table T1 - 2050H, table T2 - 2060H and table T3 - 2070H
MOVM,A
LXI H, 2050H ; Source 1 st table
NOC: INXH
LXI D, 2060H ; Source 2nd table
DCRC
LXI B, 2070H ; Destination
JNZNEXT
LXI SP, 8FFFH
HLT
NEXT: PUSHB ; Stores content of BC contained
5.
Write a program to transfer eight-bit numbers fr 908 ; in stack
to 9090H if bit Ds is 1 and D3 is 0. Otherwise tr o~ OH LDAXD ; load accumulator with data
by ch • b. ans,er dab
angmg it D2 and D6 from 1 to O or O to 1 A ; of [DE]
there are ten numbers • ssum1
· [2064 Shrawan] MOVB,A ; 2nd table content at B
⇒
LXI B, 9080H ; source MOVA,M ; A <-[HL] 1•1 table content
LXID, 9090H ;destination CMPB ;carry occurs w hen B>A
MVIL,0AH ; counter JCSWAPSUB
LOOPl: LDAX, B SUBB
; load A With content of (BE]
MOVH,A JMPSTORE
; H<---A
ANI28H SWAPSUB: MOV C,A
cPI20H ; AND With 0010 1000
MOVA,B
JNZCHANGE SUBC
MOVA,H
;A<---H STORE: POPB
JMPSTORE
STAXB
CHANGE: Mov A,H
; A<---H INXH
XRI44H
STORE: STAX D ; A<---data ·h INXD
Wit charged bit of Di &: 06
INXB INXB
INXo MOVA,L ; counter for 10
DCRL CPISAH ; L from S0H to 59H
JNZLOOPI JNZNEXT
HLT ; continues I00 HLT
P for 10 times.

PROGRAMMING WITH 8085 MICROPROCESSOR

I..
 7. Write an assembly language program to cou.
elements in a data block containing 16 bytes :; of , :o,
the count at the end of the block if the count • ilta; 11. JNZ STOREFF
1s great ~
8 otherwise store 0. [206S cz.~· er MOVA, C
'lllllrq) RLC
⇒

Assume: The data are located from C0S0H RLC

LXIH, COSOH RLC
RLC
MOY C, lOH ; counter 16
JMPSTORE
MOY B, OOH ; count-ve element
STOREFF: MVI A, FF
NEXT: MOY A, M
STORE: STAX D
RLC
INX D
JNCDOWN INXH
INRB OCR B
DOWN: INXH JNZNEXT
DCRC HLT
JNZNEXT 9. Write a program for 8085 to add corresponding data from
MOY A, B two table if the data from first table is smaller than the
CPI09H second table else subtract data of second table from first
JNCSTORE table. Store the result of each operation in the
corresponding location if the third table? Assume each
MVIA,OOH
table has ten eight bit data. [2066 Magh]
STORE: MOV M, A
⇒ Assume 1•1 table is at 2050H, 2 nd table is at 2060 H, and 3,d table is
HLT at 2070 H.
8. Write a p
rogram for 8085 to s . LXI SP, 2FFFH
and lower four b't ) wap nibbles (upper fow bib LXIH, 2050H
800 1
s of ten 'gh Source 1st table
OH and transfe t ei t bit number stores al
have Ds==l else stor: Fo ne_w location 8050H if the numbfl
LXI D, 2060H Source 2nd table
FH in the destinat·10n. LXIB, 2070H Destination
⇒
NEXT: PUSHB ; Stores the BC content in stack
LXI H, 8000H [2066 Shrawan]
LXI D, 8050 H ; source LDAXD ; load accumulator with data of [DE]
MVI B, DA H ; destination MOVB,A ; B+-2nd table content B
NEXT: Moy A, M ; counter MOVA,M ; A+-[HL] l st table content
Mov C,A CMPB ; carry occurs when B> A
ANI20H ; i.e., 2nd table is greater than 1st table
CPI20H JC ADDITION ; l• t table content<2nd table
INSIGlfrs ON 1111 SUB B ; subtract 2nd table from 1st table
ICROPRocEssoRs
POOG.....NG WITH .... IOCIOOPOOCESSOR , ..
 JMPBELOW
ADDITION: ADD B st
; add 1 table and 2nd table
DCRC
BELOW: POPB
JNZNEXT
STAXB ; stores addition or subtr .
action MOVM, E
INXH
INXH
INXD
MOVM, D
INXB
HLT
MOVA,L ; counter for 10
11. A set of three reading is stored in memory starting at
CPISA 9040H. Write an assembly language program to sort the
JNZNEXT readings in ascending order. Store the smallest value in
HLT address 9054H and so on in h igher addresses.
10. (2067 Mangsir]
Write a program in 8085 to add all the numbers f
• rom ⇒ Set of three numbers means there are 06 numbers [three 16-
table of 8-b1t numbers whose higher nibble value .1
bit numbers] in a table.
greater than 6 and store the 16 bit result just after the tab):
MVI D, 06H ; Main Coun ter
⇒ (2067 Shrawan} AGAIN: LXI H, 9040H ; Source
Assume there are ten numbers in a table starting from C0SOH MVI C, 06H ; Sub Counter
LXI Ji, COSOH ; source NEXT: MOVA, M
MVIC,OAH ; counter INXH
CMPM
LXID,OOOOH
; for sum JC NOSWAP ; For ascending order
NEXT: MOY A, M MOVB,M
ANIFOH MOVM,A
; to get upper nibble DCXH
RLC
MOVM,B
RLC lNXH
RLC NOSWAP: DCRC
RLC JNZNEXT
; A+-upper nibble DCRD
CPI 07H
JNZAGAIN
JC SK!p . if n LXI H, 9040H
Mov A, ~ umber < 07 i.e. no > 06 LXI D, 9054H
ADDE MVI C, 06H
;sum in E STORE: MOVA,M
MOVE,A
STAXD
JNCS.Kip
DCRC
INRo
JNZSTORE
SKIP: INXJ-J ; carry in D
HLT
INSIGHTS ON 1111
ICROPRocessoRs
12. There is a table in memory w hich has t
en .
numbers starting at 9350H. Write a progratn f e18ht ~
transfer the numbers from this table to anoth or 8oai ⇒ LXIH,A000H ; source
starts at location 9540H by swapping bit D er ta.'blet LXI D, A030H
6 and b· ; destination
the number is greater than 90H else transfer b 11 b1
MVIC, 0AH ; counter
48H. [2068 J y ijd~
⇒
esthaJ NEXT: MOV A, M
LXI H, 9350H ; source CPI25H
LXI D, 9450 H ; destination JC BELOW
MVIC,0AH ; counter CPI 70H
NEXT: MOVA, M
JNCBELOW
CPI 91H
;CY flag set for data<"9()j STAXD
JNCSWAP
ADI48H INXD

JMPBELOW BELOW:INXH
SWAP: MOV B, A DCRC
AN144H JNZNEXT
; A-an bits zero except
;D6&D2 HLT
CPI 44H
; 0 6& D2both are 1 14. Write a program in 8085 to transfer 8-bit number from one
JZBELOW table to other by setting bit Ds if the number is less than
; no need to swap
CPI OOH 80H else transfer the number by resetting bit D6,
; 0 6& 0 2both are O
JZBELOW [2068 Bhadra]
; no need to swap
MOVA,B ⇒ Suppose first table is having ten 8-bit numbers starting from
XRI44H A000H and second table starting from A030H.
BELOW: ST AX D LXI H, A000H ; source
INXD LXI D, A030H ; destination
INXH MVIC,0AH ; counter
DCRc NEXT: MOVA, M
JNZNEXT
CPI80H
HLT
13. JC BELOW ; if number < 80H
Ten no. of 8-bit
a pro data is started .
t bl gram for 8085 m. in mem ory at AOOOH. Wri~ ANIBFH ; resets D6
a e at A03Q}i icroproces "'
24}i if the data • sor to copy the data to n,,. JMPSTORE
. 1
is ess th
an 70H and greater tbaJI
BELOW: ORI20H ; sets Ds
INSIGHTS ON [2068 Magh]
MICROPRocEssoRs
PROGRAMMING WITH 8085 MICROPROCESSOR 93
 STORE: STAX D
INXH
INXD RRC
RRC
DCRC RRC
JNZNEXT RRC
MOVB,A ; u pper nibble
HLT MOVA,M
15. Write an assembly language program for 8085 to exch ANI0FH ; lower nibble
the bits D6 and 02 of every byte of a program. Su an~ ADDB
there are 200 bytes in the program starting from m:;:11 STAXD
INXH
location 8090H. [2070 Bhadra] q
INXD
⇒
LXI H,8090H; source DCRC
MVI C, C8H ; counter 200 JNZNEXT
NEXT: MOVA,M HLT
ANI44H
17. Write a program in 8085 to calculate the n umber of on es in
CPI 44H .: check if both bits are 1
JZNOSWAP the upper nibble of ten 8-bit numbers stored in tabl e. Store
the count of ones in a location just after the table.
CPI OOH ; check if both bits are O
JZNOSWAP [2072 Ashwin]

MOVA,M ⇒ Suppose table starts from 8050H.

XRI 44H ; swap bits D6 and o2 LXI H , 8050H ; Source
MOVM,A MVI C, OAH ; Counter
NOSWAP: INX H
MVI D, OOH ; to counter result
DCRC
NEXT: MOVA, M
JNZNEXT
BLT ANIF0H
16. Write a p MVIE, 04H ; upper nibble counter
rogram for 8085 CHECK: RLC
nibble of ten 8 b"t
1 to add the upper and lower
Words st d · JNCBELOW
location 8B20H St ore tn a table that starts fro11l
· ore the s . INRD
after the table. eparate results in locations JUS1
⇒ BELOW: DCRE
LXIB,8B20B [2071 Bhadra}
; source JNZCHECK
LXI D,8B2Aii
; destination INXH
MVrc,OAB
NEXT: Moy A, M ; counter DCRC
ANIFOB JNZNEXT
MOVM,D
HLT

PROGRAMMING WITH 8085 "1CROPROCESS0Rl..-

18. Write a program for 8085 to generate multipJica .
of a number stored at 8230H and store the ge tiori tahi
nerat cl 1 20. There are two tables holding twenty data whose
starting at 8231H. For example, if location e ta 04
8
number 05H then store 05H at 8231H, OAH at :0l-f % starting address is 9000H and 9020H respectively.
823
on. [2072 AA and ~ WAP to add the conten t of first table with the content
iv1aghJ
of second table having same array index. Store sum
⇒ LXI H, 8231H ; destination
and carry into the third and fourth table indexing
MVIC,0AH ; counter from 9040H and 9060H respectively. [2074 Bhadra]
LDA8230H ; soucce ⇒ LXI B, 9000H ; Table 1
LXI H , 9020H ; Table 2
MOVB,A
NEXT: MVI E, OOH ; for carry
MVIA,00H LDAXB
NEXT: ADDB ADDM
MOVD,A ;sum
MOVM,A
JNCBEL
lNXH MVIE, 0lH
DCRC BEL: PUSHB
PUSHH
JNZNEXT MOY A,C
HLT ADI40H
19. Write an assembly l MOVC,A ; makes [BC] as Table 3
square of ten 8-bx't angubage program for 8085 to find the MOVA, D
num ers wh' h
memory location C090H IC are S OFH, stored from STAXB ; stores sum in Table 3
the source table. · 8t0re th e result from the end of MOVA, L
⇒ [2073 Magh] ADI40H
LXIH, C090H ; Source
MOVL,A ; makes [HL] as Table 4
LXID, C09AH
; Destination MOVM,E ; stores carry in Table 4
NEXT: MVIC,OA
; Counter POPH
MOVB,M
POPB
SQUARE: MVIA,OOH
INXB
ADDM
INXH
DCRB
MOVA, C
JNZSQDARE
CPI14H ; checks for 20 data
STAXo
INXH JNZNEXT
INXo HLT
I

DCRc 21. Write a program for 8085 to count the numbers for which ·
JNZNEXT upper nibble is higher than the lower nibble; and store the
HLT count at the end of table having 50 bytes data from C050H.
[2075 Bhadra]

PROGRAMMING WITH 8085 MICROPROCESSOR 97

 ⇒ LXIH, COSOH ; Source
MVIC,32H ; Counter
MVID,OOH ; Counter for upper nibbl
MOVM,B
;than lower nibble e greater INXH
NEXT: MOVA, M
NOSWAP: DCR C
ANI FOH
RLC JNZNEXT
RLC DCRD
RLC JNZ AGAIN
RLC MOV A,M
MOVB,A STA C070H ; Largest number
MOVA,M LDACOSOH
ANI OFH STA C071H ; Smallest number
CMPB HLT
JNCBELOW Alternative Method
INRD
BELOW: MVI D, 14H ; Counter
INXH LXI H, COSOH ; Source
DCRC MVI D OOH ; Largest Number
JNZNEXT MVIE,OOH ; Smallest Number
MOVM,D NEXT: MOVA, M
22.
HLT
Write a pr . CMPD
ogram in 8085 to f" d
bytes from the list of 20 b In the largest and smallest JC BEL
location cosoa s ytes stored Starting from MOVD, A
• tore the I memory
co7oa and C07Jff respectively
argest byte and smallest byte in BEL: CMPE
MVI D, 14H . . . [2076 Baishakhi JNC BELl
AGAIN: LXI LY C ' Mam Counter ' MOVE,A
n, 050H ·So
MVI C , urce BEU: INXH
, 14H . b
NE XT: Moy A , 8 u Counter DCRC
,M
IN)( H JNZNEXT
CMPM MOVA,D
JCNoswAP STAC070H ; Largest number
Moy B, M ; For ascending order MOV A,E
MovM,A STAC071H ; Smallest number
DcxH HLT
+++

PROGRAMMING WITH 8085 MICROPROCESSOR

,------------------Chapter,! Bus Interface Unit (BIU)

PROGRAMMING WITH 8 ~ The BIU sends ou t addresses, fetches instructions from

memory, reads data from ports and memory, and writes data to
MICROPROCESSOR ports and memory. In other word s, the BIU handles all transfers of
data and addresses on the buses for execution unit (EU). It has
3.1 Introduction mainly two parts: instruction queue and segment registers.
The BIU can store up to 6 bytes of instructions with FIFO
The Intel 8086 is a 16-bit microprocesso r that i s ~
(First in First Out) manner in a register set called a queue. When
be u~ed as the ~PU i_n a ~~ro~omputer. The term 1 ~;;ded 1
EU is ready for next instruction, it simply reads the instruction
~at its _anthrnetic logic urut, its mtemal register s, and mo llleilJ!
instructions are designed to work with 16-bit binary st of th from the queue in the BIU. This is done in order to speed up
8086 has a 16-bit data bus, so it can read data from Words. 'I'!\ program execution by overlapping instruction fetch with
. or Write ct t execution. This mechanism is known as pipelining.
me~ory and ports either 16 bits or 8 bits at a time. The a af
808
20-bit address bus, so it can address any one of 220 1 0486h~, The BIU contains a dedicated address, which is used to
memory locations. ' or , ~7!
produce 20-bit address. Four segment registers in the BIU are used
to hold the upper 16 bits of the starting add;ress of four m emory
3.2 Internal Architecture of 8086 M"
1croprocessor segments that the 8086 is working at a p articular time. These are
As shown in the Figure 3 1 th 80 . . . - code segment, data segment, stack segment and extra segment. The
independent functional arts· . ' e . 86 CPU is d1v1ded into two 8086' s 1 MB memory is divided into four segments w ith u p to
execution unit (EU). p . the bus mterface unit (BIU) and tr,
64KB memory for each.

Code segment register and instruction pointer (IP): The CS

contains the base or start of the current code segment. The IP
contains the distance or offset from this address to the next
I instruction byte to be fetched. Code segment address plus an offset
rl

=-=-~
value in the IP indicates the address of an instruction to be fetched
for execution.
Data segment register: Data segment contains the starting
, - - - - -- - . I address of a program's data segment. Instructions use this address
I to locate data. This address plus an offset value in an instruction,
causes a reference to a specific byte location in the data segment.
Stack segment (SS) register and stack pointer (SP): Stack
segment contains the starting address of a program's stack
segment. This segment address plus an offset value in the stack
pointer indicates the current word in the stack being addressed.
Extra Segment (ES) register: It is used by some string
(character data) to handle memory addressing. The string

PROGRAMMING WITH 8086 MICROPROCESSOR 101

instructions always use the ES and destination index (DI) to the offset address in the current stack segment. This offset is used
determine 20-bit physical address. by mstructions utilizing the based addressing mode.
Execution Unit (EU) Index register: The two index registers SI (source index) and
DI (destination index) are used in indexed addressing. The
The execution unit of the 8086 tells the BIU where to fetch
instructions that process data strings use the SI and DI ind ex
instructions or data from, decodes instructions, and executes
register together with DS and ES respectively, in order to
instructions.
distinguish between the source and destination address.
The EU contains arithmetic and logic (ALU), a control unit Flag register: The flag register, also known as a status
and a number of registers. These features provide for execution 0 ; register, is a 16-bit register that contains nine flags out of which
instructions and arithmetic and logical operations. It has nine 16- five are 8085-like flags and remaining four are new flags. Out of
bit registers which are AX, BX, CX, DX, SP, BP, SI, DI, and a flag nine, six are status flags and three are control flags. The control bits
register. First four can be used as 8-bit register (AH, AL, BH, BL, in the flag register can be set or reset by the programmer.
CH, CL, DH, DL) each.
AX register: AX register is called 16-bit accumulator a nd AL [ x I x I x I x j o I D/ I IT!SIZ/ xlA/x/Pl xleJ
D15 D1• D1, D12 Du D10 D• Ds D, D• Ds D, D3 D2 D1 Do
is called 8-bit accumulator. The 1/0 (IN or OUT) instructions always
use the AX or AL for inputting/ outputting 16- or 8- bit data from 1. O (overflow flag): This flag is set if an arithmetic overflow
or to I/ 0 port. occurs after an addition or subtraction i.e., if the result of a
signed operation is large enough to be accommodated in a
BX register: BX register is known as the base register since it destination register.·For example, if a 7FH (+127) and a 0lH
is the only general purpose register that can be used as an index to
(+1) are added, and they are signed numbers, the result is
extend addressing. The BX register is similar to the 8085's H L
80H (- 128). Because -128 is not the correct signed result, the
register. BX can also be combined with DI or SI as a base regi:ter 0 flag is set to indicate an overflow.
for special addressing.
2. D (direction flag): This is used by string manipulation
CX recnster: The ex re<nst · kn ·
o- o- er IS own as the counter register instructions. If this flag bit is '0' , the string is processed
because some instructions such as SHIFT, ROTATE and LOOP use
the contents of ex as a counter. beginning from the lowest address to the higher address i.e.,
auto incrementing mode otherwise the string is processed
DX register: The DX reg· t · k from the highest address towards the lowest addre~s i.e.,
I/O . . . Is er Is nown as data register. Some
operations requrre its use. For multi . . . . . auto decrementing mode.
operations that in 1 1 P1ication a:"-d d1v1S1on
vo ve arge values assume th AX
together as a pair kn e use of DX and 3. I (interrupt flag): If this flag is set, the maskable interrupts
rightmost 16 bits. own as EDX where DX comprises the
are recognized by the CPU, otherwise they are ignored.
Stack pointer (SP) and base . 4. T (trap flag): If this flag is set, the processor enters the single
access data in the stack segm t Thpointer (BP): Both are used to step execution mode. In other words, a trap interrupt is
en. esp· d
the current stack segment d . is use as an offset from generated after execution of each instruction. The processor
urmg executio f .
SP' s contents are automati II n o instructions. The executes the current instruction and the control is
d · ca Y updated ("
unng execution of a POP and PUS . mcrement/ decrement) transferred to the Trap interrupt service routine.
H Instructions. The BP containS
102 INSIGHTS ON MICROPR
ESSORS 103
PROGRAMMING WITH 8086 MICROPROCESSOR
5. s (sign flag) : This flag is set when the result of
·
computation is negative. ·
For s1gne any
d compu t a ti. ons, the sign 8. A 16-bit ALU in the EU maintains the MP status and control
flag equals the MSB of the result. flags, manipulates general register and instruction operands.

6. z (zero flag): This flag is set when the result of the 3 .2.2 Segment and Offset Address
computation is or comparison performed by the previous Segments are special areas defined in a program for
instruction is zero. 1 for zero result, 0 for nonzero result containing the code, data, and stack. A segment begins on a
7. A (auxiliary carry): This is set if there is a carry from the paragraph boundary. A segment register is of 16 bits in size and
contains the starting address of a segment.
lowest nibble during the addition or borrow from the lowest
nibble during subtraction. A segment begins on a paragraph boundary, which is an
8. P (parity flag): This flag is set to 1 if the lower byte of the
address divisible by decimal 16 or hex 10. Consider a DS that
result contains even number of l's otherwise reset. begins at location 038E0H. In all cases, the rightmost hex digit is
zero, the computer designers decided that it would be unnecessary
9. C (carry flag): This flag is set when there is a carry out of to store the zero digit in the segment register. Thus 038E0H is
MSB in case of addition or a borrow in case of subtraction. stored in register as 038EH.
3.2.1 Features of8086 Microprocessor The distance in bytes from the segment address to another
Intel 8086 is a widely used 16-bit microprocessor. The location within the segment is expressed as an offset or displacement.
features of 8086 microprocessor can be su1r..marized as follows: Suppose the offset value is 0032H for above example of data
1.
segment. The effective address or an actual logical memory
The 8086 can directly address 1MB of memory.
location addressed by an instruction is the sum of the segment
2. address and the offset address. Hence, we can generate the 20-bit
The internal architecture of the 8086 microprocessor is an
example of register-based microprocessor and it uses physical address by using the expression that follows.
segmented memory.
SA: OA (segment address: offset address)
3.
It pre-fetches up to 6 instruction bytes from the memory and 038EH : 0032H = 038EH x 10H + 0032H
5J_ueues them in order to speed up the iristruction execution.
4. = 038E0H + 0032H = 03912H
It_ has d~ta bus of width 16 bits and address bus of width 20
bits. So 1t always accesses a 16_b·t Therefore, physical address = 03912H
1 wor d to or from memory.
5. Programmer's Model of an 8086 Microprocessor
The 8086 microprocessor is divided internally into two
separate uruts which are bus interface uru't (BIU) d th Figure 3.2 illustrates the programmer's model of an 8086
execution unit (EU). . an e microprocessor.
6. The BIU fetches instructi ·
results. ons, reads operands, and writes
7. The EU executes instru t·
c 10ns that h
by BIU so that instru ti ave already been fetched
. k c ons fetch overla .h .
w hi ch IS nown as pipelin. ps wit execution
mg.

104 INSIGHTS ON IIIIICROP

CESSOR$
PROGRAMMING WITH 8086 MICROPROCESSOR 105
 8-b1t
Names word
A u,ord is formed with two bytt., of d a ta . The least
ignificant byte i lw~y ~tor ·d in l~P lowi·st num bered memory
ioeation nd the mo t 1grnf1c, nt bytt m the highi>f>t.

E;8
AH AX AL Accumulator
l11StnK,1.1on Po,~

BH BX BL Base lndn 0oubleWord

a fl•
Double U)()rd format I u d to lore '\2-bit numbe rs (4 by tes)
CH ex CL Count
that ar th product in mulllplication or tlw div id end in a
l~
DH DX DL Oata di 10n
0 111
SP Stac~ Pointer Real Numbe
BP lia~e PuintC"r re Otten ~.1II d fl o,i ting-point
DI Destmatum Ind
number, 1. m m11nt1i1 and an t' lJ'Ollnrl

SI SourC(." lnde. 3.3 Instruction

Figure 3.2: l'rogmmmer's model Q Rn 086 mr r o p ~ The 8086 e 1111\ ,lll•nt:-; to the
r lm I , n · 8-hll nitunprocl' sor
3.2.3 Data Formats
Th 186 m <; trm lltin, can be
Successful programming trt,rgfrr, 11nthrnrti,, t,,t 111,1111pu/a/1011, trm-.;:,
understanding of data forma m'CICWII.,, control
microprocessor c1s: A II, B D,
on
integers, 16-bit (word) signed nd uns1
(d ouble-word) signed nd un ignf'd mre or word of data
long real numbers (or floating lX)mt numbers) n th l1:cumulator
'""'..,._mr mclud iollowmg
ASCII Data

The ASCII code is 7-b,t cod / Imm h te

significant bit used to hold parity an
BCD

Binary coded d 1m J (BCD) inform.hon I

packed or unpacked forms In the me r
w hen two BCD digits are tOJ"N per mernory
w hen one BCD digit is tored per byte mory
Byte

Byte data are stored In two fo

integers.

1oa I
1NS1GHTS 0111 MIClllai..,

--
 E.g., XCHG AX, BX DIV (Divi Ion)
g.
XCHGAL, BL
- DIV Re ⇒ AX/Ki, (Remaind\!r -.. AH) and
XCHG CL, [BX) (Quotient AL)
IN AL, DX ; DX: l'ort .uidr , AH al o in AL - DIV R16 ⇒ DX:AX/R 1i, (Remainder --. DX) and
OUT DX, AL/ Al I (Quotient AX)

1. Arithmetic Instructions h. IDIV ( igned Divi Ion)

a. ADD (Addition) DIV but tak ign mtn a, <"ounl.

- ADD rcg,/ mem8 , n'gx/ m ms/1mmcdi t I. I C/D (lncnmenVl>ecffm nt by t)
-ADD reg1 , /nwm1,, reg16/ mem1 / 1mm dt If, I
E.g., ADD AH, I 'i ; It add bmaJ) number
ADD Al I, NUMI J.
ADD Al, [BX[ k.
ADD[BX],CH dditwn)
ADDA , [B ]
b. ADC (Addition with
- ADC reg/ mem, r g/ m/1mmed
c, SUB (Subtraction)
- SUB ri:g/mem, g/mem/ 1mmed1
d. SBB (Subtraction with Borrow)
2.
-SBB reg/mem, reg/mem/unmed
e. MUL (Multipllc tion)
- MUL rega/m (8-btt m, g/mem/ammediate
- MUL reg16/ mem16 (16-hat
E.g.,
MUL

MUL Rt& (multiplier) • Ra

f. IMUL (Signed Multipl ation) 1/
. Sarne oper tion MUL but

"'\ ,__,,..,.._.._,_________.... R R (Ro,-,- f)

r
 RCL (Ro tate left through carry)
Flag Operation
RCR (Rotate right through carry) •• _CLC (clear carry flag)
E.g., ROL AX, 1 ; rotate by 1 _CLD (clear direction flag)
ROL AX, CL ; if we need to rotate more than one bit
_CLI (clear interrupt flag)
RCLCX, 1
_STC (set carry flag)
RCL [BX], CL ; Only CL can be used
_STD (set direction flag)
c. Shifting
- STI (set interrupt flag
- SHL/SHR/SAL/SAR reg/ mem, 1/ CL
_ CMC (complement carry flag)
SHL (Logical shift left)
SHR (logical shift right)
_LAHF (load AH from flags (lower byte))
-Shifts bzt in true direction and fills zero in vacant place - SAHF (store AH to flags)
SAL (Arithmetic shift left) - PUSHF (push flags into stack)
SAR (Arithmetic shift right) - POPF (pop flags off stack)
-Shifts bit/word in true direction, in former case place zero in s. ST ACK Operations
vacant place and in later case place previous sign in vacant
place. -PUSHreg16
E.g., SHL AX, 1 ; rotate by 1 - POPreg16
SHLAX,CL ; if we need to rotate more than one ilit 6. Looping Instruction
SAR DX, 1 CX is automatically used as a counter.
SAR [BX], CL ; Only CL can be used - LOOP (loop until complete)
d. Comparison
- LOOPE (loop while equal)
- CMP reg/ mem, reg/ mem/ immediate
- LOOPZ (loop while zero)
CMP (Compare)
- LOOPNE (loop while not equal)
E.g., CMP BH, AL
Operandl Operand2 - LOOPNZ (loop while not zero)
CF SF ZF
7. Branching Instruction
> 0 0 0
- 0 0 1
a. Conditional
< 1 - JA Gump if above)
1 0
TEST. test bits (using AND operation) - JAE Gump if above/ equal)
TEST reg/ mem, reg/ mem/ ~ediate - JB Gump if below)
- JBE Gump if below/ equal)
0;.RS;-------------
1'11ioo~1.;;•Niss1iGGiHH,:;rs~o01NNMM1KIC:RRooPiPR"oicciEss;;;
PROGRAMMING WITH 8086 MICROPROCESSOR 111
 - JC Gump if carry) String Instructions
9.
_JNC Gump if no carry) _ MOVS/MOVSB/MOVSW ; Move string
_JE Gump if equal) DS: SI (source)
_JNE Gump if no equal) DS: DI (destination)
- JZ Gump if zero) CX (string length)
- JNZ Gump if no zero) -CMPS/ CMPSB/CMPW ; Compare string
- JG Gump if greater~ _ LOOS /LODSB/LODW ; Load string
- JNG Gump if no greater) -REP ; Repeat string
- JL Gump if less)
J.4 Operators in 8086
- JNL Gump if no less)
An operator provides a facility for changing or analyzing
- JO Gump if overflow)
operands during an assembly. Operators are active during
- JS Gump if sign) assembling but no machine language code will be generated.
- JNS Gump if no sign) Operators are divided into various categories:

- JP Gump if plus) 1. Calculation Operators

- JPE Gump if parity even) i. Arithmetic Operators

-JNP Gump if no parity) These operators include the familiar arithmetic signs
and perform arithmetic during an assembly. These
- JPO Gump if parity odd) operators are:
b. Unconditional
+ (addition), + (positive), - (subtraction), - (negation),*
- CALL (call a procedure) (multiplication), / (division), and % (remainder).
- INT (interrupt) ii. Index Operators
- JMP (unconditional jump) For indirect addressing of memory, an operand
- RETN/RETF (return near/far) references a base or index register, constants, offset
variables, and variables. The index operator uses square
- RET (return)
brackets.
- IRET (interrupt return)
8. MOV AX, [SI]
Type Conversion
iii. . Logical Operators
- CBW (convert byte to word)
The logical operators process the bits in an expression.
- CWD (convert word to do bl .
u eword) The logical operators are:
AND, OR, XOR, NOT
1<11i2211.;;1Niss1iGGiHH;Ts;co;;N;iMM1C1ciRooiP~RicoiccEessiSo~RS;;-------------
PROGRAMMING WITH 8086 MICROPROCESSOR 113
 TYPE - returns the number of bytes defined for reference
iv. Shift Operators
The shift operators shift an expression during an variable.
assembly. The shift operators are: LENGTH - returns the number of entries defined by a DUP
operator.
SHR, SHL
SIZE - returns the product of LENGTH times TYPE. THIS _
2. Macro Operators creates an operand with segment and offset values that are
A macro is an instruction sequence that appears repeated! equal to those of current location counter.
in a program assigned with a specific name. Y
Basic format of a macro definition: 3,5 Coding in Assembly Language
Macroname MACRO [parameter-list] ; Define mac-;; The assembly language programming needs good
[instructions] ; Body of macro knowledge of machine architectur_e, operating system, and
ENDM ; End of macro programming principles. Assembly language is case insensitive,
3. Record Operators therefore, program can be coded either in uppercase or lowercase
The record operators are: or combination of both. The programs written in assembly
language are compact and efficient, which has to be converted to
~ SK - r e ~ a mask of 1-bits representing the specified machine code for execution and it is performed by the translator
field, and defmes the bit positions that
. the field occup·e
1 ~
known as assembler.
WIDTH - returns a width as the number of bits in a
RECORD. Advantages of assembly language programming:
4. Relational Operators • They generate small and compact execution module.
The relational operators are: • They have more control over hardware.
EQU, GE, GT, LE, LT, NE • They generate executable module and run faster.
5. Segment Operators Disadvantages of assembly language programming:
They are: • Machine dependent
OFFSET, SEC, segment override • Lengthy code
6. Type (or Attribute) Operators • Error prone (likely to generate errors).
They are:
Assembly Language Features
l-ilGH - returns high b t
returns high word of y e of ~ expression. HIGHWORD - The main features of ALP are program comments, reserved
an expression. words, identifiers, statements, and directives which provide the
LOW - returns low byte of an expression
basic rules and framework for the language.
LOWWORD - returns low word of an ex. .
P1R - used on d t . press1on. Program comments:
a a variables and . tr The use of comments throughout a program can improve its
- modifies the NEAR ttr"b mS uctions levels. SHORT
+127 and -128 bytes. a i ute of a JMP destination that is clarity. It starts with semicolon(;) and terminates with a new line.
E.g., ADD AX, BX ; Adds AX & BX
INSIGHTS ON MICROPR
ESSORS
115
114 \ PROGRAMMING WITH 8086 MICROPROCESSOR
 'fhese statements, called directives act only during the assembly of
rogratn and generate no machine-executable code. The different
Reserved words:
Certain names in assembly language are reserved for the· ~es of directives are:
own purposes, to be used only under special conditions. Reserve: The Page and Title Listing Directives:
1.
words include: The page and title directives help to control the format of a
Instructions: Such as MOV and ADD (operations to execute) listing of an assembled program. This is their only purpose,
• and they ~ave no effect on subsequent execution of the
Directives: Such as END, SEGMENT (information to the
• program.
assembler)
The page directive defines the maximum number of lines to
Operators: Such as FAR, SIZE (used in expressions)
• list on a page and the maximum number of characters on a
Predefined symbols: such as @DATA, MODEL (returns
@
• information to the program during assembly)
line. Its format is:
PAGE [Length] [,Width]
Identifiers: For example, PAGE 60, 132 means length of is 60 lines per
An identifier (or symbol) is a name that applies to an item in page and width is 132 characters per line. The default value
the program that expects to reference. The two types of identifiers is Page 50, 80.
are name and label. The TITLE directive gives title for a program to print on line
Name refers to the address of a data item such as NUMl DB 2 of each page of the program listing. Its format is:
5. Label refers to the address of an instructi·on, proce d ure, or
segment such as MAIN and Ll : in the following statements. TITLE text [comment]
MAIN PROC FAR 2. SEGMENT Directive
Ll: ADD BL, 73 The SEGMENT directive defines the start of a segment such
as stack, data, and code. Its format is:
Statements:
Segment-name Segment [align] [combine] ['class']
An assembly language program consists of a set of
statements. The two types of statements are:
• Instructions such as MOV and ADD
Segment-name ENDS
• Directives such as COUNT DB 1 Segment name must be present, must be unique, and must
The examples of statements are: follow assembly language naming conventions. An ENDS
Identifiers Operation statement indicates the end of the segment and contains the
Operand Comment
same name as the SEGMENT directive. The operand of a
Directive: COUNT DB 1 ; initialize count SEGMENT statement may contain three types of options:
Instruction: L30: MOV AX,O ; assign AX with 0 align, combine, and class.
Directives: The align option indicates the boundary on which the
The directives are the number of t t segment is to begin; PARA is used to align the segment on
control the way in which s a ements that enables us to

116
1 a source pr
INSIGHTS ON MICROP OCESSORS
ogrnm -mbles and lists
paragraph boundary. The combine option indicates whether
117
PROGRAMMING WITH 8086 MICROPROCESSOR
 used to notify the assembler that the instructions or features
to combine the segment with other segments when they ar introduced by the other processors are used in the program.
linked after assembly. STACK, COMMON, PUBLIC, etc e
E.g., .386 - program for 386 protected mode.
combine types. The class option is used . are
to group r e1·atect
segments when linking. The class code 1s for code se'""
o•«ent Dn Directive
7,
stack for stack segment, and data for data segment. ' The Dn directive is used to define data types. Its format is:

3. PROC Directive [narne] Dn expression

The code segment contains the executable code for a The Dn directive can be any one of the following:
program, which consists of one or more procedures, defin
initially with the PROC directive and ended with the
directive. Its format is:
EN~: DB Define byte
Define word
1 byte
2 bytes
DW
Define double 4 bytes
Procedure-name PROC [FAR/NEAR] DD
Define farword 6 bytes
DF
8 bytes
Procedure-name ENDP Define quadword
DQ
10 bytes
The procedure name must be present must be ..u..,.uque,
~; and Define 10 bytes
I
DT
must follow assembly language naming conventions Th
E.g., NUM DW 1234H
operand FAR is used for the first executing procedur~ an:
rest procedures call will be NEAR. The procedure should be 8. EQU Directive
within th
e segment. The ENDP defines the end of the The EQU directive can be used to assign a name to
proced ure. constants.
4. END Directive E.g., FACTOR EQU 12
An END directive ends the enti MOV BX, FACTOR ; equivalent to MOV BX,12
the last statement. The ENDS _re p_rogram and appears as
the ENDP directive d drrective ends a segment and 9. OUP Directive
en s a procedure. Its format is· The OUP directive can be used to initialize several locations
E .
ND [procedure-name] to zero. For example, SUM DW 4 DUP(O) reserves four
5. ASSUME Directive words starting at the offset sum in DS and initializes them to
An .EXE program uses the SS re . t zero. This directive is also used to reserve several locations
DS to address the data gIS er to address the stack, that need not be initialized. In this case, (?) is used with DUP
segment and CS
segment. The ASSUME dir '. to address the code directives. For example, PRICE DB 100 DUP(?) reserves 100
purpose of each segment . thective tells the assembler the bytes of uninitialized data space to an offset PRICE.
m eprogr
ASSUME SS-sta k am. 1ts format is:
. c -name, DSd : ataseg-na
6. PROCESSOR o· . me, CS: codeseg-name
1.rective
Most assemblers a
on a basi
· c 8086 level
ssume that the
compute Th source program is to run
r. e PRf'V"'r:,c,-,,-,. 119
118 INSIGHTS ON MICRO '-'---=x:,vR directive is PROGRAMMING WITH 8086 MICROPROCESSOR
PROCESSORS ---------

\
 ·ptioD for conventional program:
Program Written in Conventional Full Segment Direct·IVe oescrl
STACK contains one entry, DW (define word), that defines
page 60,132 • 3
2 words initialized to zero, an adequate size for small
title sum program to add two numbers programs,
------------------------------------------ DATASEG defines 3 words NUMl, NUM2 initialized with
• 3291 and 582 and sum uninitialized.
stack segment para stack 'stack'
coDESEG contains the executable instructions for the
dw32 dup(0) • program, PROC and ASSUME generate no executable code.
stack ends The ASSUME directive tells the assembler to perform these
;----- ---------- - -- - - • tasks.
data seg segment para 'data' Assign STACK to SS register so that the processor uses the
numl dw3291
• address in SS for addressing ST ACK.
Assign DAT ASEG to DS register so that the processor uses
num 2dw582
• the address in DS for addressing DAT ASEG.
sum dw?
Assign CODESEG to the CS register so that the processor
data seg ends • uses the address in CS for addressing CODESEG.
• When the loading a program for disk into memory for
code seg segment para 'code' execution, the program loader sets the correct segment
main proc far addresses in SS and CS.
assume ss: stack, ds:dataseg, cs:codeseg Program Written using Simplified Segment Directives
mov ax, @data .Model memory model
mov ds, ax
Memory model can be
mov ax,numl TINY, SMALL, MEDIUM, COMPACT, LARGE, HUGE or
addax,num2 FLAT
mov ax, 4c00h TINY for .com program
int 21h FLAT for program up to 4 GB
mainendp Assume is automatically generated
•
codeseg ends
.STACK {size in bytes]
end main
Creates stack segment
.DATA: start of data segment
121
120 INSIGHTS ON MICRO PROGRAMMING WITH 8086 MICROPROCESSOR
PROCESSORS
 .CODE: start of code segment \:;,, tlink filename ➔ makes .exe
4.
DS register can be initialized as \:;,, filename.exe ➔ run the code
• s. V td filename.exe ➔ debug the code [use F7 and F8]
MOV AX, @DATA
6.
MOVDS,AX 6 Assembling, Linking, and Executing
3
:;;.--
ALP Written in Simplified Segment Directives The symbolic instructions that we code in assembly
language are known as the source program. We use an assembler
page 60,132
program to tra~late the sou_rce program into machine code,
title sum program to add two numbers.
1.<nown as the object program. Fmally, we use a linker program to
.model small complete the machine addressing for the object program,
.stack64 generating an executable module.
.data
Assembling
numl dw 3241 The assembler converts source program into object program
num2 dw 572 if syntactically correct and generates an intermediate .obj file or
sumdw ? module. But assembler complains about the syntax error if any and
does not generate the object module. Assembler may create
.code optional output files .1st and .crf (or .sbr) at run time. An .obj file
main proc far is required for linking a program into executable form. A .1st file is
mov ax, @data ; set address of data segment in ds required for error diagnostics or if we want to examine the
mov ds, ax generated machine code. A .crf file is useful for a large program
where we want to see which instructions reference which data
movax, numl
' items.
addax, num2
The assembler calculates the offset address for every data
mov sum, ax item in the dat~ segment and for every instruction in the code
mov ax, 4c00h ; end processing segment. The assembler also creates a header immediately in front
int 21h of the generated .obj module; part of the header contains
mainendp information about incomplete addresses.
; end of procedure
end main For short programs, assembling can be done manually
; end of program
where the programmer translates each mnemonic into the machine
Turbo Assembler (TASM) Assembling p ~anguage using lookup table. The assembler reads each assembly
1. Save the cod . rocess '.115truction of a program as ASCII character and translates them
e text m ASM f
folder where masm and · link filormat and save it to the saine
into respective machine code.
2. Open dos mode d es are stored.
an reach within
3. \> tasm filen that folder.
----;; ; -.-____ ame.asm ~ makes.obj
122 INSIGHTS ON MIC_R_O_ _
PROCESSORS ------- PROGRAMMING WITH 8086 MICROPROCESSOR 123

1
There are two types of assemblers:
Ed ito r
editor Prog .a sm
1. One-pass assembler
Thi assembler scans the assembly language progra
s and converts to object codThi
once e. rn
s assembler has the
program of defining forward references only. The iuntp Prog .asm
instruction uses an address that appears later in the
program during scan, for that case the progranuner ,
defines such addresses after the program is assembled,
Assembling
2. Two pass assembler
A potential problem in first pass is a fonuard reference.
The two-pass assembler typically makes two or more Prog.l•t .Prog.obJ
prog.cr1' Optional
passes through a source program in order to resolve
forward references to addresses not yet encountered in
the program. During the first pass, the assembler reads
the entire source program and constructs a symbol table
of names and labels used in the program, that is, names ptlonal

of data fields and program labels and their relative

Prog .ex•
locations (offsets) within the segment. We can see such
a symbol table immediately following the assembled
program. During the second pass, the assembler uses
Load/ Exeout.•
the symbol table constructed in first pass. Knowing the
length and relative position of each data field and
instruc~on, it can complete the object code for each Figure 3.3 Steps in assembling, linking, and executing
instruction. It then produces .obj, .1st, and .crf files as
required. Linking
When our program is free of error messages, the next step
The two-pass assembler is more efficient and easier is to link the ob1·ect module that was produced by the assemblher
th an the one-pass assembler. . d Th linker performs t e
and that contains only machine co e. e
following functions:
• The linker completes any addresses left open by the
assembler.
ssembled module
• Combines more than one separat e1Y a
into one executable program. .
d . 'ti lizes it with special
• Generates an .exe module an uu a d' g for
1
instructions to facilitate its subsequent oa m
124 execution.
INSIGHTS ON MICCIR~O>FP;ROOOCE~S~S~O;RS;-------------- 125
PROGRAMMING WITH 8086 MICROPROCESSOR
 files from the link step are .exe, .lib, .map " mov ax, 4c00h
TI~oop t Ut ~~
which last two are optional files. g int 21h
rnainendp
Loading and Executing end begin
The last step is to load the program for execution. Becau
Differences between .EXE and .COM programs:
the loader knows where the pro~~m is going to l~ad in m emory,:
.EXE and .COM both are executable file. .EXE program
is now able to resolve any remauung addresses still left incomplete
. ts of separate code, data, and stack segments while .COM
in the header. The loader drops the header and creates a program constsam consists of one segment that contams . code, data, and
segment prefix (PSP) immediately before the program is loaded in progr
memory. stack.
.EXE program
3.7 .COM Programs and .EXE Programs Program size: It uses individual segment of 64 KB maximum
for eac~ logical segment. Size of program is larger than
Writing .COM Programs
.COM program.
• It fits for memory resident programs.
s egmentation: A data segment is defined and DS is
• Code size limited to 64K. initialized with the address of the segment. Stack segment
• .com combines PSP, CS, DS in the same segment must be defined for .EXE programs in higher memory (> 64
• SP is kept at the end of the segment (FFFF), if 64k is not KB).
enough, DOS Places stack at the end of the memory. Initialization: The segment registers must be initialized
• The advantage of .com program is that they are smaller than properly by the programmer .
.exe program.
Template of a .EXE program:
• A pro~am written as .cpm requires ORG 100H immediately
. data
followmg the code segment's SEGMENT statement. The
statem~nt sets the offset address to the beginning of
execution following the PSP. . stack
.model tiny
.code . code
org 100h i start at end of psp mov ax, @ data
begin: jrnp main ;jump past data mov ds, ax
vall dw 5491
val2 dw 372
surn dw ?
main: proc near
end
mov ax, van
add ax, val2 .COM program
b Oth instruction and
movsum, ax Program size· It uses one segment f or ·
data, restrict;d to maximum of 64 KB, in cluding program
126 INSIGHTS ON MICROPRICO>CCI!ES~SOO;RSS_ _ _ _ _ _:..__ _ __ PROGRAMMING WITH 8086 MICROPROCESSOR 127
 f (PSP) Size of program is smaller th . f at of macro definition:
segment pre ix . al\
comparable .EXE program. Basic onn MACRO [Parameter list] ; Define macro
]l.1acroname
. . It combines the PSP, stack, d a ta, anct cod
Segmentation. bl e
segment mto one code segment. Assemh er automatica}\y
.
[Instructions1 ; Macro body
generates a stac k for ·COM programs at t e end of segments
(< 64 KB).
Initialization: When program loader loads .COM: for ENDM ; End of macro
execution, then CS, DS, SS, and ES are automatically
initialized with the address of PSP. MACRO
E.g. Addition
Template of a .COM program: INAX,PORT
ADDAX, BX
. code
OUTPORT,AX
org 100h ENDM

·ng argument to MACRO:

Passi . t as
To make a macro more fl ext.ble, we can define parame ers
Macro assembler: • d mmy argument
• A macro is an instruction sequence that appears repeatedly :DDITION MACRO V ALU, VAL2
in a program assigned with a specific name. MOV AX,VAL1
ADDAX, VAL2
•. The macro assembler replaces a macro name with the MOVSUM,AX
appropriate instruction sequence each time it encounters a ENDM
macro name.
.MODEL SMALL
• When same instruction sequence is to be executed .STACK64
repeatedly, macro assemblers allow the macro name to be .DATA
typed instead of all instructions provided the macro is VAL1 OW 3241
defined. 571
VAL2 OW
• Macro are useful for the following purposes: SUM DW ?
.CODE
To simplify and reduce the amount of repetitive coding.
MAIN PROC FAR
To reduce errors caused by repetitive cod ing. MOV AX,@DATA
To make an assembl J bl MOVDS,AX
Y anguage program m ore reada e.
Madero executes faster because there is no need to call ADDITION V AL1, VAL 2
an return. MOV AX, 4COOH
INT21H
MAINENDP
128 END MAIN
INSIGHTS ON MICROP 129
CESSORS H 8086 MICROPROCESSOR
PROGRAMMING WIT
 ARR DB 15, 17, 18, 21
E.g.,
Addressing Modes in 8086 MOV AL, ARR [21 ; MOV AL, 18
Addressing modes describe types of operands
. . and the w ay ~. ADD BH, ARR+3 ; ADDBH,21
which they are accessed for executing an mstruct10n. An operand
address provides source of data for an instruction to process an Indited Memory Addressing:
instruction to process. An instruction may have from zero to two s. Indirect addressing takes advantage of computer's capability
operands. For two operands, first is destination and second is for segment: offset addressing. The registers used for this
source operand. The basic modes of addressing are register, purpose are base register (BX and BP) and index register (DI
immediate and memory which are described below.
and SI)
1. Register Addressing: MOV[BX],AL
E.g.,
For this mode, a register may contain source operand,
ADDCX, [SI]
destination operand or both.
Base Displacement Addressing:
E.g., MOV AH, BL 6.
This addressing mode also uses base registers (BX and BP)
MOVDX,CX and index register (SI and DI), but combined with a
2. Immediate Addressing displacement (a number or offset value) to form an effective
In this type of addressing, immediate data is a part of address.
instruction, and appears in the form of successive byte or E.g. MOV BX, OFFSET ARR
bytes. This mode contains a constant value or an expression.
:LEABX,ARR
E.g., MOV AH, 35H
MOV AL, (BX +2]
MOV BX, 7A25H
ADD TBL (BX}, CL
3. Direct M emory Addressing:
TBL [BX] ➔ [BX+ TBL] e.g. [BX+ 4]
In this ~pe_of addressing mode, a 16-bit memory address
(offset) is duectly specified in the instruconasap
ti art 01.
f ·t 7. Base Index Addressing:
?11e of t~e operand is the direct memory and other operand This addressing mode combines a base register~ (BX or BP)
1s the register. with an index register (SI or DI) to form an effecttve address.

E.g., ADD AX, (5000H] E.g., MOV AX, (BX +SI]

Note: Here data resi'des m· a memory 1 ti · h d ta ADD [BX+Dl}, CL
segment wh ff . oca on m t e a
, ose e ective addre 8. Base Index with Displacement Addressing
5000H as the Off t ddr ss may be computed using
se a ess and t This addressing mode, a variation on base- index combines a
address. The effective d con ent of DS as segment
. a dress, here, is l0H*DS + SOOOH. base register, an index register, and a displacement to form
4. Due~t Offset Addressing
an effective address .
In . this
hm
addressing, a variation
. . of d .
ant etic operators t . u ect addressing uses E.g., MOV AL, [BX+SI+2}

130 INSIGHTS ON MICR

o modify an address.

ROCESSORS -----~~=~~--=-:::==::=.:;;~--r'ii
ADD TBL [BX +SI], CH
PROGRAMMING WITH 8086 MICROPROCESSOR
131
 nctions and Interrupts
9. String Addressing: poS fbu ard and Video Processing)
O
This mode uses index registers, where SI is used to p Olllt
. t (t<eY The .
Intel CPU recogruzes two types of interrupts namely
0
the first byte or word of the source string and DI is use dware interrupt when a peripheral devices needs attention
point to the first byte or word of the destination string,w1 to ha! the CPU and software interrupt that is call to a subroutine
string instruction is executed. The SI or DI is automaij en fro~ed in the operating system. The common software interrupts
·
mcremente d or d ecremente d to point. to t h e next bytecaUy
iocad here are INT lOH for video services and INT 21H for DOS
word depending on the direction flag (DF) . or use
services.
E.g., MOVS, MOVSB, MOVSW
Examples: tNT 21H:
It is called the DOS furlction call for keyboard operations
title program to add ten numbers
follow the function number. The service furlctions are listed below:
.model small
, # OOH- It terminates the current program.
.stack 64
.data Generally not used, function 4CH is used instead.
arr db 73, 91, 12, 15, 79, 94, 55, 89 # OlH- Read a character with echo
sum dw ?
•
Wait for a character if buffer is empty
.code
Character read is returned in AL in ASCII value
main proc far
# 02H- Display single character
mov ax, @data •
mov ds, ax Sends the characters in DL to display
movcx, 10 MOVAH,02H
mov ax,O
MOV DL, 'A' ; move 01, 65
lea bx, arr
12: add al, [bx] INT21H
jncll • # 03H and 04H - Auxiliary input/ output
inc ah INT 14H is preferred.
11: inc bx
loop 12
• # 05H - Printer service
Sends the character in DL to printer
mov sum,ax
mov ax, 4c00h • # 06H- Direct keyboard and display
int 21h Displays the character in DL.
mainendp
end main
• # 07H- waits for a character from standard input

does not echo

132 INSIGHTS ON
MICROPROCESSORS - - -- - ---------=--====~;,;;,;;-11iii33
PROGRAMMING WITH 8086 MICROPROCESSOR
 # 08H- keyboard input without echo rNNT21H
• DB "Hello world" '$'
Same as function 0lH but not echoed. cUSLMSG '
# 09H- string display
Displays string in the dat_a area, immediately followed by a
• dollar sign ($ or 24H), which uses to end the display.
Displays string until ' $' is reached.
# OAH
DX should have the address of the string to ~e displayed. • M:OVAH,OAH
; request keyboard input
• # 0AH - Read string
LEA DX, PARA_ UST ; load address of parameter list
• # OBH- Check keyboard status
1NT21H
Returns FF in AL if input character is available in keybo
~~- ~ Parameter list for keyboard input area :
p ARA_LIST LABEL BYfE; start of parameter list
Returns 00 if not.
MAX_LEN DB 20; max. no. of input character
• # OCH- Clear keyboard buffer and invoke input functions
such as 01, 06, 07, 08 or 0A. ACT_ LEN DB ? ; actual no of input characters
AL will contain the input function. KB-DATA DB 20 OUP ('); characters entered from keyboard

INT 21H Detailed for Useful Functions LABEL directive tells the assembler to align on a byte
boundary and gives location the name PARA _LIST.
• #0lH
p ARA UST & MAX_LEN refer same memory location,
MOV, AH 0l H; request keyboard input INT 21H MAX_LEN defines the maximum no of defined characters.
Returns character in AL· IF AL_ - nonzero value operation ACT_LEN provides a space for the operation to insert the
echoes on the screen· If Al- ' pressed
- zero means that user has
actual no of characters entered.
an extended function key such as Fl OR h ome.
KB_DATA reserves spaces (here 20) for the characters.
• #02H

MOV AH, 02H; request display character Example:

title to display a string
MOV DL, CHAR; character to display
.model small
lNT21H
.stack 64
Display character in D2 at
carriage return and r f current cursor position. The tab, .data
me eed char t str db 'programming is fun', '$'
operation automati ll ac ers act normally and the
# 09H ca y advances the cursor .
• .code
main p roc far
MOV Ah, 09H; request display
mov ax, @data
LEA DX, ClJST Msc·
- , local address of prompt mov ds, ax
134 INSIGHTS ON MICR
OPROCESSORS - - - - - - PROGRAMMING
- -----.:::=-::-;;;;.;;;;:i~11113535
WITH 8086 MICROPROCESS0R
 # _light pen function
movah, 09h ;display string 048
# osff- select active page
lea dx, str
MOVAH,05H
int 21h
MOV AL,page-no. ; page number
mov ax, 4c00h
int 21h INTl0H
main endp # 06ff· scroll up screen
MOV AX, 060FH ; request scroll up one line (text)
end main
MOV BH, 61H ; brown background, blue foreground
INTlOH MOV CX, 000OH ; from 00:00 through
It is called video display control. It controls th MOV DX, 184F H ; to 24:79 (full screen)
£ t l . . escreen
orma , co or, text style, making windows, scrolling etc. The co
functions are: ntrol INTl0H
AL= number of rows (00 for full screen)
# OOH - set video mode
MOV AH, 00H ; set mode BH= Attribute or pixel value
MOV AL,03H ; standard color text CX= starting row: column
INf lOH ; call interrupt service DX=-ending row: column
# 01H- set cursor size # 07H-Scroll down screen
MOV AH,0lH Same as 06H except for down scroll
MOV CH, 00H ; Start scan line # 08H - Read character and attribute at cursor
MOV CL, 14H ; End scan line MOVAH,08H
INT lOH ; (Default size 13:14) · ; page number 0(normal)
MOVBH, OOH
# 02H -Set cursor position:
INT10H
MOV AH, 02H
MOV BH, 00H AL= character
; page no
MOV DH,12H BH= Attribute
; row/ y (12)
MOV DL, 30H # 09H -display character and attribute at cursor
; column/ x (30)
INT lOH MOVAH,09H
# 03H- return cursor status ; ASCII for happy face display
MOV AL,OlH
MOV AH,03H MOVBH,00H ; page number
MOVBH,OOH- ; Blue background, brown foreground
MOVBL, 16H
lNT lOH , ; No of repeated character
MOVCX,60
D Returns: CH- startin
H- row, DL-column g scan line, CL-end scan line, INTlOH

37
_ _ _ _ _ _ _ _P_R_OG_RA_M_M_IN_G_WIT_H_80_88-:-:M::IC=R::OP;;:;:R;-;;;OC:;;E;,;S;;SOR~l\l11°i1
136 INSIGHTS ON M -
ICROPROCESSORS - - - ----
 ~ODIi· Read pixel dot
# oAH-display character at cursor
Reads a dot to determine its color value w hich returns in
MOV AH, OAH
AL-
MOV Al, Char MOV AH,ODH
MOV BH, page _no MOV BH, 0 ; page no
MOV BL, value MOV CX, 80 ; column
MOV eX, repetition MOV DX, 110 ; row
INTlOH 1NT10H
# Olm- Set color palette #OEII- Display in teletype mode
✓ Sets the color palette in graphics mode Use the monitor as a terminal for simple display
✓ Value in BH (00 or 01) determines purpose of BL MOV AH,OEH
✓ BH= OOH - select background color, BL contains 00 to MOV AL,char
OFH (16 colors) MOV BL, color; foreground color
✓ BH = OlH - select palette, BL contains palette
INTlOH
MOV AH, OBH #OFH - Get current video mode
MOV AH, OBH MOVAH,OFH
MOV BH, OOH; background
INT10H
MOV BH, 01H; select palette Returns values from the BIOS video.
MOV BL, 04H; red AL= current video mode
MOV BL, OOH; black AH= no of screen columns
INT21H
BH = active video page
INT21H
Examples:
#OCH- Write pixel dot Write a program in 8086 to convert uppercase letters into
1.
Display a selected color
lowercase.
AL=color of the pixel, ex--coumn
1
.model small
BH=page number, DX= row ,
.stack 99h
MOVAH, OCH
.code
MOV AL, 03
mainproc
MOV BH,O mov ax, @ data
MOVCX,200 mov ds, ax
MOV DX,50 mov si, offset str
lNT lOH m: mov dl, [sil
· I at column 200
It sets pl)(e mov cl, dl
,row SO
cmp dl,' $'
138 INSIGHTS ON
_ _ _ _ _ _ _P_R_OG
_ RA_M_M_IN_G_WIT_H_80_86 1 l9
_ M-:::IC=RO::P:::R::OC;:;;E:;SSO;;:;;R;-7\11t
NIICftOPROCESSORS
 je 11
jen inC Si
cmp di, 60h
inc bl
jl 1 jmp 12
k: mov dl, cl mov cl, bl
mov ah, 02h 11:
mov ch, 00h
int 21h dee si
inc si mov al, [si]
jmpm 13:
mov [di], al
I. mov dl, cl
dee si
add dl, 20h
inc di
mov ah,02h
loop 13
int 21h
mov ah,09h
inc si mov dx, offset str2
jmpm
int 21h
n: mov ax, 4c00h
mov ax, 4c00h
int 21h
int 21h
mainendp
.data
mainendp
str db "I am Mr Rahul", '$' end main
3. Write a program to input characters until 'q' and display
end main
the entered string. ·
2. Write a program·m 8086 to reverse the string
model small · .model small
.stack 100h .stack 100h
.data .data
str db 50 dup ('$')
strl db "My name is Rahul" '$'
str2 db 50 dup ('$') ' .code
.code main proc far
main proc far mov ax, @ data
mov bl,00h mov ds, ax
mov ax, @ data mov si, offset str
mov ds,ax 12: mov ah, 0lh
mov si, offser strl int 21h
mov di, offset str2 cmp al, 'q'
12: mov di, [si] je 11
cmp di,'$' mov [si], al
inc si 11
140 INSIGHTS ON M
ICROPROCESSORS PROGRAMMING WITH - MICRCJPROCEss<>R '
 . f)i , p/aY if numbers are with 1 digit
,mr 12 ,Jott• mo v ex, 05h
men' ,1h, 09h 1
m ov s1, OOh
rnnv dx, offset str
rnov dt arr [s i]
int 21h ):
add di, 30h
mov ax, 4cOOh
rno v ah, 02h
int 21h
int 21h
main endp rnov dl,''
end mam rnov ah, 02h
Wri te a p rogram to sort the numbers in d escend 1ng
· 0
4. dosseg rd ~,. int 21h
inc si
.model sm.aJJ
loop 1
.stack 100h
mov ax, 4c00h
.code
int 21h
main proc far
mov ax, @ data rnainendp
mov ds, ax Write a program to add f irst 100 n tu 1
5. display the result in the screen. a ra even numbers and
mov dx, 4h
dopass: mov ex, 4h
.model small
mov si, OOh .stack 100h
check: mov al, arr [si] .data
cmp arp [si+l], al ten dw 10
jc noswap .code
mov bl, arr [si + 1) main proc far
mov arr[si +1], aJ mov ax, @ data
mov arr fsi], bl mov ds, ax
noswap: inc si mov ex, 63h
loop check mov ax, 02h
dee dx mov dx, 04h
jnz dopass 11: add ax, dx
mov ax, 4c00h add dx, 02h
int21h loop 11
main endp 12: mov dx, 0000h
.data div ten ; dx: ax / 10
arr db 8,2,9,4,7 inc ex
end main add dx, 30h ; remainder
pushdx
114:42~1,;,N~SKfGiHHTrT:S~ODIN;-Mf<MIC:RROOPPiRtcO;:C;.ES~S~O-; ;-RS- - - - - - - - - - -
PROGRAMMING WITH 8081
 aJll in 8086 to add 10 11ixteen bit numbert1 in
gr
cmP ax, OOh ; quotient wrtte ~ pro
t1tO.-Y table
7,
je13 111e d••I .; n1.1 ll
,t1lll ~
;mp12 .st,,d..: ~
,z
papdX nun, dw dup (2)
}3:
movah,02h , th.,. dup (J)
0011
int 21h -.u 1nh d w 0
1oop13 s t11nl d w ll
rnov ax, 4cOCJh
.cod
int 21h
maiJtendp
end main
Write a program in 8(186 to generate the multiplication
6.
table.
.model small ""
ll :
.stack 32
.data
numl db5
num2db 1 12:
loop 11
tab db 10 dur (?)
.code tnl
main proc far main ndp
mov ax, @ data dm in
movds,a
movb ,0
movcx, 10
11: mov al, numl
mulnum2
mov tab [b ), I
Inc b
incnum2
loop 11
mo 4c00h
int 21h
mainendp
end main
 ~,., I111II 111 I ""' 11 11 t I", 1lq I !I rvlc
11111• q " wl . I 11
•· 1otl Viii t
Pt,,
lh ,I I'''" 1N1
\ I '" q11 [11tllllllrt )It '
l I Ill' I II i,1,. d s
1Jell ~1r1U olur lo of I g~l'I p ol ut ""
, I,· ii\ do•f111• ,I It tV
,,,11.. '", I ·Ill r,1q ,f, nde , ,.,,.1t1'll' ,1, C1111111 1, 11 1,, I ,r,utle
column
f, d11, 1
th• 1111111111 I I
• ' "' l , ,llrd 1111111
' nil\' 11 u1nbt•1 111 11lt1 tec; 111 11
Ill l•d 11
1f•
II • , i,tJ,,
''" ~,>".40 nl11r p, '',(,( Ji</lf ,, )

()0
qne11I C()]or 8 ' l(,fl,u\()(I If,
, • I ·ltrr 1•1Pg1,1111 (>fg<\lli7fltiwl 2•,1<40
I 11, 1 ,,r,1f; it OI < ,,lorq
• ,.,j,w of
f ulit,11( S l Ir I,cii-;,., ,,
ii pmgrnm bctflll SE' d l'l t:'t IR
, l, he 720•400 I f,
IJ ( olor 4
• · 1~1,·d
m11rt I It ,11 II' •~ 0 '
n (ln"oin" rnninl nancr of prog,nrr 1q bn
-oz 25><80
color
l t:: rs ,n 11, ,. ,rau~e 4 720,,.400 I(,
'I
t1 t1 , • • • .
• pr(l(r<Ju rr~• ,.•rr readily ident1f1ed for mod1f1cnl1on -------
03(bY
25><80 color
color!\
A CALL il procedure within the same code segmen t is default) 720><400 16
10 25><80 Mono 0
Nf:A R CALL< A f,AR CAIL ca lls a procedure lab I d Pl\ R,. 07 hromc colors
ros•rJ:,ly in anothrr rodr ~ gmrnt
D!SPLA Y PROC NEAR Pages Resolution Noof
-Graphic Color
MOY AH,091-1 color•
mode
MOY DX, OFFSET STR 8 320><200 4
04 Color
INT 21H 8 320><200 4
05 Color
RET 8 640><200 2
06 Color
DISPlA Y ENDP 8 320><200 16
OD Color
✓ To display number contained in [BX] 4 640><200 16
OE Color
D!SPLA Y PROC NEAR 2 640>e350 1
OF Mono
MOYDI, [BX] chrome
2 640,c350 16
ADDDl,30 10 Color
1 640,c480 2
MOYAH,02H 11 Color
1 640•480 16
INT21H 12 Color
13 Color 1 320•280 256
RET L

DISPLAY ENDP
Attribute
Background ~
Attribute: BL R G B 1 RGI
Bit number: 7 6 54
I - Intensity, BL - Blink

,. I'"'"'"' ON .;IC(IR~O;P;;RO~C:;ESS~O::RS:::---- - - - - - - - - PROGIWIMING WITH 1811

 ( ,,1,,r
... V I I 1,
II
'"" I di, I •cl
,11,111 1,1, '.l•ll1 ,l,n, ~,•11,11,,d" I1 h t
' ,..,
HIA• j,, 111'1\/ 1,1,, 11111, ,','''''""
, I' '11,'
!ilUP ,' I 11111v, ,11111 1 1
·'" ,f ,, I" 114 • I , JI t ' It I
l,rffflJI
lJIIII
,, 1111 1111,
Jkcl ,, 1111 I

Mit!l'"'' ,, 1111 I 111

ffrt1Wll 'I I• 11 I' 1:1.
Whitt' 11 ,1, ooh
,,II
1111,v , ,

1111 111,
A
111 Ill 1 ""' '
II d ,t.,
111 w ,II, Ill
, ol di, 1ft
v11I dh "v td• motl,I",'$'
II
"I Ill Ill

t:iuunpl : Sn n
I, Writ a pmgt1111 to dl1pl y strlnM I ( IU,40) with 11
b1rk11rotmd nd red for 11round K •1•11
do 1•~ oil
,111od1•I m II
. I, I k l(Klh
,rod,•
111 In pn1t l,11
mov ,, , (U) ti ,t 1

IIIOV d / '
nmv I, off ,•t v I I
12: mov h, ()'Jh ; f' I 1 11r II J'O Ilion
mov dh, row
mov di, 1 ol
inl JOh
11111V ,I, I ii
cmp ,I, '$'
I•· II
rnov h, 119h
mov dh, row
INlfGHfSON
M1c110,11oc 011
 movcl,ndws
~line
Wnt an a• rnbl l.anr• program to rHd • tring f
er con\f'J1 it 10 upp« cue, count the nu .... b to again•
th r \I , .--1 i ---L. 1· ·•• er mov dL[si)
;-ord and di pl.a uch wun, n cau1 •n~. (2061 Aslr, Of
U.'111}
911bdl,20h
I IJ
;,re down
nrwline
cl.a
ol words as','$' a,cbl
.town: intZlh
ineal
7
b255 dup (7)
.....
loop .....

macro
•
ah,02h
movdl,Oah
int 21h
movdl,Odh
tn 2th
pop )I

newlmemdm
mamprocw
IJIOY~

mcwda,e

•
 main pfOC far rnov ax,@data
mov ax,@data rnov ds,ax
movds,ax next:
next: rnov si,offset array
mov si,offset array rnov bl,0
mov bl,0 rnov cx,4
mov cx,4 again:
again: rnov al, [si]
mov al,[si] inc si
inc si cmp al,[si]
cmp al,[si] jadown
jc down mov dl,[si]
mov dl,[si] mov [si],al
mov [si],al dee si
dee si mov [si],dl
mov [si],dl inc si
inc si mov bl,01
movbl,01 down:
down: loop again
loop again dee bl
dee bl jz next
jz next mov si,offset array
mov ax,4c00h movcl,05
int 21h nxtbyte:mov'al,[si]
mainendp aam
end main or ax,3030h
Title arraninn · d
o---•8 in ecending order movbx,ax
.model small mov ah,02
.stack
mov dl,bh
.data
int 21h
array db 4,37,13,50,2,,$' mov dl,bl
.code
int 21h
main proc far
mov dl,0
152 INSIGHTS ON MICROPR _____ ___P
_R_OG_RAM_II_ING_WIT
_ H_IOll
~ ll:::l=CR=:OP:=ROC~ESSO;;;;;:R;--1~
: 1i53,
ESSORS
 mt 21h !llOV ah, 02h
inc si int 21h
loop nxtbyte !llOV di, Oah ; control character for for next line
mov ax,4c00h !llOV ah, 02h
int 21h int 21h
mamendp
endlil
end main . e macro ; macro defined print space gap
Write a progra m to read a string and separate the \\>or.,s
., spaC h
3. !llOV di, 09
trt
from the s n ·. g Display each word at the center of ea ch mov ah, 02h
. f
line o a c e 1 ar screen with blue background and cya n
foregroun d • [2062 Bhadra] nt21h

⇒ endm
model small input macro prlst ; macro defined to input
.stack 100h ;keyboard input
.data mov dx, offset prlst
count db OOh movah, Oah
promptl db ' enter your string: ' , '$' int 21h
pkey db' press any key ......... ' , '$' endm
temp db 50 dup ( "$" ) setwindow macro
paralist label byte ; table of the byte for keyboard input movah, 06h
maxchar db 79 ; maximum limit to enter characters mov al, OOh ; for entire screen
actlen db ? ; gives how many Character are entered by user mov bh, 13h ; blue background and cyan foreground
kb_buff db 80 dup ('$') ; this is actually the place to hold entered movcx, OOh
;charactered mov dh, 24
.code mov dl, 79
mainproc int 10h
print macro msg ;defining macro to displaystring endm
mov dx, offset msg setmode macro
mov ah,09h movah,OOh
int 21h
moval, 03h
endm
int 10h ;mod echange and screen cleared
nextline macro ; defining macro toadvance to nextline
d·15
mov di, Odh ; control character for from feed playcenter macro msg
movdh, 12
154
INSIGHTS ON MICROPROCES50tls
------ ----===:-:::::=;;uii,;ioiPRO(;ESS<O>RRllj1!15555
PROGRAMMING WITH BON MICROPROCESS
 ; initial row : column
movdl, 40 int 21h
mov bl, 15 rnov ax, 4cOOh ; exit to operating system
mov si, offset msg
2h . function code for set cursor int 21h
nxtdsply:mov ah, 0 '. set cursor in the beginning Jllairl endp
int 10h '
mov ex, 1 , ex contains the no of characters to
. nd !llain

movah, 0ah
;display at a time
; display character at cursor
4, ;y
e W ·te an assembly language program for 8086 to sort an
of ten numbers stored. in memory. Display the
numbers in the screen after sorting. [2062 Bhadra]
mov al, (si) .model small
~
movbh,.OOh ; page 0
.stack
int 10h .data
incsi ; for next pass array db 79,4,37,13,56,63,50,44,23,2,'$'
inc di
.code
dee bl main proc far
movbh, [si] mov ax,@data
cmp bh,' '
mov ds,ax
jnz nxtdsply
next:
incdh
mov si,offset array
mov di, 39 ; change row and column to nextline middle movbl,O
dee bl
movcx,9
jnz nxtdsply
again:
endm
mov al,[si).
mov ax,@data
inc si
movds, ax
cmp al,[si)
moves, ax
jcdown
print promptl
mov dl,[si)
input paralist
mov [si],al
set mode
decsi
set window
mov [si],dl
displaycenter kb_buff
nextline inc si
movbl,O1
printpkey
mov ah, 1 dOWn:
; wait for any key ........ hold screen.·····
156 INSIGHTS ON MICROPROCESSofts .
 dee bl count db 0
jz next code
mov si,offset array rnain proc far
movcl,Oah mov ax,@data
nxtbyte:mov al,[si] rnov ds,ax
aam rnov ah,0ah
or ax,3030h rnov dx,offset instr
mov bx,ax
int 21h
mov ah,02 mov bx,offset actstr
mov dl,bh
movcx,0
int 21h
mov cl,nchar
mov dl,bl
next:
int 21h
push ex
mov dl,O
mov si,offset vowels
int 21h
movcl,0ah
inc si
mov al,[bx]
loop nxtbyte
up:
mov ax,4c00h
cmp al,[si]
int 21h
jnedown
mainendp
inc count
end main
down:
5. Write an assembly language program for 8086 to read a
string count the number of vowels in the string and inc si
display the string and its vowels count in a clear screen. loop up
[2063 Kartik] inc bx
⇒ .model small pop ex
.stack loop next
.data mov [bx],'$'
'i' ,
vowels db 'a','e', 'o' ,
'u' ,
'A','E','I','0'
,'U' mov ah,OOh
str db 20 dub(?) mov al,03
instr db SO intlOh
nchar db? mov ah,09
actstr db SO dup (?) mov dx,offset actstr
int 21h
INSIGHTS ON MICROPROCE5soRs
159
 mov al,count ; for every no, ten times
rnov cx,10
aam
or ax,3030h
Jabell:
movbx,ax
1 arrnum [bx]
rnov a,
mov ah,02 ; ax=al*dl
rnul dl
movdl,bh
int 21h
;for display
mov dl,bl
push bx
int 21h
push ex
mov ax,4c00h push dx
int 21h movbx,O
main endp mov cx,10
end main no_of_digits:
6. Write a program to generate multiplication table of five movdx,O
numbers stored in memory as array, store the result and div ex ;{ dx: ax/ ex= ax dx/ ex)
display 'in following format.
5 10 15 20 25 30 35 40 45 50 adddx,30h
3 6 91215 18 2124 27 30 ... ........ . pushdx
[2064 Shrawan]
⇒ .model small inc bx
.stack cmp ax,O
.data ja no_of_digits
arrnum db 5, 4, 3, 6, 7 mov ah,02
,code
mov ex, bx
main proc far
mov ax, @data
mov ds,ax popping:
popdx
mov ax,O Int 21h
movcx,5 loop popping
movbx,O . hich were
; index popdx ; popping respective register w
pop ex
total_no_of_tab]e:
pop bx
mov di, 1
push ex ; runs for 1 to 10 for each no. ; display ends here
; storing for nested loop
160 inc dl
INSIGHTS ON MICROPRQ
CESSORS
- - - - - - -------::-:-:-:::::~;;.;~MIDICCIRUO>PPRIROCDCEEPSSOR
PROGRAMMING WITH 80B6
I"'
 loop Jabell mov a,h,09h
inc bx mov dx,offset msg
popcx int 21h
mov ah, 02h printendm
movdl,Oah
int 21h printmsg1
mov di, Odh movah,Oah
int 21h mov dx,offset maxchar
loop total_no_of_table int 21h
mov ax, 4c00h
int 21h movbx,O
mainendp mov cx,O
end main mov cl,nchars
7. Write down an assembly language program to read a string mov si,offset actstr
and count the no of vowels in the smng. Display the no. of mov di,offset newstr
vowels in the string and the string without the vowels in it
in a clear screen with reverse atmbute. [2064 Poush} again:
⇒ .model small mov ah,[si]
.stack cmp ah,'a'
.data jldown
maxchar db 30 cmpah,'z'
nchars db? jg down
actstr db 30 DUP (0) subah,20h
msgl db 'Enter any text: $' down:
msg2 db 10,13, 'No. of Vowels=$' cmpah,'A'
jevowel
msg3 db 10,13,'Here is string without vowels:$'
countdbO cmpah,'E'
newstr db 30 dup ('$') jevowel
.code cmp ah, 'I'
main proc far jevowel
mov ax,@data cmp ah,'0'
mov ds,ax jevowel
cmpah,'U'
print macro msg
jevowel
162
INSIGHTS ON MICROPRocessoRS

----
 ASSUME ds: data ,cs: code
mov ah,[si]
mov ax , SEG data
mov [di],ah
mov ds, ax
inc di
jmpNEXT
vowel:inc bl rint macro msg
NEXT:inc si P movah,09h
loop again mov dx , offset msg
mov count,bl int 2th
mov bh,70h ; reverse attribute printendm
movax,O ; code for clear screen print msgl ; output string using macro
mov dx,184Fh
movah,09h
int 10h
mov dx , offset text
printmsg2
movah,02h int 21
mov dl,count mov bx , 0000h ; to count no. of vowels
or dl,30h mov ex, LENGTH text
int 21h mov si, offset text
printmsg3
print newstr
again : mov ah,[si]
mov ax , 4c00h
cmp an, 'a'
int 21h
jl down
mainendp
cmp ah, 'z'
end main
8. jg down
Write an assembly language program to get a string input;
sub an, 20h
count no. of vowels and display message 'even vowels' on
the screen if the count is even otherwise display 'odd
vowels'. [2065 Chaitra] down: cmp ah , 'A'
⇒ # include io.h
jevowel
data SEGMENT
cmp ah, 'E'
text db 30, ? , 30 DUP($) jevowel
rnsgl db 10 , 13 , 'enter the text:$' cmp ah, 'I'
msgo db 10,13, 'odd vowels: $' jevowel
data ENDS msge db 10,13, , even vowels: $' cmp ah, 'CY
code SEGMENTs jevowel
164 cmpah , 'U'
INSIGHTS ON MICROPRO
CESSORS 165
PROGRAMMING WITH - MICROPROCESSOR
 jevowel and al,Ofh
jmpNEXT rnov dh,al
inc bx jnt2lh
vowel:
loop again and al,Ofh
NEXT:
rnov dl,al
mov ax, bx rnov al,dh

div 2 rnovbl,Oah

cmpah, 'O' mul bl

je even add al,dl
mov dx,O
print~go
mov cx,O
jmp last
movcl,Oah
even : print msge
last: mov ax, 4c00h movbl,l

int 21h movbh,al

code ENDS again:
mov al,bh
9. Write an assembly language program for 8086 to find the mulbl
sum of the following series, x+2x+3x+4x+ .......... To ten add dl,al
terms Where x is a two digit number entered by the user. inc bl
Display the result. [2066 Shrawan] loop again
⇒ .model small
mov al,dl
.stack
aarn
.data
orax,3030h
strl db 'Enter two digit number:$'
mov bx,ax
.code
mov ah,02h
main proc far
mov ax,@data mov dl,bh
mov ds,ax int21h
mov ah,09h mov dl,bl
mov dx,offset strl int 21h
int 21h mov ax,4cOOh
mov ah,0lh int 21h
int 21h main endp

166
INSIGHTS ON MICROPR
OCESSORs
----
end main

RAMMINGWITH-~
1f7

1
 Write a program in 8086 to read a single digit number and
10. Write an assembly language program to calculate 8
urn of 11. display the multiplication table of that number as 2 4 6 8
the series l2+22+32+42+ .......upto ten terms and displ ay the
1618 20 if the user enters digit 2. [2067 Shrawa!~
result. [2066 Shrawan] 1214
.model small
⇒ # include io.h ::>
data SEGMENT .stack
sum db 4 DUB('$') .data
mldb 10 , 13, ' the sum of square : $' .code
main proc far
data ENDS
mov ax, @data
code SEGMENT
ASSUME ds : data , cs : code mov dx, ax
mov ax , SEG data
mov ah, 07h ; console input without echo
movds, ax
mov dx, 0000 stores sum int 21h
mov ex, 0010 ; counter mov ex, 10
mov al, 01 mov dl, 1
again: movbh, al sub al, 30h ; to decimal value
mulbh ax+-al * an labell:
add ax,dx mov ah, 0
mov dx, ax push ax
inc al muldl ; ax=al*dl
loop again
itoasum, dx ; for display
push ex
movah, 09h push dx
mov dx , offset ml ; display msg ml movbx, O
int 21h movcx, 10

mov ax, 09h ; display sum no_of_digits:

mov dx , offset sum movdx, o
int 21h div ex ; (dx;ax/cx=ax dx/cx)
mov ax , 4c00h add dx, 30h
int21h push dx
codeENDs

168 INSIGHTS
ON MICROPROCESSORS 169
PROGRAMMING WITH 8088 MICROPROCESS0R
 cmp ax,O .Jtlodel srnall
jano_of_digits .stack 100h
movah,02 .data
mov ex, bx countdbOOh
prornptl db 'enter your string:',',$'
popping: prornpt2 db ' you entered : ' , '$'
prornpt3 db' converted string:','$'
popdx pkey db 'press any key','$'
int 21h paralist label byte ; table of 3 bytes for keyboard input
loop popping maxchar db 79
actlen db?
mov dl, 32 kb_buff db 80 dup ( '$')
movah,02h .code
int 21h mainproc
print macro rnsg ; defining macro to display string
popdx mov dx, offset rnsg
pop ex movah,09h
int 21h
; display ends here printendm
nextline macro ; defining macro to advance to next line
inc dl ; control character for form feed
movdl,Odh
pop ax ; control character for nextLine,
mov ah, 02h
loop labell
mov ah,02h
int 21h
mov ax, 4c00h
nextline endm
int 21h
space macro ; macro defined print spacegap
mainendp
end main mov dl,09h
12. movah,02h
Write an assembly Ian
memory in data guage program to read a string frolll int 21h
I segment. Chan
ower case and vice versa . ge all the upper case letterS to spaceendm
[Note: AScn code for A~ Display the result on the acreen, · d · ut
mput macro prlst ; macro defined to input keyboar mp
...... 2=9(}, a~ ...... z=122]
[2067 MJmgsirl
mov dx, offset prlst
170
rnov ah, Oah
INSIGHTS
ONMtCROPRnr.
-""SSORS 171
PROGRAl8MIMG 111TH - lll'ROPROCESS0R
 crnP al, 61h
int 21h
jc uplast
inputendm
crnP al, 7ah
mov ax,@data
jnC uplast
mov ds,ax ; convert to upper
sub al, 20h
moves, ax
mov [si], al
print promptl
input paralist uplast:
nextline inC Si

print prompt2 Joopchkupr

print kb_buff ret
nextline t upper endp ......................... .
Q • ;;;;;;;;;;;;;;IIIIIIIIIII Ill fl /lll lllllf
call uplow
................;;;;;;;;;;;;;;;;;;;;;;;,,,,,,,,,,,,,,,,,,,,,,,,, ................. .
0 •• • • • 0 • • • 0 • • • • • • • • • • • • •

;;;,,,,,,,,,,,,,,,, •••••• 0 • •• 0 0 •• 0 0 • •••• H ;;;;;;;;;;;;;;;;,,,,,,,,,,,,,,,,,,

···········;;;;;;;;;;;;;;;;;;;;;;;;;,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,
print prompt3
print kb_buff ; to lower ························;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
nextline
.... ······ .........;;;;;;;;;;;;;;;;;;;;;;;,,,,,,,,,,,,,,,,,,,,,,,, .............. .
;;;,,,,,,,,,,,,,,,,,,, ....................;;;;;;;;;;,,, ,,,,,,,, If,,
········ .........;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,
print pkey
mov ah, 1 tolower proc near
;wait for any key .. ..... hold screen .. .
int 21h mov si, offset kb_buff
mov ax, 4c00h movch,00h
; exit to operating system. t of characters entered
mov cl, actlen . ex contains the coun
int 21h I

by user
mainendp
chkdn:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;,,,,,,,,,,,,,,,,;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; mov al, [si]
;input: supplied with read string from keyboard cmp al, 41h
;output: converted to uppercase jc dwnlast
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;,,,,,,,,,,,;;;; cmp al, 60h
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; jnc dwnlast
toupper proc near add al, 20h . convert to lower
I

mov si, offset kb_buff mov [si], al

movch, 00h dwnlast:
mov cl, actlen
; ex contain the count of characters by user inc si
chkupr:
loopchkdn
mov al, [si]
ret
172 173
INSIGHTS ON MICROPROCESSORS - -------:-:=:=.;~~uijiccRCROPROCESSoR
PROGRAMMING WITH IOBI Ill
 . offset array
tolower endp JYIOV S1,
!Jl.ov bl,0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'. '.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.'.;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, JYIOV cx,4
; upper to lower and vice vrsa again:
...,,•••••••••••·••••''''"'' •; ;;;;;;;;;;;;;;;;;;;;;;;,Ill II II II II n Ill II IrUII,,; f;;; ;;; ;; ;;-'•
l l l / / l llllfl/1////IIIIIIIIIII
If •• ",,, ,, ;
ll/f/11
mov al,[si]
11111
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; jnC Si
uplow proc cJYIP al,[si]
mov si, offset Kb_buff jcdown
mov ch, OOh mov dl, [si]
mov cl, actlen ; ex contains the count of characters mov [si],al
entered by user dee si
again: mov [si],dl
mov al, [si]
inc si
xor al, 00100000b ; you can alter D5 by xoring al with movbl,01
;00100000 binary value down:
mov [si], al
loop again
inc si
dee bl
loop again
jznext
ret
mov ax,4c00h
uplow endp
int2lh
end main
mainendp
end main d display the
d a number an
13. 14. Write a program in 8086 to rea [2068 Magh]
Write a program in 8086 to sort the numbers stored in an multiplication table of that number.
array. [2068 Jestha]
⇒ .model small .model small
.stack .stack
.data .data
array db 4,37,13,50,2,'$' .code
.code
main proc far
main proc far mov ax, @data
mov ax,@data
mov dx, ax
mov ds,ax
next:
mov ah, 07h · console input wt"thoutecho
I
174
INSIGHTS ON MICROPROCESSORS RQPR()CESSOR
PROGRAMMING WITH 8086 MIC
 int 21h
mov ex, 10 popdx
mov dl, 1 popCX
; to decimal value
; display ends here
sub al, 30h
labell: jnC dl
movah, 0 pop ax
push ax Joop Jabe11
muldl ; ax=al*dl
; for display mov ax, 4c00h
push ex int2lh
pushdx mamendp
movbx,0 end main
movcx, 10 15. Write a program in 8086 to read a string and count the
number of vowels, consonants, numerals and other
characters and display the count. [2068 Bhadra]
no_of_digits:
mov dx, 0 ⇒
.model small
div ex ; (dx;ax/cx=ax dx/cx) .stack 100h
add dx, 30h .data
push dx sl db 'Enter a string$'
inc bx vowl db 'AEIOUaeiou $'
cmp ax, 0 S3 db 10, 13, 'No of vowels are $'
jano_of_digits S2 db 50 dup ('$')
mov ah,02 count dw?
movcx, bx .code
popping: mainproc
mov ax, @data
popdx mov ds, ax
int 21h ; display 'enter the string'
mov es,ax
loop popping
lea dx, sl
mov dl, 32 mov ah, 09h
movah,02h int 21h ;read the string
int 21h lea di, s2
xor cl, cl
176 INSIGHTS ON MICR0PROCESSOO;RSi_ _ _ _ _ _ _ _ _ _...-! 177
PROGRAMMING WITH-MICRQPROCES80R
 cld push d.J(
jJlC C)(
loopl: mov ah, Olh
jJlC C)(
cmp al,Odh
jz endinpt
crnP a", ()(){)Oh
jne print;display 'No of vowels are '
stosb
inc cl lead", s3
mov ah, 09h
jmploopl
;checking vowel
mt 21h; pop from stack.
endinpt:
display:
mov bl, cl
popdx
cmp cl, OOh
jnzjumpl adddl, 30h
xor ax, ax movah,02h
jmppr int 21h
jump!: loop display
cld mov ah,4ch
lea si,s2 int21h
next: mov ex, OOObh mainendp
lodsb end main
lea di,vowl 16. Write an assembly language program for 8086 to read a
string. Display each word in separate lines in a cleared
repne scasb
screen, count how many words there are, and display the
cmp cx,00 count. [2070 BhadraJ
jz novowl
inc cl .model small
novowl: dee bl .stack
jnz next .data
; jump to next line
mov dl, Oah maxchar db 50
movah,02h nchars db?
int 21h actstr db 50 dup (0)
; print count of vowels
mov ax, ex wcountdbl
pr: mov bx,OOOah .code
xor ex ' ex·' printing
. multid. . main proc far
print: xor dx, dx ig:tt number; push into stack
mov ax,@data
div bx
movds,ax
178-r-::--- 179
INSIGHTS ON MICROPRocESsois· - -- - - - - - - - ~
 iJ1t 21h
mov ah,Oah inai1' endP
mov dx,offset maxchar
end Illa.in
17, Write an assembly• language to read a text from keyboard
int 21h sp1ay on cleared
convert the text into uppercase and di ,
mov ax,O [2071 Bhadra]
int 10h screen.
mov cx,O .rnodel small
mov cl,nchars .stack
mov si,offset actstr .data
mov ah,02h rnaxchar db 50
mov dl,Oah nchars db?
mt21h actstr db 50 dup (0)
mov dl,Odh .code
int 21h main proc far
again: mov ax,@data
mov al,[si] mov ds,ax
cmp al,20h mov ah,0ah
mov dl,al mov dx,offset maxchar
jne down
int21h
incwcount
mov cl,nchars
mov dl,Oah
mov si,offset actstr
int 21h
mov ax,0
mov dl,Odh
intlOh
down: int 21h
mov ah,02
inc si
again:
loop again
mov dl,Oah mov al,[si]
int 21h mov dl,al
mov dl,Odh cmp al,41h
int 21h jb reject
mov dl,wcount cmp al,7ah
or dl,30h ja reject
int 21h cmp al,51h
mov ax,4cOOh jacheck
111
180 INSIGHTS ON MICROPROCESSoAS- - - - - - - - - -~ PROGIWIIIING WITH 111& IICROPROCESSofl
 movbx,00
mov cl, actl
check:cmp al,61h
mov ch, 00
jb reject
next:int 21h l1: crnp str[bx], 32
reject:inc si jnz s1
loop again inc row
mov ax,4c00h mov col,40
int 21h call nextline
main endp jmps2
end main sl: rnov al,str[bx}
18. Write a program in 8086 to read a string and display each call display
word in a separate line in the center of the screen.
[2072 MaghJ inc col
s2: inc bx
⇒
loop 11
.model small
call nextline
.stack64h
mov ax, 4c00h
.data
int21h
srdb "enter the string: 11 , 1$1
rnaxl db254 mainendp
actl db ?
str db 255 dup(?) nextline proc near
row db12 movah,02h
col db40 mov dl,Oah
.code int21h
main proc movdl,Odh
mov ax, @data int 21h
movds, ax
movah,02h
mov dx, offset sr
movah, 09h movbh,OOh
int 21h movdh,row
mov ah,Oah mov dl,col
lea dx, maxl int 10h
int 21h nextline endp
callnextline
display proc near
113
182 INSIGHTS ON MICIIOPROCES50Rs ---------=:::::;~;,;.RC)PIIOC&ld
PROGU,,MIMIR WITH- IIIC
 jmp bell
mov ah, 09h bel: mov arr3[bx], 0000h
mov al, dl bell: incbx
movbh,OOh loop next
mov bl, 07h mov ax, 4c00h
movcx, OOh int 21h
int Olh mainendp
display endp end main
Write an assembly language program for 8086 to read a
end main 20· number (1 to 8 only) from user and calculate the factorial of
19. Two tables contain ten 16-bit data each. Write an assembly
it and display in decimal format. [2075 Bhadra}
language program to generate the 3rd table which contains
lFFFH if the corresponding data in the 1•1 table is less than
that of 2nd table, else store OOOOH. [2073 Magh] ::) page 60,132
title read a number (0 to 8) and display its factorial result
⇒

.model small .model small

.stack 32 .stack64h
.data .data
arrl dw numdb?
l l 45h,7898h,5224h,3969h,8422h,4598h,3574 fact dwl
h, 9526h,5893h,6587h sumdwO
arr3 dw tendwlO
8263h,9200h,2301h,1234h,9156h,3468h,0034 msgl db "Enter 1 digit number (0 to 8) : ",'$'
h,9265h,5213h,6157h
msg2 db Oah,Odh,"Factorial: ",'$'
arr3 dw 10 dup(O)
.code
.code
main proc far
main proc far
mov ax, @data
movax, @data
mov ds, ax
mov ds, ax
leadx,msgl
movcx, 10
movah,09h
movbx, 0000h
next: int 21h
movax, arrl[bx]
cmpax, arr2[bx] mov ah,Olh
jnc bel int 21h
mov arr3[bx], lfffh subal,30h
movnum,al
164 INSIGHTS ON MICROPROCESSORS 185
 v,Jr1·te an asseJl\bly
• language
. • program
. in 8086 to read a
z1. . and display 1t in next hne with first 1 tt .
movax,OOh stfll'lg • e er m
rcase and rest 1n lowercase for each word
mov ax,fact upPe · Baishakh]
[2076
mov ch,OOh
mov cl,num
,:;
next: mul cx Pagef'60,132 . lowercase for each word
t letter in uppercase and rest m
loop next title irs
mov sum,ax .11\odel small
lea dx,msg2 .stack 64h
movah,09h .data
maxlen db 100
int 21h
actchar db?
call disp_num string db 100 dup('$')
mov ax,4cll0h strl db Odh, Oah, "Converted string is: ", Odh, Oah, '$'
int 21h str2 db "Enter the string: ", '$'
mainendp
.code
disp_num proc near main proc far
movax,sum mov ax,@data
movcx,O mov ds, ax
loopl: mov dx,O
div ten lea dx, str2
add dl,30h movah,09h
pushdx int 21h
inc ex lea dx, maxlen
cmpax,O mov ah,Oah
jneloopl int 21h
loop2: movch,OOh
popdx mov cl, actchar
movah,02h mov di, OOh ; index
mov ah, 01h ; space indicator
int 21h
next: mov al, string [di]
loop loop2
cmpah, 01h
ret
jne bel
disp_num endp
cmp al, 'a'
end main
jbbelow
sub al, 20h
186 INSIGHTS ON M ----,-ROGRAIIMING
____WIT_H____IIIC-R-:-OPR::::::OC:;;:;E:;,SSOR;,;;-7187
~
 Chapter-m
mov string [di], al
jmp below
be\: cmp al,'' ; compares with space
~ROPROCESSOR SYSTEM
je below
cmp al, 'Z'
ja below
add al, 20h
mov string [di], al
----- A microcomputer consists of a set of components or
!llodules of thr~e basic types: CPU, memory, and I/0 units which
_,,,urucate with each other.
co11~·
below: mov ah, 00h 1 pin configuration of 8085
cmp al,'' ; compares with space 4
.::-----
jne 12
X.
mov ah, 0lh
12: inc di "· 1
11111,D X.

loop next "· a.llGIJT

-
)
~
lea dx, strl
mov ah, 09h
IOI)

SID
'
int 21h 1MP • UAD\' 10D
'
lea dx, string
mov ah, 09h •
JO ALI
int 21h » asn T ~
Sl(IIAI.I
mov ax, 4c00h llffll
....., ,. oil
int 21h
iiM ,. I
, J2 ii>
mainendp
end main
AD, •
asr,.s

INft
,. JI fl.
"°·
AD,
:II

27
llll'l II 2' . SfAt\lS
AD,
• UADY
,, ,, ISl(lll,u.l
I

AD, 25

AD, 21 11111,D
,. ,. iliiftii
AD, u ,. , ~
AD, D
GND 21
MSPliDala
(b)
(a)
Figure 4.1 (a) Pin diagram of 8085 (b) Logical schematic of pin diagram
189
188 INSIGHTS ON MICROPROCESSORS
- --- - - _ _ _ _ _ _ _ _ _..--! MICROPROCESSOR SYSTEM
 Nfultiple"e
d Address{Data Bus
The microprocessor is capable of performing var· AD0-AD1
. . . ious • ultiplexed set of lines used to carry the lower
computing functions and making dec1s10ns to ch~ge the sequence These rn
• S-bit address as well as data bus.
of program exec ution. In large computers, a CPU rmplemented 0 order
. the opcode fetch operation, in the first clock
one or more circuit boards performs these computing function: ouring
The microprocessor is in many ways similar to the CPU, bu~ • the lines deliver the lower order address Ao - A7•
cycle,
includes the logic circuitry, including the control unit, on one chip. In the subsequent IO/memory, read/write clock cycle
The microprocessor can be divided into three segments .for the sake • . es are used as dat& bus.
the 1in
clarity, arithmetic/logic unit (ALU), register array, and control • The CPU may read or write out data through these
unit.
lines.
8085 is a 40 pin IC, DIP package. The signals from the pins
5
can be grouped as follows: ~: L---------:~s jAddressbus
1. Power supply and clock signals ALEL-----i
2. Address bus 808S AD1 _ _.EN
___..., A1
3. Multiplexed address/ data bus Latch A0
4. Control and status signals D7 Joata bus
5. Interrupts and externally initiated signals L--------Do
6. Serial I/0 ports
Figure 4.2 Multiplexed address/data bus
1. Power Supply and Clock Frequency Signals
Control and Status Signals
• Vee: +5 volt power supply 4.
- &WR )
• Vss: Ground These signals include two control signals ( RD
- Si d So) to identify the
• Xl, X2 : Crystal or R/C network or LC network and three status signals (IO/ M ' an . . al (ALE) to
connections to set the frequency of internal clock . d one special sign
generator. nature of the operation, an .
. . £ the operations.
indicate the begmrung o -
• The_frequen~y is internally divided by two. Since the
• ALE (output) - Address Latch Enable d
basic operating timing frequency is 3 MHz a 6 MHz the lower or er
crystal is connected externally. ' This signal helps to c:~tu;~tiplexed address/
• CLK (outpu~)-Clock output is used as the system clock address presented on t
•t · the pulse,
8085 beginS an
for peripheral and d ev1ces
• data bus. When i is the separate
interfaced with the ADo - ATh a5
microprocessor. operation. It generates
2. Address Bus set of address lines Ao -A,.
vooevice
• As-A1s RD (active low) - Read Memory or
• It carries the most significant
.
• location or
lected rnernory .
address th . 1 s o f the me,....,.,
8 b't _,_
This indicates that the se that the data bus is
8
or e bits of the 1/0 address. nd
1/0 device is to be read a 191
190 MICROPROCESSOR SYSTEM
INSIGHTS ON M ICROPR - - -
OCESSORS
 '[here are five hardware interrupts called,

ready for accepting data from the mem •

device. ory or 1/0
rnYfL(inputs)

• WR (active low) - Write Memory or .,.

TtQ Device
. Rsrs:U
{NTR
Titis IN'fA (output)
·tt indicates
· that the data on the d a t a b us ·
• On receipt of an interrupt, the microprocessor
wn en mto the selected memory lo . is to be
device. cation or 1/0
acknowledges the interrupt by the active low, INTA

• IO/M (output) - Select Memory or an "O

., D ev1ce
. (Interrupt Acknowledge) signal.

.
Titis status signa1 m
· d'icates that the read / . }{old (Input)
operation relates to whether the write • This indicates peripheral controller requesting the bus.
device. memory or I/0
HLDA (Output)
It goes high to indicate an I/0 operation.
. • This indicates the acknowledgement for the Hold
It goes low for memory operat'
Statu · wns. request.
s signals are used to kn h
of the microprocessor. ow t e type of current operation READY (Input)
• It is used to delay the microprocessor read and write
Table 4.1 Status signals oif8085 microprocessor
. cycles until a slow responding peripheral is ready to

S1 S2 Data Bus send or accept data.

l0/M Memory and I/0 devices will have slower response
Status
0 0 0
• compared to microprocessors.
Halt
0 Before completing the present job such a slow
0 1 Memory Write • peripheral may not be able to handle further data or
0 1 0 Memory Read control signal from CF'U.
1 0 1 IO Write The processor sets the READY signal after completing
1 1
• the present job to access the data. th
0 IO Read
0 The microprocessor enters into WAIT state while e
1 1 • READY pin is disabled.
1 1 1 Interrupt
RESETIN (Input, active low)
5. Interrupts and ~:'.:;-=~-=:--_J_.!_A~c~kn~o~w~le~d~:J
Externally Initi This signal is used to reset the microprocessor·
• They are the . . ated Signals • ' . essor is set to
e program counter mside the rrucroproc
work t e microprocessor t ~ an external device to
request h s_1gnals Initiated b • Th
· 0 0 a particular task or zero.

-- • The buses are tri-stated.

192 INSIGHTS ON MICR - -
OPROCESSORS
 Power Supply
RESETOUT (Output)
Yee GND
• It indicates CPU is being reset.

• Used to reset all the connected devices Wh

-
microprocessor is reset. en the 1NTR

7. Serial J/O: 1NTA

1n1elll'PI
• SID (input) - Serial input data line ~tertace TEST
• SOD (output) - Serial output data line NMI
t----➔
Address/data bua
ALE
• These signals are used for serial communication. RESET 8086
MPU BHE/S 7

M/10
4.2 Pin Configuration of 8086 Memory/IQ
DT/R Controls
HOLD
OMA
Maximum Minimum intertace RD
Mode
HLDA
Mode Vee WR
GNO
vcc DEN
AD1,1 Mode MNMJ +----READY
A0 1• StleCI
AD13
A10 / S 3 T
AD12 CLK
A17 / S 4 Clock
A0 11
A 10 /S 5
A0 10 Figure 4.4 Pin details with signal groups for 8086 microprocessor
A,o i S.
AD0
BHE1s 1 • The _Microprocessor 8086 is a 16-bit CPU available in
A0 0
MN/Mi("° different clock rates and packaged in a 40 pin CERDIP
A07
RD or plastic package.
AD,

AO•
8088
M1croprocesso,
R°a,m. HOLD • The 8086 operates in single processor or multiprocessor
Ra1Gf, HLDA configuration to achieve high performance. The pins
AD,
~ "WR'" serve a particular function in minimum mode (single
AD,

AD, ~ M~ processor mode) and other function in maximum mode

AO, ~ DT/lf configuration (multiprocessor mode).
s-;
A00
as0
lilli • The 8086 signals can be categorized in three groups .
NMI ALE
as, The first are the signal having common functions
INTR ililTX
CU< ~ in minimum as well as maximum mode.
GNO READY The second are the signals which have special
RESET functions for minimum mode
Figure 4.3: Pin co ,,:; . The third are the signals having special functions
n,,gurahon of 8086 .
microprocessor for maximum mode.
,.. , ,Nii..is~----------
---------- - - - - - ----MI-CROPR()CESSOR SYSTEM

i
 ....--:;;::;: (Interrupt Acknowledge): This signal is
The following signal descriptions are common for b Oth 1N'fA USed for
t acknowledge. When it goes low, the proc
modes. jJlterruP essor has
ted the interrupt.
• ADwADo: These are the time multiplexed memory I/o accep
LE (Address Latch Ena~le): This output signal indicates
address and data lines. !e availability of the vahd address on the address/ data
• Ai,JS 6,A1rjS 5,A 17/S4,A 1f/S3: These are the time multiplexed
\jJleS.
address and status lines. The address bits are separated frolll
the status bit using latches controlled by the ALE signal. vr/R (Data Transmit/Receive): This output is used to
decide the direction of data flow through the trans-receivers
• BHE /S-r; The bus high enable is used to indicate (bidirectional buffers). When the processor sends out data,
transfer of data over the higher order ( D1s-Da ) data bus. this signal is high and when the processor is receiving data,
this signal is low.
• RD (Read): This signal on low indicates the perip
~ (Data Enable): This signal indicates the availability of
that the processor is performing memory or 1/0
valid data over the address/ data lines. It is used to enable
operation.
the trans-receivers (bidirectional buffers) to separate the data
• WR (Write): This signal on low indicates the periph from the multiplexed address/ data signal.
that the processor is performing memory or 1/0 HOLD, HLDA (Hold Acknowledge): When the HOLD line
operation. goes high, it indicates to the processor that another master is
requesting the bus access. The processor, after receiving the
• READY: This is the acknowledgement from the slow d
HOLD request, issues the hold acknowledge signal on.
or memory that they have completed the data transfer.
The following pin functions are applicable for maximum
• INTR (Interrupt request): This is to determine
mode operation of 8086.
availability of the request from external devices. If
~ terrupt request is pending, the processor enters S2, Si, So (Status Lines): These are the status lines which
interrupt acknowledge cycle.
reflect the type of operation, being carried out by the
• TEST : This input is examined by a 'WAIT' instru ' processor.
Table 4.2 Status signals of 8086 microprocessor
the TEST pin goes low, execution will continue, else
-S2
•
processor remains in an idle state.
~L~ (Clock input): The clock input provides the
- 0
S1
0
So
0
Indication
Interrupt Acknowledge
timing for processor operation and bus control activity. 0 0 1 Read I/O Port
0 1 Write I/O Port
The following pin 0
0 1 Halt
operation of 8086: 1
1 0 Code Access
0
• 1 0 Read Memory
M/ IO (Memory/IO) : When it is low, it indicates the 1
1 1 Write Memory
is having an 1/0
. •
operation, and when it is high, it indi 0
1 1

-----
that the CPU 1s having a memory operation. 1 Passive -
196 INSIGHTS ON MICROPROCESSORS
_ _ _ _ _ _ _MIC
_ R _OP
_ R_OC_E
_SS -
-:-0=:RSYSTEM - ,97
 1 sus: The control bus is a group of lines used t
LOCK : This output pin indicates that other system b 0 0
• 3, contr h access to control signals and the use of th d
ol t e e ata
master will be prevented from gaining the system bus, Whi.: contr d s bus. The control signals transmit b th
d ad res . . 0
the LOCK signal is low. ail d and timing information between the system
corrunan The timing signals indicate the validity of data and
odules.
RQ / GTo , RQ / GT1 (Request/grant): These Pins are
• J1l
ddress
information, where as command signals specify
d S f th
used by the other local bus master in maximum mode, to a . to be performe . ome o e control signals are:
operations
force the processor to release the local bus at the end of
,. 6 ory Write ( MEMW ): It causes data on the bus to
processor current bus cycle. • ,,.eDl
1

be loaded into the address location.

4 .3 Bus Structure
• Memory Read ( MEMR ): It causes data from the
A microcomputer consists of a set of components
addressed location to be placed on the data bus.
modules of three basic types CPU memory and 1/0 units w
communicate with each other. A _bus is a communication path • J/0 Write ( IOW ): It causes the data on the bus to be
between two or more such components. A bus actually consist&
multiple communication pathway or lines. Each line is capabl output to the addressed 1/0 port.
transmitting signals representing binary 1 and 0. Several · • J/0 Read ( IOR ): It causes the data from the addressed
the bus can be used to transmit binary data simultaneously.
bus that connects major microcomputer components such as 1/0 port to be placed on the bus.
memory or 1/0 is called the system bus. System bus cons· • Transfer Acknowledge: This signal indicates that data
number of separate lines. Each line assigned a particular have been accepted from or placed on the bus.
Fundamentally in any system bus the lines can be classified
three group buses. • Bus Request: It is used to indicate that a module wants
to gain control of the bus.
1. Data Bus: Data bus provides the path for monitoring
between the system modules. The bus has various n • Bus Grant: It indicates that a requesting module has
of separate lines like 8, 16, 32, or 64 which is referred been granted for the control of bus.
the width of data bus .These number represents the • Interrupt Request: It indicates that an interrupt has been
bits they can carry because each line carry 1 bit. pending.
2. Address Bus: Each lines of address bus are used to d ' Interrupt Acknowledge: it indicates that the pending
the source or destination of the data on data
interrupt has been recognized.
example, if the CPU requires re~ding a word (8, 16,
of data from memory, it puts the address of desired W The types of bus are explained as follows:
address bus. The address bus is also used to ad 1. Sync h ronous Bus: In a synchronous bus, the occurrence of
ports. Bus width determines the total memor}' the events on the bus is determined by a clock . Th_e clocA~
microprocessor can handle. transmit s a regular sequence of Os & ls o f equ al duration.
the events start at beginning of the clock cycle.
198 INSIGHTS ON MICROPROCESSORS
 I-{ere, the CPU places Memory Read (Control)
and
• address signals on the bus .
fhen it issues master synchronous signal (MsYNC)
Read • . di·cate the presence of valid address and ~~
rn t to
signals on the bus.
Start

• The addressed memory module responds with the data

and the slave synchronous signal (SSYNC)
Data Bus ll'------- Machine Cycles and Bus Timing Diagrams of
4,4
.AcknOWledge Signal 11.____ 80 95 Microprocessor
Figure 4.5 Synchronous read operation --;eration of a microprocessor can be classified into
following four groups according to their nature:
Here, the CPU issues a START signal to indicate the pre
of address and control information on the bus. • Op-Code Fetch
Then it issues the memory read signal and places • Memory Read/Write
memory address on the address bus. • I/O Read/Write
The addressed memory module recognizes the address • Request Acknowledgement
after a delay of one clock cycle it places the data Here op-code fetch is an internal operation and other three
acknowledgment signal on the buses. In synchronous are external operations. During three operations, microprocessor
devices are tied to a fixed rate, and hence the system c generates and receives different signafs. These all operations are
take advantage of device performance but it is e
implement. termed as machine cycle.
2. Asynchronous Bus: In an asynchronous bus the · Clock Cycle (T state): It is defined as one subdivision of the
maintained in such way that occurrence of o~e event operation performed in one clock period.
bus follows and depends on the occurrence of Machine Cycle: It is defined as the time required to
event.
complete one operation of accessing memory, 1/0, or
Read acknowledging an external request. This cycle may consiS t of three
to six T-states.
,. Address
Instruction Cycle: It is defined as the time required
completing the execution of an instruction. The 8085 instruction
MSYNC
IL cycle consists of one to six machine cycles or one to six operations.
·

1.
Data Bus
17 Op-Code Fetch Machine Cycle
lll.i The first operation in any instruction is op-code fetch. The
SSYNC
IL in
croproc
ernory r .
.
essor needs to get (fetch) this machine co e
.
d from the
ocessor can
F"igure 4.6 Asynchronous read operation bei,;h egiS ter where it is stored before the nucropr
"'"'' to exec t th .
=-=- ---- I201
200 INSIGHTS ON MICROPR ESSORS
------ u e e mstruction.
------------------
IIICRQMOCESSOR SYSTEM 1
 Let's consider the instruction MOV C, A stored at
location 2005H . The Op-Code for the instruction is 4FH :~tnory
ORDP.ll Ml!NOll
Code fetch cycle is of 4 clock cycles. Op.
SIGNAL
C LOCK

I .....
I
■.
. 11•
ALE i
I, Figure 4.8 Timing diagram for memory read machine cycle
IOIM,S,.s. I -
!!I ~
Step 1 : First machine cycle (op-code fetch ) is identical for timing
diagram of op-code fetch cycle.
Step 2: After completion of op-code fetch cycle, 8085 places the
Figure 4. 7 Timing diagram for apcode fetch machine cycle
address 2001 on the address bus and increments PC to
Stepl: Microprocessor places the 16 bit memory address 2002H. ALE is asserted high, IO/ M =0, 51=1, So=0 for
Program Counter on the address bus. At T1, high or
address (20) is placed at As-A1s and lower order ad memory read cycle. When RD = 0, memory places the

(05) is placed at ADo- AD7 ALE signal goes high. IO/ data byte 32H on the dada bus.

goes low and both So and S1 goes high for Op-Code 3. Memory Write Machine Cycle
Step 2: The control unit sends the control signal RD The memory write machine cycle is executed by the
processor to write a data byte in a memory location. The processor
, .... .
· .,. the memory chip and active during T2and T3. takes, 3T states to execute this machine cycle.
Step 3: ~e byte from the memory location is placed on the
us that is 4F into Do-D7 and RD goes high impedance.
Step 4: The instr uc ti on 4FH is decoded and content
accumulator will be copied into re<nster C dn.-ino
cycle T4 • o· --"D
2. Memory Read Machine Cycle
Let's consider the instructi
location 2000H. on MVI A, 32 H stored at

. Here two machine cycles are . .

which consists of 4 clock presented, first 1s op-code
. 1
cycesand d' d
cons1sts of 4 clock cycles. secon 1s memory rea
Figure 4.9 Timing diagram for memory write macltille cycle
---... _
203
202 INSIGHTS ON MICRO'IIOCESSOlls ------z-- -----· -MICROPR()CESSORsvsTEM
4. 1/0 Read Machine Cycle -·~ - ~ - - _.,.... --

• The I/O read cycle is executed by the process or to

a data byte from I/O port or from the periphera 1 W}\j
read
is 1/0, mapped in the system. ' ch
Port Address
• The processor takes 3T states to execute this mach,_
cycle. · 'lllle

• The IN instruction uses this machine cycle durin .' . ,, 1 Port Address

execution. g the

SIGNAL
CLOCK

... ~......
. ·. I I1/0 Port Address
1111 ,I 10/M=I, S =O, S =l

_, ••I-·
Data (D7-D8) Figure 4.11 Timing diagram for 1/0 write machine cycle

Step 1: In machine cycle M1, the microprocessor sends RD

lllll11
• I S =I, S =O
control signal which is combined with IO/ M to generate

•
- l 1•
• the MEMR signal and processor fetches instruction code
D3 using the data bus.
Figure 4.10 Timing diagram for l/0 read machine cycle Step 2: In machine cycle M2, the 8085 microprocessor places the
next address 2051 on the address bus and gets the device
5. 1/0 Write Cycle
address 01H via data bus.
Let's consider the instru f
location 2050H. c ion OUT 01H stored at m st'P 3: In machine cycle M 3, the 8085 places device address OlH on
low-order as well as high-order address bus. IO/ M goes
2050 D3
high for IO and accumulator content are placed on data
2051 01 bus which are to be written into the selected output port.
Op-Code Fetch Cycle
4T
Examples:
Memory Read Cycle
3T
I/O Write Cycle 1. Timing diagram for STA S26AH
3T
• ST A means store accumulator. The contents of lhe
accumulator is stored in the specified address (526 AH) .

- --
• The opcode of the ST A instruction is 32H. It is fetched
204 f · C clc
INSIGHTS~MICROPROcES50~;;;R;S----------_....j rom the memory 41FFH -Opcode Fetch Maclnne Y

~ - -~· - - - - MICROPROCESSORSYSTEM 205

 Then the lower-order memory address (6A) is the port address COH from 4126H.
• .
Memon; Read Machine Cycle.
read
. • Rea d
d the content of port COH and send it to the
Rea •
• The higher-order memory address (52) is react • accumulator .
Memory Read Machine Cycle content of port is SEH.
Letth e
• The combination of both the addresses are consid
. . erect
• ~

and the content from accumulator 1s written in s2 6Al:i. Address Mnemonics Opcode
Memory Write Machine Cycle ~

4125 IN C0H DBH

• Assume the memory address for the instruction and
the content of accumulator is C7H. So, C7H fr 4126 COH
accumulator is now stored in 526A.
Address Mnemonics Opcode
Opcode Fetch Memory Read 1/0 Read
• I• • I II •I
41FF STA526AH 32H

4200 6AH

4201 52H

Opcode Fetch Memory Read Memory Read Memory Wri

Figure 4.13 Timing diagram for IN COH.

Timing diagram for MVI B, 43H

Adclnss Mnemonics Opnie

2000 MVI B, 43H 06H

Figure 4.12 Timing diagram for STA 526AH
2. Timing diagram for IN COH - 2001 43H

• Fetching the opcode DBH from the memory 4125H

1•soGHTS oN "'''-sso"' ------ --- - - - - SYS-TEM~r207

-- - - - - --- - - MICROPROCESSOR
 101M. h,--H--t---tt-oiicodi;f°'I 1, s,~o
s,. so '---+-t--+--,..

Figure 4.14 Timing diagram for MVI B, 43H

• Fetching the opcode 06H from the memory
(Opcode Fetch Machine Cycle)
Figure 4.15 Timing diagram for TNR M
• Read (move) the data 43H from memory 2
(Memory Read Machine Cycle) 8086
Read and Write Bus Timing of
4. Timing diagram for INR M Microprocessor
• Fetching the opcode 34H from the memory 41
(Opcode Fetch Machine Cycle) Read Cycle Timing Diagram for Minimum Mode
, . ode configuration
• Let the memory address (M) be 4250H (Memory • The working of the mmunum m f the timing
Machine Cycle - to read memory address and data) system can be better described in terms O .b. the
diagrams rather than qua li·ta t·iv ely descn mg
• Let the content of that memory is 12H. operations.
• Increment the memory content from e similar. Hence
• The op-code fetch and read eye les ar . parts the
(Memory Write Machine Cycle) · d m two ,
the timing diagram can be categorize d the second
AddrM1 Mll!IIDnirs first is the timing diagram for read cycle an
q,cade
is the timing diagram for write cycle.
4105 INRM . sertion of address
34H • The read cycle begins in T1 with the as _ .
M / IO s1gna.1
latch enable (ALE) sigrial and also lid
. al the va
During the negative going edge of thi s sign '
address is latched on the local bus.
---- -- ---
209
 ta remains on the bus until middle of T st t
'fhe d a . . 4 a e.
• The BHE and Ao signals address low, high or b
- Oth
• \\TR
-'fhe becomes active at the begmning of 1 2 (unlike
bytes. From T1 to T4 ' the M/ IO signal indicates a RD is somewhat delayed in T2 to provide time for
memory or I/ O operation.
floating) .
• At T2, the address is removed from the local bus anct. The BJ-IE and Ao signals are used to select the proper
sent to the output. The bus is then tri-stated. The rea~ • byte o
r bytes of memory or I/ 0 word to be read or
( RD ) control signal is also activated in T2. write.
ihe M/ IO , RD and WR signals indicate the type
• The read ( RD ) signal causes the address device to
• of data transfer as specified in table below.
enable its data bus drivers. After RD IT, IT IT IT IT, IT,

valid data is available on the data bus;

Clk

• The addressed device will drive the READY line hi

ALE
When the processor returns the read signal to hi
level, the addressed device will again tristate its b ADD I sTATl'~ D l f . _ A,iL___s,_-_s_,- - -~X~----
drivers
ADD I DATA~ Au - Ae X V■Ud data D., - D, X~----
WR.

DT I R

Figure 4.17 Write cycle timing diagram for minimum mode

ADO/DATA
3. Memory Read Timing DlaRJ"am for Maximum Mode of
Ro 8086

Clk
DTIR

ALE

Figure 4.16 Read cycle timing diagram for minimwm 1'KNh S-1 - -S-o

2. Write ~ycle Timing Diagram for Minimum Add/Stata~

Operation
Add/Data

• A write cycle also begins with the assertion of ALE Mlffi<· -·-7__--1
the emission of the address. The M/ IO signal is DT 1 t r

r-
asserted to indicate a memo .
after sending th dd
ea ressinT
ry or I/0 operation. In
th
_;-~
data to be ·tt 1, e processor sends DEN- --------

,
----- - - wn en to the addressed location.
. .H T S O N M ~ -----=-- Figure 4.18 Memory read timing diagram Jor m
.
---.:::--
- - - - - - - -MIC--=-ROPR==:;;;;;ocessOR svsTEM
aximum mode
211
 are various types of memory which can be .
'fhere . classified
4. Memory Write Timing Diagram for Maxi . groups: pnmary memory and secondary m
of 8086 ___ rnutn Mode .,,, rnalfl emory.
jJltO ,,. 0
prilllatY Memory
1- . the memory
It 1s .
used by microprocessor to execute
C lk
.,,..s
pro gra ... · The nucroprocessor can access only those items
.
ALE
that are stored in thi_s memory. Hence, all data and program
_ _ ....c..:..:.:..:..:..:._ _ _ Y.,_ ____l!'_•_c_t ! ' : ~ - - ~ ~ must be within primary memory prior to its executioQ
prirnary memory is much larger than processer memory that
ADD/STATrs BlIE S7 -S,
is included in the microprocessor chip.

primary memory is divided into two groups:

l\l WTC or IOWc i. RfW Memory (RAM)
DT i !f Microprocessor can read from and write into this memory.
J'>EN This memory is used for information that are likely to be
altered such as writing program or receiving data. This
Figure 4.19 Memory write timing diagram for maximum mode memory is volatile i.e., the content will be lost if the power is
turned off, and is commonly known as RAM. RAM are
4 ·6 Memory Devices
basically of two types:
Mmxy a. Static RAM (SRAM): This memory is made up of flip
I
flops and it stores bit as voltage. A single flip flop stores
binary data either 1 or 0. Each flip flop is called storage
cell. Each cell requires six transistors. Therefore, the
I memory chip has low density but high speed. This
Smirarmn
Access memory is more expensive and consumes more power.
I
Disks b. Dynamic RAM (DRAM): This memory is made up of
Fl<ffl' MOS transistor gates and it stores the bit as charge. The
HOO
ctRQ\,f advantage of DRAM are it has high density, low pow~r
DVD
consumption and cheaper than SRAM. But the ~it
Figure 4.20 Classification oT inform,ation leaks therefore needs to be rewritten again
M . J memory system th
every few milliseconds. It is called refreshing .e
emory is an essential co
system. It is used to store both inmpon~nt of the microcompu memory and requires extra circuitry to do this. It is
store both instructions d struchons and data It used 15· slower than SRAM.
an data M · ii.
and the number of bits stored . . en:'ory is made up of re . Read Only Memory (ROM)
Memory wor d is • identifi d b m a re'"ste · called memory w
~OM contains a permanent pattern of data that cannot ~
o· r is
16 bit address , th en thereewill Ybean address
. · If microprocessor
• u c anged. It is non volatile that is no power source is
addresses ranging from OOOOH maxunum of 216 = 6SS36 memory requir d ROM are
toFFFFH. b . e to maintain the bit values in memory.
as1cally of 5 types:
1•m>owM11e1ciR~O;PRRiociEEiSSO~RSis____________
-·- - ---- ----.. . IIICROPROC~"T"
 ccess ti
·me: It is the average time required to wr·t th
1e e
Masked ROM: A bit pattern is permanently record write~ rrnation on memory.
a. lll11t of info
. pro d uc ti. on.
by the manufactures dunng ect
te (ra) = 1/ta
p.ccess ra
b. Programmable ROM: In this ROM, a bit pattern l11a 1..
.. Yue ime (tc)
written into only once an d t h e wnhng process is eye l e T
2. . the avera ge time that lapses between two successive read
performed electrically. That may be performed by a It 1s
supplier or customer. operation .
r )=bandwidth= 1/tc
c. Erasable PROM (EPROM): This memory stores a bit in c ycle ra te ( C
the form of charge by using EPROM programmer J\'fodes of Memory
w hich applies high voltage to charge the gate
.Information can be erased by exposing ultra violet
Aecess
dont acces s·• In random access mode, the ta is independent
1. Ran ti n from which the data is accessed like MOS
radiation. It is reusable. The disadvantages ~re : of the loca o
memory.
- It must be taken out of circuit to erase it
Sequentia • l ace ess·. In that mode, the ta is dependent of the
- The entire chip must be erased 2.
location orm which the data is accessed like magnetic type.
. f
- The erasing process takes 15 to 20 minutes. . dom-access·• The sernirandom access combines thesed
3. Semiran
d. Electrically Erasable PROM (EEPROM): It in magnetic disk, any track can be accesse
two For examp1e, b • ·a1
functionally same as EPROM except that informati . d
at ran om. But the access within the truck must e m sen
can be altered by using electrical signal at the re · fashion.
level rather than erasing all the information. It
expensive compared to EPROM and flash and can The Memory Hierarchy
erased in 10 ms.
Cap acity, cost, and speed of different types of memory play
• . . a memory system for computers.
a vital role while designing
e. Flash Memory: It is variation of EPROM. The d'
is that EPROM can be erased in register level but . more a pplica tion will get
memory must be erased in register level but
• If the memory has larger capacity,
space to run smoothly.
memory must be erased in its entirety or at block le
far as possible to
2. Secondary Memory • It's better to have fastest memory as h practical
achieve a greater performance. Moreover for t e
The device~ that provide backup storage are called se system, the cost should be reasonable.
memory. It mcludes serial access type such as magnetic
and random access type such as magnetic disks. It
• There is a tradeoff between these three
characteristics cost,
. II these
nonvolatile memory. capacity and access time. One cannot achieve a
quantities in same memory module because d
Performance of Memory
. ·ncreases (slower) an
1. Access Time (t.) If capacity increases, access time 1
due to which cost per bit decreases. d
R~ad a_ccess ti~e: It is the average time required to read acity decreases an
urut of information from memory. If access time decreases (faster), cap
due to which cost per bit increases. __
214 I '"..""°" MIOIO-- ....______ ---~ ------ ------=-::::-
MICROPR
--M
OCESSOR svsTE - -115
 • The designer tries to increase capacity because cost p . m
.. me ory to a relatively
. faster
. cache rnernory
decreases and the more app1.t~a ti' on pro~am caneq,t be atl)(iliaIY high speed processmg logic. The fic,-,,?e be!ow
accommodated. But at the same time, access t1111e inc accesSI'ble toemory hierarchy. o"--'
illustrates m
and hence decreases the performance. reases
So the best idea will be to use memory hierarchy.

• Memory hierarchy is to obtain the highest possible access

speed while minimizing the total cost of the memory syste
• Not all accumulated information is needed by the CPU rn. at
the same time.

• Therefore, it is more economical to use low-cost storage

devices to serve as a backup for storing the information that
is not currently used by CPU
• The memory unit that directly communicate with CPU is
calied the main memory
• Devices that provide backup
memory Figure 4.21 Memory Hierarchy

• As we go down in the hierarchy,

The memory hierarchy system consists of all storage device,
employed in a computer system from the slow by high- Cost per bit decreases
capacity auxiliary memory to a relatively faster main Capacity of memory increases
memory, t? an even smaller and faster cache memory Access time increases
•
The main memory occupies a central position by being a Frequency of access of memory by processor also
to communicate directly with the CPU and with au · · decreases .
memory devices through an I/0 processor
•
~
special very-high-speed memory called cache is used 4.7 Address Decoding
mcrease the speed of processing by ma.king c
programs and data available to the CPU at a rapid rate - The read/write memory is . ma d e O f b'registers, and each
f information;
• register has a group of flip-flops that store its of b't tored in
C~U logic is usually faster than main memory access · these flip-flops are called memory cells. The n umber o. I s s egisters
with the result that processing speed is limited primarily a register is called a memory word. In a memory c~p, a11 r mbers
the speed of main memory
• The cache is used f t ·
are arranged in a sequence and 1·den tif.ie d by bmary nu
called tnernory address.
. or s onng segments of progr
currently being executed in the CPU and temporary da
frequently needed in the present calculations . to: To communicate with memory, the processor should be able
•
The memo?' hierarchy system consists of all storage devicea Select the chip
employed In a computer system from slow but high capacity
216 Identify the register
Read from or write into the regi5ter

MICROPROCESSOR SYSTEM 217

 Th address decoding circuit enables MPU to
e . ~~
address within memory chip or I/0 chip and then react or1 ~n 0
i..;ch I / M = o.
Here, chip select
. signal of each dev1ce
. .
into it through the available data bus and thus avoid contenti~ te w,.,·ved fro m 16-bit address lines thus total add . 15
ressmg
data collision within the data bus. n °r
def!ability
_ 1·s 64K bytes. Usually memory mapped I/O 1s .
Microprocessor is connected with memory and I/o d . cap to ma p memories like RAM, ROM, etc.
used
via common address and data bus. On1y one device . can sendevices
d d. on the address that are allocated to the device
at a time and other devices
· can onI . thatd ata. If rnore ata
y receive Depen mg · d · th f II · '
ddress d eco ding are categonze m e o owing two groups:
one device sends data at the same time, the data gets garbled.1 the a •
order to avoid this situation, ensuring that the proper device .
Unique Address Decoding .
addressed at proper time, the technique called address decoding 1, h address lines on that mapping mode are used for
used. If all t e h d d. . 11 d ·
address decoding' then t . at .eco mg 1s ca e unique address
In address decoding method, all devices like memory bl decodmg.
. It means all 8 Imes m I/0 mapped I/0 and all 16
I/0 units, etc. are assigned with a specific address. The address
the device is determined from the way in which the address · Jinesm
- m emory mapped I/0 are used to derive _ cs signal. It
are used to derive a special device selection signal known as is
. expens1·ve and complicated but fault proof m all cases.

select (CS). If the microprocessor has to write or to read fro

device, the CS signal to that block should be enabled and

address decoding circuit must ensure that

devices are not activated.
cs signal to

Depending upon the number of address lines used

gener~te chip
classified as: select signal for the device, the address decod'
1.
1/0 Mapped 1/0
th th
In is me od, a device is identified with an 8-bit ad Figure 4.11 Vmque address Clecod tng
and operated by l/O related functions IN and OUT
If Au is high and A 1- A7 are low and if !OW becomes
which IO/M = 1. Since only 8-bit address is used, at
256 bytes _can be identified uniquely. Generally lower low, the latch gets enabled.
address bits (AO-A 7) . ,
(A.ii • are Used and higher order address The data to the LED can be trans f erre d in onlv• one case
. -A1s) are considered don't care. Usually I/0 mapped
is used to map devices like 8255A 8251A t and hence the device has umque
• a ddress of 01 H.
2. , , e c.
Memory Mapped 1/0
In this method a d · - .
,
operated by mernorev1ce is identified With 16-bit address

T. . . . .
1
Y re ated functions such as STA, LDA

Miciio.~-
. .IIICROPiioc•SIOR svsTBI I"'
 Eight J/P switch interfacing at 53H (01010011):
2732 (4K x 8): EPROM, address range should be .
ii, ooooH and additional 4K memory space shou~n at
available for future expansion. be

iii, 61l6(2K x 8): CMOS R/W memory.

Sl·gn a memory address decoding circuit first
To d e . , ca1cu 1ate
nu!Il ber of address pms.
used by the memory device depend mg·
th
eon th e memory capacity they can handle. Then deterrnm e th e
up . addresses for memory devices (RAM, ROM). Then
IOSEL lllapplilg dd . h' h
deterJillil the different a . ress pms w 1c need to provide the
. e
input for n x 2n decoder. Finally s_e lect the me~ory chips by using
the appropriate decoder output hne and requrred control signals
Figure 4.23 Input inteifacing at 53H ~O/ M ' RD I WR ).
b) Non-Unique Address Decoding
Let us draw a circuit diagram of a memory device
If all the address lines available on that mode
add d d are not used interfacing where one 4Kx8 EPROM chip, additional 4K x8 for
ress eco ing, then that decoding is called non .
address decoding. Though it is cheaper, there may be -un, future expansion and one 2Kx8 CMOS R/W chip at address
of address conflict. ac OOOOH.
Step 1: Calculate the number of address pins
D,
4KX8 chip requires 12 no. of address pins and 2KX8 chip
Data Bus requires 11 no. of address pins. This can be calculated from
latch
Do
n = log (memory capacity in bytes)/ log (2)

Latch
Step 2: Memory mapping table
Enable Memory Address
Ats A1i Au Au Au IA11 A, As A1 Ai; As ~ AJ A2 A1 Ao
Block
EPROM 13tart:OOOOH
Figure 4 24 N, . 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
· on-unique d.'d End :OFFFH 0 0
a ress decoding I I I 1 1 1 1 1 1 1 1 1 1 l
RAM 13tart:2000H
If Ao is low and IOW . 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
End:

---
H is ow. Then latch gets enabled. 0 0 I I
ere A1-A7 is neglected . 27FFH I 1 1 1 1 1 1 1 1 1 1 11
enable the latch. that ts any even address
Examples:
liere, after placing EPROM, we need to reserve 4K x8
I.
Design an interfacing c· . rnernory for future expansion; hence starting address of
1rcu1t for foll 0 . RA.M comes to 2000H instead of 1000H.
i. 74LSI38· 3 t 0 8 D Wing problem.
_ • ecoder
220{ INSIGHTS ON MICROP_R_ ----- -
OCfSSoRS · - - - - -~ - -

---------- - · - - - - - - - - - MICROPROCESSORSYST•• , " -- r,,

 Step 3: Decide decoder pins emory chips by using the appropriate d
1 ct the m ecoder
Here bits Au and A13 address lines are different fo . and required control signals (IO/ M , -RD
see ut ltne
ou tp
,
referring d2
to end address Ii nes. We nee d to use a 3)(8 rchips
so we need to add one address lme . and here we can ecodet, wif>-
We can use address lines A14 and Ais to generate chipUse A12• . a circuit diagram
Qrawmg h. of a dmemory device interfacing
signals for 3X8 decoder. enabJe ith one 4KB EPROM c 1p, an . two 2KB RAM chips at
Step 4: Draw a decoding circuit w
address BOOOH involves the followmg steps.

The output from decoder Y1 (001) selects the EPROM and Step 1: Caku1ate the number of address pins.
(100) selects RAM. The address decoding circuit is di:
below. 4 8 chip requires 12 no. of address pins and 2Kx8 chip
require
KX. s ll no. of address pins. This can be calculated from
n = log (memory capacity in bytes)/ log (2)
+5V
Step 2. Memory mapping table
~

Memory Address A,s A,. A13 A12 An A10 A• As A1 As

A10 As A. A, A, A, Ao
Block
74LS 138 Address;
3x8 Active 100 lines
Low Decoder EPROM Start:8000H 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001 Ao
End:8FFFH 1 0 I I I 1 1 1 1 1 1 1 1 1 1 1
RAM! Start:9000H 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
End:97FFH 1
A11 0 I I I 1 1 1 1 1 1 1 1 1 1 1
D7 RAM2 Start:9800H 1 0 0
Address: 1 1 0 0 0 0 0 0 0 0 0 0 0
lines 4Kxs : Data
Ao .
EPROM / lines
Do
End:9FFFH 1 0 I I I 1 1 1 1 1 1 1 1 1 1 1

Step 3: Decide decoder pins

2 Fig.: Address decoding circuit
- Design an interf · • . Here, bits An, A12 and A13 address lines are different for 3
an d two 2KB R/W acing
memcircuit f to interface one 4KB EPR h
c 1ps
. referring to end address Imes.
. So, we need to use a 3X8
ory or 8085 microprocessor. d
To design a memory add . ecoder. We can use address lines A14 an d A 15 to generate
th e num ber of address ress . decodmg circuit, first c chip enable signals for 3X8 decoder.
depending u 0 th pins used by the memory de Step4• Dr
P n e memory • · aw a decoding circuit
determine the ma . capacity they can handle.
(RAM RQA,n for memory dev·
' .. ,,. ThenPPmg
dete addresses
n-,;_ The output from decoder Y1 (001) selects the EPROM, Y2
. The
h . h
w ic need to prov·d h .' r .• .,ue the different address (OlO) selects RAMl and y 3 (011) selects RAM 2 chips.
I e t e mput for nx 2n decoder. p· address decoding circuit is drawn below.
"/ ,.;,.;,,.-, .,.-...,"°'"""'sioiis-
-------- - - - - - - - - -MICRQPROCESS()RSYSTEM 223
 ~aru . cuit diagram of a memory device interfactn g
+5V
oraw 2KXB ROM chip, 2KX8 RAM chip and one 4K XB
E, , E2, E3
A10 , cs Rf> Wk with
ROM . a 1 add<ess AOO0H Uwolves the following s~p, .
onechip
Address/ 2K X 8
74LSJ38
3x 8 Active l~ ' RAM2 EP
1. Calculate t
he number of address pins
Low Decoder
step · hip requ1·res 11 no. of address pins and 4Kx8 chip
A10 requrr 12 no. of address pins. This can be calculated from
2KX8. es
c
Adder n"' log (memory capacity in bytes)/ log (2)
lines
Ao ory mapping table
Step 2•Mem
·
r---
Memory · Address A1sA1t An A12 An Arn A9 A., A1 A,
As A, A, A, A, A,,
All
Address
cs R5 n----
! 4K X 8 i Data
Block
r'jioM rStart:AOOOH 1 0 I I I 0
lines i EPROM / lines 0
0 0 0 0 0 0 0 0 0 0
Ao End:A7FFH 1 0 1 0 0 1 1 1 1 1 1 1 J 1 1 1
Fig.: Address decoding circuit 'RAM Start:A800H 1 0 I I I 0 0 0 0 0 0 0 0 0 0 0
3.
End:AFFFH 1 0 1 0 1 1 1 1
With a neat diagram, explain the interfacing circuit 118" 1 1 1 J 1 J 1 1
3:8 decoder (74LSI38) needed to connect the foll EPROM Start: BOOOH 1 0 I I I 0 0 0 0 0 0 0 0 0 0 0
memory units to the 8085 microprocessor consecuti~ End:BFFFH 1
starting from memory location AOOOH. 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
i. 2Kx8 ROM chip
Step 3: Decide decoder pins .
ii. 2Kx8 RAM chip
iii. 2Kx8 EPROM chip x
Here, bits A11 and A12 address rmes are different for 3 chips
referring to start or end address rmes. We need
1· toduse a 3we8
here
To design a memory address decoding circuit, first cal
d
decoder, so we nee to a dd one address me an
d A to generate
the number of address pins used by the memory d
can use A13. We can use address lines A14 an 1s
depending upon the memory capacity they can handle.
deterzni.ne the mapping addresses for memory devices chip enable signals for 3X8 decoder.
ROM). Then, determine the different address pins which Step 4: Draw a decoding circuit (lOl)
to provide the input for n>Qn decoder. Finally, select
memory chips by using the appropriate decoder output The output from decoder Y4 (100) selects the
OMROM,
The Ys
address
selects RAM and y 6 (110) selects the EPR ·
and required control signals (IO/ M , RD , 1vif ).
decoding circuit is drawn below.

"'------------ - - - · - - - - - · - - - - -·---·----- -SYSTEM

MICROPROCESSOR /225
 r dity of required signal.
ks the va 1
heC d .
A15 It c •nter as output ev1ce.
A14 ~- con
sider the pn . ..
. roproc essor checks ideal condition of printer' if
CS RD

•
I }!ere,I tnuc
hen sends the data to be printed and required
E,. E2, E3 4K X 8 I .. ·dea
74LS 138 ". • I EPROM 1
nunan d for that.
".
I>•
3x 8 Active
High Decod er II co . of typical microprocessor to 1/0 devices such
RT, prmter etc ., all need 1/0 interface
for interfacing_ . . circuits which
I k
as in1 two types.
eyboard, C . parallel interface and senal interface.

•
Address [ areofma y
lines i
Ao . llel Interface
. ..,ac1•ng refers to a multiline channel, which is
4,8.1 Para llel mter
1
A Opara . .
f transmitting several bits of data simultaneously.
h This
.

■
A10
capable .
Bel mter facmg
. transfers n-bit data at
. t e same
. time,
.
Address i
means, para f wires. In parallel mterfacmg with
Ao
lines /
• using n
number o . /
-based system, microprocessor and mput o_utput
microprocess~r ted with multiline channel al!owmg a
. are mterconnec . . th
Fig.: Address decoding circuit devices . hi her data rate and hence maxuruzes e
system to achieve
d 'dth Before USBg ports became common, most personal ·
4.8 Input/Output Devices
computers
ban w1 .(PCs) had at least one parallel interface for connecting a
Input/output devices are the means through which printer using a parallel port.
microcomputer unit communicates with the outside world. 11te
between the I/0 devices and the microprocessor is maintained Data Transfer Modes of Parallel Interfacing
circuitry known as I/0 module. This circuitry includes the s , transmission of data ts
. use d. for
interfaces needed for I/0 devices as well as control functions Parallel . short
Thi distance
f rm ofwhere
data
. transter 18
the speed of information · critical. s ter0 peripheral
implement the I/0 transfers within the computer. 1/0 d ·
. . . f
communication 1s oun 1 d . n newer type of compu
. haracters per
usually are appeared as passive devices which take action
when instructed to do. The CPU monitors the status of the I
.
equipment with transfer speed O f t O one .mil1dion
. c and various
second. The equipment inclu d es pnn. ters, disk nves,
devices and selects them according to availability and need.
other forms of peripheral components. d
Consider the keyboard as input device and the steps
the key is pressed are
The information exchanged between a microprocessor an
d t and control
an 1/0 interface circuit consists of input or output . a a rocessor to
• Microprocessor detects the key change in status of ke
i.e., the key is pressed. information. The status information enables the nucrop eive data.
. the device and when it is rea dY then send or recr to cause
lltoIUtor
• It receives the encoded information Control infonnation is the command by microp"""'"', d~-
pressed key.
1/o device to lake some action. If the devke ope,ates a a,ticul"1

-r
speed s, then microprocessor can be used to select da top transfer
226 INSIGHTS ON IIIIICROPROCESSORS sPeect of operation of the device. The techniques use

- - - - - - - - - - - - : -::MIC:::RQPROCE~Mt:1!1SSOR&&
 data between different speed devices and computer is lJ sffi ~
synchronizing. There are var~ous . ca ed
ways of synchronization
techniques which are inv_olved m parallel _data transfer such as
simple input and output, simple strobe I/0, single handshaking, illld
double handshaking.
Data-==><=====
Figure 4.29 Simple strobe J/O

1. Simple 1/0 The send 1·ng device outputs parallel data on the data lines,
To get digital data from a simple switch into and th en outputs STB .signal to. represent the valid data is
.
microprocessor; switch is connected on input port line froll'Ia present • In this technique, microprocessors
. need to wait
which port can be read. The data is always present ilnd until the device is ready for the operation and also known as
ready so that it can be read at any time. Similarly, to outp simple wait J/0.
data to a simple display device like LED, the input of L
buffer is connected on an output port pin. And output Single Handshaking
logic level required turning on the light. The LED is alw Handshaking is the method of synchronizing the actions of
there and ready so that data can be sent at any time. slow peripheral devices with that of high speed
microprocessor. It can have two transfer schemes:
Data.==x===

Figure 4.28 Simple J/O

Input handshake (peripheral to microprocessor):
The peripheral outputs some data and sends some strobe
This timing waveform illustrates the simple 1/0 where
signal to microprocessor. Microprocessor detects asserted
lines represent the time at which a new data byte beco
valid on the output lines of the port. Absences of o strobe signal (SIB) and reads the byte of the data . Processor
waveforms indicate that this output operation is not then sends acknowledgement signal (ACK) to peripheral to
dependent on any other signals.
indicate that the data has been read and can send next byte
2. Simple Strobe 1/0 of data.

In ~any applications, valid data is present on an exte ffi--~ ;---

~evice only at a certain time and must be read in at
tim_e. Here a strobe pulse is supplied to indicate the time
which data is being transmitted F
\ ~..-----.~
ACK ·
.
discuss
. .
the ASCII encoded keyboard. orWh
.
an examp
k 1.e, we
ena ey15
circuitry on keyboard sends out ASCII code for pressed
on eight parallel data lines and th d
Data=
Figure 4.30 Single handshaking
signal on anoth . . . en sen s out a s
.
on eight er line to mdicate that valid data is
data lines • The peripheral outputs some data and send STil ,,signal
to microprocessor to tell "Here is the data for you ·
• .
Microprocessor detects asserted -5TB si·gna1' reads
CK) the
to
data and sends an acknowledge sign · al (A

- - ----- - -----
 indicate data has been read and peripheral can senct
next data, "I got tha t one, send me another". . heral then sends data and raises its 8TB .
•
Penp . 1me 1ow to
say "Here is some vahd data for you."
• Microprocessor sends or receives data when peripheral
is ready. Microprocessor then reads the data and drops its ACK
• to say "I have the data, thank you and .
Output handshake (peripheral from microprocessor): Jine ' ' 1 await
your request to send the next byte of data."
Microp rocessor outputs data to peripheral and asserts a
Outpu_t handshake (peripheral from microprocessor)'·
strobe (5TB) signal. I£ peripheral is ready, it answers back
with acknowledgement (ACK) signal to microprocessor. Micropro
. cessor sends a strobe (SIB) signal and data and
4. Double Handshaking . h eral sends acknowledgement (ACK) signal.
pertp

For data transfers where even more coordination is requir Programm able Peripheral Interface {PPI) - 8255A
between the sending system and the receiving system, The Intel 8255A is a general purpose programmable I/0
double handshake is used. It can have two transfer schemes.
. des1gn
device · ed for use with. Intel. microprocessors.
. . It has 24 I/0
Input handshake (peripheral to microprocessor): pins
. that can be grouped pnmanly m two 8-b1t. parallel ports: A
and B, with the remaining bits as port ~- The 8 b1~s of port C can be
Peripheral asserts strobe (5TB ) line low to ask recei use d asm· di·v1·dual bits or be grouped m two 4-bits ports: C. upper
device whether it is ready or not for data recepti (Cu) and c lower (CL)- The functions of_these ports are defined by
Receiving system raises its acknowledgement (ACK) · writing a control word in the control register.
high to indicate it is ready. Peripheral device then sends
byte of data and raises its strobe (5TB) line high.
microprocessor reads data, it drops its acknowledg
-
""""'{-- -Gll()
(ACK) line low and requests sending system to send n
byte of data.

srn~
ACK___)__,~

:x =
..,
Data-=
Figure 4.31 Double handshaking
• The peripheral asserts its 8TB "'""'
microprocessor "Are you ready?" u ___J
•

I
The microprocessor raises its ACK line hi h to say
am ready". g Figure 4.32 Internal block diagram of 825SA
230 MIOlc>PRocruoRS ---~ --
------------
INSIGHTS ON
 The 8255A has the following main blocks:
Table 4.3 Port selection of 8255A
a. D ata bus buffer ,----
A1 Ao Selection
The 3-state bidirectional 8-bit buffer is used to interface th cs
,------
8255 A to the system data bus. Data is transnuttect e
0 0 0 Port A
received by the buffer upon execution . of mput
. Ot
or output ,-------
0 0 1 Port B
instructions by the CPU. Control words and status ,---
0 1 0 Porte
information are also transferred through the data bus buffer. r
b. Read,lwrite control logic 0 1 1 Control register
'
1 X X 8255A is not selected
The function of this block is to manage all of the intern.a) cllld:
external transfers of both data and control or status words. Group A and group B controls
accepts inputs from the CPU address and control buses
Funchona
. l configuration of each port is programmed by the
in tum, issues commands to both of the control groups.
system software · In essence, the CPU outputs a control word
• Chip select (CS): A "low" on this pin enables he 8255A. The control word contains information such as
communications between the 8255A and the CPU.
to t
"mode", "bit set", "bit reset ,, , etc. that uu
. ·h·a1·1ze the
functional configuration of the 8255A. Each of the control
• Read (RD ): A "low" on this input enables the 8255A blocks (group A and group B) accepts "commands" from the
send the data or status information to the CPU on read/write control logic, receives control word from the
data bus. In essence, it allows the CPU to read from internal data bus, and issues the proper commands to Its
8255A.
associated ports.
• Write (WR): A "low" on this input pin enables the • Control group A - Port A and port C upper (C7-C)
to write data or control words into the 8255A.
• • Control group B - Port B and port C lower (CJ-Co)
Reset (RESET): A "high" to this pin dears the con
register and sets all ports (A, B and q in the in The 8255A functions in two modes:
mode.
• Bit seVreset mode: The BSR mod e ts
· u sed to set or reset
• the bits in port C.
Ao and A1: These input signals control the selection
one of the three ports or the control word register. • J/0 m~e: The 1/0 mode is further divided into three
are connected to the least significant bits of the ad
bus. modes: mode O mode 1, and mo d e 2· In mode 0,. all
ports function , as simple 1/0 po ~ · M~el ~a bits
h
The .CS signal is the master chip select, and Ao and andshake mode whereby ports A and/or B use d hake
f
th .
rom port C as handshake s1gna ls· In the han s be
below. one of e l/O ports or the control register as gi
specify
rnocte, two types of 1/0 d a t a transfer cande 2
.tmplemented: status check and mterru
. pt· In mo
transfer'
port A can be set up for b 1.d.tree tional data n be
Uslllg
. handshake signals from port C and port 8 ca
set up either in mode O or mode 1.

---MICROPROCESIORsvinarr
 The 8255A is a widely used, programmable, Parallel l/o
device. The features of 8255A are:
ro I word:
1D JD j D1l DoJ
It J/0 C0 nt
be programmed to transfer the data ,,
can . . -.nde ~jD
5 4 3 2
various conditions - from sunple 1/0 to mterrupt I/o 1 L.._Group~

• It is compatible with all Intel and most other - l ~

Port C lower
1 "'Input
microprocessors.
0"' Output
It is completely ITL compatible. Port B
1 "'Input
It has three 8-bit ports namely port A, port B, and P0rt
0"' Output
c which are arranged in two groups of 12 pins,
Mode Selection
port has a unique address and data can be read from
written to a port. In addition to the address assigned
- 0"' Mode0
1 =Model
the 3 ports, another address is assigned to the con
register into which control words are written
programming the 8255 to operate in various modes. L___ Group A~
Its bit set/reset mode allows setting and resetting Port Cupper
individual bits of port C. ~

1 =Input
0 = Output
The 8255A can operate in three 1/0 modes
mode 0, mode 1, and mode 2. Port A
1 = Input
8255 Control Word
0 =Output
When Ao and A1 pins have value 1, Mode Selection
00 =Mode0
addresses the control register which is the 8-bit register to wri 01 =Mode 1
specific content according to the port conditions although it c 1x = Mode 2
be read. The content of this register is called control word w
specifies an I/0 function for each port.
• 1 = I/O Mode
Q = BSRMode
The MSB (D7) of the control word tells which control
we are sending it, that is, it specifies either the I/0 function or
Figure 4.33 8255A co11/ro/ word fonnat for I/O mode
bit set reset function. If bit D7 = 1, bits 0 -0 determine 8
6 0
functions in various modes as shown in figure. If bit D7 = 0, SR control word:
operates in the bit set/ reset (BSR) mode. The BSR control
does not affect the functions of ports A and B. This control word, when written m
0
°
. con tr I register, seb or
resets ne bit at a time, as specified in Figure 434 ·

,...,..TSO. Moc,.,..oc,;,,,., -- -
MtcROPROCESSOR sm•• I"'
 D7 D6 Ds D4 D3 D2 D1 00
outputs are latched
O ~R
, Inpu ts are not latched
6 d •fferent input/ output configurations are .
Set,,, 1 1 mode.
this 1 possible in
BSR Mode Reset,,, 0
BSR Mode (Bit Set/Reset)
Not Used 2.
Generally Set = 0 gsRm
0 de is concerned only with eight bits of port C
. .
hi
, w ch
can be set or reset by wntmg an appropriate control word in
000 = Bit 0 the control register. A control word with bit o " is
7 0
recognized as a BSR control word and it does not alter any
001 = Bit 1 previously transmitted control word with bit D7 " 1; thus the
If O operations of ports A and B are not affected by a BSR
0JO = Bit 2 control word. In the BSR mode, individual bits of port c can
be used for applications such as on/ off switch.
011 = Bit3
Mode 1 (Strobe Input/Output)
100 = Bit4
The functional configuration provides a means for
101 = Bit 5 transferring I/0 data to or from a specified port in
110 = Bit 6 conjunction with strobes or handshaking signals. In mode 1,
port A and port B use the lines of port C to generate or
111 = Bit 7 accept these handshaking signals.

Figure 4.34 8255A control word format for BSR mode Mode 1 basic functional definitions:
Operating Modes of the Intel 8255A • Two ports, port A and port B can operate in mode 1.
l. Mode O(Basic InpuVOutput) The 8-bit data ports (port A and port B) can be either
This functional conf . input or output. Both inputs and outputs are latched.
.
output operal!on igurahon
for each provides
f simple input
0 • The separate 3 bits from port C are used to provide
'handshaking" 1s• required·
. d t • . . the three ports. control and status for 8-bit data ports.
from a specified port. ' a a is simply written to or
Mode 2 (Strobe Bidirectional Bus J/0)
Mode O basic functional def' 't•
in1 10ns:
• Two 8-bit ports ( t' A
The functional configuration provides a means for
(port C Jowe :or and port B) and two 4-bit
r anL port C upper) can operate in mode
c~rnrnunicating
81
8
with a peripheral device or a structure on a
~gle -bit bus for both transmitting and receiving data
• Any port can be input or output (b1directional bus I/0). "Handshaking signals" are provided
to Itlaint · . · il r manner
236TINSIGHTS ON MICROPRoc ftounction
am proper bus flow discipline m a 5 ,m a
rnoct e 1. Interrupt generation and ena ble/d1sable
.
/ EssoRs
_ s are also available.

MICROPROCESSOR SYSTEM
 Mode 2 basic functional definitions: . J· l ~ -3V to -25V
Sena.
• Only port A can operate in mode 2. O ~ +3V to +25V

• The 8-bit data port (port A) can be either input or para IIe I ·· 1 ~ +5V
output. Both inputs and outputs are latched. a~ov
• The 5 bits from port C are used to provide control and
status for 8-bit data port. Voltage 1o ss is not much a problem in serial communicafion.
• ~~ . 1 transmission requires less number of wires thM
4 .8.2 Serial Interface /Serial Data Transmission
parallel and so cheaper to transmit data.
Within a microcomputer, data is transferred in paralle~
because that is the fastest way to do it. For transferring data over • Crosstalk is less of an issue because there are fewer
long distances, however, parallel data transmission requires too conductors compared to that of parallel cables.
many wires. Therefore, data to be sent long distances is usual)y Many ICs and peripherals have serial interfaces.
converted from parallel form to serial form so that it can be sent on
a single wire or pair of wires. Serial data received from a distant Clock skew between different cables is not an issue.
source is converted to parallel form so that it can easily bf Serials can be clocked at higher data rate.
transferred on the microcomputer buses.
Serial cable_ can be longer than parallel.
Serial Data Transmission
• Cheaper to implement.
In a serial data transmission, the data are sent one bit at a
Serial data systems may be simplex, half-duplex, and full-
over the transmission channel. However, since most proc
process data in parallel, the transmitter needs to tr duplex. A simplex data line can transmit data only in one direction
incoming parallel data into serial data and the receiver needs to (a commercial radio station is an example). Half-duplex
the opposite. transmission means that the communication can take place in
either direction between two systems, but can only occur in one
Computer A
10010110 direction at a time (an example is a two-way radio system, where
Transmitter Computer B
one user always listens while the other talks). The term "full-
-
~

Receiver
duplex" means that each system can send and receive data at the
.J
same time (a normal phone conversation is an example). Serial
Figure 4.35 Serial transmission data can be
sent synchronously or asynchronously.
In case of serial transmi · d .
bit • sswn, ata 1s sent in a serial form
by bit. on a single line. Also, the cost of communica 1. Serial Synchronous Data Transmission
hardware 1s considerably reduced . . .
channel is required for the . I since only a smgle wtre rec • In serial synch ronous data transm1sszon,
. . • transmitted or
data IS
. . . sena bit transmission Serial eivect b d f data
transnuss10n is slow as compared t II . ·. trans . ase on a clock signal. At a specific rate 0
0
para el transnuss10n. mission th b. t ch dock
Puls I ' e transmitting device sends a data It a ea .
Advantages of serial data transfe e. n orct . • · device
lltust k er to mterpret the data correctly, the receiving .
r over parallel:
• Longer data transmission m· s . lltust knnow the start and end of each data unit. The transnutther
ena 1mode 1
eceive ow the number of data units to be trans ferre d and .t e
1•S1GHrs ON M1C,o,""'5soR5- -- - _ ·----- r lllust b boundanes.
. _______
------- -e synchronized with the data

- -MIC-ROPROCESSOR SYSTEM
239
 Therefore there must be synchronization between the tr mmunication is used generally
~~ tw
'
and receiver. Usually one or more sync characters are lter
S1rfl
,won°usare co
co
nununicating to each other at a high
. .
When
speed
o
indicate the start of each synchronous data scream or frain used to
co·filPuters . is commurucatmg to the computer. 0r a
e of dat
d terJ11llla 1 .
uf{ere
Transmitter sends a large block of data characters a,
O b and disadvantages of
the other with no time between characters. Transmittingned aft.er vantages synchronous
sends data continuously to the receiving device. If the data 1ce t' M nication:
ornntU
ready to be transmitted, the line is held in marking conditio 8 not c . dvantage of synchronous data communicatio . h
lvfa!Il a . . n 1st e
. d.1ca te th e start of transm1ss10n,
m · · th e cransrrutter
· sends out n. To
. h spee • The synchronous commurucahons
d . require high- sr,ee d
more sync characters or a unique bit pattern called aone fl h1griphera 1s/ devices and a good-quality, high banctw·ctth 1
depending on the system being used. The receiving device w~ pe ·cation channel.
con1J1l!!Ill
for data, when it finds the sync characters or the flag then
. s The disadvantage includes the possible inaccuracy. Because
mterpreting the data which shifts the data following the
characters and converts them to parallel form so they can be whenar eceiver goes out of synchronization,
. loosing tracks of
in by a computer. . dividual characters begm and end, correction of errors
where ill
takes additional time. '
Clock
2. Serial Asynchronous Data Transmission
The receiving device does not need to be synchronized with
Transmitter
the transmitting device The transmitting device can send one or
Sync Sync
more data units when it is ready to send data. Each data urut must
be formatted i.e., must contain start and stop bits for indicating
Start
Time- beginning and the end of data unit. It also includes one parity bit
to identify odd or even parity of data. To send ASCII character, the
Figure 4.36 Synchronous sen·a1 transmission Jonnat
framing of data should contain:
·nt SJ:1cru:onous transmission has the advantage that the
1 start bit: Beginning of data
I ormation is accurately aligned to the received data allo
operation at much higher d t '
th . a a rates. It also has the advantage 7 or 8-bit character: Actual data transferred
e receiver cracks any clock drift h· h . .
d ue to temperature variation) Thew ic 1may. arise (for ms 1 parity bit: Parity
complex interfaces d . · pena ty 1s however a • 1 or 2 stop bits: End of data
· esign, and potentiall a
mterface to configure (since th y
options). ere are many hi h When no data is being sent, the signal line is in a con5tant
• g_ or marking state. The beginning of the data character is
Data transmission takes lac . ;"tard1catect by the line going low for 1-bit time and this bit is called a
adjacent characters. Howev ~ e_ Without any gap between
is a continuous stream 0 f her, ata is sent block by block. A bl oth t bit· The d ata bits. are then sent out on the hne · one after the.
er Where th 1 fi t Parity bit
fixed speed. We will f cd aracters or d a ta b·1t pattern coming a sh 0 1
u ct conta.
e east significant bit is sent out rs ·
. . Aft r the data
In a sync bit bit,nct In to check for errors m received data. e b"t
blocks of data and hence th pattern between any ~ a p · t I ast 1-
~ e data transm·1ss1on
. . synchroruzau.
--~ tilt\e to 1.d anty bit, the signal line is returned high for a _e b·t 1
I _ _ _ __
IGHTS ON IIIIICROPRocrsscis . .
1s
.- -- - - ·- - - - - teferrect entify the end of the character, this alwavs high 1 15
----to as a stop bit. Some older systems use 2 st op bits.
241
MICROPROCESSOR SYSTEM
 □
Marlang
Asynchronous SYnchronous
Start and stop bits Sync cha.racte

CLK-l] L ASCII ___J

r----Cbaractcrs
Time---.
~
Receiver

character.
.
are sent with each sent with
character.
rs are
eac
h

Hardware/ software Hardware

rrnp Ieinentation
Figure 4.37: Asynchronous serial transmission format 5
In asynchronous transmission, each character is transrnittl!(j · Synchronous Asynchronous Receiver
univers~I (USART) - 8251A
separately, that is one character at a time. The character (8-bits) ia nsnutter .
preceded by a start bit (I-bit), which tells the receiving end w1teze rra 82SlA is a programmable senal communication
the character coding begins, and is followed by a stop bit (1 or •
2 f Thechip d es1•gned for synchronous and . asynchronous
. serial
bits), which tells the receiver where the character coding ends, iJlter acemmuruca
. t·i on • As a peripheral device of a microcomputer
There will be intervals of ideal time on the channel shown as ga data parallel data from the CPU
5t co it receives
. . and. transmits serial
Thus there can be gaps between two adjacent characters in sy em,after conversi•on. This device also receives senal data from the
asynchronous communication scheme. In this scheme, the ·
data and transrm·ts parallel data to the CPU after conversion.
outside
within the character frame (including start, parity and stop bi
are sent at the baud rate.
Features of 8251A:
The start bit and stop bit including gaps allow the recei · Wide power supply voltage range from 3V to 6V
and sending computers to synchronize the data transmiss' Wide temperature range from -400 C to 850 C
Asynchronous communication is used when slow s
peripherals communicate with the computer. The Synchronous communication up to 64 Kbaud
disadvantage of asynchronous communication is slow s Asynchronous communication up to 38.4 Kbaud
1
transmission. Asynchronous communication however, does Transmitting/receivmg
• operations
• und er double buffered
requ~e the complex and costly hardware equipments as configuration.
required for synchronous transmission.
Error detection capability (parity, overrun, a nd framing)
Synchronous versus
transmission: asynchronous The functional block diagram
. of 8251A consists of five
serial
sections. They are:
S.N. Parameter
A&ynchronous Read/Write Control Logic
1. Fundamental
Transmission is not Transmission Transmitter
based on dock signal on dock signal Receiver
2. Data Format
One character at Data Bus Buffer
time
i.e., a Modem Control
3. Speed characters
Low(< 20 Kbps)
High (> 20 Kbps)

-- -------~-
------ - - - - _- ~ - - Ert
-- ~MICROPROCESSOR SYST riii
 o,. o. ..,,.,
1'r•••mlt

(P ➔ SI
Td) rra
·tter section
nsrn•
fhe tra
conver
nsmitter section accepts parallel data f
ts them into serial data.
ro111 CPU
anct

smitter section is double buffered i e •t h

fhe tran
Ti~y
' · ·, 1 as a buif
TtEMl'Ty . ter to hold an 8-bit parallel data and anoth . er
: - reg1s . er register
I
·I
0
ii
fie
ca ll e
d output register to convert the parallel dat . .
a Into senal
~ bits.

..,,.,
::
~
Re«I"• When output register is empty, the data is transferred &om
bD buffer to output register. Now the processor can again load
CP ._SJ
another data in buffer register.
lliiRDY If buffer register is empty, then TxRDY is goes high.
lie
SVNDIIT/
If output register is empty, then TxEMPTY goes high.
F" BIUr::Dl!T
tgure 4.38 Functional block diagram of 8251A-USART The clock signal TxC controls the rate at which the bits are
Read/Write Control Logic transmitted by the USART.
• The read/ write contr 11 . .
determines the fun ~ ogic mterfaces the 8251A with The clock frequency can be 1, 16 or 64 times the baud rate.
c mns of the 8251A
control word written. t ·t according to Receiver Section
m o I s control register
• It monitors the data flow. .
• The receiver section accepts serial data and converts them
• This section has three re ·sters into parallel data.
status register and data bgiufc and they are control regis
,er. • The receiver section is double buffered, i.e., it has an input
• The active low signals RD \YR register to receive serial data and convert to parallel, and a
used for read/wr·t . ' ' CS , and C/ D buffer register to hold the parallel data.
I e operations "th h
• -
When C/ D is high, the co
wi t ese three registers.
. When the RxD line goes low, the control logic assumes it as
writing control w d ntrol register is selected a start bit, waits for half a bit time, and samples the line
again.
- or or reading status word.
• When C/ D is l •
ow, the data b If the line is still low, then the input register accepts th e
read/write operation. uffer is selected following bits, forms a character and loads it into the buffer
• When the RESET is hi h .
register. '
• The clock input i
g , it forces 8251A .
mto the idle mode• The CPU reads the parallel data from the buffer regi 5ter.
.h s necessary fo
825 •
wit CPU and this clock d r IA for communication Wh_e n the input register loads a parallel data to buffer
transmission or the recept· oes not control either the serial register th Rx
ion rate. , e RDY line goes high.
• The cloc k signal
. -RxC controls the rate at w hich bits are
™~mns-oNMtcRoP-Ro-- - --
/ CESSORS rec·
----__:ived by the USART. __
--- - -------'72,s
- - MICROPROCESSOR svSTE•
/
 • During asynchronous mode, the signal SYNDET/B 10
. 1 •s changing every 3 ns, then
will indicate the break in the data transmission. Rl<DEy If s1gna t
• During synchronous mode, the signal SYNDET/B 1 3
will indicate the reception of synchronous character. Rl<DET 13aud ra te == -10 = 10 x109= 3x1Q8:: 300 Mbct
MODEM Control
3ns
• The MODEM control unit allows to interface a Moo
Not\ 1 frame of data is coded with. 1 bit, then baud rate and bit rate
8251A and to establish data commurucat· E.M to
MODEM over telephone lines. ion thro ugh ares am e· When frame . Qf dllta ant coded With two or more b·ts 1 ,
then baud rate and bit llOt laRle.
• This unit takes care of handshake signals
interface. in Serial 1/0
4, 10 Standards
4.9 Bit and Baud rate The serial I/O technique is commonly used to interface
different peripheral terminals such as printers, modems with
. The difference between bit rate and baud rate is c I" -
microcomputers which are designed and manufactured by various
and mtertwining. Both are dependent and inter-related. omp icated
manufacturers. Therefore, a common understanding must exist,
• Bit rate is how many data bits are transmitted per second. among various manufacturing and user groups that can ensure
• :oaud rat_e i~ the number of times per second a signal in a_ compatibility among different equipment. The standard is defined
mmun1cations channel changes. as the understanding which is accepted in industry and by users. A
Bit rates measu th standard is normally defined by professional organizations such as
transmitt d . re ~ number of data bits (that is O's and 1' IEEE (Institute of Electrical and Electronics Engineers), EIA
e m one second 10 a co . .
2400 b'ts mmurucation channel. A figure ol (Electronic Industries Association) as a de jure standard. However,
1 per second means 2400 zeros
in one second, hence the abbreviation ,, or ~~es c~~ be transmitfe4' a widespread practice can become a de facto standard.
(for example letters o be bps. Ind1v1dual characteJ:1t
, r num rs) th t I In serial 1/0, data can be transmitted as either current or
are composed of several b"tI S.
a are a so referred to as bytat,
voltage. When data are transmitted with current signal such for
A baud rate is the numbe . teletype equipment, 20 mA (or 60 mA) current loops are used.
communications channel h r of hmes a signal in a
2 c anges state · When a teletype is marking or at logic 1, current flows; when it is
400 baud rate means that th h or vanes. For example, Z'::
· e c annel can h at logic O(space), the current flow is interrupted. The advantage of
times per second. The term ,, h c ange states up to 240fl, th
change from 0 to 1 or fro 1 c ange state" means that it can e current loop method is that signals are relatively noise-free and
are · b
m to O up to X (' h suita le for transmission over a distance.
per second. It also refers to th m t is case, 2400) timelll
as voltage, frequency or ph elactuaJ state of the connection, such . When data are transmitted with voltage signal, th ere are
, ase eveI). various st d . .
The main difference betw an ards which are explained in this section.
~e can transmit one bit, or sli htl~ ~ t w o is · t h at one change of 1. RS-232C
depends on the modulation tec~y more or less than one bit, that
. a I transmission of data is used as an eff"icten
Seri · t means..for

~=lly
and baud rate (baud per second) ha~t ~sed. So, the bit rate (bps) tr
24 --- - . this connection· anslllittin d · . . . the ex1st.lllg

te::~SfEM ~,
con..- . g igital information across long diS tances,
6 INSIGHTS ON MICROPRocrsso-;;--- - - - - . - ~ - - - - - - ·•u11un1catio l" r can be used to
the

1
 RS-232C
tr ansfer information which saves a lot of hardware. RS-232c . Cable
MCl488 .
interface developed to standardize the interface between 1S d ii!) Transm11
2
. .
terminal equipment (DTE) and data commurucation equiPlllent <1ta
--9V
(DCE) employing serial binary data exchange. Modem and Other +J .4 V 9 V
o.2 v - + .
devices used to send serial data are call_ed data communic<1tion Receive J
equipment (DCE). The computers or terminals that are sending or Till l>CE
MCl489
receiving the data are called data terminal equipment (DTE). MCl488

_ _ _ _G_N_D ONO_ _ _ _..JGND

1 7 7 1--.;;.;...;
ON"D

Figure 4.40 Con nection of DTE and DCE through RS-232C interface

Figure 4.39 RS-232C DTE and DCE connector plugs MC1 4B8 line driver converts logic 1 to -9V, logic Oto +9V
RS-232C is the interface standard developed by electronic MC1 489 line receiver converts RS-232 to TTL
industries Association (EIA) in response to the need for the signat
Signa1 1ev els of RS-232 are not compatible
. with that
. of .the
and handshake standards between the DTE and DCE. RS-232C haa.c DTE and DCE which are 1TL signals for that !me dnver
following standardize features.
such as MCl488 and line receiver MC1489 are used.
• It uses 25 pins (DB - 25P) or 9 Pins (DE - 9P) standard w Table 4.3: RS-232C signals used in handshaking
9 pins standard does not use all signals i.e. data, cont:n4'
timing and ground. DE-9P DB-25P
• 1
It describes the voltage levels, impendence levels, rise Protective Ground
fall times, maximum bit rate and maximum capacitance 3 2 TxD
all signal lines. Transmitted Data
• 2 3 RxD Received Data
·It specifies that DTE connector should be male and
connector should be female.
7 4 RTS Re uest To Send ·
•
It can send data at 20kBd for a distance of ft.
• 50 8
The voltage level for RS-232 are: 5 CTS Clear To Send

- A logic high or 1 or mark, -3V to -lSV 6 6 DSR Data Set Read

- A logic low or Oor space, +3y to +]SV 5 7
• GND Si al Ground
Normally, ±12V voltage levels are used .
1 8 DCD Data Carrier Detect

4 20
9 22 RI
23 DSRD

MICROPROCESSOR SYSTEM
 Data terminaJ ready {DTR ): 23
After the terminal power is turned on and terzninal runs J!S-4 " Jem with RS-232C is that it can only"'"'"'"
any I A .,,jot prob t 50 ft at its maximum rate of 20Kbd. u long~
self checks, it asserts data terminal ready (DTR) signal to tel) the for abou h b dr ·
modem that it is ready. data reJiably d the transmission rate as to • e al astically reduced
. es are use . al lines with a common sign ground. Another
Data set ready {DSR ): jjJ1 to opend si~
doe . improvement over RS-232C is RS-423A. The
whic h is
When the MODEM is powered up and ready to translllit or f)A standar f tures of RS-423 are:
daed ea . .
receive data, it will assert data set ready (DSR ) to the terillinaI. standat 5 standard specifies a low impedance smgle-ended .signal
Thi . .
Under manual control or terminal contro1✓ modem then dials up be sent ove r 50 ,Q coaxial cable
. and partially ternunated
the computer. If the computer is available, it will send back which can_ .
ece1vmgen d to prevent reflection.
specified tone. at the r
Voltage levels:
Request to send (RTS ):
• Logic High: -4V to -6V
When a terminal has a character ready to send, it will assert
• Logic Low: 4V to 6V
a request-to-send (RTS) signal to the modem.
It allows a maxi·mum data rate of 100 Kbd over 40 ft line or a
Data carrier detect (DCD ):
maxunum
. bau d rate of 1 J<bd over 4000 ft line.
The modem will then assert its data-carrier-detect (DC.ii + 12V
+SV
signal to the terminal to indicate that it has established conn
with the computer. MC3C8IA
driver
Clear to send (CTS ):
mtogic
When the modem is fully ready to receive data, it asserts 4500
clear-to-send (CTS) signal back to the terminal.
Ring indicator (RI): RS-423
interface
4l!OQ -=-
It indicates that a ring has occurred at modem. Deactiv
-12V ~MC3488
DTR _o r DSR breaks the connection but RJ works independent1f -::-
3--
DTR 1.e., a modem may activate RI signal even if DTR is not ac · reoeiv•

Transmitted data (TxDJ: Figure 4.41 MC3488 driver and MC3486 receiver
. usedfor RS-423A
The terminal then sends serial data characters to the mo interface
Received data (RxD): Rs-422A
18
Modem wilJ receive data from terminal through this line. It . a newer standard for serial data transfer. It specifies
. that
· a
Data signaJ rate detect (DSRD):
each sivn 1 . tw ad1·acent wires l.ll
libbo o«a Will be sent differentially over O . am lifier to
r. n cable or a twisted pair of wires uses differential pthat the
It is used for switching different baud rate. ~ect noi ,..._ . dard means
si""-J se. • ne term differential in this stan . ther than
1•slGtm()N MICRoPftac~- · · ·
o<1e1 Volt
betw
.
age is developed between two Sign
. al Imes ra
een signal line and ground as in RS-232C and
RS-4Z3A. Any
- --

MICROPROCESSORSvsTEM l2s1
 . I 01se
. mduce
. d m. one signal line will be induced equ~i,
"'I}'
. II/O Standards
·electnca . 1 rme · A diffe,entIBI
n · s1gna
the other b line <eceiv.,.
. . !lfca,,,
uo f seria
responds only to th e vo ltage difference etween its. two Inputs so ar1s
. oil O 4 Comparison
. of serial J/0 standards
m
--r------

...,
cofllP Table 4. ---
. l that is induced equally on two mputs Will not 1
any noise
have vo tage
any effect on th e ou tput of the differential receiver. RS-232C RS-423A RS-422A1
100 Kbaud at 40 ft 10 Mbaud a
•' 1 Kbaud at 4000 ft 0 ft

I 0 ft 000 ft
100 Kbaud at
000 ft

--
+3 V to +15+4 Vto +6 V line> a line
Figure 4.42 MC3487 dn·ver and MC3486 receiver used for RS-422A in V
3 V to -15-4 V to -6 V a line > b line
RS-422A has foJiowing standardized features:
•

·-
Logic high is transmitted by making 'b' line more
than 'a' line.
•
Logic low is transmitted by making 'a' line more
than 'b' line.
o ingle
•
The voltage difference between the two lines must be
than 0.4V but less than 12V.
I··-': . . nded
input
• output

.II,.
The MC3487 driver provides a differential voltage of
2V. oise
• llUllunity
The center or common mode voltage on the lines
between -7V and +.7V.
KOhm>4KOhm >4KOhm
• I •. • •
Transmission rate is 10 MBd for 40 ft and 100 I<Bd for 2500
ft.

• The high data transfer is because of differential

functions as a fully terminated transmission line.
I. OOmA 150mA 50mA

• MC3486 receiver only responds to the differential

eliminating noise. 4·11 Introduction to Direct Memory Access (DMA) &
~rollers on.,;
--·r
co DUring
. any given bus cycle, one of the system
of thecomp
bus. Th.is
tlnected to the system bus is given control de and the
I • I • . I I . colllp . . that cy
<>nent ,s said to be the maste, dunng

-- - - - ~SYSTEM 53
· - - - -MICROPROCEISO
 . al ts
. a bus grant signal which indicates that
componen t 1•t 1s communicating with is said to be the slave• 'l"'l
'Ile
, rT pA
signsor h as indeed released control of its buses
fl...,
CPU with its bus control logic is normally the master, but Other fhe ·croproces t their high-impedance states.
specially designed components can gain control of the bus by ' ttie lJll . the buses a
sending a bus request to the CPU. After the curre~t bus cycle is bY pJacJ!lg . has a higher priority than the INTR or
OLD in~ut
completed the CPU will return a bus grant signal and the '[he I-I pt inputs.
component sending the request will become the master. r,rMiinterru

Taking control of the bus for a bus cycle is called cycle ste~ oata rra nsfer Scheme
Just like the bus control logic, a m~ster_ must be capa~l~ of pla~
addresses on the address bus and directing the bus activity dllling l
p~A t) mode o f data transfer:
bus cycle. The components capable of becoming masters - Block (bUCS. heme, the I/O device withdrawsd the DMA request
processors (and their bus ~ontrol . logic) . and _DMf\ c o ~ Jn thiS sc b tes have been transferre .
Sometimes a DMA controller IS associated with a single mterface, o~Y after all the data y
they are often designed to accommodate more than one interface.
aling technique:
This is a process where data is transferred between Cycle ste hi h b tes are divided into several parts and
peripherals directly without the involvement of scheme, t e Y · · b kt
Int f s . g every par t the control of buses 1s given ac o
microprocessor. This process employs the HOLD pin on
after trans ernnstolen b ack when MPU does not need it.
microprocessor. The external DMA controller sends a signal ~ MPU and later
HOLD pin to the microprocessor. The microprocessor co
the current operation and sends a signal on HLDA and stops
the buses. Once the DMA controller is done, it turns off the
Programma bl e OMA Controller - Intel 8257
_
,.....
1111
signal. and the microprocessor takes back control of the buses. CNTII

....,.
Basic DMA Operation
• DRQ,

The direct memory access (DMA) technique provides 11111

access to the memory while the microprocessor ....__

R-,
CNnl Dlll:K,

...,.
temporarily disabled. logic

• OR02
A DMA controller temporarily borrows the address • 11111

data bus, and control bus from the microprocessor N ca CNTII IS1leR,
tr~sfers the q.ata bytes directly between an 1/0 port anll e.
series of memory locations. DRO,
•
The DMAtransfers.
memory transfer is also used to do high-speed m e ~ IS1leR,

•
Two control si_gnals are used to request and acknowled.,e a
DMA transfer m the microprocessor-based system.
•
~e HOLD signal is a bus request signal which asks the
microprocessor to release control of the buses after tllt
current bus cycle. Figure 4,43 Functional block diagram of DMA controller .

254
-----
INSIGHTS ON MICROPROCESSO'Rnsr-~-----------
¾d
It is a device
. . ti between 1/0 device
to transfer the data d1rec Y
sPeedtndell)ory Without through the CPU. So it performs a
~~
high-

ri
.
"-------- ansfer between memory and 1/0 device.

------- - - - - MN:RoPROCESSOII Svsmi

 The features of 8257 are:
ddress d e coding circuit to interface an input
• The 8257 has four channels and so it can be us d an a •ght tn
·a1t
oeSlt,· . put switches and a LED output device
•
provide DMA to four I/O devices. e to
deVlce d 42fl respec tively.
. with et [2064 Shrawan]
• Each channel can be independently progranunable to 41fl an ·t
transfer up to 64kb of data by DMA. at
veco d"ng
1 Circu1 :
.4ddress A 7A 6AsAi A3A2A1Ao
• Each channel can be inde~endently perform l'l!li(
transfer, write transfer and verify transfer. J/0 Mapping . o1 oo o0 o1
Device (41H).
The functional blocks of 8257 as shown in Figure 4.43 ._ Input
t Device (42H):
o1 OO OO1 0
data bus buffer, read/write logic, control logic, priority reso
and four numbers of DMA channels. outpu used to enable the external decoder.
1 A2 to A7 are
B·t
Operation of8257 DMA Controller • d A 1 are used for the device selection (as an
• Bits Ao an d )
input to the external deco er .
• Each channel of 8257 has two programmable 16-bit re
named as address register and count register. Among t h eab o ve two address, Ao and A 1 bits decides,
.
• Address register is used to store the starting • whether t h e giv
. en device is input or output (1.e. for
memory location for DMA data transfer. selection of 1/0 device).
• The address in the address register is auto
D, Input tn-state
incremented after every read/write/verify transfer.
D.
• The count register is used to count the number of Do cs
buffer (60H)

iOR
word transferred by DMA.
~ wooden block for
• A1
2• 4
01
shielding

active 10
• In Write transfer the data is transferred from J/0 d Ao
low
II
memory. decoder D, Output Lactch
Do (61 H)
• Verifica tion operations generate the DMA addresses wi Do EN iow
generating the DMA memory and I/O control signals. +Vee
• The 8257 has two eight bit registers called mode set
and status register.

Fig.: Address decoding circuit

Desio-n . . t rface two RAM
bJ o<• an address decoding circuit to in e • address

MIC.~·- r
4oocks and a ROM block each of 4 KB starting at h·

----- -
ooa. [2064 Pous '11
 and A 13 are used for RAMs and ROM
Address Decoding Circuit: bl
·t temal decoder), bit A14 and A are
1-; to ex
A12
15
RAM (4KB): f{ellc~, (as an P
seJeetton ble externa1 device and bit Ao to Au are given to
d wena ROM.
Base Address = 4000H use ~ A ~A's and o o
f~•• 0 l

End Address = Base Address + (Number of locations in .i(B

RAM-1) 4
10° !. . . . . . . .,!
= 4000H + (1024X4-l)D J/P Buffer

= 4000H + OFFFH 4FFFH

l1J
=4FFFH D RAMI
RAM2(4KB) i,,
4000H
O/P Buffer
Base Address = End Address of RAM 1 + 1 00

= 4FFFH + 0001H Au

=S000H 2•4 01
active
b1gh
End Address = Base Address +(Number of locations in flCI decoder
10
RAM-1)
SFFFH
A12
= 5000H+0FFFH
=SFFFH
ROM (4KB)

Base Address = End Address of ROM +1

= SFFFH + 0001H Do 0,
= 6000H

End Address = Base Address+ (Number of location in 4

RAM-1)
IL
6FFFH
Au
6000H + OFFFH
=6FFFH
RAM 1(4KB) A15A,-AuAu
,--. ........... Ao ROM
Base Address (4000) :j o 1 '0 oj AuA10A.Aa
A,AoA,A. D
End Address (4FFFH): j O 1 lo Oj 0 0 0 0
0 0 0 0
AtA,A,.A,

0000
cs 6000H
RAM 2 (4KB) • , i 1 1 1 1
1 1 1 1 1 1 1 1
Base Address (SOOOH),! 0 1 O 1;
End Address (SFFFH): / 0 1 °0 1 f 0 0 0 0
0 0 0 0 0000 0,
Do
ROM (4KB)
I 1 1 1 1
1 1 1 1 1 1 1 1
Base Address (6000HJ4
1 1 0/
' Fig.: Address decoding circuit h
End Address (6FFFH): j 0 0 0 0
1 1 oi 0 0 0 0 0000 Present a complete plan to use 2 RAM chi P 8 of 16 KB
·-- ········• 1 1 1 1 . r} eac
With 8085 lll1croprocessor.
1 1 1 1 1 1 11 • [2065 Cha1tra
258
-·-
INSIGHTS ON MICR~tQlp;;;;R;;O;CE;:SSo:::-R::S::--------------
th
Let e starting address be 4000H

--------M-IC:::-:RO::::::PR;;;.OCE~SSORUt']ilUSYSTEII
-
 RAMl (16KB)
Base Address = OOOOH
At
End Address = Base Address + (number of locations in l<B A15 3FFFH
RAM-1) 16
= OOOOH + (16 X 210 -l)D Ao RAMl
D
= ODDOH + (16384-l)D cs
= ODDDH + 16383D l" 2 OOOOH
O'PBuffer
=3FFFH Active ....................
A1
RAM2 (16 KB) High
~ D7
Base Address = End Address of RAM 1 +1 l)ecOder
= 3FFFH + OOO1H
=40DOH
End Address= 4OOOH + (16 X 210 -l)D ~ D7
~
= 7FFFH

At
RAM1(16KB) 7FFFH
A1SA14A13Au AuAwAeAe A1AeAe"4 AeAzAtAa
Base Address:(OOOOH)
I Tr · • •································································-- MEMW
ioioioo 0000 0000 oooe
End Address: (3FFFH)
j OjOj1 1 1111 1111 1 1 1- 4000H
RAM2 (16KB)

Base Address: (4000H)

j i.. J.. ..
bit Ao. to.A13 are given. to. ID.of '":

End Address :( 7FFFH)

i~ b1 0
0000 0000
ioi1i11 1111 1111 Fig.: Address decoding circuit
;__;.1-...........................................................................
bit Ao to A13 are given to ID of RAM2 Design a unique address decod ing
. cu ddre
• c:uit using memory
mapped J/0 interface to read input from port a . •8
FFF9H and output port address FFF8H. [2067 Mangs,r]
A
Hence, bit A14 is used for RAM selection (as an input rnong the above two addresses, ~ b it . d ea·des whether the
external decoder) and bit A 15 is used to enable e
given
· device is 1/P or 0/P (i.e., for selection°
• f mp
· ut/output
device and bits Ao to A13 to Internal Decoder(ID) of device)
and bits Ao to A13 to ID of RAM 2.

260 INSIGHTS ON IIIIICROPROCESSORS

MICROPROCESSOR SYSTEM 2f1

 ... eJJlory and J/0 read/write· instructions u
sos5, ... d se extr
J.t! • cycle for memory an 1/0 read write O • a
0, chine f perati on
JJla ti'Jlle diagram or MOV R, M and OUT ·
+5V D6 the OU!
use . ns to illustrate the statement. {2067 Ma .J
Do instrtlc0 o ngsir

0
fotr.-fOVR,M
Jx 2
Ao
ff : opcode of MOV R, M
acti~ 2050
low +Vee

decoder 0, r-Oitput~-1.a-tch- Instruction MOV R, M

0. (FFFSH)
Opcode Fetch (M1) Memory Read (M ~
Do iiiM,;

IO'M MiMii

>
Ri5

A15-A,
I
~ : 20➔
I I I
:
I
~
I I
1
I
:
I

AD,-AD,~-e~------f0---®i
Fig.: Address decoding circuit
5. Draw the bus timing dia am .
34H is executed. gr when the instruction
2060H : opcode of ADI [2067 Shrawan] : : :
2061H : 34H

Instruction ADI 34H

ALE _n h'-!--~
Opoode Fetch (M,)
I Memory Read (Mz)
\"----~'r.:'
~
RDl - " " T -...... I

Ti I T2 I T3 I T4 I T1 I T2 I T3
: : : ''
\ /
-V : ' WR j,r-+---+--:--_;__..;....-~,--~
ADrADo± ! 20~
, ,
:
· ....;I\. ;20H , 1'
A,s-A8~-e:
:
:
:
,
-1"C:/ Opcode ·······f./wj\
I
i
:
~ .
'-=.:/•••~
:
'
: : : : :

I
IO/M 1\-.. ~-~--4--...:--~-+----,~
ALE-hi ;
! / ~;
--; - I :
! !
; Fig.: Timing diagram
I

'
'
I
~-- . .'
.
:
t i

WR _f,- I
IOIM : :
T'-;:i-t-+-;__.i_;_JI'
2&2!~:::-:::-----F.~ig:·~:Timinuo d'1agram
: 262 INStGHTso N MICROPRoc=E_SS_O_R_S_ _ _ _ _ _ _ _ _ _ __

MICROPROCESSOR svsTEII
 ForOUT0lH

2050H : opcode of OUT (D3) --- -1-

2051H: 0lH i,,:-

_.___ - J!
......._ ....,
_--
~-OUT
T,
.. ,to,c-~,
T, T, T,
I
T, T, lltC, Cl,'() ...--;;;;---_
1
~
!f
I Ju,-,.,.1
T, T,
.... T, r-;- ~ ~· i
'°" 10.
I r--'-
r,:-- i
~ «
" ..... V

C ------
:c:
I "'" "-" o'" }- ~- --
fE D---{ 8--~ ) ~. .,: II

n
r\ \
\
n n - .,:
>< -r-
_L
i
~

--
J l
1111
~ n
I/
I I~· :c:
~J l l-\ I I Ill I ....._ ~ rr
R r i'
'\ I ~
►
I
::c
I >-c "-r" C
-
iiE

~
I,\
.:· t
;:>
I
I
I
I

7.
Draw the bus tinu•
.
d.
ng 1agram
Fig.: Timing diagram
lo\

J.,;
>-c

!
I
_l.
,. - ..__

instruction is at location 8256H.

8 256 : opcode of IN
for IN 86H when the
[2068 Jestha] l .=·
':i. iii
J
8257: 86H .... r-"C ~

I
►
:-- =-- C r-- "'

Fig.: Timing diiigram

8. .
Draw the timing diagram of the 8085 111structi on STA
8050ft. [2073 Bhadra]
COOOH: Opcode
COOlH:SOH
C002H:80H
264 INSIGHTS ON MICROPIIOCE5SORS
 a culate the time taken to execute the foll owmg
. progr
C l
9, ii 1' == 1 Jllicro second. am

J\,{VI A, 05H
_AOJ20H
oursoH [20 72 Magh}
}IL1' Clocks
1'-States

,-, -- JnstrUctions
MVIA,05H;
7
7
7xl
7xl

..
_:__
- ADI, 20H;
oUTB0H;
HLT;
10
5
l0xl
Sxl
Total Clocks: 29
li1
J? If T = 1 micro second, time taken to execute the program =
29 micro seconds.

i ''", -, 10.
Draw the timing diagram of LXI D, 2465H. Calculate the
lf. ... - time required to execute this instruction if the crystal
. frequency is 6 MHz. [2073 Magh}
Assume that this instruction LXI 0, 2465H is located in
memory address COO0H.
C000H : opcode (LXI D)
C00lH : 65H
C002H :24H
The timing diagram of LXI D, 2465 H showing the flow of
address/ data at different T-states is shown below.

2061
INSIGHTS ON MICROPROCESSOR$
--
------ MICROPROCESSOR sVl'f&II
 Opcode Fetch (M1)
Memory Read (M2) Memory Read <Mi)

CLK

ALE

RD

WR ' ' '

10;-M ; ; : '
, ;
.1.,.~:; ---.---=,----:x
s0, s I·=x::::,.,,:0:. o.o., '
I X-----:-i_o._0.1_,/_....
'
LOA =Low Order Address
HOA =Hlgh Order Address
Fig.: Timing diagram
As per the RTL and timing diagram, LXI D uses 10 cl
cycles, and crystal frequency is 6 MHz.

Time required to execute 1 dock cycle : 1 / 6XlQ-6

Hence, time required to execute 10 dock cycles
=10 / 6X1Q·h 1.66 µs

11. An instruction is stored at memory location as follows:

Memory Location
Hex Code
2050
3A (op-code)
2051
80
2052
20
. d',a.,oram
Fig.: Timing ..
This instruction loads the content of memory location 2080
into accumulator. Draw timing diagram of this instruction.
The instruction is LOA 2080H.
•••
-2-6"'8/
.'"T- ,N-S-IG_H
_T
_S_O~N~M::I.C.:R_O~~~-----------
 .i... ; is a very wasteful use of the process So .
I" uuS or. mt
aear 1 1 • Iarly useful when interfacing I/0 devic h errupts
arncu es t at pr .
Chapter_, are P . data at relatively low data transfer rate ovide
orrequrre . ·
·th interrupts, the processor can be engaged .
WI m executin
INTERRUPT OPERATIONS -- other !fl
.

d
.
. strUctions while an 1/0 operation is in pro g
gress. The
t is a process of ata transfer whereby an exte al d .
i)lterruP . m ev1ce
5.1 Introduction eripheral can inform the processor that it is re d f
or a P . . a y or
Virtually all computers provide a mechanism b - - - - unication . and 1t requests attention. The response t
coJlll!l . . o an
other modules (I/ 0 , memory) may interrupt th y Which i)lterrupt request 1s directed or controlled by the microprocessor.
processing of the processor. Interrupt is signal send b e norinal
d · h Y an extern ..., _ Polling versus Interrupt
evI_ce to t e processor, to request the processor to """ 52
particular task or work. Table 5.1 lists the most co perform a The interrupt process allows the microprocessor to respond
interrupts. mmon classes
to external requests for attention or service on a demand basis and
Table 5.1: Classes of interrupts leaves the microprocessor free to perform other tasks. On the other
Programs hand, in the polled or status check 1/0, the microprocessor
Generated by some condition th t
result f • . a occurs as a remains in a loop doing nothing, until the device is ready for data
. o an mstruct10n execution, such
anthmetic overflow' diVISion
· · by zero attempt as transfer.
t
execute an illegal machin . ' . o
e instruction, and
reference outside a user's allowed
• Each time the device is given a command, for example
" move the read head to sector 42 of the floppy disk'' the device
memory space.
Timer driver has a choice as to how it finds out that the command
Generated by a timer withi h
perform certain functi n t e processor to has completed. The device drivers can either poll the device
ons on a regular basis. or they can use interrupts.
J/0 Generated by 1/0
co . an controller, to signal normal
mplehon of an operation or to . .
• Polling the device usually means reading its status register
every so often until the device's status changes to indicate
of error conditions. signal a vanety
that it has completed the request.
Hardware
Failure
Generated by a fail
memory par·t ure, such as power failure or • Polling means the CPU keeps checking a flag to indicate if
I Yerror. something happens.
~ terrupts are provided r·
processmg efficiency Fo
.
p unarily as a way to imp
• An interrupt driven device driver is one where the hardware
· r example device being controlled will cause a hardware interrupt to
slower than the , most external devices are mu
. processor. Su os occur whenever it needs to be serviced.
transferrmg data to . PP e that the processor .
d. . a printer usin
15cussed m the previous h
h .
g t e mstruction rvcle
• With interrupt, CPU is free to do other things, and when
• tify the
c apter Aft -✓ something happens, an interrupt is generated to no
processor must pause and . ·. er each write operation, th
Th 1 remam Idle ·1 CPU. So it means the CPU does not need to check the flag.
e ength of this pause m be unh the printer catches up,
even thousands of instr t~y on the order of many hundreds or
• • like picking up your phone every few seconds to
Polling is
uc Ion cycles th see 1·f ·ting for the
at do not involve memory. you have a call. Interrupts are like wai
Phone to ring.
270 INSIGHTS ON MICROPROC
ESSORS

INTERRUPT OPE ~I
 • Interrupts win if processor has other work to do . which the routine polls each device Th
order Jll . . h h hi . . e processor
·
response time · not en·ti' ca1.
1s ctnd event ,,~ the startmg wit t e ghest priority de .
chec~ . vice. Once it
-;nes the source of the mterrupt it bran h
• Polling can be better if processor has to respond to deter., ..... · .
. routine for that device.
' c es to the
ASAP; may be used in device controller th an event service
dedicated secondary processor. at contains
Pollin
Advantages of interrupt over polling:
• Interrupts are used when we need the fastest
response t0
event.
. For. example, we need to generate a series. of an
usmg a timer. The timer generates an . PUises Microprocessor
interrupt h Device I Device 2 • • • • Device n
overflows and within 1 or 2 sec, the interrupt . w en it
. all service ro .
is c ed to generate the pulse. If poll' Utine INTRt---_.......,__ _ __.__ _ _ __j
d 1 mg were used the 1_ _ _ _ _...,
e ay would depend on how often the poll ' . , Figure 5.1: Polled interrupt
could delay response to several rnsecs Thimg_ is done and
times slower. · s IS thousanda
Here several eternal devices are connected to a single
• Interrupts are used to save power consum t· interrupt line (INTR) of the microprocessor. When INTR
battery powered applications the . p 10n. In many signal goes up, the processor saves the contents of PC and
I , rmcrocontroll •
s eep by stopping all the clocks and ~r IS put to other registers and then branches to an address defined by
consumption to a few micro am s reduc~g power the manufactures of the processor. The user can write a
the controller from sle p . Interrupts will awaken program at this address to find the source of the interrupt by
ep to consume
needed. Applications of thi h power only whe starting the polled from highest priority device.
s are and held d ·
TV/vCR remote control!ers. ev1ces such
5.3.2 Daisy chain (vectored) interrupt
• Interrupts can be a far more efficie
are used for program d b . nt way to code. Interrup In polled interrupt, the time required to poll each device
e uggmg. may exceed the time to service the device through software.
5.3 Interrupt Structures To improve this, the faster mechanism called vectored or
daisy chain interrupt is used. Here the devices are connected
A processor is usually .
· on the chip. The f
pms provide d wit
· h one or more interrupt in chain fashion. This configuration is governed by the
h . re ore a spe .al . . priority of the devices. The device with the highest priority
andle mterrupts from c1 mechanism is necessary tQ
interru t i- several devices th is placed first followed by the second highest priority device
P mes. There are main} at share one of these
polled interrupts and daisy h . y two ways of servicing interrupts: and so on. When INTR pin goes up, the processor saves its
c am (vectored) interrupts th
current status and then generates INT A signal to e
S.3.1 Polled Interrupts · th
higheSt priority device. If this device has generated e
Polled interrupts · · · ill ush
l are hand! d b interrupt, it will accept the INTA; otherwise it w__!'....
s ower than hardware . e Y using software and is ~ . JNTAis
g enera l (common) • Interrupts. Here the processor' has the TA to the next priority device until the
d . Interrupt s . accepted by the interrupting device.
ev1ces. TI1e priority f erv1ce routine (ISR) for all
rNSIGHTS o.
-- 0 the d ·
272 M - ev,ces is det&mined by tire
ICROPRocess~ -----
 ssor loads the program counter with th
When INTA is accepted, the device provides a m '[he pro Ce e entry
. eans to the . of the interrupt-handler program that will res d
processor for findings the mterrupt address vect 1oeatton h pon to
or us· . terrupt that is, t e control is transferred t h
external hardware. The accepted device responds b U\g t}us in ' ot e
t-handler program.
a word on the data lines w hi ch becomes the vecto Y Placing i,nterruP
r add
with the help of any hardware through which the ress At this point, the PC and PSW relating to the interrupted
. . d . . processor
points to appropnate ev1ce service routine. Here no program have been saved on the system stack. However, m •
interrupt service routine need first that means appr!en~ra} addition, the contents o~ the processor registers need to be
ISR of the device will be called. Pnate saved, because these registers may be used by the interrupt-
handler. Typically, the interrupt handler will begin by
saving the contents of all registers on the stack. Now, the PC
Microprocessor
is updated to point to the beginning oi the interrupt service
routine.

Do-D7 The interrupt handler may now proceed to process the

~-----:_..:..__ _ _ _ _--J Vector Generating interrupt. This will include an examination of status
Hardware
Figure 5.2: Vectored (daisy chain) interrupt information relating to the 1/0 operation or other event that
caused an interrupt. It may also involve sending additional
5.4 Interrupt Processing Sequence commands or acknowledgements to the 1/0 device .
. The occurrence of an interrupt triggers a number of ev When interrupt processing is complete, the saved register
both in the processor hardware and in softw Th . values are retrieved from the stack and restored to the
d . I/ ~ e~
nven O operation takes the following steps: registers.
• The I/0 · ·
exchange :i~~::~:s::e::;;~t signal to the processor • Finally, the PSW and PC values are restored from the stack.
As a result, the next instruction to be executed will be from
• !~e processor .finishes execution of the current instru previously interrupted program.
e ore responding to the interrupt.
• Main Line
Program
Interrupt Service Routine
: p; ~e::~~:ests forknan interrupt, determines that there
an ac owledge t · . Push Flags
that issued the • t men s1gna1 to the de Push Registers
in errupt.
Fetch ISR Address
• The processor now needs
the requested routin to prepare to transfer control
II
begin, it needs to s e ca .ed interrupt seroice routine (ISR).
~urrent program at~~: inf~rmati~n needed to resume
information required is tomt of interrupt. The minim Pop Registers
the location of th ~e program status word (PSW) Pop Flags
. e next mstru ti. . •
contamed in the p c on be executed, which
rograrn cou t (P Return from !SR
and PC are pushed ont0 th n er C). The contents of
e stack.
Figure 5.3: Interrupt processing
~ IGHrs ONMICRoPR-o - •:::-:_---_
I CESSORS
 . IRP
The figure summa rizes these steps. The processor
. pushes the
.
flag register on th e stack' disables the INTR. mput and does
. 1y an m
essential . d ire
. ct call to the interrupt service
. procedure.
. "-
'vt
IRET fu nction
. a t the end of interrupt service procedure retu,-,..-
,,.,, IRET
execution to the main program. IRP
55 Multiple Interrupts and Priorities
~·~~~~:.:::::.:.:..::.:.!__ _ _~ : - - ~ - - - - - -
u to this point, we have discussed about the occurrence of a
single ~errupt. Suppose, however, that multiple interrupts can
occur. For example, a program may be receiving data from a Figure 5.4 Sequential interrupt seroice
communications line and printing results. The printer will generate
an interrupt every time it completes a print operation. 11w . "tywise processing of intenupts
Pnon
communication line controller will generate an interrupt ev The drawb ac k o f sequential processing. is .that
. it does not
time a unit of data arrives. It is possible for a commurucati t f relative priority or time cnhcal needs. The
take accoun o . .. .
interrupt to occur while a printer interrupt is being processed. alternative
. form of this is to define pnonhes for interrupts
Two approaches can be taken to dealing with mul · d t ll ow an interrupt of higher priority to cause a lower
an oa .. ·t t
interrupts. The first approach is to disable interrupts while priority interrupts pause until high pnonty m errup
interrupt is being processed. A disabled interrupts simply completes its function.
that the processor can and will ignore any new interrupt 'req
IRP3 IRP2 IRPI
signal. But this does not take into account of relative priority
time-critical needs. For example, when input arrives from
communications line, it may need to be absorbed rapidly to
room for more input. If the first batch of input has not
processed before the second batch arrives, data may be
because the buffer on the I/O device may fill and over
Therefore, another mechanism has to be implemented - se
approach. If the processor gets multiple interrupts, then we need Figure 5.5: Prioritywise interrupt service
deal these interrupts one at a time and the dealing approaches Interrupt Service Routine
1.
Sequential processing of interrupts
An interrupt seroice routine (ISR) 15 xaminethat
. a software routine an
When user program is executing and an interrupt ~ardware invokes in response to an interrupt. ISRs ~die the
interrupts are disabled immediately. After the inte ~lerrupt and determine how to handle it. ISRs entral
service routine completes, interrupts are enabled llllerru . . te pt value. Its c
Pt, and then return a logical m rru trol to the
resu~~g the user program and the processor checks to Purpo 1. d th return con
. se s to process the interrupt an en •d lowing
if additional interrupts have occurred.
drnalil Program.
th An ISR must perform very f a st to avo1f alls lower
~\Vn e operation of the device and the operati~n
Priority 18 . truction m
°.
an JSR
sh Rs. As in procedures, the last ms
ouJct be IREr.
_2_7_6-.---IN_S_IG_H_T_
S 0-N-MICRoPRO-:
CE::-:S:-
S-0 -RS_ _ _ _ _ _ _ _ _ __
 d Non-Maskable Interrupts
1<able an
. respons1·bJe for doing the following things:
!SR 1s Mas . t rrupts are those which can be enabled or
1. Saving the processor context
kable in e b . .
},1as b the microprocessor y executing instructions
Because the ISR and main ~r~~am use the same processor disabled 1 y d DI. These interrupts are either edge-triggered
registers, it is the respons1bil~ty . of the ISR to save the such as E .anered so they can be disabled. INTR, RST 7 5
vel-trigg ' ·'
processor's registers before begmmng _any processing of the or le 5 RST 5.5 are maskable interrupts in 8085
RST 6. I
interrupt. The processor context consists of the instruction
Jllicroprocessor.
pointer, registers, and any flags. Some processors perfol'Il\
ble interrupts are those which cannot be enabled or
this step automatica!Iy. Non-mas ka . . .
.
d1sab1e d by microprocessor by executing
. instructions. TRAP
2. Acknowledging the interrupt
is a non-maskable interru~t. It co~ists ~~ both level as _well
The ISR must clear the existing interrupt, which is d as edge triggering and 1s used m cntical power fa!lure
either in the peripheral that generated the interrupt, in
conditions.
interrupt contro!Ier, or both.
Vectored and Non-Vectored Interrupts
3. Restoring the processor context
Vectored interrupts are those which have fixed vector address
After interrupt processing, in order to resume the
(starting address of sub-routine) and after executing these,
program, the values that were saved prior to the
program control is transferred to that address.
execution must be restored. Some processors perform
step automatically. Non-vectored interrupts are those in which vector address is
not predefined. The interrupting device gives the address of
5.6 Interrupts Types sub-routine for these interrupts. INTR is the non-vectored
In differentiation with the occurrence of interrupts, they interrupt.
be classified into various categories based on different param 4. External and Internal Interrupts
1. Hardware and Software Interrupts . . a computer sys te m interrupt that
An external interrupt is ,
. When microprocessors receive interrupt signals t happens as a result of outside. .
inter ference, whether that s
~ms (hardware) of microprocessor, they are known as har, from the user, from peripherals, fr om 0 ther hardware
interrupts. There are 5 hardware interrupts in 8085 micropr devices or through a network.
~amely INTR, RSI 7.5, RSI 6.5, RSI 5.5, TRAP; and 2 hard . . . type Of interrupt thatti· isn
mterrupts in 8086 microprocessor namely NMI and INTR. An internal interrupt is a specific
· the execu 0
caused by instructions embed d e d m . al
Software interrupts are those which are inserted in be .
instructions of a program or process. Typically' intern ," or
the program which h 11
means t ese are mnemonics of microp
There are 8 softwar · t .
•
interrupts resist changes by users, and h appen "natura \ gram
e m errupts m 8085 microprocessor "automatically" as a processor works thro~gh pro ts or
~~~L ~t~a~~~~~6~7~
software mterrupts · 8 086 . '
. b
instructions, rather than being caused Y ex .
ternal even
Hy by
FFH. m nucroprocessor namely INT OOH to netw ork connections. These are m . d"ica ted mtema and
. d"vide by zero,
exceptional conditions such as overflow, 1 writes a
execution of illegal op-code. The user usuadyt 11 provide
278 INSIGHTS ON MIC.;.RO~P~R::o=c=Es=-=so~RS_ _ _ _ _ _ _ _ _ _ __
service
· routine to take correction meas ures an °
279
------------:::,N;;:;TE;,;;R;;RU;-;;,.PT OPERATIONS
 . program. These types of interrupts wh
rnaJll ere
an indica tion in order to inform the user that e the . ns cause interrupt requests are known as softw
xcepti 0 jrlStructIO are
condition has occurred. na1
jrlterrupts.

----
5. 7 In terrupts in 8085 are Interrupts
Jiardw
The 8085 mterrupt process can be described as follows :
z. INs on the 8085 allow peripheral devices to interrupt
some P .
I. The interrupt process should be enabled using instr .
the main program for 1/ 0 operati~ns. ~en an interrupt
which sets the interrupt enable flip-flop. The instruu~~Ion Er 8085 completes the execution of instruction it is
occur 5,
resets the flip-flop and disables the interrupt process. c Ion DI currently executing and transfers the program control to an
2. When the microprocessor is executing a program ·t interrupt service routine that services the peripheral devices.
IN . . . ' I checks tlra Upon completion of the service routine, execution returns to
TR !me dunng the execut10n of each instruction at the nd -:"j:
2 the main program. These types of interrupts where MPU
state of last machine cycle. T.
PINs are used to receive interrupt requests are known as
3. If .the line INTR is high and the interrupt Is
· enabled
nucroprocessor completes the current instr t · ' hardware interrupts.
h . uc 10n, disab
t e interrup t enable flip-flop, and sends an in
software Interrupts
acknowledge signal ( INTA ).
The 8085 has eight software interrupts from RST Oto RST 7.
4. The program control is transferred to the . t The vector address for these interrupts can be calculated as
tin 1nerru~
rou e (JSR). Now the processor saves the follows.
address of the next instruction and the contents of reme· Interrupt number >< 8 = vector address
on the stack.
For example, 5 >< 8 = 40 = 28H
5. The ~rocessor services the interrupt usin interru t
routine. At the end of th b . g P Vector address for interrupt RST 5.5 is 0028H
. e su routine, the RET ins •
retrieves the m d Table 5.9 shows the vector addresses of all interrupts.
. t emory a dress where the program
rn errupted and continues the execution. Table 5.9: Vector addresses/or software interrupts
Types of8085 Interrupts
Instruction Hexcode Vector Address
The 8085 microprocessor h .
supports two types f . as multilevel interrupt sy RSTO C7H 0000H
. o interrupts· ha d .
interrupts. · r ware interrupts and so RSTl CFH 0008H
I. Software Interrupts RST2 D7H 0010H
8085 allows some s ecial . . RST3 DFH 0018H
program Aft p . instructions to interrupt the
· er executin th .
the execution of . g. ese instructions, 8085 c RST4 E7H 0020H
instruction I·t •
transfers the progr Is currently executing ~RST5
am control t • EFH 0028H
Upon completion of the se . o an interrupt service rou
rvice routine, execution returns ~RST6 F7H 0030H
280 RST7 FFH 0038H -
INSIGHTS ON MICROPRO CESSORS
~ ~ : : - - - - - - - - - - - - - -~
211
INTERRUPT OPERATIONS
 pis general ly used for critical events such as
. EL rRA d emergency shut-off
Hardware Interrupts cllOJl f ilure an
Jl1ltfll power a TRAP interrupt.
The 8085 has five hardware interrupts. 0JJell s to clear .
Table S.10 8085 hardware interrupts sfltere are f:WO way nucroprocessor that is by giving low signal on
resetting 1) .
S.N. Interrupt Trigger Priority Maskable Vector 1. l l ~ . N (external signa ·
R£SETI .
Address . h TRAP acknowledge (internal signal).
1s1 •ving a h1g
1 TRAP Edge No 2. lly gi
and
Level ncf 7,5 . skable vectored interrupt. It has
"" 5 . terrupt is a ma d b
2 RST7.5 Edge 2nd Yes The RST 7. rn . I . ositive edge sensitive an can e
t priority t 15 P d d
3rd
the second highes uls~ that is input goes to high an none~
3 RST6.5 Level Yes
·ggered with a short p fl ·t recognize . d . It can be enabled with
4 RST 5.5 Level 4th Yes trt ·ntain high state un 1 1 t) and SIM (Set Interrupt
to mat El (Enable lnterrup 1.
5 INTR Level 5th Yes two
mstructions . .
his interrupt is tr1ggere '
d the program contro 1s
Mask). When t
When any of these PINs except INTR is active, the · transferred to location 003CH.
control circuit of 8085 produces a CALL to a predet
RST 7.5 can be disabled by
memory location. This memory location, where the service
starts is referred to as vector_ed location and such interrupts 1. Using DI instruction.
known as vectored interrupts. The INTR is not a ¥ 2. System or processor reset.
interrupt, it receives the address of ISR from the external devi
3. After reorganization of interrupt.
In 8085, all interrupts except TRAP are maskable.
logic signal is applied to a maskable interrupt input, the RST 6.5 and RST 5.5
interrupted only if that particular input is enabled. maskable vectored
interrupts can be enabled or disabled under program con The RST 6.5 and RST 5.5 both are h RST 5.5
. d · rity whereas t e
disabled, 8085 disables an interrupt request. The interrupt interrupts. The RST 6.5 has the thir pn~ ered that is input goes
non-maskable that means it is under program control. has the fourth priority. These are level trigg b bled with
. d · Itcan eena
to high and stay high until it is recogruze (Set Interrupt
TRAP
two instructions EI (Enable Interrupt) a nd SIM control is
M . tr1ggere
· d ' the program
This interrupt is a non-maskable vectored interrupt, ask). When RST 6 5 interrupt 1s . t rrupt is
unaffected by any mask or interrupt enable. TRAP has the .
transferred to location 0034H and when RST 65 : me002CH
priority and is edge and level triggered. This means that the triggered, the program control is trans ferred to location
must go high and remain high until it is acknowledged. It
They can be disabled by
be acknowledged again until it makes a transition from high flit
to high. This avoids false triggering caused by noise and tr l. By using DI or SIM instructions.
When this interrupt is triggered, the program control is tr 2.
System or processor reset.
to location 0024H without an external hardware or interrupt 3
· After reorganization of interrupt.
282 INSIGHTS ON MICROPROCESSORS

------------ - - - - - · - - -- -
-·-------=:ON5-r·3
- INTERRUPT OPERATI
 t,le Jnterrupt)
61 (f:ita t·on sets the interrupt enable flip-flop. Thus
INTR
in5tfUC 1
file El R5T _5, RST 5.5 and I_NTR are enabled using EI
. is a maskable non-vectored m
The .INTR · terrupt. I 6
lowest pnon ty. It can be enabled by EI (E b t has th e ¢'f 7.S'. When any interrupt 1s acknowledged or system
• . . na le In
im,trucbon. It 1s a level triggered interrupt that . .
high and it is necessary to maintain high state
. --
un: terrupt)
~put goes to
it recoo-n;
j(IStructton- pt enable flip-flop resets and disables all
reset, interru
To enable interrupt m . further process it is
interrupts.to execute El instruction within interrupt service
A fter receiv ing INTA signal, it has to supp Iy th e address ofo•uZed.
IS
R. necessarY .
. It is 1-byte instruct10n and no flags are affected.
ft can be disabled by routJ.Ile.
1. By using DI or SIM instructions. DI (Disable Interrupt)
instruction resets interrupt enable flip-flop. Thus it
2· SyStem or processor reset.
1
~isables RST 7.5, RST 6.5, RST 5.5 and INTR interrupts. It is
3. After reorganization of interrupt. of 1-byte instruction and no flags are affected.
Theh followin g sequence of events occurs when INTR .
h.
1g . signal gates SIM (Set Interrupt Mask)
This instruction is used to set interrupt mask and to send
1. The 8085 checks the status of INTR . serial output. It transfers the content of accumulator to
execution of each instruction. signal dur.qag interrupt control logic and serial 1/0 ports. Thus it is
2. ~f INTR signal is high, then 8085 . necessary to load appropriate contents in the accumulator
rnstruction and sends a t· 1 . complete Its cun.r before execution of SIM instruction. It is of 1-byte instruction
c ive ow interrupt kn
signal INTA . . ac owledp- and no flags are affected. The format of SIM instruction is
, if the mterrupt is enabled.
shown in figure below.
3. In response to INTA .
instr . signal, external logic plllC!lll • D7 D6 D5 D4 03 D2 D1 Do
uchon opcode on th d
byte instruct' . ~ ata bus. In the case of SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5
ion, additional ·
machine cycles mterrupt acknow
are generated b th
additional bytes . t Y e 8085 to trans
4 . mo the microprocessor. Serial Don't 1 = Reset I = Mask I = Mask I = Mask
Output Care RST 7.5 RST 7.5 RST 6.5 RST 5.5
· On receiving the . Data
of next instrucfmstruction, the 8085 save the ad
·
mstruction. IOn on stack and execute
1 = Serial Data Enable Mask Set Enable
8085 Interrupt Instructions
. O= Serial Data Disable I = Masking 1s Enabled
0 = Masking is Disabled
Maskable interru t .
F",gure 5.11 SIM instruction format
or unmasked using pr:grs are enabled or disabled that is
used for am control Th Actually ' SIM does the following
. three tasks:
SIM an program control in 8085 : ere are four ins
d RIM. rrucroprocessor namely EI, 1· Masks th ·
b·t . e interrupts, bits O to bit 2 set/reset the mask
1 s in Inter
m k rupt mask register. Bit O masks RST 5. 5, b't
1 1
en:: :s R~T 6.5 and bit 3 masks RST 7.5. Bit 3
284 rNSK;HTS oN M1ci.o,ROCESSORS
- -- - ------- 1 I disables the masking control of bits O- 2.
-- - ---~·---- INTERRIJPTOPE1'J'1-T
 -" serial input of data; bit 7 is used for 5 . 1
perfor "~ ena
4- pata Jnput.
Resets RST 7.5, bit 4 is used to reset it whether RST 7
2.
is masked or not. This JS mainly used to overwrite RsS rupts in 8086
C • h
wit out serving 1t.
7 .::>
. . T 111ter interrupt can come from any one of three sources.
Implements serial I/0. If bit 6 = 1 is used to enab 80 86
All t rnal signal applied to NMI pin or to INTR pin, and
3.
serial I/ 0 and bit 7 is used to transmit serial out le ()Ile 1. anexe .
d to as hardware interrupts. Another source of an
5
da ta bit. put are ~~~. ecution of the interrupt . . . and 1s. referred to
instruction
RIM (Read Interrupt Mask) if!ter! upt 1s ex
•nterrupt. The third source of interrupt is some error
3.
The RIM instruction loads the status of the interrupt m k as 5oftware
.. i roduced dunng
. .
the execution .
of an instruction.
t~e pending interrupts and the contents of serial input ~: ' cond1t10!1S P
The 8086 interrupt process can be described as follows:
lme, SID,_ mto accumulator. Thus it is possible to monitor th
At the end of each instruction cycle, the 8086 checks to see if
status of mterrupt 1:'ask, p~nd~g interr~pts and serial inpu
The format of RIM mstructJon JS shown m figure below. any interrupts have been requested.
D3 Dz DI Do 1f there is any interrupt, the 8086 pushes the flag register on
D1 D6 Ds D..
SID 17.5 16.5 15.5 IE M7.5 M6.5 M5.5 the stack.
The 8086 disables INTR input by clearing the interrupt flag
l PeLing
l
I =Mask
l (IF) and resets the trap flag (IF).
serial Status of 0 =Unmask l=Mask The contents of current code segment register and
Input Data O=U nmask
RST 6.5 RST 7.5
RST5. 5 instruction pointer are pushed on the stack.
Pendmg I =Mask
Status
RST of 0 -- Unmask Then, the program control is transferred to interrupt service
Pendmg 5
5 · lntemJpt RST 6.5
Status of Enable Flag
routine. An IRET . instrUction at the end of ISR returnS
RST 7.5 I = Enabled execution to the main program by retrieving the contents
0 = Disabled
which were pushed on the stack before.
Interrupt Service Routine
Figure 5.11 RIM instruction format
Push Registers
Actually, RIM does the following four tasks: Main Line Push Flags
Program ClearlF
1. Checks whether RST 5.5, RST 6 5 an ClearTF
;;::sked o, not bit Oto bit 2 show fue ,u';,!';.;! Push CS
Push IP
mask status of interrupts RST 5 5 RST 6 5 d g Fetch ISR Address
7.5. logic 1 m
· d.JCates the interrupt is masked.
· ' • an
2. Checks the
shows wheth ·
sta:s i~t~r\upts are enabled or not; bit
indicates that the i~te1rrn errutpt enable flip flop. Logk Pop IP
up s are enabled. Pop CS
Pop Flags
3. Checks whether RST 5 5 RST Pop Registers
interrupts are e d" · ' . 6.5, and RST 1RET
status of pend _P n_ mg or not; bit 4 to bit 6 show
7.5. Logic 1 ind:!tte~r~pts RST 5.5, RST 6.5, and
es t e mterrupt is pending. Figure 5.12 8086 interrupt response
--;;;-;;--r~ ----- ---------,N-T-ER_R_U-:PT::-:0::P:;;ERA~TIMON~S12287
286 INSIGHTS ON MICROPROCE~SS;O~RS~-----------'4
 from 00000H to 003FFH. These are 2 byt
ss range 5 e
addre . IP is loaded from (type x 04H) and CS is loaded
8086 Interrupt Types i11struct1ons-
the next address given by (type x 04H + 02H). Some
There are two types of Interrupts in 8086. They are: fro11 1 ftware interrupts are:
i!XIJ'.'ortant so .
1. Hardware Interrupts (External Interrupts) . Divide by Zero Interrupt
• Type 0 .
Hardware interrupts
. are those interrupts which are caused W}len the quotient fro~ _either a DIV . or IDIV
y any peripheral
b ifi d · device by sending a signal thro h . struction is too large to fit Ill the result register; 8086
ug, a
spec e pm to the microprocessor. There are two hard
· t • . Ware :terrupt Types will automatically execute type o
m errupts m 8086 nucroprocessor:
interrupt.
i. NMI (Non-Maskable . Interrupt) - It is a single pmnon-
·
mas~able hard~are mterrupt which cannot be disabled Type 1 : Single ~tep Interrupt
It . 1s the highest priority interrupt in 8086 The type 1 interrupt is the single step trap. In the single
nucroprocessor. After its execution, this mterru~
· step mode, system will execute one instruction and wait
generates
. a TYPE 2 interrupt · IP is loaded from wo for further direction from user. Then user can examine
locat10n 00008H and CS is ,loaded from the the contents of registers and memory locations and if
locat10n 0000AH. they are correct, user can tell the system to execute the
ii. INTR (Interrupt Request) - It provides a s· next instruction. This. feature is useful for" debugging
~1terrupt request and is activated by I/0 port. assembly language programs.
~terrupt .can be masked or delayed. It is a I
triggered mterrupt. It can receive any interrupt type Type 2 : Non-Maskable Interrupt (NMI)
•
the :alue of IP and CS will change on the interrupt , As the name .suggests, this !"terrupt cannot be disabled
received. The INTA is the response pin for I by any software instruction. This interrupt is activated
request. by low to high transition on 8086 NMI input pin. In
_J Edge Triggered Input response, 8086 will do a type 2 interrupt.
NMI
=_r- Level Triggered Input • Type 3 : Breakpoint Interrupt (INT 3)
The type 3 interrupt is used to implement break point
INTR
function in the system. The type 3 interrupt is produc~d
INTA Response to INTR Input by execution of the INT 3 mstruction. Break pomt
8086 function is often used as a debugging aid in cases whe:
F igure
" single stepping provides more detail than wanteth ·
5.13 8086 hardware interrupts . . th tem executes e
2. Wh en we msert a breakpomt, e sys the
Software Interru p ts (In ternal Interrupts) instructions up to the breakpoint, and then goes to e
· t procedure w
These are instructions that ar . b reakpoint procedure. In the brea k P0111
to generate interrupt Th e mserted within the pro • uister contents'
can write a program to display . reo-that J.5 . requ ired
8086 microprocessor s~ ~re are ~56 software interrupts
type where type . e mstructions are of the format memory contents and other infortnati on·nsert as u-· _,.ny
1
ranges from OOH to FFH. The sta . to debug our program. We can
......._ breakpoints as we want in our program.
288 INSIGHTS ON MICROPR~O - - - - - - - --
. CESSORS
- - - - --
------------------ - - - - - - INTERRUPTOPERAT!oNS
 e to type 4) are dedicated to
, types (typ O .
t five d" •de-by-zero interrupt, the smgle-
1oweS s the 1v1
'fJ1e ts such a k ble interrupt, the breakpoint
• Type 4 : Overflow Interrupt (INT 0) . terruP on-mas a
The type 4 interrupt is used to check o.verflow condition s.f~ Jicilltei1lrruPd t'thetheovernfl Ow. mterrup
. t Interrupt types 5 to 31 are
·
omplex microprocessors. The
. ed arithmetic operation. m the .system. The ,ter t art e in more c
after any sign iJ11erfl.lP' 111tel for us 32 to 255 are available for us to use
8086 overflow flag (OF), will be se~ if the signed resu1t ed by t types from
of an arithmetic operation on two s1~ed _n umbers is too ,e¢"' 224 jr\terrup m· terrupts. .
large to be represented in the destination register or ~rr·ner dware or software
for ha!
memory location.
. IVT structure (organization)
. "ti"ze the 8086 interrupts as follows: Figure 5.14, .
W e canpnon 3FFH Type 255 Pomter:
Table 5.5: 8086 interrupt priority (Available)
3FCHL--~_:_____;---i
Interrupt Priority

Divide Error, INT(n), INTO Highest

Available Interrupt Type 33 Pointer:
Pointers (224)

l
NMI (Available)
INTR 084H Type 32 Pointer:
Lowest (Available)
Single Step
osoHL--.2.----:-.---7
0?FH Type 31 Pointer:
Interrupt Vector Table (IVT) (Reserved)
.The interrupt vector table is a feature of the Intel 8086 familr
of microprocessors. An interrupt vector is a 4-byte number stored ia Reserved Interrupt
the first 1024 bytes of the memory (00000H - 003FFH). There art Pointers (27)
Type 5 Pointer:
256 different interrupt vectors. Each vector contains the address c,t. (Reserved)
an interrupt service routine. Each vector contains a value for 014H L---T.;._ype_4_P~o--:-in-:te-r:-:- 7
and CS that forms the address of the interrupt service routine.
(Overflow)
first two bytes contain the IP, and the last two bytes contain the
Thus, in terrupt vector table (IVT) is a 1024 bytes sized table 0l0H Type 3 Pointe~:
l-Byte Instruction
contains the addresses of interrupt service routine. The purpose
the IVT is to hold the vectors that redirect the microprocessor Dedicaed Interrupt
Pointers (S)
0OCH L__ Type 2 Pointer:
~-l
_J(~B~re~ak~p~o~in==:t:)
the right place when an interrupt arrives. Non-maskable
The figure below shows the organization of interrupt V 008HL---:T;ype.::::.=.~1EP~o:nin;te;r:--"J
table. The iriterrupt number is used as an index into the table to Single-Step
the address of the interrupt service routine. When the
CS Base Address
004H
··
L-_:~~~-7Type 0 Pointer:
responds to a particular type interrupt, it automatically multi · ..... ···························· Divide Error - - -
the type by 4 to produce the desired address in the interrupt V lP Offset
table. It then goes to that address in the table to get' the startillll 000H i..i......----16 Bits-
address of the interrupt service routine.

290 INSIGHTS ON MICROPROCESS~-----· INTERRUPT OPERATIONS

 ---;: input. Vector address, used by the
cessor a
t itS INT .
to the service subroutine of the
0 01
DOS & BIOS interrupts: ~e(ll·1croPr r to uans f e r contr
·J d by the 8259A on the data bus.
ces50 · prov1 e
Do~ in terrupts services link applications with os services iicJopr 0. device, is . architecture of 8259A PIC.
!-UCh as opening file, reading, writing content using certain P t111Pti!lg the interna1
Jflte ·.rt1re shows INT
function-. of INT 4H. BIOS interrupts control the screen disk fieloll'fib- liiifA
co ntro ller and keyboard operation using INT lOH, 13H,16H etc.
cONTROl LOGIC

5.9 Priority Interrupt Controller (PIC)

The INTR pin can be used for multiple peripherals, and to
determine priorities among these devices when two or more
peripherals request interrupt service simultaneously, priority _.1,..1,.-i....__ ...

111tc1rupt controller (PIC) is used. The PIC includes a status register, "•
~
a priority comparator, and a priority encoder. "•
Ills

1....---...,.Jr--~
~ ---~1--A
_D_,,_0 _ _ _ _ _ __ ; - - - - - ~ IRo
Interrupt
Microprocessor AD Data Bus! PJC Inputs c,.sCADE
SUFFER
I~ cis,

cis,--,..---
coMPflRATOR

INTR OOA~-------mTA INT

Figure 5.15 Multiple interrupts using PIC

---- Figure 5.16 Intel 8259A programmable interrupt controller

If there are simultaneo~s requests, the priorities ate-

~~~~ th 825AA
determined by the priority encoder; it responds to the higher ie. This bidirectional 8-bit buffer is used to interface e
input, ignoring the lower level input. The drawback of this scheme
is that the interrupting device connected to input IR7 always
the highest priority. This drawback has been solved with t1ie
* to the microprocessor data bus.

Read/Write & Control Logic th microprocessor. It

advent of 8259A programmable interrupt controller.
It accepts output commands sent f rom e .5t d
Programmable interrupt controller (PIC) is a device that .iJ contains the initialization comm.and word (ICW) regi ers _an
h tore the vanous
used to combine several sources of interrupt onto one or moN operation command word (OCW) registers W hic s 0f
~PU lines, while allowing priority levels to be assigned to ill th stah1S
control formats for device operation. It also allows e
mterrupt outputs. When the device has multiple internfl't 8259A to be transferred to the data bus.
outputs to assert, it asserts them in the order of their relatift'
pri~rity. This 8259A programmable interrupt controller is specillDJ lnterruPt Request Register (IRR)
I f service. It
designed to work with Intel microprocessor 8085 and 8086. . t stores all the interrupt inputs that are reques mg . ll 1·t
t
The 8_259A has eight interrupt request inputs IR1-1Ro· 11te : an B-bit register; one bit for each interrupt requeS . Ba~ica Uy,
eeps tr k . f Or service. an
8259A uses
_ its INT output to interrupt the microprocessor
. ·•---•·•
UUV"'8"" int ac of which interrupt inputs are asking ·t .1..,.0
errupt. . . t ·gnal on t 'u ....
INTR pm. The 8259A receives interrupt acknowledge pulses front input 1s unmasked, and has an mterrup si

----·--------
- - - - - - - - - - - -,-NT_E_R_RU_P_T-::0-=PE:::RA:;;;TIO;;NMAS
 Chapter-I

the corresponding bit in the IRR w ill be set. The content of this
regis ter can be read to know the status of pending interrupts.

Interrupt Mask Register (IMR) . rocessin

s stems
en viewed as a sequentia
· 1
The IMR is used to disable (Mask) or enable (Unmask) 1 fdultl h computer has ~e 1 guages require the
individual interrupt request inputs. ·This is also an 8-bit register. ;, Traditionally ~p:ter programnun~eq~ence of instrUction_s-
Each bit in this register corresponds to the interrupt input with the . e. :Most co cif algorithms as_ chine instrUctions m
sa me n um ber. The IMR operates on the IRR. Masking of hi&her oiachll1aJ)l!Jler to spe y ms by executing ma ter has never
p riority input will not affect the interrupt request lines of IOW41r rrogr executes progr~ This view of the compu
priority. To unmask any interrupt, the corresponding bit is set'9'-.
"'oCessor
1• done at a hme.
ase<\-tu·~ ely true. lved and as the cost o f
In-service Register (ISR) 11een en
1 has evo ht
rnp uter techno ogy ter designers have soug
The in-service register keeps track of which interrupt As co d ped .compu enhance
hardware has rop ' llelism usually to
are currently being serviced. In 8259A, during the service computer opportunities for para . ' is an example of
m terrupt requ est, if another higher prioritf interrupt more and mored availability. Multiprocess1hng . g the common
performance an lti" ple CPUs s arm
active, it will be acknowledged and the control will be tr h. h uses mu
from lower priority interrupt service subroutine (ISS) to
parallelism w ic torage device etc.
resources such as memory' s
priority ISS. Thu s, more than one bit of ISR will be set ·
the number of interrupts being serviced. Characteristics of Multiprocessing System ocessors of
Contains two or more similar general purpose pr
Priority R esolver
comparable capability.
, t ommon memory.
All processors share access o c
All processors share access to I I
o
d ices either through the
ev d . s
. h t the same ev1ce .
same channels that provide pat s o
tin system that
System is controlled by an integrated opera g
d their programs.
provides interaction between processors an

Common Resources
RAM Memory
Plotter
High Speed Printer
Figure 6.1: Organization of multiprocessing system
294 INSIGHTS ON MICROPROCESSORS
'--------- - - -A
-D-VA
- NC--=Eo::-:T=.0;.;PICS;;;.12211
 wbacJ.<s:
pra d f the system is limited by the cycle time because
Here, the processors can communicate with each other fhe spee o ferences must pass through the common bus.
through memory. The CPUs can directly exchange signals as all memory re
mdicated by dotted line. The organization of multiprocessor M1dtiport Memory .
and I/ 0 module has dedicated path to each
system can be divided into three types. 2, Ssor
:Each procemodule this system has mort; performance and
1. Time Shared or Common Bus memory •ty than earlier· one. F or th'1s syst em, 1t
· 1s
· poss1"ble to
comP
nfi 1ex1
ure portions of memory as private. to one or more
Memory unit
~PU; and/or I/0 modules. This feature allows increasing
•ty against unauthorized access, and the storage of
secun
recovery routines in areas of memory not susceptible to
modification by other processors.
IOP2
Memory
Figure 6.2: Time shared system modules

There are number of CPUs, 1/0 modules and me

modules connected to the same bus. So the time sh
system must distinguish the modules on the bus
determine the source and destination of the data.
module in the bus can temporarily act as a master.
one module is controlling the bus, the other should Figure 6.3: Multiport memory system
locked out. The access to each module is divided on the
of time. The time shared multiprocessing system has 3. Central Control Unit
following advantages and drawbacks. It manages the transfer of separate data streams back and
forth between independent modules like CPU, memory and
A dvantages:
1/0. The controller can buffer requests and perform
Simplicity arbitration and timing functions. It can also pass status an~
The physical interface and the addressing time sharing 1 control messages between CPUs. All the co-ordination is
of each processor
. . remains the same as in a singe
. 1 proc concentrated in the central control unit un-disturbing ihe
system, so 1t 1s very simplest approach. modules. It is more flexible and complex as well.
Flexibility
6·2 Real and Pseudo-Parallelism ---
In the simplest sense parallelism is the simultaneous use of
mhultiple computer resourc:s to solve a computational problem- In
Reliability t is con . art5 that caJ\ be
cept, a problem is broken into discrete P . f
. should not the failure
The failure of any att ac h ed d ev1ce so ved t a series o
the whole system.
I concurrently. Each part is further broken down
·instructi °
. u.Itaneouslv on
stJJ\
ons. Instructions from each part execute ·
-
296- - - --- -
INSIGHTS ON MICRO;PR;.O:;;C:;;E;SS;;:O:::R=s- - - - - - -- - - -
- - - - -- - - -- - - - ----:-:-::-::;:;;;;;;:
ADVANCEOTCJPICS 217
 . Fl nn's classification distinguishes multi-
Jassification. Jtectures according to how they can be
fl),r111' 5 c coillPuter arc independent dimensions of Instruction
different CPUs. Parallelism can have two different forms: ,oees_sodr along the thw oe dimensions can have only one of two
0
parallehsm and pseudo-parallelism. real- r Jie ta Eac h of t e s Multiple . The matnx
cia . below defines. the 4
55
Real-pamllelism consists of the parallel modes of h . dva .
aJ1 ·ble state .
s· Sing 1e or .
. s accordtn to Fl nn.
.
devices so tha t each can carry parallel operations to ea Ph ysical possi cJassification
T c othe
p
ossible s I •s D Single Data sIMD
Single Instruction, Multiple Data
wo or more processes are actually running at once because thr.
computer system is a parallel processor i.e., has more th e T ____-::-;-:;::;-::-------i
Singl1ee·~In:s::tr1.1:=c:t1:..on__:'_ _:..._ _ _
processor. an one M I SD MIMD
. Instr1.1ction, Single Data Multiple Instruction, Multiple Data
Process 1 CPUl l',fulhP1e
~
ction Single Data (SISD)
Process 2 CPU2 Singl e In Stru ,
~ 1, . 1 processor executes a single instruction stream to
Figure 6.4: True/real parallelism A sing e
operate on data stored in a single memory.
Pseu do-parallelism consists of the same de . .
parallel o . vice carrying the CU: Control Unit
peration. Concurrent processing using parallelis ......_ PU : Processing Unit
pseudo-paralle 1·ism w hi ch operates either in time divis' m ts .uic MU: Memory Unit
other types of parallel al orithm ton or usm, IS : Instruction Stream
the ill . f g s. In pseudo-parallelism one '---
usron o a parallel processor. Two processes are swi·tched
' •-v•
M--"
DS: Data Stream
executed concurren tly thr ough a smgle
. processor. -

. ----
Figure 6.6: SISD
Process 1 CPl/ J •· Examples: Uniprocessors such as older generation
, ,. CPU 1 ~ :ceu 1 mainframes, minicomputers and workstations, most modem
Process 2
; CPU 1 .: ; CPI/ 1
- .,
•
day PCs.
2. Single Instruction, Multiple Data (SIMD)
Figure 6. 5: Pseudo-parallelism
Single machine instructions controls the simultaneous
For example, computer b .
printing on a printer while ~an . e readmg from a disk m execution of a number of processing elements on a lockstep
m ultiprogramming system, the ; g ~ user program. In ll basis. Each processing element has an associated data
program, running each switches from program t9 memory, so that each instruction is executed on a different
the CPU is runnin nlprogram for a fraction of second. Alth-...a.
CP g o y one program t . ~ set of data by the different processors.
U speed is very high so it c a any mstant of time. At
second. It gives user an ill a~ work on several programs in•
processes are being
. .
usmn of parallelism i e
processed at th . · .,
sevaw:
switching back and forth of th e same time. This rapkf
illusion of parallelism and is t e CPU between programs gives •
ermed as pseudo-parallelism. LM: Local Memory
6.3 Flynn 's Classification
There are different ways to 1 . -
of the more widely used cla;sif' ~ assifr parallel computers. cit
icahons, muse since 1966, is callld
Figure 6. 7: SIMD
298 INSIGHTS ON MICROPROCESSORS
 Examples:
Array Processors: Connection Machine CM-2, MasP
MP-1 & MP-2, ILLIAC IV ar
Vector Processors: IBM 9000, Cray X-MP, Y-MP & c
90
Fujitsu VP, NEC SX-2, Hitachi 5820, ETAlO '
Most modem computers, particularly those with graphi
processor units (CPUs) employ SIMD instructions ~ I

execution units. ~IS_~

3. Multiple Instruction, Single Data (MISD)
~
A sequence of data is transmitted to a set of processors, eq Figure 6.9: MIMD
of which _executes a different instruction sequence. MISD
structure 1s only of theoretical interest since no practiQI Examples:
systems has been constructed.
M~ t current supercomputers, .
networked parallel
hlh
computer clusters and "grids", multi-core PCs w c
include SMPs (symmetric multiprocessors), NUMA
systems.

6.4 Instruction Level, Thread Level and Process

Level Parallelism
Instruction-Level Parallelism
Instruction-level parallelism (ILP) is a measure of how many of
Figure 6.8: MISD the operations in a computer program can be performed
Some conceivable uses of MISD might be: simultaneously. Consider the following program:
Special purpose stream processor (e.g., digital fil 1. e=a+b
~ultiple cryptography algorithms attempting to 2. f=c + d
single coded message. 3· g= e * f
4.
Multiple Instruction, Multiple Data (MIMD)
itcannOperation 3 depends on the results of operations 1 and 2, so
~ set . of proccessors simultaneous}
instructions sequences on different data :ets.
execute
operati:~e/alculated until both of them are completed. However,
can be 1 and 2 do not depend on any other operation, so they
ca culated . 1 .
can be simu taneously. If we assume that each operatiOn
can he completed in one unit of time, then these three instructions
3/2. completed in a total of two units of time, giving an ILP of

tak ;\ goal of co ·1 • · tify nd

-----
300 INSIG HTS ON MICROPROCES:;.SO~RS;;;-- - - - - - - -- - -- - e actvant mpi er and processor designers tS to 1den a
-----.. . age of as h . • ~-"- are
------ muc ILP as possible. Ordinary progrcu,..,
-- 3~
ADVANCED TOPICS
 nning code on a 2-
if we are ru d
xatrtple, . arallel environment an
-111ple e " " & "b") 1Il a P. CPU "a" to do
f.S 3 s1 (CplJs a " ·tis possible tote11
t\ p1cal l\' wri tten under • a seq uential execution
. model wh ere r systelll "A" and "B , • 'B" simultaneously, thereby
,,.;:esSo do tasl<s " to do task
f
m,truc tion.; e ecute one a ter tl1 e other and m the order specif
1e d r.,.. hto
1
"b
b:; the programmer. lLP allows the_compil_e r and e processor to
th iewis d cPlJ e execution.
i i, "A" 311 .., time of th d. tributed (parallelized)
oYerl.ip the execution of multiple instructions or even to change tas~ the ru•· h ·zes the is
the order in vvhich instructions are executed. .,~ciJlg llelisrn ernp as1 pposed to the data (data
~ d para hr ds) as o .
'f)u'ea ssing (i.e., t ea , here on a contmuum
How much ILP exists in programs is very application f the proce ams fall somew
s penfic. In certain fields, such as graphics and scientific computing nature o ) Most real progr d data parallelism.
the a mo unt can be very large. However, workloads such as aUelisJll . arallelisrn an
par een thread p . tes task parallelism:
cryptography exhibit much less parallelism. tietw d below illustra
The pseudoco e
Micro-architectural techniques that are used to exploit 11.P
program:
includ e:
• Instruction pipelining where the execution of multip)e
if CPU="a" then
instructions can be partially overlapped.
do task "A"
• Superscalar execution, VLIW, and the closely relal!INI
Explicitly Parallel Instruction Computing concepts,. fa
else if CPU="b" then
which multiple execution units are used to ~ do task "B"
multiple instructions in parallel. end if
Thread-Level Parallelism
TI1read parallelism (also known as task parallelism, end program
parallelism and control parallelism) is a form of parallelization The goal of the program is to do some n et total task ("A+Bn).
computer code across multiple processors If we write the code as above and launch it on a 2-pllrocessor
en vironments. Thread parallelism focuses on system, then the runtime environment w1·11 execute it as fo ows.
execution processes (threads) across different parallel co
n odes. It contrasts to data parallelism as another fonil • In an SPMD system, both CPUs will execute the code.
parallelism.
• In a parallel environment, b oth w1·n have access to the
It w as later recognized that finer-grain parallelism same data.
w ith a single program. A single program might have
• The "if" clause differentiates between the CPU's. CPU
threads (or functions) that could be executed separately
parallel. Some of the earliest examples of this "a" will read true on the "if" and CPU "b" will read true
implemented input/output processing such as direct on the "else if", thus having their own task.
access as a separate thread from the computation thread. A • Now, both CPU's execute separate code blocks
g eneral approach to this technology was introduced in the simultaneously, performing different tasks
w hen systems were designed to run multiple computation simultaneously.
in parallel. This technology is known as multi-threading (MT)
Code executed by CPU "a":
program:

ADVANCED TOPICS
 d on the res ult of the previous
. ration depen s 11 I As the size of a problem
. 5iJlce each i;rforlJled in par;e~~m available usually does
auo!l· arinot be p f data-para
do task "A" itd theY c mount o ,
oJle, r the a
bigge'
oets
end program 0
veil, l rsrn tr l
Code executed by CPU "b": asi I paral e I . f one or more cen a
program:
sLeve . the use o The
proces • el parallelism i~ sin le computer system.
process-I~ (CPUs) within a g pport more than one
do task "B" . units .. f a system to su Th
roeessing t the ability o k between them. ere
p a)so refers o b'lity to allocate tas s d f "tion of
end program teflll or and/ or the a i . basic theme, and the e rm
proeess variations on this ry with context, mostly as a
This concept can now be generalized to any number ef
are
manY r can va
I vel paralle ism . d (
d"
ltiple cores on one ie,
processors. process e CPU are define mu tern
function of how s k ge multiple packages in one sys
Data Parallelism . in one pac a '
multiple d,es
Data parallelism is parallelism inherent in program I ~
which focuses on distributing the data across different compu ·
unit, etc.). . on who ou talk to. In the past, a
This varies, depending up y inanlar execution
nodes to be processed in parallel. Parallelizing loops often leads P • g Unit) was a S---o-
similar (not necessarily identical) operation sequences or twrtctl"-Fit:
CPU (Central rocessm lti le CPUs were
for a computer. Then, mu p
being performed on elements of a large data structure. ~ component . d Then individual CPUs were subdivided
scientific and engineering applications exhibit data parallelism. incorporated into a no e. ' . . unit CPUs
into multiple "cores", each being a unique execution . .
A loop-carried dependency is the dependence of a 11M- . •0·.-- "1th multiple cores are sometimes called "sockets". The result 18 a
iteration on the output of one or more previous iterations. ~
node with multiple CPUs, each containing multiple cores.
carried dependencies prevent the parallelization of loops.
example, consider the following pseudocode that compu.- • During the past 20+ years, the trends indicated by ever
first few Fibonacci numbers: faster networks, distributed systems, and multi-processor
PREV1 :=O computer architectures (even at the desktop level) clearly
PREV2 := 1 show that parallelism is the future of computing.
do: ' ~ this same time period, there has been a greater than lOOOx
CUR := PREVl + PREV2 increase in supercomputer performance, with no end
currently in sight.
PREV1 := PREV2 65
PREV2 :=CUR ' ~~~er-p~ocess Communication, Resource
ocataon, and Deadlock
while (CUR < 10)
IQter-Pro ---<...;;:.::.::._:::~~~~-----------
This loop cannot be parallelized because CUR depends Cid.·" '"·""r•·• cess Conununication
itself (PREV2) and PREVl, which are computed in each loop llletJi0In coin.Putin ·
., ds for th g, inter-process communication (IPC) is a set of
'"ore e exchang f d .
304 INSIGHTS ON MICROPROCESSORS Processe p e O ata among multiple tbn=ads m one or
s. rocesses may be running on one or more

ADVANOEDTOl'a -
 ·1 cate certain resources for it to be able to run
computers connected by a network IPC methods are d " . uter to a 10 ·
the cornP could be access to a section of the computer's
methods for message passing, synchronization sh
and remote procedure calls (RPC). The method' of
vary based on the bandwidth and latency of
:;~d
IV1ded into
memory,
used rnay
sueh resources
d t in a device interface buffer, one or more files, or the
emory, a a . .
lil . d rnount of processing power.
between the threads, and the type of data being co communication require a
Th nunurucated A cornputer with a single processor can only perform one
ere are several reasons for providin a . s at a time regardless of the amount of programs loaded by
aJlows process cooperation: g n environment that proces '
the user (or initiated on start-up). Computers using single
• Information sharing rocessors appear to be running multiple programs at once
• Speedup ~ecause the processor quickly alternates between programs,
• Modularity processing what is needed in very small amount of time. This
• Convenience process is known as multitasking or time slidng. The time
• Privilege separation allocation is automatic, however higher or lower priority may be
given to certain processes, essentially giving high priority
. IPC may also be referred to as in
and inter-application communicati ter-thread communication programs more/bigger slices of the processor's time.
on.
On a computer with multiple processors, different processes
The combination of IPC with
the foundation for address. space . d the address space· concept is can be allocated to different processors so that the computer can
Th . m ependence/isolation truly multitask. Some programs, such as Adobe Photoshop, which
e single operatin . can require intense processing power, have been coded so that they
resources in a m lti" g s_ystem controls the use of
. u processing • system are able to run on more than one processor at once, thus running
multiple jobs or process may envrronment.
b . In thi s system,
more quickly and efficiently. ·
responsibility of . e active at one tirn
h operating syst e. The
sc e~ule the execution and to all:m or system software is to Deadlock
multiprocessor operating cate resources. The functio f A process requests resources; if the resources are. ~ot
system are: ns o
available at that time, the process enters a wait state. Waiting
• An interface betwee processes may never again change state, because the resour~es ti:1ey
• R n users and machin
esource man agement e ~ave requested are held by other waiting processes. This situation
• Memory management 18called
p a deadlock. • reasonable order.
• Prevent deadlocks rocesses need access to resources 1Il 8 t
•• Abnormal program termination Suppose a process holds resource A and requests
same time another process holds B and requests A;
~:i. -;
Process scheduling
blocked and remain in deadlock. .
• Managers security
.. A set of processes is deadlocked if each process in theA~..:
· the set can ...........
Resource Allocation
In computing
application t0 b e run' on
resource
th allocation is
· necessary for any
waiting for an event that only another process 1Il
Usually the event is release of a currently held
the processes can run, release resources and then be a
res<>=~
None of

---------~-- -
. w ill be countede system. When the user opens any
program, this
as a process, an d therefore, requires

306 INSIGHTS ON MICRO PROCESSORS

- - - - - - -- - - - -
 Deadloc k can be s tudl
.ed under two categories: User
(a) process deadlock (b) syS tem deiJ.dlock.
Conditions for deadlock:
(i) Mutual exclusion
Applications
Shared resources are used in a mutually exclusive manner.
(ii) Hold and wait

Processes hold onto resources they already have While

waiting for allocation of other resources.
(iii) No preemption Operating
System
Resources cannot be preempted until the process release
them.
(iv) Circular wait

Cb-cular chain of P'<>Mse, exist in Which each Process hold,

Hardware
resources wanted by the next process in chain.
Figure
. , • Operating system
610· •
6.6 Operating System
features of operating system: ften
An operating system i, a collection of software that
pmvides services for computer prog,am.,_ In other fenns, an When talking about features o f an o Perating
. system,perating
o
operating system is a composition of a kernel and utility prog,am,; they get mixed up with its functions.
system's feature as a pronunent a 1· We define an °
ting system;
the kernel ront,ofa the aUoeation of hardware resource, while 0., . ttr ·bu te of the opera
in other words, its major components.
utility progr.am, enhance the Usefulness of the computer. .An
open,tJng system kerne1 is a compute,- prog,an, that serves as an i. System calls
inte,media,y layer between the hardware and application
prog,ams. A kernel make, it J'OSsible fo, software to inte,-act witli On modern nucroprocessors, there are a eas
the underlying hardware of the operating system. Such software
. t I t two modes of
operation, kem.,1 mode and user mode. If an app ICO
(mostly application software) achieves thi, by issuing semc,, I. tion
'Unning U, use, mode rr;es to perform a privileged operation
request, to the ken,eJ. (These reques~ are called system calls.) (such as directly accessing the hardware), the CPU Will most
When a service request is received, the kernel h-an.,Jate, it inlu likely throw an exception. So, then, how does an application
instructions
compu fo, the CPU or other elecrronic components of th<
ter to execute. "'•d U>put from the keyboard or write to the screen? It does
so by <end;,,g
0 a request to the kernel. Of course, thls slOW1
down the peration, hut ensures that application program.
do Dote _,_ the

308 · INSIGHTS ON MICROPROCEssoRs

,·'"'Ply
:•~ni.
•ecute <ode that could damage or comprou=
These requests that application programs send "'
ared called 'Ystem calls. A system call can thu ti,be
defin
e ernei
operatin e as a request b_ a computer program to
~ :te111's kernel.
--- ........
 turned b a ck to the l
contro1 is r e a few Periphera s
event, - ver, only h to poll the
When a svstem call is invoked, control is transferred to the siJlg the am- Howe at drivers ave
Proees d progt . h means th
kernel which, in turn, determines whether the calling P
"J1terru te
. rrupts whic there IS. a n even t to process.
application should be granted the requested service. It , port J!lte k whether
granted, the kernel executes the necessary instructions,
sup e i.e. as
causes a switch into user mode, and returns control back to nardwar ' ce on a storage
the caUing program. Most operating systems however t nt . a linear spa e
file sys e . . stored m . ddress on storag ,
provide an intermediary interface that sits _between ,;. ter hie IS h fie has its a th
a pplications and the system caJis layer, in a form of a library Every corn~~te capacity. Eac I ber of byte offsets from e
or an Application Programming Interface (API) . Such an device .ofdeternu
fim ·ned by the num
d. m Bu t then, there is the need d
intermediary interface makes it possible for prograllls which is f the storage me Ill . . e of data begins an a
written in high level languages to invoke system ca1Js. beginning o Us where one p1ec track of
M oreover, it is easier and more portable to use a library or tructure that te File systems keep
API than to code the system call in assembly language
an tructions.
for as it ends-a file .system.
where . .
k as well as add1hona information
ins unuse 1
d space on the dis . ner creation date,
ii. Device drivers th name stze, ow ,
about each file such as . e t w' hat is more, file systems
1 ry
A computer system is usually made up of several devices access contro ' enc phon, e c. d the mapping o f f"l I e
d • t y structure an be
• uch as &sk drives, keyboa,d,, mice, video adapte,-s, '"""'l manage the_ irec or I blocks. A file system can thus
cards, etc. When a user attaches such devices to their names to file contra . and a set of
defined as a structured data representation
computer, Jjley expect the operating system to identify the
metadata that describe stored data.
device and make use of ;1. Indeed, the opemtmg •Ystem-,
know what the device is but not how to communicate With ff. iv, User interface
The la tter problem is solved by means of a driver. A de!Yiee
driver is a computer program that controls a Particular This is another feature of an operating system: its user
device a ttached to a computer. It provides an interface interface. An operating system's user interface determines
thrnugh Wfuch the Opecating ,Ystem can h-ansparenay ...... how the user interacts with the computer. The two most
calls to the device. In fact, device drivers have built-ill common forms of a user interface are the Command Line
function, that ace meant to be called by the ope,afing •i-m
or other privileged programs. ln~riace (CU) and the Gcaphical User Interface (GUI). A
CT.I P<ovide
by-line d f . at which commands can be given line-
Thi8 ak'P<ompt
Device, ace genecaJly slowec compru-ea wHh the CPU. Thlo
Program ·
call d
m o interface is usually implemented with a
means that wl1ereas the CPU could be doing other stuff, it
many times waits for a busy but slow device to finilh collUnands ase t at command
. line shell,, which accepts
whatevec job H ;, do;ng. This bad behav;o,, however, la . oper ex
appropriate r input and converts them to the
Illltiga ted by the use of hardware interrupts. Interrupts cause 8Powerful for experien
a _mg system
d functions. CLis can be quite
_c ontrol to be transferred to a routine designed to process the Ysteni. Well 00 ce users, but if one does not know the

r•
mle,-n,p1. Fo, example, when a key ;, pcesse,J on a compuler of Cl!, are ~ ';;", lhey can become quite lost. Examples
key boacd, a hacdwace U>tenupt;, genecated, Wltich Ulvokel
th Pton,pt. e ND( shells and the Windows Commanc1
_ , ke~ d,;vec. Aftec the drive, ha, Brushed In contrast
ON MICROPRocfssoii, devi ' a GDJ Prov· ct ·
1
ce
Perform_(sach as es
a lll.ouse) is a visual
d environment when, a
ike - use to navigate the system and
CLJs Where performm
 become slow and error-prone (such as when very Ion
commands are to be entered), GUis present the user . g
. ~~
• Processor management - Allocates the processor (CPU)
widgets that trigger some of the operating systein's to a process and de-allocates the processor when it is no
commands, reducing complexity and the need to memo . longer required.
command names and their parameters. For many use rize
G U~ p resents a more accessible user interface; however,~a
th
• Device management - Keeps track of all the devices.
This is also called 1/0 controller that decides which
ch oice of a user interface is simply a matter of person;
process gets the device, when, and for how much time.
p reference. Examples of GUis are those implemented .
Microsoft ~indows, Apple's Mac OS X, and GNOME/I<D~ • File management - Allocates and de-allocates the
for the X Windows system on Unix-like operating systems. resources and decides who gets the resources.
Objectives of operating system: • Security - Prevents unauthorized access to programs
The objectives of the operating system are : and data by means of passwords and other similar
techniques.
• To make the computer system convenient to use ·
efficient manner. man • Job accounting - Keeps track of time and resources
used by various jobs and/ or users.
• To hide the details of the hardware resources from th
users. e • Control over system performance - Records delays
• To provide users a converu·ent . t £
between the request for a service and from the system.
computer system.. m er ace to use the • Interaction with the operators - Interaction may take
• To act as ru:1 int~rmediary between the hardware and its
place via the console of the computer in the form of
instructions. The Operating System acknowledges the
uthsers, makmg it easier for the users to access and use
o er resources. same, does the corresponding action, and informs the
• To manage the resources of a computer system.
operation by a display screen.
• To keep track of wh0 · • . • Error-detecting aids - Production of dlmlpS; traces,
resource requests andis usmg
d. which
. resource' granting error messages, and other debugging and error-
from different p ' me Iating conflicting requests · detecting methods.
rograms and users.
• To provid e efficient and fa1·r • C d" tion between other software aad 1IIN!IN -
oor ma piJ inte lers
~mong users and programs. sharing of resources Coordination and assignment of com ~ ,pie '
assemblers, and other software to the vanous users of
Characteristics of operating system: the computer systems.
Here is a list of some of the . .
features of operating systems: mo st promment characteristic 6.7 Different Microprocessor Architectures
• Memory man Accumulator-Based Arch 1·tecture .
memory i e arment - Keeps track of the primary based microprocessor architecture,
• ' ·. ., w at part of it is in use by whom what In accumulator: . ·cant register in comparison to other
part is n ot m use etc d , accumulator is the mos~i~thmetic and logical operations are
' · an allocates the memory when a t
process or p r ogram requests it. registers and moS of :,ator. Data can only enter into the ALU
erformed through ac_cu_m_----- -7,;;_;.:~~;;;;;;;~. .~
J /SIGlfTSON MICROPR<>mso.,- - p _ ,_ _ /'"
 from accumulator and the out pot of the ALU can be
. stared 1ll
accumulator through data bus. The 8085 microprocessor . CISC machines have large number of. complex instructions
example of accumulator-based architecture. is an • based onmultiple numbers of addressing modes .
Register-Based Architecture CISC machines processer does not consist of large number of
• registers due to large cost. So th~e rnac~es have to
Unlike an accumulator-based microprocessor archit
perform various memory read and wnte operations.
register-based microprocessor architecture has one or mo ecture, a
purpose registers. Data can enter into the ALU from anyre gene . ral • CISC machines are preferable where the speed of processer
Th e 8086 microprocessor is an example of re . registers. is not the prime issue and where general applications are to
architecture. gister-based be handled. Processers like 8085, 8086, 8086,8086,8086,8086
The advantages of register-based architecture is ext d. . . etc are based on CISC processers and even today's pc.
and flexibility in programming. However the d. d en ibiJity
. , 1sa vantage IS. RISC Architecture
requrrement of complex circuitry.
68 The term RISC represents reduced instruction set
· RISC and CISC Architectures computing/ computers. It focuses on a small set of instructions
~c:,s:C:-=A-r ~
c h~ i~te_c....:tu...::...r:.:e=.::...:.::..:::'.~~~'...=~--------- which simplifies the hardware design and improves the processer
performance. Generally, RISC processers include the following
c 1 · features.
ornp ex instruction set computers is the acron
and machine based on this archite tur h ym for CISc
M
ost of the personal com t c. e ave complex instructions.
. • The number of instructions is minimized i.e., less than 100
CISC architecture. Follo1::rs which are used today are based on and each can be executed in a single dodt cycle the data
machines. g are the characteristics of CISC path cycle time is the time required lo &fdi'h operations
from the registers, run them through ALU.,. _._ the
• CISC machines have complex result back to register which is very small hi Jil5C.
large cycles for execution. instructions which need a
• • the number of addressing modes is ~iiliill!i
The transfer of data amon th . than 3 and only few instructions are mas~· _
among memory and
b
ased on memo d
g e register is much faster than
processor In Cisc
·
.
, various instructions
link lode and store so that RISC permits heavy..,,
,ft;
gets reduced.
ry an processer h
so t e processing speed
• Th . .
e processing 1~ regis
• ter intensive, ~
nwst of the ~ - ,-
• Pipelinin · th many more regist':5 an:
performed using registers ange
from 32 ~ I D . . -
g Is e process of fet hin
another instruction • c g one instruction when than 100 registers. . RISC machines tor
. is executing ·
instruction this featu m parallel. Due to complex . coorams m
machines. re cannot be heavily used in CJSC
• There is no oucro-P ti.'.:,., The most instructions ue
. trUC .,._.
interpreting the UU:he hardware.
• Micro-operations f
h . orm the instru ti directly executed b~ include support for high level
e micro-program Wh . h .
Pe £ IC IS Writt
c 0 n and instruction form
. • Design considerations opriate seJection of instruction and
gh appr
r orm timing and en tn control memory to Iansuages thrOU jJerS.

---
imple . sequencing of th . . optimization of cotnP
mented in CISc. e nucro-operatiOl16
-;:;:;:,::------- -
314 INSIGHTS ON MICROPRoce____ _ _
SSORs - - - - _ _ _ _ __,. -----
 • . · ~cmd reSearch oriented tasks Where th e
Usuallyf m scien . x issue RJSC machines are Us d
sers 1s ape - ' .e
speedrep
and o 1acmg
proces C w due to reduce the price f
· CIS no - o
hardware.
• RISC based system are R4400SC from MIPS, PA7JO() fro ...
.,.
HP, Power PC fr om APP '
ie IBM and Motorola, uper spare
from sun, iB6QTM from Intel etc.
Differences between RISC and CJSC architecture:
RISC
1. Simple
instructions taking 1.
one c cle.
2. Most operations are register
2. In CISC
to regi$ter with only LOAD machine,
and read & writ operatJons
STORE operations
accessin memor . inherent p rt for e et'Uting
instructions
3. Heavily
pipelined, 3 Not/les pipelined
erformance.
4.
4.
5. Instructions
have fixed 5.
format.
6. format.
Few number of instructions
and addressin modei;. b.
7.
Comp lexity is in the design
of compiler. 7.
8.
Instructions are executed by
hardware. B.
ar

9. Since RISC processor an• 9

simpler than
processors, the , can
designed more quick! '.

10. Examples include SPAR , Hl. Example

MIPs R400(1, etc. 170/J 68, VA 11 I

'"I '"'""'"ON ..1e.0P11oc,.,.,.,-

- ---- 808t,, 80286, 80386,
--~------~
 phones, wgi . in n1:uJi;~
_,, ·ta1 SI·gna1 processors (DSPs) hared u sed ' '-'lleclJ
computers, video recorders, CD pla~ers, ar . disk drives, digit ii
d • modems and other applications to improve the . aj
APPENDIX
ra 10 , . . • . sign
quabty. DSPs are also used in televis10n a~phca hons. For exain laj
television converters use DSP to provide compatibility ~ e,
- - . f 8085 Instructions
L1st o Bytes
various television standards. 1h
rnstrUction
• • 11111 Machine
Cycles
T-States

--
An important application of DSPs is in signal coznpre .
and decompression. In CD systems, for example, the music onss10th11
ACI 8-bit data 2 2 7
■
I
CD is in a compressed form so that it doesn't use as much stora e
space. It must be decompressed in order to be reproduced. ~ ADC Reg. 1 1 4
signal compression . is used in cell phones to allow a greater ADCMem. 1 2 7
n umber of calls to be handled simultaneou sly in a local cell.

•
Application areas of DSPs are: ADD Reg. 1 1 4

- II
1. ADDMem. 1 2 7
Telecommunications
2. ADI 8-bit data
Music processing 2 2 7
3. ANA Reg.
Speech generation and recognition 1 1 4
4.

-- -
Radar ANAMem. 1 2 7
5.

■
Image processing ANI 8-bit data 2 2 7
6.
Implementation of digital filters CALL 16-bit 18
address 3 5
(unconditional) - · ··

-I
CMA 4
1 1
CMC 4
1 1
CMPReg. 1 1 4

-
CMPMem. 1 2 7
CPI 8-bit data 2 2 7
DAA

DAD Reg. pair

1 1
3
4
10
■
1
DCRReg. 1 1 4

DCRMem. 1 3 10
1 1 6
DCX Reg. pair
1 1 4
DI
318 1 1 4
EI
INSIGHTS ON '-'11CROPROcEssoRs
Af'PENDIX
r1•
 Instruction
Bytes Machine Bytes Machine
T-States Instruction T-States
Cycles Cycles
HLT
1 2ormore
~
~
5 or RAR 1 1 4
more ....-
IN 8-bit port address RLC 1 1
2 3 4
INR Reg. 10 >--

1 1 RRC ,1 1 4
INRMem. 4
1 3 RET (unconditional) 1 3
10 10
lNX Reg. pair
1 1 - RlM 1 1
JMP 6 4
16-bit address RST
3 3 1
(unconditional) 10 3 12
SBB Reg. 1
LDA 16-bit address 1 4
3 4 SBBMem.
LDAX B/ D reg. pair 13 1 2 7
1 2 7 SBI 8-bit data
LHLD 16-bit address 2 2 7
3 5
LXI Reg. pair,16-bit data 16 SHLD 16-bit address
3 5 16
3 3
MOV Reg.,Reg. 10 SIM
1 1 1 4
1 4 SPHL
MOV Mem.,Reg. 1
1 1 6
2 7
MOY Reg.,Mem. STA 16-bit address
1 3 4 13
2 7
MVI Reg.,Data STAX B/D reg. pair
2 1 2 7
MVI Mem.,Data
2 7 src
2 1 1 4
NOP 3 10 SUB Reg.
1 1 1 4
ORA Reg. 1 4 SUBMem.
1 1 2 7
ORAMem. 1 4 SUI 8-bit data
1 2 2 7
ORI 8-bit data 2 7 XCHG
2 1 1 4
2 7 XRAReg.
OUT 8-bit port address 1 1 4
2 3
PCHL 10 XRAMem. 1 2 7
1 1
POP Reg. pair 6 XRI 8-bit data 2 2 7
1 3 XTHL
PUSH Reg. pair 10 1 5 16
1 3
RA L 12
1 1 4
320 INSIGHTS ON MICROPROCESSORS
APPENDIX
 R,me,h s. G ,onk "· Microprocessor Architecture, Progranznzinc, o, .,,
Applirulion, wdh th, 8085. s• ed. Penran, !nte,-,,•tio"'1J
Publishing (India) Private Limited, 2011.

P,1,, Abel. IBM PC A=mbiy language and Prog,an,n,fog. S•h ed.

Pearson Education Inc., 2001.

D. v. li,JJ. M;,mp,_,, and

1 lnieif•cfog, Progran,n,/ng, .,,,
Hardware.. 4 hed. Tata McGraw Hill, 2000.

Wm;.m Slalling,. Ope,aling Sy, tem,. <• ed. hentice 1-laJL 2012.
Willfam SlaJJ;ng,.
Prentice Cnm,,ute, O,ganizalion and A,chUecture. 9• ed.
Han, 2012.

Sh;bu I(. V. Intmduclion lo En,bofded System,. McG,aw H;n

Education (India) Private Lilllited, 2009.

11,oma, Electmn;, Dev;,,,_ ID• ed.

L Floyd,2011.
Education, New Jersey, Pe_,

322
 •
j i{ence ! and·'Smi{e ,izre two powe,fu[ words. 'Smz[e' is tn f.
sorve many pro 6iems
r. r -
and 'Si{ence' e way tM
is tlie way to avoia mam,p 6' .
, .., ro ie11!s.

Er. Hari Prasad Aryal

M.Sc. in In format ion Sys tem Engi neer ing. PU

Er. Hari Prasad t\ryal is an Assistant l\fanagcr in Smart Choicl'

Tec hno logies Ltd . ( SCT-Nct\\'ork) and is ali gned with the compa nv
since ~IHI<, AD . l\lr. Aryal with teaching experience of more than 1~1
years is a lso a\ isiting Professor in I limala ya College of Engineering. ,
Ach a need Co ll ege of En gineering and l\lanagement. National College
of Engi neering. Sagarmatha En gineering College. llillside College of
Engi neer ing. li e lectures l\licroprnccssors. Computer Organization
and Arc hitecture. and Instrumentation -11. I le is al so the main ;iuthlir of
a Textbook : /11sit!hls 011 /11s1111111c111:i1io11-I/ ( .:0/s 1 \ fJ) .