HA13609ANT

Three-Phase Brushless Motor Driver

ADE-207-232 (Z)
1st. Edition
May 1997

Description
The HA13609ANT is a 3-phase brushless motor driver IC with digital speed control. It is designed for use
as a PPC or LBP scanner motor driver and provides the functions and features listed below.

Function
• Power MOS and power bipolar transistor driver circuits
• 16-bit serial interface
• Variable-speed digital speed control circuit
• Digital PLL
• Digital ready circuit
• PWM oscillator circuit
• Charge pump circuit
• Integrating amplifier circuit
• Current limit circuit
• Overshoot prevention circuit
• Braking function (with braking compete signal)
• Forward/reverse direction circuit
• Hall open circuit protection
• Watchdog timer (LVI, POR, and RST outputs)
• Stuck rotor protection

Features
• High breakdown voltage (50V/30mA) power transistor drive circuit
• PWM drive
• Variable speed control is possible (varying the servo filter constants is not required)
• Selectable rotation control method (discriminator control, PLL plus discriminator control)
• Selectable feedback type (voltage or current)
• Allows both PWM frequency switching and 100% duty operation
• Selectable current limiting level
• Braking mode selection (reverse braking, regeneration braking)
HA13609ANT

Block Diagram

VSS (5 V) VPS
VSS = Bip use
C101 C102
VSS 10 to 50 V= MOS use
21 25
R101 Hall amplifier
U+ + U
42 36 (Open collector)
Hu
U– – U
41 35 (Push-pull)
V+ + V
40 34
Hv Matrix
V– – V
39 33
W+ + W
38 32
Hw
W– – W
37 31
VSS
Open circuit
R102 protection FH × 3
R126 R/F RWD/FWD Over- PWM OSC 12
20 shoot C106
1.25 V preven- OSI
R127 tion fPWM
22 P.O.R L.V.I Duty 100
C108 – Error
amp
40 k – 27 Current feedback input
RST 8 BRAKE BRAKE +
No/8 PWM +
Counter 17 Error amplifier input
Monitor output comp.
7
(Ready: Low) MASK
MOTOR ON Current VSS
DATA OUT 4 BRAKE (2 bit) sense
– MASK 26
DUTY 100
R106
CLK 1 READY +
fMAX = 8 MHz O.S.I ON 24
VRef (2 bit) VRef R107
VRef 18
ENABLE 2 Serial port MASK
1.1 V
(16 bits) CONTROL
RWD/FWD –
DATA 3 +
D1 (2 bit) Stuck rotor
Buffer
FH × 3 D2 (2 bit) protector 23
Rotation monitor output 6 PLL SEL OR Icp, PC ON C105
VP (3 bit)
PC
fPWM (2 bit) Precharge 16
VSS MODE SEL
1.4 V
D1 C3
Ready Integral R3
29 + Wave- Ready
MR AMP form D1 ±4, ±8% – +
28 – shaping CONT.
Icp × 2 15

SPEED CLK 5 R7
Programmable
Charge
(0.2 to 5 kHz) D2 discriminator
pump
(1024 to 4095)

Discrimi- 19
9 OSC D2 PLL nator
R1
Vp Vp
10 11 30 13 14
1M
R4
R6

20 p 8 MHz 20 p C4
MAX R5

2
 HA13609ANT

Pin Functions
Pin No. Pin Name Function
1 CLK Serial port reference signal input
2 ENABLE Serial port data write/latch signal input
3 DATA Serial port data input
4 DATA OUT Serial port data transfer complete signal output
5 SPEED CLK Speed command signal input
6 TACHO OUT Rotation monitor (MR, Hall ×3) output
7 READY Ready and braking done (no/8) output (open collector output)
8 RST Power supply (V SS ) monitor output. High when a reduced power-supply
voltage is detected.
9 OSC IN Oscillator circuit input. Reference signal for all circuits other than the
serial port.
10 OSC OUT Oscillator circuit output
11 S-GND Small-signal ground
12 PWM OSC Connection for the capacitor that sets the oscillator frequency.
13 PLL OUT SPEED CLK vs. speed detection signal speed comparison output
14 DIS OUT SPEED CLK vs. speed detection signal phase comparison output
15 INTEG IN Integrating amplifier input
16 CP OUT Charge pump and integrating amplifier output
17 ERROR AMP IN Error amplifier input
18 BUFFER OUT Buffer amplifier output. Connect to pin 17 when current feedback is
selected.
19 R1 Charge pump output current and PWM oscillator frequency setting
20 LVI Reduced voltage detection level setting
21 VSS Small-signal circuit power supply. 5.5V maximum
22 POR Power-on reset delay time setting
23 LOCK PRO Motor rotation constraint mode coil current on/off time setting
24 VRef Current limit setting
25 VPS Output driver power supply. 50V maximum
26 C Sense Motor coil current detection
27 CFB Current feedback input
28 MR IN – Speed detection input
29 MR IN + Speed detection input
30 P-GND Output driver ground

3
HA13609ANT

Pin Functions (cont)

Pin No. Pin Name Function
31, 33, 35 U, V, W Lower arm driver push-pull output. Driven by a PWM signal. (Connect
power NMOS or NPN transistors.)
32, 34, 36 U, V, W Upper arm driver open drain output. (Connect a power PMOS or PNP
transistor.)
37 to 42 U+, U– Hall signal inputs
V+, V–
W+, W–

4
 HA13609ANT

Serial Port Input Data Structure

MSB LSB
A4 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Dummy Mode control

A0 = 1

Dummy Data control

A0 = 0

DATA OUT

DATA Mode control register (11 bits) Mode control

Serial A0 = 1
CLK port
(16 bits)
ENABLE Data control register (11 bits) Data control
A0 Decoder A0 = 0

Mode Control Register (A0 = 1)

Bit Symbol 1 0
MD0 MOTOR ON MOTOR ON MOTOR OFF
MD1 1 0 0 1 *1
MD1 BRAKE 1
MD2 0 0 1 1
MD2 BRAKE 2 BRAKE OFF Brake Brake Brake
1 2 3
MD3 DUTY 100 DUTY 100% DUTY
MD4 READY 4% 8% *2
MD5 O.S.I ON Active Non Active
MD6 0 1 0 1
MD6 VRef 1
MD7 0 0 1 1
VRef VRef ← ← ←
MD7 VRef 2 ×2 ×1 ×0.75 ×0.5
MD8 MASK ×2 ×1 *3
MD9 CONTROL Discriminator Discriminator + PLL
MD10 R/F Reverse Forward

5
HA13609ANT
Data Select Register (A0 = 0)

Bit Symbol 1 0
DD0 D1 A DD0 0 1 0 1
DD1 0 0 1 1
DD1 D1 B D1 1/1 1/2 1/4 1/8

DD2 D2 A DD2 0 1 0 1
DD3 0 0 1 1
DD3 D2 B D2 1/1 1/2 1/4 1/8

DD4 PLLSEL1 OR Icp DD4 0 1 0 1 *4

DD5 0 0 1 1
DD5 PLLSEL2 OR PC ON PLL OUT(Vp-p) ← ← ←
×100% ×75% ×50% ×25%
DD6 VP1 DD6 0 1 0 0 1 1 0 1 *5
DD7 0 0 1 0 1 0 1 1
DD7 VP2 DD8 0 0 0 1 0 1 1 1

DD8 VP3 VP (V) 2.2 +0.15 +0.3 +0.45 +0.6 –0.15 –0.3 –0.45

DD9 fPWM1 DD9 0 1 0 1 *6

DD10 0 0 1 1
DD10 fPWM fPWM ← ← ←
fPWM2 ×1 ×1.4 ×1.9 ×2.8
Notes: 1. Off: The brake function does not operate.
Brake 1: Braking up to No/8.
Brake 2: Braking up to No/8, and then regenerative braking.
Brake 3: Regenerative braking. The No/8 signal is output.
During a braking operation, when the MR frequency when braking completes cannot be detected
in the circuit (During braking, the speed detection signal for under setting is not output over the
2/D1 occurrence. Thus this occurs more easily for lower settings.), reverse rotation may continue
in some cases. Note that this bit is also used to set the rotation monitor output (FH × 3 or the MR
frequency). FH × 3 is only output from the rotation monitor when motor on (MD0 = 1) and brake 3
are selected.
2. The ready setting range has the following manufacturing variation:
4.3% ±25% (@MD4 = 1)
8.6% ±25% (@MD4 = 0)
3. This function masks the current limiter input (pin 27) (incorrect operation due to the recovery
current). See page 20 for details.
4. The PLL output setting indicates a change relative to 3.5 Vp-p. See the electrical characteristics.
This is valid when MD9 = 0 (PLL control). Note that DD4 also functions as the Icp selection in
discriminator control mode.
VR1
Icp =
4 · R1
DD4 = 1 . . . . . Icp × 2
@MD9 = 1
DD4 = 0 . . . . . Icp × 1

6
 HA13609ANT
DD5 also controls the PC on function to reduce motor rotation overshoot when MD9 is 1
(discriminator control). This function does not operate when D9 is 0. The precharge voltage (i.e.,
the integrator output voltage initial clamp voltage) can be set by Vp1 to Vp3 (DD6 to DD8). The
figure shows the precharge operation.

MD0 or MD10
Ready lock range
(MD4)
NO
Integrator output Vp

0V

Precharge
5. The Vp setting indicates the change relative to 2.2V. See the electrical characteristics.
6. Indicates the change relative to f PWM. See the setting formula.

7
HA13609ANT

Timing Chart (Forward Mode)

Hu Hv Hw
+

Hall amplifier input 0 Vhys

VOH1
U output

VOL

VOH1

V output

VOL

VOH1
W output

VOL

VOH
U output PWM PWM

VOL

VOH
V output PWM PWM

VOL

VOH

W output PWM PWM

VOL

8
 HA13609ANT

Serial Port Timing Chart

tr, tf < 20 nsec, tsu, th > 20 nsec The tr and tf times are stipulated
tw > 40 nsec at 10% and 90%, respectively.
th
ENABLE tsu th
50%

tsu

CLK 50%

tw tw

DATA A4 A3 D1 D0 50%

tsu th tsu tsu

DATA OUT 50%

td1 td2
≤ 50 nsec ≤ 50 nsec

Braking Function

Input and Output Logic

Serial Port Input Output

MOTOR ON BRAKE 1 BRAKE 2 R/F
(MD0) (MD1) (MD2) (DD10) Rotation Direction Braking
1 * * 0 Forward OFF *1
* * 1 Reverse OFF
0 0 0 * — OFF *2
* * 0 Reverse Brake *3
* * 1 Forward
Notes: 1. OFF: The braking function does not operate.
2. The IC goes to standby mode.
3. See the description of mode control for details on the braking operation.

9
HA13609ANT

N1 Braking set

Forward Braking or
regeneration
braking
0

Reverse
Regene-
ration
braking

N2

MDO
(MOTOR ON)

MD10 (R/F)

*3
tset up
MD1 (BRAKE1)
Rotation monitor
to Rotation monitor output set *2 output set
MD2 (BRAKE2)
Braking set *1
*3 *3
thold tset up
SPEED N1 N2 N1
CLK input

Monitor output *4
No/8
(open drain) Ready Ready detection Ready

Notes: 1. The IC goes to standby mode when MOTOR ON, BRAKE1, and BRAKE2 are all 0.
2. Hold the data values here.
1
3. thold, tset up > ×4
fSPEED CLK
4. The No/8 (braking completion) function does not operate when BRAKE1 and BRAKE2 are 0.
Note that the No/8 detection signal is initialized to the high level in the mode in note 1
(standby mode).

10
 HA13609ANT

Basic Application Circuit (Bipolar Transistor Circuit, Discriminator + PLL, Voltage

Feedback, and Hall Elements)

VSS VPS

C101
VSS
21 25
R114
R101 VSS VPS
R108
42 U+ U 36 Q1
Hu D1
41 U–
R109 D2
40 V+ U 35 Q2
Hv
39 V– R117
R115
38 W+ R110
Hw
37 W– V 34 Q3
VSS D3

R102 R111 D4
R126 V 33 Q4
20 LVI R118
R127 R116
R112
22 P.O.R W 32
C108 Q5
D5
8 RST
R113 D6
W 31 Q6
7 Monitor output R119

4 DATA OUT R120

Current limiter 26
MPU C107 RNF
1 CLK

C106 VSS
2 ENABLE PWMOSC 12
R106
3 DATA VRef 24
C105 R107
5 SPEED CLK Lock protection 23
VSS
Current feedback
29 MR IN+ input 27
MR
28 MR IN– Error amplifier input 17
Buffer amplifier
Rotation monitor output 18
6 output
Integrator output 16
C103 C3 R3
9 OSC IN
Integrator input 15
X’tal R105
19 R7
10 OSC OUT Discrimi- R1
C104 PLL nator
11 30 13 14
R4
R6
C4
R5

11
HA13609ANT

Application Circuits

Application Circuit 1 (Discriminator)

Error amplifier input 17

Buffer amplifier output 18

Integrator output 16
C3
C1
Integrator input 15 R2

Discrimi- 19
PLL nator R1
13 14

Application Circuit 2 (MOS Transistor Circuit)

VSS VPS

C101 C102

21 25 ZD1
VSS VPS R114
R108
U 36 M1
D1

R109 D2
U 35 M2
R117

ZD2
R115
R110
V 34 M3
D3

R111 D4
V 33 M4
R118

ZD3
R116
R112
W 32 M5
D5

R113 D6
W 31 M6
R119
RNF

12
 HA13609ANT

Application Circuit 3 (Current Feedback)

RNF
R125
Current feedback input 27
R121
Error amplifier input 17
C110
Buffer amplifier output 18

Application Circuit 4 (Hall IC input)

VSS

R103

R104 C101
VSS
21
VSS
R122
IC 42 U+

41 U–
R123
IC 40 V+

39 V–
R124
IC 38 W+

37 W–

Application Circuit 5 (External Reset Input)

VSS

R126
20 LVI
External reset input
H: standby
22 P.O.R
C108

8 RST

13
HA13609ANT

External Components
Recommended
Part No. Value Purpose Note
R101, R102 — Hall element bias current 12
R103, R104 — Hall IC applications, Hall input voltage 14
R105 1MΩ Oscillator stabilization
R106, R107 — Current limiter reference voltage 15
R108 to R113 — Power transistor base current limiter 16
R114 to R119 — Power transistor base-emitter resistors (gate-source resistors) 16
R120 ≥ 4.7kΩ Current limiter filter 13
R121 — Current feedback input filter 9
R122 to R124 — Hall IC output current 14
R125 — Current feedback input gain adjustment 10
R126, R127 — LVI operating voltage, external reset input pull up 11
RNF — Current detection 1
R1 ≥ 1.5kΩ Integration constant, PWM carrier frequency 2, 3, 5
R2 — Integration constant 2
R3 to R7 — Integration constant 3
C101, C102 ≥ 0.1µF Power supply stabilization
C103, C104 10p to 50pF Oscillator stabilization 7
C105 — Lock protection operation time 4
C106 — PWM carrier frequency 5
C107 — Current limiter filter 13
C108 — Power-on reset delay time 11
C110 — Current feedback input filter 9
C111 to C113 — Hall output stabilization 8
C1 — Integration constant 2
C2 — Integration constant 2
C3, C4 — Integrator filter 3
ZD1 to ZD3 ≈ 20V MOS power transistor gate destruction protection 8
D1 to D6 — Fly wheel diodes 8
X’tal 4 to 8MHz Oscillator 6, 7
Notes: 1. Current limiter operates according to the following formula:
V
Iop = Ref [A]
RNF
Here, V Ref is the value according to the VRef select function.

14
 HA13609ANT
2. Use the following formulas as a guideline for setting the integration constant (@MD9 = 1). To
minimize rotation deviation, set R1 to a relatively small value.
2π
ωo ≤ · f · D1 [rad/s]
20 MR
9.55 · VR1 · KT · R2
R1 = ·A [Ω]
4 · J · ωo · No
However, R1 must be in the range 1.5kΩ ≤ R1 ≤ 15kΩ.
C1 = 1 / (√10 · ωo · R2) [F]
C2 = 10 · C1 [F]
Here, No : Rotation speed [min–1 ]
f MR : MR frequency [Hz]
D1 : Divider determined by D1 select
VR1 : Charge pump bias voltage 1.16 [V]
KT : Motor torque constant [N·m/A]
J : Motor moment of inertia [kg·m2]
A : PWM comparator current gain [A/V]
2Vps – 0.83VE – Vsat
Voltage feedback method: A =
Rm · Vosc
GB
Current feedback method: A =
RNF
VPS : Power system power-supply voltage [V]
VE : Motor back EMF [V P-P/T·T]
Vsat : External transistor saturation voltage [V] (See the electrical characteristics)
Rm : Motor coil resistance [Ω/T·T]
Vosc : PWM amplitude voltage [V P-P] (See the electrical characteristics)
GB : Buffer amplifier gain [V/V] (See the electrical characteristics)
3. Use the following formulas as guidelines for setting the integrator filter:
First determine the angular frequency of ωP for DIS OUT and PLL OUT.
ωP = 2π · fMR · D1 [rad/s]
Determine the angular frequency of ωM for Motor.
9.55 1 Vref
ωM ≈ · KT · – TL [rad/s]
No J RNF
Determine the ωo.
ωo = √ωP · ωM [rad/s]
Determine the integrator’s DC gain G(E) .
J · ωo 1
G(E) = ·
9.55 · KT · A Z Kø
· D1 · 2π · · PLL SEL
60 ωo
Here, Kø : PLL gain = 0.28 [V/rad/s]
TL : Rated load torque [N·m]
PLL SEL : PLL output ratio
Vref : Current limiter reference voltage [V]
Z : MR pulse per round [P/R]

15
HA13609ANT
Set C3 and derive the integration constants from following formulas.
R6 = 0 Ω
R3 = 1
ωP · C3
R3
R5 =
G(E)
1
C4 =
2 · R5 · ωo
R7 = R5
Next, determine R4 to match the phase of PLL OUT.
(3.46 – VP) R3
R4 =
(VP – 1.2) – (1.9 – VP) · R3 / R5
Here, VP : See the electrical characteristics.
When log ωP/ω M is greater than 2, a phase advance to compensate for this phenomenon is
required. Use the following formula to set the phase advance;
C5 · R8 > 20 · 2
ωP
R4
DIS R6 R7
R8
PLL C4
R5
C5
4. The following formulas determine the stuck rotor protect detection time t LP (detects the current
limiter operating time), the output off time t OFF, and the setup time tset. The figures show the
operating waveforms.
tLP = ∆V1 · C105 ≈ 0.09 × 106 · C105 [sec]
Isink
∆V2
tOFF = · C105 ≈ 0.32 × 106 · C105 [sec]
Isource
V
tset = LH2 · C105 ≈ 0.0005 × 106 · C105 [sec]
Is
See the electrical characteristics for the definitions of ∆V1, ∆V2, Isink, Isource, and Is.
Standby
(MD0k to 2 = Low) Enable
Current limiter
operation

IRNF
0

Lock VLH1
protect VLH2
∆V1 ∆V2
pin
VLL
tLP tOFF tLP
0
tset Output off
Note that a capacitor with a leakage current sufficiently smaller that Isource must be used for
C105.

16
 HA13609ANT
5. The PWM carrier frequency fPWM is determined by the following formula:
1
fPWM = 0.0489 [Hz]
C106 · R1
6. The relationships between the crystal oscillator frequency fOSC and the speed command clock
f CLK , the speed detection signal fMR, and the discriminator resolution (number of counts) C are
shown below.
f CLK = fMR·D1
f OSC = fCLK ·1 / D2·C [Hz]
However, C must be in the range 1024 ≤ C ≤ 4095
Here, D1 : The MR signal divisor determined by D1 select
D2 : The crystal oscillator frequency divisor determined by D2 select.

Configuration of the speed control and phase control blocks when @MD9 = 0

Buffer amplifier

Speed signal fMR’

D1 16
fMR

C3 R3
– +
SPEED CLK CLK counter
fCLK
Discriminator
counter setting

Discriminator Charge
X’tal D2 15
fOSC (1024 to 4095) pump
R7

19
R1
4Icp

PLL Discrimi- Vp
nator
Discriminator
PLL SEL output
14
4% pulse R4 R6
PLL output C4
13
R5

Note: If possible, Tr and Tf for the SPEED CLK signal should be under 20 ns when using this circuit.

17
HA13609ANT

Timing in phase control mode

fMR'

A A

≈ 3.6 V
Discriminator output
≈0V
ACC ACC ACC ACC
A × 4% A × 4%

DEC DEC
≈ 3.6 V
PLL output
≈ 1.85 V

≈0V
ACC ACC

∆Vo

Integrator output

Configuration of the speed control block when @MD9 = 1

fMR’ Buffer
Speed signal D1 amplifier
fMR

SPEED CLK CLK counter

fCLK
Discriminator 16
counter setting C2
R2 C1

X’tal Discriminator Charge

D2 pump
fOSC (1024 to 4095)
R1
19
R1
4Icp

Note: If possible, Tr and Tf for the SPEED CLK signal should be under 20 ns when using this circuit.

18
 HA13609ANT
7. The table below lists reference values for the stabilization capacitors C103 and C104 for the
crystal oscillator element according to the frequency used.
X’tal (MHz) C103, C104 (pF)
4 to 6 ≈ 20 to 40
6 to 8 ≈ 10 to 20
Use a resonance resistance of under 50Ω as a criterion for selecting the crystal element used.
8. Include these components if required.
9. The cutoff frequency of the filter formed by C110 and R121 should be between 3 and 10 times
the PWM oscillator frequency.
10. The gain, GCTL, from the error amplifier input to RNF is given be the following formula:
Rif
GCTL = 1 +
R125
11. The formulas below determine the relationship between capacitor C108, which sets the power on
reset (POR) delay time, and the resistors R126 and R127, which set LVI.
R126
VLVI = VSD 1 + [V]
R127
However, V LVI > 3V
VHYS = R126 · IHYS [V]
However, V LVI – VHYS > 2.5V
t POR = 0.052 × 10 6 · C108 [sec]
The time t POR is the time required for the oscillator to reach stability. This time should be 20ms or
longer.
VHYS VSD, IHYS: See the electrical characteristics.
VLVI

VSS
< 2.0 V

0V 2.0 V
POR 1.3 V
0V

tPOR tPOR
RST

0V
When using an external reset input to set the IC to the standby state, pin 20 must be set to a low
level that is under 0.4V.
12. When the Hall inputs are common mode input, the open circuit protection circuit makes the
output transistors non-operational. When all the Hall input phases are open, the lower side
output transistors become non-operational.
The output transistors will be disabled if one or two phases are disconnected (become open) only
when the Hall inputs are common mode.

19
HA13609ANT
13. When setting up the current limiter filter consisting of R120 and C107, R120 should be 4.7kΩ or
larger, and C107 and R120 should function as a filter for the recovery current. This filter masks
the recovery current due to internal circuits for the current limiter input (pin 26) and the C107
discharge operation determines the PWM off time (by making the current limiter input a low
impedance). See the figures.
1/fPWM

ON ON
Output (U to W)

VRNF

C107 discharge

tMASK tMASK

Current limiter input

voltage (pin 26)
≈0V

For recovery current masking:

48 64
tMASK = to [SEC]
fosc fosc
@MD8 = 1
24 32
tMASK = to [SEC]
fosc fosc
@MD8 = 0
14. Use the formula below as a guideline for determining the values of R103, R104, and R122 to
R124 when a Hall IC is used.
R103 // R104 = R122 to R124 < 20kΩ
15. Take the current limiter input current (see the electrical characteristics) into consideration when
determining the values for R106 and R107.
16. Determine the values of R108 to R119 based on the characteristics of the output power
transistors used and the output driver characteristics (see the electrical characteristics).
17. Design the wiring in applications so that the potential of the pin 11 ground (the small-signal
ground) does not become higher than that of the pin 30 ground (the output stage ground) as
shown in the figure.
11 30
VSS

20
 HA13609ANT

Absolute Maximum Ratings

Item Symbol Rated Value Unit Note
Power-supply voltage VSS 5.5 V 1
VPS VSS to 50 V 2
Input voltage VIN VSS V 3
Output voltage Vout 50 V 4
Output current Iout 30 mA 5
Allowable power dissipation PT 0.8 W
Operating temperature Topr –20 to 70 °C
Storage temperature Tstg –55 to +125 °C
Notes: 1. A surge voltage of 6.0V is allowed for up to 10ms. Note that the operating range is as follows:
VSS = 4.25 to 5.5V
2. The maximum is VSS if bipolar transistors are used as the output transistors.
The maximum is 50 V if bipolar transistors are used as the output transistors.
3. Applies to the logic input pins 1, 2, 3, 5, and 9, and to the analog input pins 17, 20, 24, 26 to 29,
and 37 to 42.
4. Applies to the output pins 32, 34, and 36, and to pin 7, the monitor output pin.
5. Applies to the output pins 31 to 36. The maximum value for the monitor output pin is 10mA.

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HA13609ANT

Electrical Characteristics
Test Applicable
Item Symbol Min Typ Max Unit Condition Pins Notes

Current drain ISSO — 3.0 6.5 mA MD0 to 2 = 0, 21 6

VSS = 5.5V

ISS — 15 25 mA MD0 to 2 = 1,
VSS = 5.5V

IPSO — 0.13 0.5 mA MD0 to 2 = 0, 25 6

VPS = 50V

IPS — 2.5 3.5 mA MD0 to 2 = 1,

no load,
VPS = 50V

Logic Input low- IIL — –50 –100 µA 1 to 3, 5, 9

inputs level current

Input high- IIH — 0 ±10 µA

level current

Input low- VIL — — 1.5 V

level voltage

Input high- VIH 3.5 — — V

level voltage

Clock fCLK 4 — 20 MHz 9

frequency

Logic Output high- VOH1 3.5 4.6 — V IOH = 0.5mA 4, 6, 8, 10

outputs level voltage

Output low- VOL1 — 0.25 0.4 V IOL= 0.5mA

level voltage

Hall Input Rh — 10 ±25% kΩ 37 to 42

amplifier resistance

Common- Vh 1.5 — VSS–1.5 V

mode input
voltage range

Differential- Vd 70 — VSS/2 mV
mode input
voltage range

Hysteresis VHYS — 40 — mV Rh = 400Ω 1, 2

Output Output high- VOH2 VPS–1.8 VPS–1.6 — V IOH = 20mA, 31, 33, 35
drivers level voltage VPS = VSS

VOH2 10 12.5 15 V IOH = 1mA,

VPS = 24V

VOH2 5.5 9.0 — V IOH = 1mA,

VPS = 12V

22
 HA13609ANT

Electrical Characteristics (cont)

Test Applicable
Item Symbol Min Typ Max Unit Condition Pins Notes

Output Output leakage ILEAK — — ±100 µA VOH1 = 50V 32, 34, 36

drivers current

Output low- VOL2 — 0.15 0.3 V IOL = 20mA 31 to 36

level voltage

Output TPHI — — 1.0 µs IO = 10mA 3

response time

TPLH — — 1.0 µs

PWM Oscillator low- VL — 1.1 ±10% V 12

oscillator level voltage
and

PWM Oscillator high- VH — 2.8 ±10% V

com- level voltage
parator

Oscillator fPWM 2 — 30 kHz 2

frequency
range

Oscillator ferr1 — 7.7 ±10% kHz fPWM × 1,

frequency R1 = 6.2kΩ,
precision C106 =
1000pF

Comparator VPHYS — 50 — mV 2
hysteresis

Current Input current IIN1 — — ±10 µA Vi = 0 to 2V 24, 26

limiter

Offset voltage VOFF –15 –25 –40 mV Vi = 0.5 to 2V 26

Speed Common-mode VCM 1.5 — VSS V 28, 29

detection input voltage –1.5
amplifier range

Differential- VDIFF 60 — VSS mVP-P

mode input
voltage range

Gain Gain — 32 — dB f = 1kHz 2

Input current IIN2 — — ±20 µA Vi = 1.4V

I28 –146 –95 –62 µA Vi = 0V

I29 –67 –53 –39 µA Vi = 0V

Input current Iratio 1.45 — 2.25 — I28 / I29

ratio

Input sensitivity VS 15 — — mV 6 2

23
HA13609ANT

Electrical Characteristics (cont)

Test Applicable
Item Symbol Min Typ Max Unit Condition Pins Notes

Clock Oscillator fosc 4 — — MHz X’tal 9, 10

oscillator frequency range

Oscillator ferr2 — — ±0.01 % X’tal = 8MHz 2

frequency
precision

Program Count range N 1024 — 4095 Count 14, 16

-mable

discrimi- Operating fdis — — 20 MHz 4

nator frequency

Count error DC 0 — 1LSB —

Charge R1 voltage VR1 — 1.16 ±10% V R1 = 1.5kΩ 19

pump

Charge current ICP+ — 190 ±10% µA R1 = 1.5kΩ, 16

Discharge ICP– — 190 ±10% µA Vo = 2.0V

current

Current ratio ICP+/ICP– 0.8 1.0 1.2 —

Leakage current Ioff1 — — ±100 nA Vi = 1.5V

Clamp voltage Vclamp 2.8 3.0 — V

Digital Lock range ∆N — — ±25 % 7

ready manufacturing
variation

Pre- Clamp Vcp(1) — Vp ±10% V 16

charge voltage (1)

Buffer Internal Vref — 1.15 ±10% V 16

amplifier reference
voltage

Output Ro 9.8 14 18.2 kΩ 18

resistance

Maximum output VB(MAX) — 0.7 ±10% V

voltage

Voltage gain GB –8 –6 –4 dB

Error Input current IIN3 — — ±150 nA Vi = 1.5V 17, 27

amplifier

Offset voltage Voff — –25 –50 mV

Voltage gain Ge — 60 — dB Vi = 2.5V 2

Gain-bandwidth Be — 0.1 — MHz 2

product

Feedback Rif — 40 ±25% kΩ VSS = 5V

resistance

24
 HA13609ANT

Electrical Characteristics (cont)

Test Applicable
Item Symbol Min Typ Max Unit Condition Pins Notes

Inte- Internal Vp — 2.2 ±10% V DD6 to 8 = 0 15, 16

grating reference
amplifier voltage

Internal ∆Vp — 2.2+∆Vp ±10% V

reference
voltage
difference

Input current IIN4 — — ±250 nA Vi = 1.5V

Output voltage VOH3 2.75 3.0 — V Io = 0.5mA

VOL3 — — 0.9 V Io = 0.5mA

Voltage gain GI — 60 — dB Vi = 2.5V 2

Gain- BI — 0.3 — MHz 2

bandwidth
product

PLL and Output high- VOH4 — 3.6 ±10% V Io = 0.1mA 13, 14

offset level voltage

discrimi- Output low- VOL4 — 0.1 0.2 V

nator level voltage
output

Monitor Output leakage ILEAK2 — — 50 µA VOH = 50V 7

output current

Output low- VOL5 — 0.2 0.4 V IOL = 10mA

level voltage

Stuck Minimum tLP — 40 ±25% ms C105 = 0.47µF 23 2

rotor detection time
protector

Output off time tOFF — 165 ±25% ms

High-level VLH1 3.0 3.2 — V

voltage VLH2 2.5 2.7 — V

Low-level VLL — 1.4 1.6 V

voltage

Potential ∆V1 — 1.9 ±10% V VLH1–VLL

difference ∆V2 — 1.35 ±10% V VLH2–VLL

Detection-time ISINK — 25 ±30% µA Pin 23 voltage

sink current = 2.5V

Output off ISource — 5.0 ±30% µA Pin 23 voltage

source current = 2.5V

Standby-mode IS — 4.7 ±35% mA Pin 23 voltage 2

source current = VLH

25
HA13609ANT

Electrical Characteristics (cont)

Test Applicable
Item Symbol Min Typ Max Unit Condition Pins Notes

LVI Internal reference Vsd 1.13 1.21 1.29 V Turn on 20

voltage

Hysteresis IHYS — 50 ±25% µA

current

Output voltage VLV 2.0 — — V 21

maintained range

P.O.R Delay time tPOR — 24.5 ±25% ms C108 = 0.47µF 8, 22

Notes: 1. Timing chart
2. Design target values. These are not tested at delivery time.
3. The figure below stipulates the output response time. This is not tested at delivery time.
90%

10%

TPLH TPHL
4. Stipulated at the discriminator input frequency.
5. See the timing charts.
6. Stipulated at conditions in which the OSC input is fixed.

26
 HA13609ANT

Reference Data

Current Drain vs. Supply Voltage Current Drain vs. Supply Voltage
30 4
Tj = 25°C Tj = 25°C
Current Drain ISS, ISSO (mA)

Current Drain IPS, IPSO (mA)

3
20 IPS

2
ISS

10
1

ISSO IPSO

0 0
0 1.5 2.5 3.5 4.5 5.5 0 10 20 30 40 50
Supply Voltage VSS (V) Supply Voltage VPS (V)

Output Driver Low-Level Voltage vs. Output Driver High-Level Voltage vs.
Output Current Output Current
0.4 15
Output Driver High-Level Voltage VOH (V)
Output Driver Low-Level Voltage VOL (V)

Tj = 125°C Tj = 25°C

5°
C
12
=
0.3 Tj VPS = 50 V
10 Tj = –20°C

°C
= 25
0.2 Tj

Tj = 125°C Tj = 25°C
20°
C 5
–
0.1 Tj =

VPS = 50 V
Tj = –20°C
0 0
0 10 20 30 0 10 20 30
Output Current IO (mA) Output Current IO (mA)

27
HA13609ANT

PWM Frequency vs. R1 Voltage vs.

Junction Temperature Junction Temperature
10.0 1.4
C106 = 1000 pF R1 = 6.2 kΩ
R1 = 6.2 kΩ
fPWM × 1
PWM Frequency fPWM (kHz)

9.0 1.3

R1 Voltage VR1 (V)

8.0 1.2

7.0 1.1

–20 10 40 70 100 125 –20 10 40 70 100 125

Junction Temperature Tj (°C) Junction Temperature Tj (°C)

Error Amplifier Rif vs. Integrator vs.

Junction Temperature Junction Temperature
70 2.4
Integrator Reference Voltage VP (V)

60 2.3
Error Amplifier Rif (kΩ)

50 2.2

40 2.1

30 2.0

–20 10 40 70 100 125 –20 10 40 70 100 125

Junction Temperature Tj (°C) Junction Temperature Tj (°C)

28
 HA13609ANT

Monitor Output vs. Lock Protector vs.

Output Current Junction Temperature
0.4 300
C105 = 0.47 µ

Lock Protector tLP, tOFF (ms)

Monitor Output VOL (V)

0.3
5°
C
12 200
=
Tj tOFF

0.2
25°
C
Tj =
100
0.1 °C
–20
Tj =
tLP

0 0
0 2 4 6 8 10 –20 10 40 70 100 125
Output Current IO (mA) Junction Temperature Tj (°C)

LVI Reference Voltage vs. POR Delay Time vs.

Junction Temperature Junction Temperature
1.4 30
C108 = 0.47 µ
LVI Reference Voltage VSD (V)

POR Delay Time tPOR (ms)

1.3 25

1.2 20

1.1 15

–20 10 40 70 100 125 –20 10 40 70 100 125

Junction Temperature Tj (°C) Junction Temperature Tj (°C)

29
HA13609ANT

Package Dimensions

Unit: mm

37.34
42 38.0 Max 22

14.6 Max
13.4

1 0.89 1.0 21
2.54 Min 5.10 Max

1.27 Max 15.24

0.51 Min

0.25 +– 0.05
0.10

1.78 ± 0.25 0.48 ± 0.10

1° – 13°
Hitachi Code DP-42SA
JEDEC Code —
EIAJ Code SC-551-42
Weight 4.42 g

30
Cautions

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Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

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