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Unit V VHDL: Entity Entity - Name Declaration Entity - Name

VHDL is a hardware description language used to model digital systems. It allows modeling using different styles such as dataflow, behavioral, and structural. An entity in VHDL describes a hardware module using an entity declaration, architecture, configuration, package declaration, and package body. The document provides examples of VHDL code modeling basic logic gates such as AND, OR, NOT, counters, adders, and subtractors.

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Abii Baluu
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54 views

Unit V VHDL: Entity Entity - Name Declaration Entity - Name

VHDL is a hardware description language used to model digital systems. It allows modeling using different styles such as dataflow, behavioral, and structural. An entity in VHDL describes a hardware module using an entity declaration, architecture, configuration, package declaration, and package body. The document provides examples of VHDL code modeling basic logic gates such as AND, OR, NOT, counters, adders, and subtractors.

Uploaded by

Abii Baluu
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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UNIT V

VHDL
VHDL stands for very high-speed integrated circuit hardware description language.
It is a programming language used to model a digital system by dataflow, behavioral
and structural style of modeling. This language was first introduced in 1981 for the
department of Defense (DoD) under the VHSIC program.
Describing a Design
In VHDL an entity is used to describe a hardware module. An entity can be
described using,

 Entity declaration
 Architecture
 Configuration
 Package declaration
 Package body
Let’s see what are these?
Entity Declaration
It defines the names, input output signals and modes of a hardware module.
Syntax −

entity entity_name is
Port declaration;
end entity_name;
An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The
direction will be input, output or inout.

In Port can be read

Out Port can be written

Inout Port can be read and written

Buffer Port can be read and written, it can have only one source.

Architecture −
Architecture can be described using structural, dataflow, behavioral or mixed style.
Syntax −

architecture architecture_name of entity_name


architecture_declarative_part;
begin
Statements;
end architecture_name;
Here, we should specify the entity name for which we are writing the architecture
body. The architecture statements should be inside the ‘begin’ and ‘énd’ keyword.
Architecture declarative part may contain variables, constants, or component
declaration.

Data Flow Modeling


In this modeling style, the flow of data through the entity is expressed using
concurrent (parallel) signal. The concurrent statements in VHDL are WHEN and
GENERATE.
Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also
be used to construct code.
Finally, a special kind of assignment, called BLOCK, can also be employed in this
kind of code.
In concurrent code, the following can be used −

 Operators
 The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
 The GENERATE statement;
 The BLOCK statement

Behavioral Modeling
In this modeling style, the behavior of an entity as set of statements is executed
sequentially in the specified order. Only statements placed inside a PROCESS,
FUNCTION, or PROCEDURE are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that
are executed sequentially.
However, as a whole, any of these blocks is still concurrent with any other
statements placed outside it.
One important aspect of behavior code is that it is not limited to sequential logic.
Indeed, with it, we can build sequential circuits as well as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also
restricted and they are supposed to be used in sequential code only. VARIABLE
can never be global, so its value cannot be passed out directly.
Structural Modeling
In this modeling, an entity is described as a set of interconnected components. A
component instantiation statement is a concurrent statement. Therefore, the order
of these statements is not important. The structural style of modeling describes only
an interconnection of components (viewed as black boxes), without implying any
behavior of the components themselves nor of the entity that they collectively
represent.
In Structural modeling, architecture body is composed of two parts − the declarative
part (before the keyword begin) and the statement part (after the keyword begin).

Logic Operation – AND GATE

X Y Z

0 0 0

0 1 0

1 0 0

1 1 1

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity and1 is
port(x,y:in bit ; z:out bit);
end and1;

architecture virat of and1 is


begin
z<=x and y;
end virat;
Waveforms

Logic Operation – OR Gate

X Y Z

0 0 0

0 1 1

1 0 1

1 1 1

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity or1 is
port(x,y:in bit ; z:out bit);
end or1;
architecture virat of or1 is
begin
z<=x or y;
end virat;
Waveforms

Logic Operation – NOT Gate

X Y

0 1

1 0

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity not1 is
port(x:in bit ; y:out bit);
end not1;
architecture virat of not1 is
begin
y<=not x;
end virat;
Waveforms
Logic Operation – NAND Gate

X Y z

0 0 1

0 1 1

1 0 1

1 1 0

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity nand1 is
port(a,b:in bit ; c:out bit);
end nand1;
architecture virat of nand1 is
begin
c<=a nand b;
end virat;
Waveforms
Logic Operation – NOR Gate

X Y z

0 0 1

0 1 0

1 0 0

1 1 0

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity nor1 is
port(a,b:in bit ; c:out bit);
end nor1;
architecture virat of nor1 is
begin
c<=a nor b;
end virat;
Waveforms
Logic Operation – XOR Gate

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port(a,b:in bit ; c:out bit);
end xor1;
architecture virat of xor1 is
begin
c<=a xor b;
end virat;
Waveforms
Logic Operation – X-NOR Gate

X Y Z

0 0 1

0 1 1

1 0 1

1 1 0

VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity xnor1 is
port(a,b:in bit ; c:out bit);
end xnor1;
architecture virat of xnor1 is
begin
c<=not(a xor b);
end virat;
Waveforms

VHDL Code for a Half-Adder


VHDL Code:

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b:in bit; sum,carry:out bit);
end half_adder;

architecture data of half_adder is


begin
sum<= a xor b;
carry <= a and b;
end data;

VHDL Code for a Full Adder


Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);


end full_adder;

architecture data of full_adder is


begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

VHDL Code for a Half-Subtractor


Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(a,c:in bit; d,b:out bit);
end half_sub;

architecture data of half_sub is


begin
d<= a xor c;
b<= (a and (not c));
end data;

VHDL Code for a Full Subtractor


Library ieee;
use ieee.std_logic_1164.all;
entity full_sub is
port(a,b,c:in bit; sub,borrow:out bit);
end full_sub;

architecture data of full_sub is


begin
sub<= a xor b xor c;
borrow <= ((b xor c) and (not a)) or (b and c);
end data;

VHDL Code for a 4 - bit Up Counter


library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end counter;

architecture virat of counter is


signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)

begin
if (CLR = '1') then
tmp < = "0000";
elsif (Clock'event and Clock = '1') then
mp <= tmp + 1;
end if;
end process;
Q <= tmp;
end virat;

VHDL Code for a 4-bit Down Counter


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dcounter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end dcounter;

architecture virat of dcounter is


signal tmp: std_logic_vector(3 downto 0);

begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp <= "1111";
elsif (Clock'event and Clock = '1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
end virat;

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