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Design Unit-II: Choose The Correct Option From Following A. Space Requirement

1. The document discusses various topics related to VLSI design and MOS transistors including transistor parameters like threshold voltage, induced charge, transit time, and saturation region characteristics. 2. It also covers topics like transistor width, channel length, transconductance, switching speed, pass transistors, depletion and enhancement modes, and the operation of a CMOS inverter. 3. The document concludes with multiple choice questions related to transistor modeling, mobility, capacitance, threshold voltage, conductivity, and other parameters.

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Urstruly Sri
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40 views

Design Unit-II: Choose The Correct Option From Following A. Space Requirement

1. The document discusses various topics related to VLSI design and MOS transistors including transistor parameters like threshold voltage, induced charge, transit time, and saturation region characteristics. 2. It also covers topics like transistor width, channel length, transconductance, switching speed, pass transistors, depletion and enhancement modes, and the operation of a CMOS inverter. 3. The document concludes with multiple choice questions related to transistor modeling, mobility, capacitance, threshold voltage, conductivity, and other parameters.

Uploaded by

Urstruly Sri
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VLSI DESIGN

Unit- II
Bits

1. The effective gate voltage, Vg = Vgs - Vt


2. Induced charge, Qc = Eg εins ε0 WL
3. Transit time = length of channel/velocity.
4. For a non saturated region the condition is Vds<Vgs -Vt
5. It is possible to increasing width (w).
6. Saturation begins when Vds= Vgs-Vt.
7. A reduction in channel length results higher Trans conductance.
8. A fast circuit requires gm be as high as possible.
9. Switching speed depends on gate voltage above threshold & on carrier mobility
10. The relay contacts between several transistors switched in series is called pass transistor.
11. For the depletion mode, transistor gate is connected to the source, so it is always on.
12. For a CMOS inverter when Vin =logic 1 pMOS is off and nMOS is on.
13. For a depletion mode transistor Vgs=0.
14. Tran conductance of bi polar is far greater than MOS.
15. Latch up may be induced by glitches on the supply rails or by incident radiation.
16. Latch up condition in which the parasitic components give rise to establishment of low resistance
conducting path between VDD & VSS.
17. With no injected current the parasitic transistor will exhibit high resistance.
18. MOS transistor can be modeled with varying degrees of complexity.
19. In complementary transistor pull up no current flows either for logical 0 or 1 inputs.
20. In nMOS enhancement mode dissipation is high since current flows when Vin=1.

Choose the correct option from following


21. Load resistance (RL)is not used because of
a. Space requirement
b. Low speed
c. High power
d. High gain
22. For equal margins around the inverter threshold we set Vin=___
a. VDD
b. 0.5Vdd
c. Vgs-Vdd\
d. 3/2Vdd
23. In enhancement mode VGS=___
a. -Vinv
b. 2 Vinv
c. 3Vinv
d. Vinv
24. In depletion mode Vgs+=_____
a. VDD
b. Vin
c. 0
d. –Vin
25. The ratio of Zpu to Zpd is
VLSI DESIGN
Unit- II
Bits

a. 4:1
b. 2:1
c. 1:1
d. 6:1
26. The typical value of mobility of electron is µn
a. 125cm2/vsec
b. 25 cm2/vsec
c. 1250 cm2/vsec
d. 20 cm2/vsec
27. The typical value of mobility of holes is µp
a. 48 m2/vsec
b. 120 m2/vsec
c. 480 m2/vsec
d. 12 m2/vsec
28. Electric field from drain to source is given as Eds
a. Vds/L
b. L /Vds
c. 2Vds/L
d. 3Vds/L
29. Typical value of µn at room temperature
a. 240m2/vsec
b. 24 m2/vsec
c. 650 cm2/vsec
d. 25 m2/vsec
30. Typical value of µp at room temperature
a. 25 m2/vsec
b. 240 cm2/vsec
c. 12 m2/vsec
d. 260 m2/vsec
31. εins value for a silicon dioxide is
a. 6.0
b. 5.0
c. 3.4
d. 4.0
32. Gate capacitance per unit are Cg is related with C0 as
a. C0wL/2
b. 2C0wL
c. C0wL
d. C0wL/4
33. For nMOS enhancement mode transistors when VSB =0, Vt =__
a. 0.2VDD
b. 0.1 VDD
c. VDD
VLSI DESIGN
Unit- II
Bits

d. VDD/2
34. For nMOS enhancement mode transistors when VSB =5, Vt =__
a. VDD
b. 0.3 VDD
c. 0.4 VDD
d. VDD/2
35. For nMOS depletion mode transistor VSB=0, Vtd=___
a. -0.7VDD
b. 0.7VDD
c. 0.3 VDD
d. 0.2VDD
36. For nMOS depletion mode transistor VSB=5, Vtd=___
a. -0.7VDD
b. -0.6VDD
c. 0.3 VDD
d. 0.2VDD
37. Output conductance gds can be expressed
a. δIds/δVgs
b. δVgs/δIds
c. δVds/Ids
d. δIds
38. channel length is related to as λ α
a. L
b. 1/L2
c. 1/L3
d. 1/L
39. Current from drain to source is related to length as
a. 1/L
b. L
c. 1/L2
d. 1/L4
40. The value of µs/µ is
a. 0.4
b. 0.5
c. 0.3
d. 0.2

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