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Experiment-1: Simulation Result For Half Adder and Full Adder Circuit

The document describes an experiment involving the design and simulation of half adder and full adder circuits. It includes the truth tables, Boolean expressions, VHDL code using different modeling styles (dataflow, behavioral, structural), synthesis reports, circuit diagrams, and simulation waveforms. The goal was to write and test half adder and full adder circuits using Xilinx tools and an ISM simulator. Results showed that all three coding styles for the full adder produced identical delays in synthesis, despite using different VHDL approaches.

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Himanshu Rajan jain
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© © All Rights Reserved
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40 views

Experiment-1: Simulation Result For Half Adder and Full Adder Circuit

The document describes an experiment involving the design and simulation of half adder and full adder circuits. It includes the truth tables, Boolean expressions, VHDL code using different modeling styles (dataflow, behavioral, structural), synthesis reports, circuit diagrams, and simulation waveforms. The goal was to write and test half adder and full adder circuits using Xilinx tools and an ISM simulator. Results showed that all three coding styles for the full adder produced identical delays in synthesis, despite using different VHDL approaches.

Uploaded by

Himanshu Rajan jain
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Experiment-1

Aim:- Write truth table, Boolean expression ,VHDL code ,synthesis report and
simulation result for half adder and full adder circuit.

Software Used:- Xilinx Tool, ISM Simulator.

Activity 1:- Half adder circuit by using dataflow modeling.

Truth table:-

Input A Input B Sum Carry

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Boolean Expression:-
Sum=A’B+AB’=A XOR B

Carry=AB

Code:-
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity half is

Port ( a,b : in STD_LOGIC;

s,c : out STD_LOGIC);

end half;

architecture DF of half is

begin

s<=a xor b;

c<=a and b;

end DF;
Synthesis report:-
Number of Slices: 1 out of 768 0%

Number of 4 input LUTs: 2 out of 1536 0%

Number of IOs: 5

Number of bonded IOBs: 5 out of 124 4%

Delay: 7.824ns (Levels of


Logic = 3)

Circuit diagram:-

Schematic Diagram :-

Simulation Result:-
Activity 2:- Full adder circuit by using

i) Dataflow modeling.

ii) Behavioral modeling.

iii) Structural modeling.

Truth table:-

Input X Input Y Input Z Sum Carry


0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean Expression:-

Sum = X’Y’Z+X’YZ’+XY’Z’+XYZ = X XOR Y XOR Z

Carry = X’YZ+XY’Z+XYZ’+XYZ

= XY+YZ+XZ

Code:-
Dataflow Behavioral Structural

library IEEE; library IEEE; Structural library IEEE;


use use
use IEEE.STD_LOGIC_1164.A IEEE.STD_LOGIC_1164.A
IEEE.STD_LOGIC_1164. LL; LL;
AL; entity fullbha is entity fullstruct is
Port ( x,y,z : in Port ( x,y,z : in
entity FA is STD_LOGIC; STD_LOGIC;
s,c : out s,c : out
Port ( x,y,z : in STD_LOGIC); STD_LOGIC);
STD_LOGIC; end fullbha; end fullstruct;
architecture Behavioral of
sum,carry : out fullbha is architecture structural of
STD_LOGIC); begin fullstruct is
process(x,y,z) component half
end FA; begin Port ( a,b : in STD_LOGIC;
if(x='0' and y='0' and z='0') s,c : out STD_LOGIC);
architecture DF of FA is then end
s<='0';c<='0'; component;
begin elsif(x='0' and y='0' and signal
z='1') then t1,t2,t3: STD_LOGIC;
sum<=(x xor y) xor z; s<='1';c<='0'; begin
elsif(x='0' and y='1' and h1 : half port map(x,y,t1,t2);
carry<=(x and y) or (y and z='0') then h2 : half port map(t1,z,s,t3);
z) or (z and x); s<='1';c<='0'; c<=t2 or t3;
elsif(x='0' and y='1' and end structural;
end DF; z='1') then
s<='0';c<='1';
elsif(x='1' and y='0' and
z='0') then
s<='1';c<='0';
elsif(x='1' and y='0' and
z='1') then
s<='0';c<='1';
elsif(x='1' and y='1' and
z='0') then
s<='0';c<='1';
elsif(x='1' and y='1' and
z='0') then
s<='1';c<='1';
end if;
end process;
end Behavioral;

Test bench code:-


LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY test2_fullbha IS
END test2_fullbha;

ARCHITECTURE behavior OF test2_fullbha IS

COMPONENT fullbha

PORT(

x : IN std_logic;

y : IN std_logic;

z : IN std_logic;

s : OUT std_logic;

c : OUT std_logic

);

END COMPONENT;

signal x : std_logic := '0';

signal y : std_logic := '0';

signal z : std_logic := '0';

signal s : std_logic;

signal c : std_logic;

BEGIN

uut: fullbha PORT MAP (

x => x,

y => y,

z => z,

s => s,

c => c

);

stim_proc: process

begin

x<='0';y<='0';z<='0';

wait for 100 ns;

x<='0';y<='0';z<='1';

wait for 100 ns;

x<='0';y<='1';z<='0';

wait for 100 ns;

x<='0';y<='1';z<='1';
wait for 100 ns;

x<='1';y<='0';z<='0';

wait for 100 ns;

x<='1';y<='0';z<='1';

wait for 100 ns;

x<='1';y<='1';z<='0';

wait for 100 ns;

x<='1';y<='1';z<='1';

wait for 100 ns;

wait;

end process;

END;

Circuit diagram:-

Schematic Diagram :-
Simulation Result:-

Result:- The waveform of halfadder and fulladder arrived successfully.

Conclusion/report:-

Dataflow Behavioral Structural


Number of Slices: 1 out of 768 Number of Slices: 2 out of 768 Number of Slices:
0% 0% 1 out of 768
Number of 4 inpu LUTs: Number of 4 input LUTs: 0%
2 out of 1536 0% 3 out of 1536 0% Number of 4 input LUTs :
Number of IOs: 5 Number of IOs: 5 2 out of 1536 0%
Number of bonded IOBs: Number of bonded IOBs: Number of IOs: 5
5 out of 124 4% 5 out of 124 4%
Number of bonded IOBs:
Delay: 7.824ns IOB Flip Flops: 2
5 out of 124 4%
Total Delay 7.82ns
Total Delay 7.824ns

The totel delay in all three coading style are same

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