Experiment 8

American International University- Bangladesh

Department of Electrical and Electronic Engineering
EEE4106: Telecommunications Engineering Laboratory

Title: Study of Delta Modulation

Introduction:

Delta Modulation (DM) is one voice digitization technique of simple type. It encodes
analog signal into single bit digital signal by comparing each sample with approximation
signal. The positive difference value is encoded with bit 1 and negative difference value
with bit 0. Approximation signal (tracking signal) is produced from feedback of encoder
and level of the signal is increased or decreased by fixed magnitude (that is called delta
step size) according to the sign of the difference signal. If the sign of the difference signal
is positive, then the tracking signal’s level is decreases by delta and is increased by delta
on negative sign of the difference signal. Since DM is single bit encoding method,
sampling rate should be much higher than the Nyquist rate (oversampling).

Advantage of DM is its simplicity of conversion of analog speech into digital signal. One
of disadvantages of DM is high operating sampling rate that puts requirement of higher
transmission bandwidth than that of PCM (Pulse Code Modulation) and DPCM
(Differential Pulse Code Modulation).

Delta modulation finds application in low capacity voice communication system. It is

also used in digital signal processing system.

The objectives of this experiment are:

1) To understand basic principles of Delta Modulation (DM)

2) To design and implement modulator and demodulator of DM
3) To observe modulation and demodulation process of DM practically

Theory and Methodology:

The Delta Modulation is arranged as follows. The analog signal to be transmitted is taken
to the '+' input of a VOLTAGE COMPARATOR, which compares this with the signal at
its '-' input (more about this signal in a moment), and produces a logic '1' or '0' at its
output, depending on which voltage is greater.

The comparator's output is then latched into a D-type BISTABLE, which is clocked at
regular intervals by the Transmitter clock signal. The result, at the bistable's output, is a
stream of logic '1's and '0's which are produced in synchronism with the Transmitter
clock.

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The bistable's output then drivers a LEVEL CHANGER, which converts '0' and '1' logic
levels into voltage levels of +4V and -4V respectively.

This bipolar output is taken to the input of an inverting INTEGRATOR, so that the
integrator's output:

1. Ramps up linearly when the level changer output is at -4V (bistable output at
logic '1').
2. Ramps down linearly when the level changer output is at +4V (bistable output at
logic '0').

Fig. 1: Modulator and demodulator of Delta Modulation

The integrator’s output is then connected back to the voltage comparator's '-' input, to
complete the modulation loop.

To understand how the Delta Modulation operates, consider the analog input waveform
shown in Fig.2 below, applied to the comparator's '+' input:

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 Fig. 2: Wave-shapes of operations OF Delta Modulator

Just before some arbitrary time t=0, suppose the integrator output voltage is lower (i.e.
more negative) than the analog input. This causes the voltage comparator output a logic
‘1’, which is latched into the D-type bistable at time t=0 by the rising edge of the
Transmitter’s clock signal (TX.CLOCK). This in turn causes a ‘1’ to appear at the
bistable’s Q output, which is translated into a -4V level by the level changer. The
integrator output therefore ramps up to ‘meet’ the analog input.

One Transmitter clock cycle later, at time t=1, the integrator output has become more
positive than the analog input, so this time a ‘0’ is latched into the bistable, causing the
integrator to ramp downwards, once again bringing its output back in towards the analog
input signal.

As Fig. 2 shows, the final result over several clock cycles is an integrator output signal
which tries to follow changes in the analog input signal, and is itself an approximation of
the analog signal. The bistable’s output which generates a digital bit stream as the
integrator’s output changes, is used as Delta Modulator Output.

The Delta Modulator receives the transmitter data stream, which is clocked into a second
D-type BISTABLE by the receiver clock signal. This signal clocks data into the bistable
at in the center of each transmitted data bit, ensuring that the incoming data is clocked in
correctly.

The bistable’s output drives a second LEVEL CHANGER circuit, which once again
converts logic 0 and 1 levels into voltage levels of +4 and -4 respectively. The level
changer output then goes to the input of a second inverting INTEGRATOR identical to
the first.
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Since the Demodulator’s bistable output produces an identical bit steam to that generated
by the Modulator’s bistable, and since both bistables drive identical level changer and
integrator circuits, it follows that the output of the Demodulator’s integrator will be
identical to that of the Modulator’s integrator, but slightly delayed in time. In other
words, the Demodulator’s integrator output is also an approximation of the Modulator’s
analog input signal.

In order to smooth out the sharp output transitions of the Demodulator’s integrator, and
so obtain a close approximation to the original analog signal, the Demodulator’s
integrator output is then filtered by a low-pass filter, which removes signals above the
audio band.

The final result should be a signal at the low-pass filter’s output which is a close
approximation to the Modulator’s analog input signal. However, as we shall see in this
experiment, the Delta Modulator/Demodulator system has limitations which prevent this
from always being the case.

Pre-lab Homework:

 Gain in depth knowledge about the principle of delta modulation.

 Gain basic knowledge about the transmitter and receiver of DM.

Apparatus:
 Oscilloscope

 MODICOM 4 board

 Power supplies (+5 V, +12 V, 0 V, -12 V)

Precautions:
 Students are not allowed to work alone in the laboratory.

 Understand the operation of the trainer boards before using them. Permission
from the lab supervisor must be obtained if any changes to the
settings/configuration are to be made.

 Handle all the trainer boards with care.

 Do not take any things out of the laboratory without special permission.
Experiment must be completed within the given time.

 Report all damage to equipment, hazards and potential hazards to the lab
instructor and lab staff.

 Do not touch any exposed wires.

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  Do not unplug the cable while the power is switched on.

Experimental Procedure:

1. Connect supplies to the MODICOM 4 board. The d.c. supply requirements are
+5V, 100mA and ±12V @100mA/rail.
2. Connect the board as shown in the connection diagram of Fig.4. Functionally, the
Modulator (Transmitter) and Demodulator (Receiver) are now configured as
shown in the block diagram of Fig.1
3. Ensure that the CLOCK FREQUENCY SELECTOR block’s A and B switches
are in the A=0, B=0 positions.
4. Ensure that the switches in the INTEGRATOR 1 block are in the following
positions:
a. GAIN CONTROL switch slider in the left-hand position (towards
switches A and B);
b. Switches A, B in A=0 and B=0 positions.
5. Ensure that the switches in the INTEGRATOR 2 block are in the following
positions:
a. GAIN CONTROL switch slider in the right-hand position (towards
switches A and B);
b. Switches A, B in A=0 and B=0 positions.
6. Turn the ˜250Hz, ˜500Hz, ˜1kHz and ˜2kHz presets in the FUNCTION
GENERATOR block to their fully clockwise positions.
7. Turn on power to the board.
8. As an introduction to the operation of the Delta Modulation system, and in order
to ensure that the system is set up for correct operation, we will first take the
Delta Modulator’s analog input to 0 volts.

So connect the ‘+’ input of the Delta Modulator’s VOLTAGE COMPARATOR

to 0V, and monitor on an oscilloscope the output of INTEGRATOR 1(t.p. 13) and
the output of the Transmitter’s LEVEL CHANGER (t.p. 19).

If the Transmitter’s LEVEL CHANGER output has equal positive and negative
output level, INTEGRATOR 1’s output will be a triangle wave centered around 0
volts, as shown in fig.3 (a) below. However, if the level changer’s negative level
is greater than the positive level, the integrator’s output will appear as shown in
fig.3 (b). Should the level changer’s positive output level be the greater of the two
levels, the integrator’s output will resemble that shown in Fig.3(c).

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 Figure-3: Output Signal of Integrator Circuit

The relative amplitudes of the level changer’s positive and negative output levels
can be varied by adjusting the LEVEL ADJUST preset in the BISTABLE &
LEVEL CHANGER CIRCUIT 1 block. When it is turned anticlockwise, the
negative level increases relative to the positive level; when turned clockwise, the
positive level increase relative to the negative level.

Turn the preset from one extreme position to the other, and note that all three of
the waveforms in Fig.3 can be obtained at he output of INTEGRATOR 1 (t.p. 13).
Try to explain what is happening in the Delta Modulator circuit, in the case of
each of these waveforms. If necessary, examine the signals at other points within
the Delta Modulator, until you fully understand what causes each of these three
waveforms to appear at the integrator’s output.

9. Adjust the Transmitter’s LEVEL CHANGER preset until the output of

INTEGRATOR 1 (t.p.13) is a triangle wave centered around 0 volts, as shown in
Fig.3(a) above. The peak-to-peak amplitude of the triangle wave at the
integrator’s output should be 0.5V (Approx); this amplitude is known as the
integrator step size.
The output from the Transmitter’s BISTABLE circuit (t.p.18) will now be a steam
of alternate ‘1’s and ‘0’s; this is also the output of the Delta Modulator itself.
The Delta Modulator is now said to be ‘balanced’ for correct operation.
10. Examine the signal at the output of INTEGRATOR 2 (t.p.49). at the Receiver.
This should be a triangle wave, with step size equal to that of INTEGRATOR 1,
and ideally centered around 0 volts. If there is any D.C bias at the output of
© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 6
 INTEGRATOR 2, remove it be adjusting the Receiver’s LEVEL ADJUST preset
(in the BISTABLE & LEVEL CHANGER CIRCUIT 2 block). This preset adjusts
the relative amplitudes of the positive and negative output levels from the
Receiver’s LEVEL CHANGER circuit; only when these levels are balanced will
there be no offset at the output of INTEGRATOR 2.

Receiver’s LOW PASS FILTER (whose break frequency is 3.4kHz) then filters
out the higher-frequency triangle wave, to leave D.C. level at the filter’s output
(t.p.47). If the Receiver’s LEVEL ADJUST preset has been adjusted correctly,
this D.C. level will be 0 volts; the Delta Demodulator is now also balanced for
correct operation.
11. Disconnect the voltage comparator’s ‘+’ input from 0V and reconnect it to the
250Hz output from the FUNCTION GENERATOR block; the Modulator’s
analog input signal is now a 250Hz sinewave.
Monitor this analog signal at the VOLTAGE COMPARATOR’s ‘+’ input (t.p.7-
trigger the scope on this signal), together with the output of INTEGRATOR 1
(t.p.13). Note how the output of the Transmitter’s integrator follows the analog
input, as was illustrated in Fig.1 above.
Note: It may be necessary to readjust slightly the Transmitter’s LEVEL ADJUST
preset (In the BISTABLE & LEVEL CHANGER CIRCUIT 1 block) in order to
obtain a stable, repeatable trace of the integrator’s output signal.
12. Display the data output for the Transmitter’s BISTABLE (at t.p.18), together with
the analog input at t.p.7 (again trigger on this signal)
13. For a fuller understanding of how the Delta Modulator is working examine the
output of the VOLTAGE COMPARATOR (t.p.8), the BISTABLE’s CLOCK
INPUT (t.p.17) and the LEVEL CHANGER’s BIPOLAR OUTPUT (T.p.19)
14. Display the output of INTEGRATOR 1 (T.p.13) and that of INTEGRATOR 2
(t.p.49) on the scope. Note that the two signals are very similar in appearance,
showing that the Demodulator is working as expected.
15. Display the output of INTEGRATOR 2 (t.p. 49) together with the output of the
Receiver’s LOW PASS FILTER block (t.p.47). Note that although the
integrator’s output has been smoothed out somewhat by the low pass filter, some
unwanted ‘ripple’ still remains at filter’s output. This ripple is due to
‘quantization noise’ at the integrator’s output, which caused by the relatively large
integrator step size.
This step size can be reduced by increasing the rate at which the system is clocked
(I.e the sampling frequency), since this reduces the sampling period, and hence
the time available between samples for the integrators to charge up and down.
16. The current system clock frequency is 32kHz. This is set by the A, B switches in
the CLOCK FREQUENCY SELECTOR block, which are currently in the A=0,
b=0 positions. While monitoring the same signals, increase the system clock
frequency to 64kHz, by putting the switches in the A=0, B=1 positions.

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 Note: If the integrator’s output no longer gives a stable trace after changing the
clock frequency, make a slight adjustment to the Transmitter’s LEVEL ADJUST
preset (in the BISTABLE & LEVEL CHANGER CIRUIT 1 block), until the trace
is once again stable.
Notice that, at the integrator’s output (t.p.49), the frequency of the triangular error
signal doubles and the peak to peak amplitude of that error single (i.e. the step
size) is now halved.
17. By changing the system clock frequency to first 128kHz (CLOCK FREQUENCY
SELECTOR switches in A=0, B=0 positions), and then to 256kHz (switches in
A=1, B=1 positions) note the improvement in the low-pass filter’s output signal
(t.p.47)
Once again, it may be necessary to adjust slightly the Transmitter’s LEVEL
ADJUST preset, in order to obtain a stable oscilloscope trace.
18. Using a system clock frequency of 256kHz (which gives a step size of
approximately 60mV), compare the low pass filter’s output (t.p.47) with the
original analog input (t.p.7). there should now be no noticeable difference
between them, other than a slight delay.
19. While continuing to monitor the Transmitter’s analog input (t.p.7) and Receiver’s
low-pass filter output (t.p. 47), disconnect the comparator’s ‘+’ input from the
˜250Hz sinewave output, and reconnect it to the ˜500Hz, 1kHz and 2kHz outputs
in turn. Note that, as the frequency of the analog signal increases, so the low pass
filter’s output becomes more distorted and reduced in amplitude.
20. In order to understand what has caused this distortion, leave the comparator’s ‘+’
input connected to the ~2kHz sinewave output of the Function generator, and
examine the output of INTEGRATOR 2 (t.p.49). Note that the integrator’s output
is no longer an approximation to the analog input signal, but instead somewhat
triangular in shape.
Compare this with the output of INTEGRATOR 1 (t.p.13), and note that the two
signals are exactly the same; the problem obviously starts in the Delta Modulator
circuit.
21. Compare the ~2kHz analog input signal (t.p.7) with the output of INTEGRATOR
1 (t.p.13) - it should now become clear what has happened.
The analog signal is now changing so quickly that the integrator’s output cannot
ramp fast enough to ‘catch up’ with it, and the result is known as slope
overloading.
22. Although the system clock frequency (i.e. the sampling frequency) determines
how often the integrator’s output direction (up or down) can change, it does not
affect how quickly the integrator’s output can ramp up or down. Consequently,
changing the system clock frequency will not help the slope overload problem;
prove this by changing the CLOCK FREQUENCY SELECTOR switches, and
noting that the problem is still present.
Return the switches to the A=1 and B=1 (256kHz clock frequency) position
before continuing.
© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 8
 23. If slope overloading is to be avoided in practical Delta Modulation system, the
transmitter integrator must be able to ramp up or down at a rate which is at least
as great as the maximum rate of change at the Transmitter’s analog input. If the
incoming analog signal is a sinewave, its maximum rate of change occurs at the
zero crossing point, and is proportional to both the frequency and the amplitude of
the sinewave. Hence the likelihood of slope overloading can be reduced by either
reducing the maximum input frequency, or by reducing the maximum input
amplitude to the Delta Modulator.
We have already seen how slope overloading can be avoided by reducing the
frequency of the analog input signal since there was no problem with the
~250kHz analog input. Now check that the problem can also be avoided if the
amplitude of the input signal is reduced; do this by slowly turning the ~2kHz
preset anticlockwise. Note that there comes a time when the integrator’s output
can once again follow the analog input signal.
24. Another possible way of overcoming slope overloading is to increase the gain of
the integrators, so that they can ramp up and down faster, and so follow even
those analog input waveforms that change very quickly.
To illustrate this, first return the ~2kHz preset to its fully clockwise (maximum
amplitude) position, so that slope overloading can once again be seen on the
scope.
In each of the two INTEGRATOR block, there are two red switches labeled A
and B. The 2-bit binary code produced by these switches selects one of four
integrator gains, the lowest gain being when the switches are in the A=0, B=0
positions. For each increasing step in the switch code from a=0,b=0 through to
A=1, B=1, the integrator gain si doubled.
Change the codes produced by the switches (in both INTEGRATOR 1 and
INTEGRATOR 2 blocks) from A=0, B=0 to A=0 and B=1, to double the gain of
the two integrators; note that slope overloading still occurs.
Change the codes produced by the switches to A=1 and B=0 position and finally
to the A=1, B=1 position, to show that slope overloading can be eliminated if the
integrator gain is large enough. Once again, it may be necessary to make a slight
adjustment to the Transmitter’s LEVEL ADJUST preset, in order to obtain a
stable trace on the oscilloscope.
Note that, although it is the gain of INTEGRATOR 1 alone which determines
whether or not slope overloading will occur, INTEGRATOR 2 must have the
same gain if the amplitude of the Demodulator’s analog output is to be equal in
amplitude to the Modulator’s analog input.
25. We have seen that slope overloading can be overcome by either
a. Reducing the maximum input frequency to the Delta Modulator
b. Reducing the maximum input amplitude, or
c. Increasing the integrator gain

In a practical Delta Modulation communications system, the signal at the

Modulator’s analog input would normally be in the audio band, so that the
© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 9
 maximum input frequency could not be reduced below about 3.4 kHz without
losing speech information. This rules out solution (a) above.

The problem with reducing the amplitude of input signals (solution (b)) is that
smaller input signals then become lost in the quantization noise, since they
become smaller in amplitude than the integrator’s step size.
Finally, if the integrator gain is increased [solution c], much the same problem
results as for solution b, since the larger step size increases quantization noise and
once again ‘drowns out’ the smaller signals.

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 10

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 11
Questions for report writing:
1. Draw all the wave shapes and explain those waveshapes. Also give reasoning
if you find any unexpected result.

2. Explain digitization process of delta modulation.

3. What are advantages and disadvantages of DM?

4. Why should oversampling be applied to the analog signal of DM?

5. Explain different types of noises in DM.

6. How is the tracking signal’s level adjusted with the analog signal?

7. How does the receiver of DM operate?

Discussion and Conclusion:

Analyze the findings of the experiment and explain about deviation of the outputs. Make
discussion about the sources of errors and possible ways of improving of the
experimental findings.

References:

1. Simon Haykin, Communication systems, John Wiley & Sons, 2008.

2. Bellamy, John C. Digital Telephony (Wiley Series in
Telecommunications and Signal Processing). Wiley-Interscience, 2000.
3. Telecommunication Lab Manual of AIUB

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 12