ANNA UNIVERSITY – CHENNAI
B.E/B.TECH PRACTICAL EXAMINATION OCT 2012
Name of the College :471 / A.K.T OF ENGINEERING & TECHNOL. MEMORIAL COLLEGE OGY
Department : Electronics and Communication Engineering
Year and Semester : II / III
Name of Lab : DIGITAL ELECTRONICS LAB
Subject code : EC2207
Date : 29.10.2012 & 30.10.2012
Max.Marks : 100
Duration : 3 hrs.
LIST OF EXPERIMENTS
1. a) Design and implement HALFADDER using logic gates.
b) Design and implement 16-bit odd/even PARITY CHECKER using IC74180.
2. a) Design and implement HALF SUBTRACTOR using logic gates.
b) Design and implement BCD to EXCESS-3 CODE CONVERTER using logic gates.
3. a) Design and implement 4:2 ENCODER using logic gates.
b) Design and implement BINARY to GRAY CODE CONVERTER using logic gates.
4. a) Design and implement 4:1 MULTIPLEXER using logic gates.
b) Design and implement 4-BIT BINARYADDER AND SUBTRACTOR using IC7483.
5. Design and implement EXCESS-3 to BCD CODE CONVERTER using logic gates.
6. a) Design and implement 16-bit odd/even PARITY GENERATOR using IC74180.
b) Design and implement GRAY to BINARY CODE CONVERTER using logic gates.
7. a) Design and implement BCD ADDER using IC7483.
b) Design and implement SISO shift register using D FF.
8. a) Design and implement 1:4 DEMULTIPLEXER using logic gates.
b) Design and implement PISO shift register using D FF.
9. Design and implement 2-BIT MAGNITUDE COMPARATOR using logic gates.
10. a) Design and implement MOD10 RIPPLE COUNTER using JK FF.
b) Design and implement 8-BIT MAGNITUDE COMPARATOR using IC 7485.
11. Design and implement of 3-BIT SYNCHRONOUS UP/DOWN COUNTER using JK FF.
12. a) Design and implement FULL SUBTRACTOR using logic gates.
b) Design and implement MOD12 RIPPLE COUNTER.
13. a) Design and implement 2:4 DECODER using logic gates.
b) Design and implement SIPO shift register using D FF.
14. a) Design and implement FULL ADDER using logic gates.
b) Design and implement PIPO shift register using D FF.
15. a) Design and implement HALFADDER using logic gates.
b) Write a verilog program for synchronous up/down counter using HDL.
16. a) Design and implement 4:1 MULTIPLEXER using logic gates.
b) Write a verilog program for full adder using HDL
17. a) Design and implement 4:2 ENCODER using logic gates.
b) Write a verilog program for half subtractor using HDL.
18. a) Design and implement BCD to EXCESS-3 CODE CONVERTER using logic gates.
b) Write a verilog program for 4:1 mux using HDL.
19 a) Design and implement BINARY to GRAY CODE CONVERTER using logic gates.
b) Write a verilog program for SISO shift register using HDL.
20. a) Design and implement FULL SUBTRACTOR using logic gates.
b) Write a verilog program for 1:4 Demux using HDL.
INTERNAL EXAMINER EXTERNAL EXAMINER
Ms.P.Priya,
Lecturer/ECE,
AKTMCET.
ANNA UNIVERSITY – CHENNAI
B.E/B.TECH PRACTICAL EXAMINATION OCT 2012
Name of the College : 471/ A.K.T OF ENGINEERING & TECHNOL. MEMORIAL COLLEGE OGY
Department : Electronics and Communication Engineering
Year and Semester : II / III
Name of Lab : DIGITAL ELECTRONICS LAB
Subject code : EC2207
Date : 29.10.2012 & 30.10.2012
Max.Marks : 100
Duration : 3 hrs.
ALLOCATION OF MARKS
ALLOCATION MARKS
AIM & PROCEDURE 10
CIRCUIT DIAGRAM 30
TRUTH TABLE 20
CONNECTIONS & EXECUTION 20
RESULT 10
VIVA VOCE 10
TOTAL 100
INTERNAL EXAMINER EXTERNAL EXAMINER
Ms.P.Priya,
Lecturer/ECE,
AKTMCET.
