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System-on-Chip Design: 2ECDE54

This document discusses processor architecture and types. It covers topics such as processor types by function including GPUs, DSPs, media processors and network processors. It also discusses processor types by architecture like SIMD, MIMD, SISD, and VLIW. The document describes processor architecture implementations like sequential, Von Neumann, Harvard, and modified Harvard architectures. It provides an overview of pipelined architecture and instruction level parallelism. The document includes diagrams illustrating Von Neumann, Harvard and VLIW architectures as well as sequential, pipelined and superscalar processor models. It also discusses ILP and SoC soft core processors.

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Pragya jhala
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59 views

System-on-Chip Design: 2ECDE54

This document discusses processor architecture and types. It covers topics such as processor types by function including GPUs, DSPs, media processors and network processors. It also discusses processor types by architecture like SIMD, MIMD, SISD, and VLIW. The document describes processor architecture implementations like sequential, Von Neumann, Harvard, and modified Harvard architectures. It provides an overview of pipelined architecture and instruction level parallelism. The document includes diagrams illustrating Von Neumann, Harvard and VLIW architectures as well as sequential, pipelined and superscalar processor models. It also discusses ILP and SoC soft core processors.

Uploaded by

Pragya jhala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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2ECDE54

System-on-Chip Design

Lecture: 4
Processor Architecture:Overview

Course Coordinator: Dr Nagendra P Gajjar


Procesor Architecture
• Processor Types by Function
– GPU : 3D Graphics, Rendering, Shading,Texture
– DSP : Generic, Sometimes sued with Wireless
– Media Processor : Video and Audio Signal Processing
– Network Processor : Routing , buffering
Processor Type by Architecture
• SIMD: Single Instruction applied to multiple Functional
Units
• MIMD _ Multiple Instruction Multiple Data
• SISD: Single Instruction Single Data
• SIMD: Single Instruction Multiple Data
• Vector Processor: Single Instruction Applied to Multiple
Pipeline registers
• VLIW: Very long Instruction Word
– Multiple Instruction issued each cycel under compiler
control
• Superscalar : Multiple Instruction issued
in each cycle under hardware control
Processor Architecture implmentations
• Sequential Processor
• Von Neumann Architecture
• Harvard Architecture
• Modified Harvard Architecture
• Pipelined Architecture
• Instruction Level Parallelism(ILP)
– Multiple Operations an be executed in Parallel within a program
– Multiple Consecutive iterations without any dependency in parallel
– Multiple independent programs can execute in parallel
– Parallelism at procedure level, depends largely on the algorithms used
in program
– One or more inter connected Processor elements( PE) solving a signel
problem
Von Neumann Architecture
Harvard Architecture
Processor: A Functional View:
• Instruction Execution Sequence:
– IF- Instruction Fetch
– ID- Instruction Decode
– AG- Address Generator
– DF- Data Fetch – Memory Read/Access
– EX- Execute
– WB- Write Back : Memory Write
• GPU: Shading/ Rendering/ Texturing etc
• Media Processor: Codec, Data Manipulation,
Compression
• AI/ML: CNN/DNN/TPU / Statistical Operation etc.
VLIW Processor Model
VLIW Architecture Exmaple-TI
SuperScalar Processor Model
Processor: An Architectural View:
• Simple Sequential Processor
– Actions of the stages can be overlapped but result has
to be in sequential order.
– One or more operations per clock cycle
– Instruction is container that represents the smallest
execution packet managed explicitly by processor.
– One or more operations are contained in instruction.
– Scalar and Superscalar processor consume more
instruction per cycle, where each instruction contains
single operation.
Sequential Processor Model
Pipelined Processor
• Pipelining is a series of stages where some
work is done at each stage in parallel.
• The stages are connected one to next form a
p[ipe- instructions enter one end , progress
through the stages and exit at the other end.
Pipelining Case: Laundry
• 4 loads of laundry that need to washed, dried,
and folded.
• 30 minutes to wash,
• 40 min. to dry, and
• 20 min. to fold.
• We have 1 washer, 1 dryer, and 1 folding station.
• What’s the most efficient way to get the 4 loads
of laundry done?
NonPiplined
Pipelined
Questions:

(1) What to do if performance is to be improved?


(2) If Dry Cycle is 35 minutes what will be saving of
time?
(3) What are mechnism of Pipelining?

Pipelining is an speed up technique where


multiple instructions are overlapped in
execution on a processor.
Time Graph
ILP
• Instruction-level parallelism (ILP) is a measure of how
many of the instructions in a computer program can be
executed simultaneously. ...
• Architecture that allows overlap of Instructions Execution
• E.g.
– 1. e= a+ b
– 2. f = c *d
– 3. g= e - f
• If we assume that each operation can be completed in one
unit of time and three instructions can be completed in a
total of two units of time, giving an ILP of 3/2
Instruction Timing in ILP
SoC Soft Core Processor
• Xilinx Microblaze 32 bit 3 stage I/D Cache: 64 KB – FPU
FPGA
• ALTERA : NIOS- II 32 bit 6 stage 64 KB Cache FPGA
• ARC 600 16/31 5 stage : 32 KB FPU FPGA
• Tensilica Xtensa 16/24 5-7 stage 32 KB cache FPU : ASIC
• LEON2/3 32/64 bit 5 stage : 128 KB cache FPU and
peripherals FPGA/ASIC
• RISC –V 32/64 bit 5 stage : 128 KB cache FPU and
peripherals FPGA/ASIC
• OpenSPARC T1/T2 6 stage : _____cache FPU and
peripherals FPGA/ASIC
• ARM CORTEX M Series

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