A TUTORIAL ON SETTING UP

ELECTRIC VLSI

BITS PILANI, PILANI-333031

Prepared by
Pawan Sharma

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Download electric from the link http://cmosedu.com/cmos1/electric/electric.htm
and LT-Spice from the link http://www.linear.com/designtools/software/ and install
LT-Spice. Also, ensure that JAVA is installed on your system.
Double click on the downloaded .jar file to start Electric VLSI. This opens Electric with
default 64 MB memory. For larger designs, the memory required is more and hence,
change the default memory allocation to 512 MB by going to File -> Preferences ->
General -> General in the following way.

LT-Spice is required for running simulations with Electric and hence, Electric should
be set up to use LT-Spice for simulations. Go to File -> Preferences -> Tools ->
Spice/CDL and make the changes shown in the following figure. Note that Run
Program should have the address where LT-Spice has been installed on the system.

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Next, go to menu item Window -> Color Schemes -> White Background Colors.
Electric is being set up for use in on Semiconductor’s C5 process and fabrication
through MOSIS.
This tutorial uses the MOSIS scalable CMOS (SCMOS).
While the C5 process is an n-well process, the p-well, which will be ignored during
fabrication, will still be drawn just to make the layouts more portable between
processes.
Next, go to File -> Preferences (or just hit the wrench/screwdriver menu icon) then
Technology -> Technology to get to the window seen below.
Change the information to match what is seen below. Note that the “Analog”
Technology is selected. This selection shows the resistor and capacitor Nodes unser
the Components tab.

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Next, the scale (lambda) for the C5 process is 300 nm using the MOSIS Scalable
CMOS (mocmos technology in Electric, see image above) submicron design rules. To
set the scale, go to File -> Preferences -> Technology -> Scale and set mocmos scale
to 300 nm as shown below.

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Click on Mark All Libraries for Saving in the File menu to ensure that the changes
made are reflected in all the libraries.
Now, the key bindings for various frequently used operations will be set up in Electric
such that every time, going to the menus is not required and the operations can be
performed using the keyboard shortcuts only. The following key bindings will be set –
(a) Fill Window – F9
(b) DRC – F5
(c) Well Check - W
(d) NCC (LVS) – L
Go to File -> Preferences -> General -> Key Bindings -> Window -> Fill Window as
shown below and set the key binding to F9. Click on Add and Check for conflicts.
Conflicts happen when more than one operation is set to the same key and make
sure there are no conflicts. In case there are, click on the Remove All button.

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Now, go to File -> Preferences -> General -> Key Bindings -> Tools-> DRC. Click on Add
and bind it with F5. Check for conflicts and make sure there are none.

Similarly, set the key binding for NCC (LVS) and Well Check to L and W respectively.

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One of the electrical rule checks (ERCs) is to verify that the p-well (here, this means
p-substrate) is always connected to ground. Further, in this n-well process, if the
design contains only digital circuits, then always the n-well must be connected to
VDD.
To setup the ERC Well Check, go to File -> Preferences -> Tools -> Well Check and do
the following settings.

To avoid making all the manual settings as explained above, just download
electricPrefs.xml in which all the settings are made and previously stored and to
import these, go to File -> Import -> User Preferences followed by navigating to
where the preferences were saved. We now have Electric set up to fabricate a chip in
the C5 process via MOSIS (technology code is SCN3ME_SUBM with a lambda of 0.3
um).

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A TUTORIAL ON SCHEMATIC
DESIGN IN ELECTRIC VLSI

BITS PILANI, PILANI-333031

Prepared by
Pawan Sharma

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 This is a tutorial on how to design a schematic in the Electric VLSI
software. The schematic of a D flip-flop has been designed in this
tutorial to show the steps of how a schematic is designed in this
software.

(i) Go to cell->new cell and select schematics view.

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(ii) Next, go to the Components tab and select/place the NMOS Node, circled, as
shown below.

(iii) Fill the window using Ctrl+9 and then, edit the node properties by selecting
the NMOS and pressing Q.

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(iv) Resize the width to 10 and the length to 2 and press OK. The final figure will
look like the following.

(v) Next, select the NMOS Node (symbol) and go to Tools -> Simulation (Spice) ->
Set Spice Model. The following figure is obtained.

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(vi) Edit the SPICE-model text using Ctrl+I.
In the C5_models.txt file which is used for the simulations, the NMOS model name is
NMOS and the PMOS model name is PMOS. Hence, change the model name to
NMOS and Rotation to 270 as shown below.

The final figure will look like the following.

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(vii) Repeat the same series of steps for PMOS (selecting the PMOS model in the
Components tab). The following figure is obtained.

(viii) Copy the instances of PMOS and NMOS (by selecting each model and the
pressing Ctrl+C and CTRL+V).
A, B and AnandB are off page nodes. Select the off-page node in the
components tab and place it in the schematic. Copy it and place three such
nodes.
Click on each of the node and press Ctrl+E. A following window will appear.
Write the export names of the pins (A,B and AnandB) and select OK.

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(ix) Wire the circuit in the following manner using Left Click for starting node of
the wire and Right Click for the ending node. The final schematic of the NAND
gate will look like the following.

(x) Then use View -> Make Icon View to make a new icon view. This view will be
instantiated in the schematic as seen below. Remember that this view will be
instantiated in the schematic as shown below.

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(xi) Go into the icon view and delete the box. Show the grid (Ctrl+G). Rotate and
move the AnandB Pin/Arc as shown below.

(xii) Next, add a circle and change its properties so that “Degrees of circle” is 180
as shown below.

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(xiii) Rotate this semicircle and add another circle. Change this added circle so that
both its x and y sizes are 1.

(xiv) Move the objects to start forming the icon of the NAND gate.

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(xv) Next, add the Opened-Polygon Node to the icon.

(xvi) With the Node selected use Edit -> Modes -> Edit -> Toggle Outline Edit (or
just press Y) to change the shape of the Node. When in this mode the mouse
pointer changes to a pencil, to add a vertex to the Polygon right click the
mouse button in the same manner as adding to an Arc. To exit press Y again or
use the menu Edit -> Modes -> Edit -> Toggle Outline Edit.

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(xvii) Adjust the shape of the polygon until it looks like the following.

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(xviii) Go back to schematic view and move the instantiation of the icon until the
contents of the cell look similar to the following.

(xix) Turn off the grid and save the library. Before moving on to the layout let’s
simulate the operation of this NAND gate. Make schematic view of a cell
called NAND_sim. Place the NAND_2 icon into this cell and connect Arcs to the
inputs and output as shown below.

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(xx) Label the Arcs and add Spice Code and power as seen below. Spice code is
found under the arrowhead on the Misc. menu item. Make sure to check your
design, F5.

(xxi) Do the similar thing to make NAND_3 model. This NAND gate takes three
inputs A,B and C and gives (A nand B nand C) as the output. One additional
PMOS and one additional NMOS is required for this design and the design
procedure remains same as that for the 2-input NAND gate. Here, the PMOS
size is 10 and NMOS size is 15. The schematic for 3-input NAND gate is shown
below. Also, create an icon view for the 3-input NAND gate and let the symbol
be a rectangular box only (no need to make the actual gate icon, that was only
for the understanding).

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(xxii) Now, create a new cell named d_ff (schematic view). Drag the instances from
the icon views of NAND_2 and NAND_3 and wire them to get the following
circuit.

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(xxiii) Make the icon view for d_ff as well and arrange the inputs and outputs to get
the following.

(xxiv) To check its functionality, put reset to vdd (using the power symbol from the
components tab).

(xxv) Then, add the following spice code by going to Components->Miscellaneous

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(xxvi) Now go to Tools->Simulation (Spice)->Write Spice Deck as shown below to
open LT-Spice.

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The following window would appear.

(xxvii) Now, click on the Waveforms icon as highlighted in the above figure. The
following would appear. Select the signals which are required to be plotted
(V(clk), V(d) and V(out)).

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Click OK and the following plot would be obtained.

(xxviii) Close the LT-Spice window. The following window is pops up. Go to the
Explorer tab and select d, clk, out from the trans-signals to obtain their
waveforms in Electric VLSI.

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 A TUTORIAL ON LAYOUT
DESIGN IN ELECTRIC VLSI

BITS PILANI, PILANI-333031

Prepared by
Pawan Sharma

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This is a tutorial on how to design a layout in the Electric VLSI software.
The layout of a D flip-flop has been designed in this tutorial to show the
steps of how a layout is designed in this software.
(i) Click on Cell->New Cell. The following window pops up.

Select layout view and name the cell as NAND_2.

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 (iii) Select each one of them. To select two, first select one and then, while
holding down on the Shift key, select the other. Press Ctrl+I for node
properties and set the rotation as 90.

The following figure will be obtained.

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(iv) Select each one of the components and change the width to 10 in the node
properties. Keep the length as 2 only.

(v) Select nAct node under the Components tab and place it on the sides of 2
nMos as shown below. Similarly, place the pAct nodes as shown.

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 (vi) Now select n-well and p-well under the Components tab and place them as
shown.

(vii) Set the y-size of pAct and nAct as 10 and x-size of n-well and pwell as 30 by
editing their properties.
The following figure will be obtained -

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(viii) Wire the pAct nodes and PMOS and nAct nodes and NMOS in the similar
way as in the schematic and the following figure will be obtained.

(ix) Take them close to each other just by selecting the using the Left mouse
click and moving them such that they just overlap to get the following.

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(x) Join the gates of nMos and pMos (similar to wiring) as shown below to
match the schematic.

(xi) Wire the circuit using Metal-1 arc (blue coloured metal) under the
Components tab as shown below.

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(xii) Select Metal-1-Polysilicon-1-Con under the Components tab and place it in
the layout at 2 places as shown below.

(xiii) Connect them to the two gates as shown below.

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(xiv) Select Metal-1-Metal-2-Con under the Components tab and place it at 3
places in the layout as shown below.

(xv) Connect them using Metal-1 as shown in the figure below.

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(xvi) Next, move the pins placed above as shown in the figure below.

(xvii) Export A,B,AnandB,vdd and gnd by selecting the particular pins and
pressing Ctrl+E. The figure will look like the following figure.

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(xviii) DRC the layout by selecting DRC in the Tools menu to ensure that there are
no errors in the layout.

(xix) Now, make create a new cell called NAND_sim. Instantiate the NAND_2
layout into this cell by dragging the NAND_2 layout and add Arcs as shown
in the figure. DRC the resulting layout to ensure that there are no errors.

(xx) Label the metal2 arcs as in, vdd, and out (corresponding to the labeling in
the schematic. Now, export the vdd and gnd pins and perform Well Check
in the Tools menu.

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 (xxi) Copy the Spice Code from the figure view and increase the text size to 3.
Note that the size of the vdd and gnd exports is acceptable; however, the
Arc names are difficult to see. Increase the Arc name text size to 5 then
perform a DRC, Well Check, and NCC in the Tools menu.
The layout/schematic don’t pass the NCC check. When the power symbol is used in
the schematic, export the vdd pin using Ctrl+E after connecting as shown below.
Simply connect the vdd and NAND input together as shown in the layout below. DRC,
NCC, and Well Check the resulting layout (it should pass now).

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(xxii) Follow the same steps to get the layout of a 3-input NAND for the NAND_3
schematic. The following layout will be obtained.

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(xxiii) Follow the similar procedure and drag the schematic of NAND_3 in
NAND_Sim1 cell (create this cell) and draw the following inputs and
outputs.

(xxiv) Now make a new layout view. Exports the pins in NAND_2 and NAND_3
and drag them in to this layout view. Now wire them according to the
schematic of the D flip flop to match the layout shown below.

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(xxv) Check for DRC, LVS and WELL errors (there shouldn’t be any). Add the
Spice code by going to Tools->Simulation (Spice) ->Write Spice Deck.

(xxvi) LT-Spice window will open similar to the simulation of the schematic.
Select appropriate waveforms (V(clk), V(out) and V(d)). The following will
be obtained.

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(xxvii) Now, close the LT-Spice window and select the clk, out and d waveforms
under the Explorer tab in Trans-signals so that the final output is obtained
in the Electric window.

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