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University of Ottawa
School of Information Technology and Engineering

Name (surname, first name):____________________________________

Number:___________________________________________________

Please circle CEG2131A CEG2131B

CEG2131A&B Computer Architecture I

Examiners: Professor Dan Ionescu

Professor A. H. G. Al-Dhaher

Final Examination, December 11, 2003 Time allowed: 3 hours

Notes:

 You may use the back of the pages for any side work. This will not be
marked.

 Instruction formats and PSR format for the ARC are given on page 8.

 ARC ALU operations are given on page 9.

 Microprogram for the ARC is given on page 10 & 11.

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Question 1 (20 marks):

The following 10 questions are a multiple-choice type. Circle the correct answer.

1. Converting (167)8 to decimal number is equal to:

(a) 119
(b) 504
(c) 55
(d) None of these

2. Converting (12B)16 to decimal number is equal to:

(a) 43
(b) 299
(c) 3652
(d) None of these

3. The ARC architecture contains 32 bit program counter, the purpose of this counter is:
(a) Keeps track of instruction being executed
(b) Shows size of the program
(c) Shows size of the memory
(d) Keeps track of return address

4. In ARC architecture the state of the processor is given by:

(a) PC
(b) SP
(c) Link register
(d) SPR

5. In ARC architecture sethi instruction is used to:

(a) Increment the stack pointer
(b) set the high 22 bits and zero the low 10 bits of a register
(c) Store a value in a certain memory location
(d) None of these

6. The ARC ALU operations include ADDCC and ADD, these operations:
(a) Both carry out additions using two’s complement on A, B buses
(b) The first one (ADDCC) only carry out additions using two’s complement
(c) The second one (ADD) only carry out additions using two’s complement
(d) None of them carry out additions using two’s complement on A, B buses.
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7. In order to access data item whose address is known at assembly time we use:
(a) Immediate addressing mode
(b) Direct addressing mode
(c) Indirect addressing mode
(d) Register indirect addressing mode

8. In ARC architecture, the ALU operation RSHIFT5 (A) do:

(a) Shift the operand on A bus to the right by 5 bits, copying the left most
significant bit into the 5 new bits on the left
(b) Shift the operand on A bus to the right by 5 bits, putting zeros into the 5 new
bits on the left
(c) Shift the operand on A bus to the right by 5 bits, putting ones into the 5 new bits
on the left
(d) None of the above

9. In microprogramming the first line: R[i]  AND(R[PC], R[PC]),

(a) Clear the value of the PC
(b) Double the value of the PC
(c) Put the value of the PC on the A bus
(d) Clear the value of the instruction register

10. Given 16M x 1 bit RAM module, in order to construct 32M x 8 bit RAM you need:
(a) 8 modules
(b) 16 modules
(c) 32 modules
(d) None of the above
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Question 2 (20 marks):

Part A (12 marks)

(i) The following is a single-precision IEEE 754 bit pattern. Show the numerical value as
a base 2 significand with an exponent (e.g. 1011 x 24). Note: spaces are only shown for
clarity

1 1000 0000 0000 0000 0000 0000 0000 000 Answer:.. - 1 x 21……

(ii) Write the IEEE 754 single precision bit pattern for the following number:

- 1 x 23 Answer: 1 1000 0010 0000 0000 0000 0000 0000 000…

(iii) Add (255)10 and (-63)10 in signed BCD, using four-digit words.

Solution:
to get the tesn’s complement of 120:
9999
- 0063
9936
1
9937

0000 0010 0101 0101

1001 1001 0011 0111
0000 0001 1001 0010
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Part B (8 marks):

Show the process of serial unsigned multiplication for 11.1 (multiplicand) multiplied by
01.1 (multiplier) by treating the operands as integers. Compare your results to its decimal
equivalent.

Initial values

Multiplicand (M):

111

C A Q Comments
000 011
0 111 011 Add M to A
0 011 101 Shift right
1 010 101 Add M to A
0 101 010 Shift right
0 010 101 shift right
0 010 1.01 fixed decimal
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Question 3 (20 marks):

i) Write three-address, two-address, and one- address programs to compute the function
A= (B-C)*(D-E). Assume 8-bit opcodes, 16-bit operand and addresses and that data is
moved to and from memory in 16-bits chunks. Also assume that the opcode must be
transferred from memory by itself. Your code should not overwrite any of the
operands. Use any temporary registers needed.
ii) Compute the size of your program in bytes.
iii) Compute the memory traffic your program will generate at execution time, including
instruction fetches.

Solution:

3-addresses 2-addresses 1-address

SUB B, C, A MOV B, A LOAD B
SUB D, E, Tmp SUB C, A SUB C
MPY A, Tmp, A MOV D, Tmp STO Tmp
SUB E, Tmp LOAD D
MPY Tmp, A SUB E
MPY Tmp
STO A

Size 7 x 3 = 21 bytes 5 x 5 = 25 bytes 3 x 7 = 21 bytes

Traffic 3 x 4 + 3 x 3 = 21 5 x 3 + 2 x 2 + 3 x 3 = 28 7 x 2 + 7 = 21 words
words words
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Question 4 (20 marks):

Part A (10 marks)
The binary words of a micro-coded macro in the ARC assembler are given below.

Each of he binary words can be interpreted as a microinstruction.

i) Write the mnemonic and the comments, i.e the micro-operations corresponding
and comments, to each of the binary words using the ARC micro-assembly language
as introduced in the class (Chapter 6 of your textbook on datapath and control).
ii) What are the op and op2, and op3 codes for the macro and what operation is the
macro implementing?

Solution:
(i)
1584: R[temp0]  SEXT13(R[ir]); /extract rs2 operand

IF IR[13] THEN GOTO 1586; /Is second source immediate?

1585: R[temp0]  R[rs2]; /extract sign extended

/immediate operand

1586: R[temp0]  NOR(R[temp0], R[0]); /Form one’s complement of

/subtrahend

1587: R[temp0]  INC(R[temp0]); GOTO 1603; /form two’s complement of

/subtrahend

(ii)
1584 = 1024 + 512 + 32 + 16
= ( 1 10001100 00 )2

op = 10
op2 = 001
op3 = 001 100
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Part B (10 marks)

Assume that the ARC computer is to be designed, and you are one of the designers. You
are required to extend the ARC instruction set to include a new instruction called
exclusive-NOR or the equivalence and it assembler name is xnorcc – which means that it
performs and exclusive NOR on the operands, and sets the condition codes accordingly.
This new assembler instruction is an Arithmetic format instruction. The op3 field is
010011. Write the microprogram that implements this new instruction giving also the
comments.

Solution:
A B XOR XNOR
0 0 0 1
1 0 1 0
0 1 1 0
1 1 0 1

XNOR = AB + A B

let rs1 = A, rs2 = B

1612: IF IR[13] THEN GOTO 1614; /is second source operand

/immediate

1613: R[temp0]  R[rs2]; /get B operand in temp0

GOTO 1615;

1614: R[temp0]  SIMM13(R[ir]); /Sim B and put it in temp0

1615: R[temp1]  R[rs1]; GOTO21;

21: R[temp2]  NOR(R[temp0], R[temp0]); /get complement of B in temp2

22: R[temp3]  NOR(R[temp1], R[temp1]); /get complement of A in temp3

23: R[temp1]  AND(R[temp1], R[temp0]); /temp get AND (A,B)

24: R[temp2]  AND(R[temp3], R[temp2]); temp2 gets AND(A , B)

25: R[rd]  ORCC(R[temp1], R[temp2]);

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Question 5 (20 marks):

Part A (10 marks)
A Programmable Read Only Memory (PROM) is used to implement an ALU. The
configuration of the PROM ALU is shown in the Figure below.

Fill in four memory locations for the lookup table shown above, in which each of the four
operations: add, subtract, multiply, and divide are performed on A=16 and B= 4. Show
the address and the value for each case.

Solution:
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Part B:
A Random Access Memory (RAM) unit is designed using 8x8 RAM chips. In this
question you are required to design a 32-word memory unit, whose word is on 32 bits
using the above chips. Give all the details of your design showing how the data in the
designed memory is written or read from a specific address.

Solution:

Similar to the combination of the two solutions given below, in one single diagram
containing four rows and four columns.
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Instruction formats and PSR format for the ARC

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ARC ALU operations

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Microprogram for the ARC (continues on next page)

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Microprogram for the ARC (continued from previous page)