Computer Interfacing

CSE 360
Lectures

Prepared By

Ejaz Jamil
Contact
Name: Consultation Hours:
Ejaz Jamil Mon, 2:00-3:20PM,
In the Lab,
and on Appointment
Email:
[email protected]
Office:
12 Kalabagan 1st Lane
Phone: Dhaka 1205
01776196371
 Sections
1 Classes: 2 Classes:
Mon (UB30602)
Mon, Wed (UB30603)
9:30-11:00AM
3:30-4:50PM
Thu (UB30401)
Lab:
Thu (UB50201,UB60806) 12:30-2:00PM
2:00-4:50PM Lab:
Mid Term: Monday (UB40401)
11:00AM-1:50PM
February 27
Mid Term:
Final:
February 27
April 8
Final:
Project:
April 8
April 7
Project:
April 7
I Instructors Discretion
N
F Grading Attendance 5%
O Extra Credit 10%

Quiz 1 5%
Quiz 2 5%
Quiz 3 5%
Homework 20%
Final Exam 30%
Mid Term 15%
Sub Total 80%
Product Design Project 10%
Lab + Lab Assignments 10%
Total 100%
I
N
T Syllabus Hardware Coverage:
E Sensors/transducers

1. Hardware Interfacing
R 
Datasheet Analysis
Multiplexing
Memory (SRAM, DRAM, SDRAM, DDR)
F 
Hardware Design using Timing

A Datasheet Display (LED, LCD, OLED, Raster)

Power Electronics
C 
Eagle Cad Schematic DC Motors (Brushed, Brushless, Stepper)

I

PCB Design 4. AC Motors (Induction, Synchronous)

Product Design 8. Heatsinking
N Serial Interfaces (I2C, RS-232, 422, 485, USB, 1394,

Prototyping
G 
2. Software Design
SATA, SAS)
10. Power Supplies (Standard, Switching)

Writing Generic Micro 11. GPIO
12. Bus Interfacing
Kernel
13. DMA

IPC and I/O 14. Parallel Interfaces (SCSI, ATA, PCI)

Event Driven Programming 15. Wireless

Interrupts UARTs

Timers & Watch Dog 17. Hard Disks, SSD
19. Laser

Device Drivers
Input Devices (keyboard, touch, mouse)

Memory Management A/D - D/A Converters

User Interface

Multi-processing
I
N
T
R Text Books
O
1. Volume 1, Introduction to ARM Cortex-M
Microcontrollers (fifth edition, 2nd printing- June
2014), 2014, ISBN: 978-1477508992
2. Volume 2, Real-Time Interfacing to ARM Cortex-
M Microcontrollers (fourth edition, 1st printing
June 2014), 2014, ISBN: 978-1463590154
3. Volume 3, Real-Time Operating Systems for
ARM Cortex-M Microcontrollers (third edition,
9/2014), 2014, ISBN: 978-1466468863

Valvalno's UT Austin Page:

http://users.ece.utexas.edu/~valvano/
Product Design Flow

1. Is it necessary? Will it sell?

2. Price? Is it competitive?
3. Availability of parts?
4. Budgeting
5. Specification
6. Design
a. Mechanical b. Electronic c. Parts
7. Test
a. Mechanical b. Electronic c. Parts
8. PROTOTYPING
I
N
F
O Project

A working electronic project with 4 or more sensors or
I/O devices

Options: Arduino, PIC, Raspberry PI, Banana PI,
MSP430, ARM Cortex. (Other boards, please let me
know)

Interface the sensors

Design and Etch PCB

Develop the Software

3D Print Enclosure

Write the User Interface (if Display present)

Demonstrate

Presentation

Submit Report (In IEEE paper format)
I
N
F
O Project Deliverable
1. Presentation (10 minute, equally divided to
each member.
2. Working demo (10 minute)
3. Datasheet (5 minute)
4. How to market, proposed funding
requirements, pricing. (5 minute)
5. Paper submission (one paper per group) (5
minute)

See sample template:

\Homework\IEEE_Conference_Paper_Template.doc
I
N
F Product Design Goal
O
Your product must focus on one or more of the
following. You goal is to design a product not just
learning but also to create a benefit.

1. Something you can Sell.

2. Something that solve and existing problem.
3. Something that can create export.
4. Something that can create jobs.
5. Something that can reduce imports.
6. Something that compete with a foreign product.
7. Something that no body have done before.
8. Something that implements a great idea even
though there is no exclusive need for it.
Report Template
REPORT SHOULD BE IN TWO COLUMN

Abstract: (required)
Introduction: (required)
Topic titles: (these titles are related to the subject matter of the paper)
Summary: (required)
Author Biography: (optional)
Acknowledgments: (optional)
References: (required)

See sample template:

\Homework\IEEE_Conference_Paper_Template.doc
I
N
F Microcontroller
O
MSP430F413x
I
N
F Abbreviations
O

1. JTAG = Joint Test Action Group, a standardized

method of testing printed circuit board.
2. WatchDog = controlled system restart after a
software problem occurs or a general count down
timer.
3. RISC = Reduced Instruction Set Computer (ARM)
4. CISC = Complex Instruction Set Computer (Intel
x86 processors)
5. FRAM = Ferroelectric RAM, similar to Flash, uses
ferroelectric material (electrical hysteresis) instead
of dielectric
D
A
T
A Understanding Datasheet
S Datasheet is the detailed information of a chip
H
E Sample circuits
E Detailed timing diagrams
T Detailed operations
Detailed technical data
Architecture
Block diagram
Interfacing methods
Application data
Typical application
D
A
T
Datasheet – No
A
S
Breadboarding
Studying datasheet thoroughly will need
H
E no breadboarding
E Breadboarding is almost impossible for a
T
processor with pin-count over 64.
Breadboarding causes too much
capacitance and inductive interference
Breadboarded circuits must be
underclocked
Prone to error and misconnection
N
O
T
E SCHEMATIC DESIGN RULE
S
ALWAYS PUT ALL COMPONENT VALUES
ALWAYS SHOW VCC VOLTAGE
ALWAYS SHOW GROUND (GND)
KEEP THE CIRCUIT READABLE
BREAK CIRCUIT INTO MULTIPLE PAGES IF
NEEDED
USE LABELS IN ALL ICs
SHOW ALL COMPONENT NAMES
SHOW PIN CONNECTION

SOLUTION? USE EAGLE CAD FOR SCHEMATICS

D
A
T Interfacing
A
S
H
E
Mechanical
E Design
T

Man Machine PCB

Interfacing
Interface Design

GUI
D
A
T Prototype Design
A
S Mechanical DesignSpark
3D Printing
H Design Mechanical
E
E
T Electronic
Eagle CAD
Schematic PCB Layout PCB
Design Design Design Etching

Solder Mask
Metal Stencil
Etched
Solder Paste Pick & Place
PCB
Solder Mask
UV Method

Completed Reflow
PCB Oven
 Brake
Simple 3 story elevator
Flywheel
Speed Control Motor
Speed
Control
Sensor
M = We-Wc
3 1 Horsepower = One metric horsepower
Hall Sensor is needed to lift 75 kilograms (avg. body
Accelerometer L1 weight of a person) by 1 meter (3.28 feet)
in 1 second.

Pressure
Sensor
We F2
2
Work = Mg(3h)
L2 Magnet

Counterweight
F1 How many
1 horsepower motor is
Wc needed?
Alignment
Sensor
W1 h 10 hp
F0
10 people
W2
0
Hydraulic Damper or
Shock Absorber
S
E
N
S Sensors - Accelerometer
O
https://www.sparkfun.com/products/10953
R
S

m F=ma
m Piezoelectric

m Capacitor
Si
S
E
N
S Accelerometer Integrator
O
R
S C
C
from
Accelerometer,
Vacc Vn i
R
Velocity Vn i
R
Distance
i Vp
i Vp
Opamp Opamp
Integrator Integrator

INS = Inertial Navigation System

S
E
N
S (Hall effect)
O
Can be used for alignment
R
S
S
E
N
S Sensors – Hall Effect
O
Voltage changes under magnetic field
R
S
S
E
N
S
Sensor – Optical Proximity
O
Sharp FLX-A201-A Optical Proximity Sensor
R
S Reflector
LED

PHOTO
DIODE

In Proximity
 Von Neumann vs Harvard
Arch.
Program and Data memory Program and Data memory
are same. are separate.
BUS INTERFACING

●
Modern processors use
Harvard Arch.
●
Reads Instruction and Data at the same
●
Cannot read Instruction and Data at the time
same time ●
Data memory may be of different byte
●
Data memory must be same length as length than Instruction
Instruction
 Bus – Data, Address, Control
bus
A tri-state bus which is shared by all
devices
BUS INTERFACING

In Tri-state, only one device

can access the bus at any
one time.
 Interfacing - Chip Select
Chip
Select
BUS INTERFACING

Display
CPU

If chip select is not enabled,

it is as if the chip does not
exist. Memory
All I/O are in Z state.
Control
Logic (Note: consult the datasheet
for actual behavior)

I/O
 Bus Errors/Conflict
Only one I/O is allow to share a bus at any one time as
OUTPUT.
If two or more I/O use the bus as OUTPUT causes bus
BUS INTERFACING

conflict.
If one I/O is used as OUTPUT and multiple I/O are used
as INPUT causes NO bus error.

Causes of Bus Error:

1. Caused by multiple device using the bus as Output
2. Wait states are not maintained
3. If an I/O device causes the bus pin to stuck at 1 or 0.
4. Caused by glitch.
 GPIO – General Purpose IO
Software configurable IO ports of a
processor or chip.
BUS INTERFACING

I/O Types:
1. Open Drain
2. Open Collector
3. Read Only
4. Write Only
5. Read/Write
6. TTL
7. Unbuffered
 Electrical Characteristics of
Pins V IH,max
This transistor does not
VCC VIH,min
exist in Open Drain ICC
Output VIL,max
ELECTRICAL ANALYSIS

0V
I/O VIL,min
IS
VCC = Supply Voltage
TS ICC = Supply Current
RPU IS = Source Current
Vout IK = Sink Current
IIL RPU = Internal Pull Up Resistor
RPD = Internal Pull Down Resistor
Vin VIH,max = Max logic high voltage
VIH,min = Min logic high voltage
IIH TK VIL,max = Max logic low voltage

RPD CI VIL,max = Min logic low voltage

IK CO Imin = Max current dissipation
IIL = Input leakage current, input
Imax LOW
IIH = Input leakage current, input
HIGH
Vout = Tri-State → TS & TK are CI = Input capacitance
OFF GND CO = Output capacitance
Glitch

B
Y
A
Inverter Delay

AND Delay

A
B
Y
 74, 54 and 40 Series Glue
Logic ICs

Used for interfacing with other circuits

74 and 54 is the Transistor Transistor Logic
GLUE LOGIC

(TTL), presently have CMOS version.


Modern 74 → 74HC

Modern 54 → 54HC

40 series is a CMOS series.

See \Lectures\GlueLogic for 74, 54 and 40

series datasheets. Other datasheets of
specific IC is also available.
 Heat Sink
Heatsink is required in all power circuits that dissipate
continuous power.
To select appropriate heat sink, choose a lower thermal
resistance Heatsink with that of the IC.
MOTOR

Thermal resistance is the rise of temperature per watt of

electrical power dissipation. It is measured in oC/W.
Heatsink may be inadequate to cool down the IC at the rate
the IC is heating up. In that case, fan may be employed to
rapidly remove the hot air from the heatsink.

AAvid Thermalloy (http://aavid.com) one of the well known

manufacturer of heatsinks.
 ASIC – Application Specific IC

Usually created using Verilog or VHDL
EDA tool

The generated RTL is transferred into IC
GLUE LOGIC

by fabrication
 FPGA – Field Programmable
Gate Array

FPGA is an array of gates

Interconnection between gates are
GLUE LOGIC

programmable

Put all your external logic gates into a
single FPGA

Minimize chip count by using FPGA

Popular FPGA vendors: Xilinx, Altera

Density: 1M+ gates

Use VHDL or Verilog to build your logic
circuit.
74HC Series by Function
Buffers/inverters/drivers Analog switches
Bus switches Decoders/demultiplexers
Counters/frequency dividers Digital comparators
Encoders Digital multiplexers
Gates FIFO registers
- AND gates Flip-flops
- Combination gates Full adders
- Configurable multi-function Level shifters/translators
gates Multivibrators
- EXCLUSIVE-NOR gates Parity generators/checkers
- EXCLUSIVE-OR gates Phase-locked loops
- NAND gates Schmitt triggers
- NOR gates Shift registers/LED drivers
- OR gates Transceivers
Latches/registered drivers

See details: Lectures\GlueLogic

Load Consideration – Fan In
Fan In = Number of inputs that a gate can accept

Wired And
CO1 . RO1 .
. .
. .
. .
. .
. .
CO2 . RO2 .
. .
CO = CO1 + CO2 + 1 1 1 1
= + +
CO3 R I RO 1 R O 2 R O 3

CO3 RO3

Effects Fan In
- Input Capacitance Increases
- Input Resistance Decreases
 Load Consideration – Fan
Out
Fan Out = Number of outputs that a gate can drive

RI1

. .
CI1 .
.
. .
. RI2
.
. .
. .
. CI2 .
. .
1 1 1 1 RI3
= + +
CI = CI1 + CI2 + CI3 RO RI 1 RI 2 RI 3

CI3

Effects
- Input Capacitance Increases
- Output Resistance Decreases
- Source IS & Sink Ik current is shared by more inputs
Open Drain/Collector Output
Some device's output is open drain (for CMOS) or collector (for
bipolar) to allow the following:

1. Wired AND operation.

2. Larger load capability. VCC VCC
RL RL
Outside Device
Inside Device
Open Drain Open Collector

TK TK

Effects
- If a terminal is open drain or collector, the terminal must pass through a
load to VCC.
 Simple Zener Regulator
V CC −V Z
VCC RM=
IM

IM Zener Rating: VZ &

ELECTRICAL ANALYSIS

RM
IP = I A + IB + … + I K IM
IM = IZ +
…
IP
VZ IA IB IK
IZ
A B … K

How to calculate Zener Rating for voltage

regulator use.
 Zener Network
VCC

IM
RM
ELECTRICAL ANALYSIS

IM = IZ + RP VA RAB VB … RBK VK
IP
VZ IA IB IK
IP IAB IBK
IZ Z
IZA
A RA IZB
B RB … I K RK
ZK

How to calculate Zener Rating for voltage

regulator use.
Zener
Ratings:
Z → V Z & IM IBK = IZK + IK R BK=
V B −V K
RM=
V CC −V Z
I BK IM
A → V A & IP IAB = IZB + IB + IBK R AB =
V A −V B
I AB
B → VB & IAB IP = IZA + IA + IAB V Z −V A
K → V K & IK R P=
IP
 Current Limiting Resistor
Forward Diode Drop, VCC VCC
VD:
V CC −V D
1. Diode = 0.7V RP R P=
IK
2. LED = 2.0V
ELECTRICAL ANALYSIS

3. Zener = 0.7V V CC −V D
R P=
VD = IS
Diode
Drop RP
I/O I/O
IK IS VD =
Diode
IK = Sink Current Drop
IS = Source Current
RP = Current limiting/protection
resistor
How to find the value of current limiting resistor to drive LED

NOTES
1. Always consider Diode Drop (0.5V – 0.7V for diode/zener, 2V for LED)
2. Get IK and IS from datasheet
3. Do not use value less than protection resistor RP.
 Wrong Circuits
VCC VCC
Missing RP Missing RP
ELECTRICAL ANALYSIS

I/O I/O
IK IS
IK = Sink Current
IS = Source Current
RP = Current limiting/protection
resistor
How to find the value of current limiting resistor to drive LED

NOTES
1. Current limiting resistors must be present.
2. Excessive Source or Sink current will flow, if the limiting resistor is not
present.
3. Excessive heat will be generated.
4. Will damage the LED
 Zero Crossing Detector
Positive Cycle Current How to calculate value of current
Diode Drop, limiting/protection resistor.
0.7V
On each Diode
ELECTRICAL ANALYSIS

VS
VS = 2 * 0.7 + RP.IT + 2.0
AC → RP.IT = VS – 3.4
V S −3 . 4
R P=
IT

Positive Cycle Choose a Vs at which the Opto-

Current
Transistor is to be triggered.

RP IT
NOTE: LED voltage drop is higher
than diode voltage drop.

RED
LED Choose Opto-Transistor that meets:
Drop,
2V
Reverse breakdown voltage > VS,max
IT = Opto-transistor Trigger IT = current through RP
Current
RP = Current Protection Resistor
 Level Translator
ELECTRICAL ANALYSIS

High Low
Voltage Voltage
Logic Logic
Level
Translator

NOTES
1. Low and High voltage circuits are isolated.
2. Assures proper level translation without overdrive.
3. Interfaces low voltage powered device with higher voltage powered
device.
4. Can be implemented with very simple circuits
 Level Translator Design
VCC,L VCC,H VCC,L VCC,H
ELECTRICAL ANALYSIS

RP RP RP

VLV VHV VLV VHV

Body Diode
VCC,L
VCC,H
VCC,H

RP VHV
VLV Inverted
Output
VLV VHV
 Transistor Properties
VCC V C =V CC −I CE RL =V CC −h FE I BE R L

I CE
where , h FE=
ICE I BE
ELECTRICAL ANALYSIS

RL

VB RB VC Typical hFE value is

Inverted 100
Output
IBE
VCC,L
Assume Low state sink
Current = 1mA
VCC,H
R PU =V CC , L∗1000 RB
RB =(V CC , L −0.7)∗1000 RPU RL
R L=V CC , H∗1000

For analog signals, computation of RL VLV VHV

and RB effects each other. Proteus IN OUT
simulation is required.
 Multiplexers Inputs

Output
BUS INTERFACING

Selector
 Demultiplexer
Input Output
BUS INTERFACING

Selector
 Johnson Counter
Johnson counter is
useful to delay pulses
BUS INTERFACING

by specific number of T
0
clock cycles.
1 T
2 2T
3 3T
0 4
1 5 nT
Input
6
Output
T 7

7
Outputs

n = bit index

Selector
 4017 Johnson Counter
Expansion
BUS INTERFACING

CLK CLK CLK

E E E
 Semiconductor Memory
System
SRAM – Fastest. Use: cache, buffer, pipeline
DRAM – Fast. Use: Mass memory, data
SDRAM – Fast with auto-refresh. SDRAM
MEMORY

today replaces DRAM in most cases. Has

built in commands. SDRAM has clock.
FLASH – Slow (NAND), slightly fast for NOR.
NAND for mass storage. NOR for boot
ROM and program memory.
FRAM – Faster than flash. Boot ROM and
program memory.
 SRAM
GENERAL MEMORY ACCESS CONCEPT

1 Bit Data Storage

cells

000 DRAM
Column Addr
Selector
B
CAS
Bit 7 1 0
line
0
A
MEMORY

1
Data
Word line Output
Logic

Row Addr
Selector
Address,
RAS
101011 RAS
001
(53h)
000 001

CAS

Memory access is designed on the above general concept where the cell intersected by two demultiplexer (address
decoders, A and B). The selected is then multiplexed into a common output. NOTE. The organization of each memory is
different, but the general memory access concept is similar.
 STATIC RAM
1. Very Fast
2. Used as On-chip Cache
3. Less dense than DRAM
4. Expensive
5. Retains data for little power
MEMORY
 DRAM File: Memory\DRAM_MSM5117400F.pdf

4 M x 4 DRAM
MEMORY

RAS CAS A* WE OE DQ*

0 1 row 1 1 X

0 0 col 1 1 X

0 0 - 1 0 data read

0 0 - 0 1 data to write

DRAM IS REPLACED BY SDRAM

 DRAM READ/WRITE TIMING

address
MEMORY

read write
 DRAM [Continued]
MEMORY

P or DMA
 Synchronous DRAM (SDRAM)
SDRAM has Clock
Micron MT48LC32M8A2 – 8 Meg x 8 x 4 banks
File: Memory\SDRAM_Micron_MT48LC32M8A2.pdf
MEMORY
 SDRAM ADVANTAGES

Read/Write burst mode.

Synchronized with main clock
MEMORY


Auto refresh feature

Built-in commands

Faster than DRAM
 READ/Write Burst
READ
MEMORY

WRITE WRITE/READ
 DDR SDRAM
File: Memory\DDR2_SDRAM_Micron_1Gb_DDR2.pdf
READ or WRITE

or WRITE
MEMORY

READ/WRITE
 Ferroelectric RAM (FRAM)
1. Practically no restrictions on read/write limits
2. Almost 151 years data retention
3. Fast serial interface (SPI or I2C)
MEMORY
 ATmega2560 Memory Map
MEMORY

See Datasheet: Atmel-2560-16-bit-mcu-doc2549.pdf

 ATmega 2560 [Continued]
MEMORY
 ATmega 2560 – External
SRAM
MEMORY
 ATmega 2560 – External Memory
MEMORY
 ATmega 2560 [Continued]
MEMORY
 ATmega 2560 [Continued]
MEMORY
 Flash Memory

NAND
MEMORY

NOR
 Micron 8GB NAND Flash
MEMORY
 Micron NAND Flash Page
Read Timing [Micron flash...]
MEMORY
 Micron NAND Flash Page
Read Timing [Micron flash...]
MEMORY
 Micron NAND Flash Random
Read Timing [Micron flash...]
MEMORY
 Micron NAND Flash Block
Erase Timing [Micron
flash...]
MEMORY
 NAND Flash NOR Flash

Read Speed One third the speed of NOR 3-4 times the speed of NAND

Erase Speed Fast Very Slow

Write Speed Fast Slow

Interface I/O Random Access

Density Twice the density of NOR Half the density of NAND

Power Low Power Consumption Significantly High

MEMORY

Erase Cycle 100K-1M Times 10K-100K Times

Bit Flipping More, needs error correction Less

Life 10x more than NOE Less

Device Driver Required Not Required

 USB Flash Drive IC
\Lecture\Memory\USB_FlashMemoryController_CD00055081.pdf


Contains the full circuit for a flash drive

USB 2.0

Supports Numonyx, Hynix, Samsung, Toshiba, Micron, Renesas
MEMORY

flash chips

Up to 12 MB/s for read and 8 MB/s for write operations in single
channel

Up to 4 NAND Flash supported per channel

NAND Flash support table (page 10, section 4.1)

Upto 4GB x 4 = 16GB flash support
 Micro SD
4 Bit bus
MEMORY
 Designing With Memory

1. Design a Memory Map

2. Design Address Decoding Circuit using Demux (or Decoder)
MEMORY

3. If there is a Address/Data Strobe needed by the Processors, Design

the Strobing Circuit
4. Connect the Address Bus to Processor's Address Bus
5. Connect the Data bus to the Processor's Data Bus
6. Connect the Memory Control Lines to Processor's Control Line
7. Connect the Chip Select to the Decoder output.
 LED Forward Voltage Drop
ELECTRICAL ANALYSIS
 7 Segment BCD
Light Test → Usually A, B, C, D →
connected to HIGH (Vcc). To BCD inputs.
test all the segments, set it to
LOW.

a
A a
b
B c
DISPLAY

C d f b
D g
74LS248 e
LT 74HC4511 f
BI g e c
RBI h
d h

Blanking Input → Usually Ripple Blanking Input →

connected to HIGH (Vcc). LOW Usually connected to HIGH
will cause display to go blank. (Vcc). Intensity of the display Current Limiting Resistors –
Depending on the current
may be controlled by passing
requirements of the 7-
ripple with varying pulse width.
segment, these resistor limits
the maximum current.
 Multi 7 Segment

Any microcontroller
DISPLAY

To output ports of microcontroller. Drive the

segments one at a time at 1KHz.

Multiple segments can be

added using scan technique.
 LED Matrix – 5x7, 8x8
●
Single or multi color
●
RGB available
DISPLAY
 Multiplexed Display (Raster
Type)
A and B are scanned
1=Off, 0=ON
until all LED are
addressed.

000

X
B LED
DISPLAY

Col 7 1 0 R G B
0
A 1 R
1= On Row G
0=Off
B
7

Y
Intensity of each LED
(3,5) is controlled by PWM
001 or Current Limiting
 Raster Timing
1/64 Frame
DISPLAY

1 Frame = 64
LED

30 Frames per second required for smooth display

 Single Chip Solution – MAXIM MAX 6953
DISPLAY

Model available in Proteus 8

 LCDs – Liquid Crystal
Displays
DISPLAY
 OLED
Operation

1. Voltage applied: Anode(+) and

Cathode(-).
2. Electrons from -ve terminal reach
emissive layer.
3. This emissive layer become negatively
DISPLAY

charged, conductive layer positively

charged.
4. Holes from conductive layer jumps
the boundary and meet a hole emitting
light.

Basic OLED
Construction
-
Cathode

Emissive Layer

Conductive Layer

Anode
+
 OLED (Continued)
Types of OLED Basic AMOLED
1. AMOLED = Active Matrix Construction
OLED
-
Cathode
2. PMOLED = Passive Matrix
DISPLAY

OLED Emissive Layer

Conductive Layer
PMOLED is composed of TFT (Thin Film Transistor)
+
OLED cells organized in
matrix without TFT. Storage In AMOLED, each OLED cell
Capacitor sits on a TFT.
Anode Each TFT also feature a
storage capacitor which holds
a charge to keep the LED
brightness high during
OLED cell is refresh.
sandwitched
Cathode

between andode
and cathode
 Pulse Width Modulation
By changing the pulse,
A the RMS value of the
V signal can be
DATA ACQUISITION

Vrms controlled

t
TH
T RMS of two pulse: RMS of three pulse:
2 a12+ a22 2 a12+ a22 +a23
a =
rms a =
rms
2 3
a1 a3 a4 a5 a6 an
RMS of n pulse:
... TH

t 2 2 2
a + a ... a
∑n a 2
n δt ∑ a
2
n ∫ a 2 (t)dt
a2rms=
1 2 n n 0
= = =
1 2 3 4 5 n n n n δt T
TH TH TH
1 1 A2 T
a = ∫ a (t) dt= ∫ A dt= ∫ dt= A2 H
2
rms
2 2
T 0 T 0 T 0 T

a rms= A
√ TH
T
=A √ D where, D=
√ TH
T
= duty cycle of the pulse
 Heat Sensors - Thermistor
Ni/Mn/Co Oxide

Thermistor
MORE SENSORS

Symbol PTC = Positive Temperature Coefficient, RT  KT

NTC = Negative Temperature Coefficient, RT  K/T
VCC

RT
10R
NTC Type
Thermistor R
To ADC

Features: 0.1RT

1. Non-linear response Opamp

2. Relatively sensitive Amplifier
3. Very inexpensive
 Heat Sensors – Thermocouple

Thermocouple
MORE SENSORS

10R

To ADC
Symbol
Features:

Opamp 1. Fairly linear response

R 2. High Temperature
Amplifier
3. Inexpensive
4. Long Lasting & Reliable
 Audio Sensor - Microphone

VCC
VCC

Rb

Rm
CF R R2
1
Permanently
Charged Electret
-
Diaphragm +

Rb

Mic DC
Bias Audio
Isolation
Circuit Pre Amp

R2
A=
R1
 Op Amps Ideal OpAmp
A=
Ri = 
Non- +VCC
Inverting Very Large Gain, Ro = 0
Input typically 106

Low Output Impedance

Very low voltage drop due
A
OP AMP

to internal impedance

Inverting -VSS
Input
Ro
+
High Input
Vi Ri AVi Vo
Impedance _
Current drain by
inputs are low

Gain = A
 Op Amps (contd.) V0

Vin
Non-inverting OpAmp

Vp
Vin R1
V n=( )V
Vo R1 +R 2 O
Vn The output is in phase
R2 with the input in non-
 V O=(1+ )V inverting configuration
OP AMP

R1 n
R2

For ideal OpAmp,

Vo = AVi = A(Vin – Vn)

R1
Vin – Vn = Vo / A = 0 [A → ]

Therefore,

Vin = Vn

R2
V O=(1+ )V in
R1
 Op Amps (contd.) V0

Inverting OpAmp Vin

R2

The output is in 180 degrees out

Vin R1 Vn of phase with the input in
inverting configuration
OP AMP

Vo
Vp For ideal OpAmp,

Vo = AVi = A(Vin – Vn)

Vin – Vn = Vo / A = 0 [A → ]

Therefore,

Vin = Vn
V in −V n −V o−V n
=
R1 R2
 V in −V o
=
R1 R2
R2
 V =−( R 2 )V V O=(− )V in
o
R 1 in R1
 Op Amps (contd.)
Summing OpAmp
R1 i0 R0
V1 i1 +i 2 +i+3=i 0

i1
Vn V 1 −V n V 2−V n V 3 −V n −V 0−V n
R2  + + =
V2 R1 R2 R3 R0
OP AMP

V 1 V 2 V 3 −V 0
i2 Vp Vo  + + =
R1 R 2 R 3 R 0
R3
V3
R0 R R
V o =−( V 1+ 0 V 2 + 0 V 3 )
R1 R2 R3
i3

For ideal OpAmp,

Vo = AVi = A(Vin – Vn)

Vin – Vn = Vo / A = 0 [A → ]

Therefore, R0 R0 R0
V o =−( V 1+ V 2 + V 3 )
Vin = Vn R1 R2 R3
 Input – Mechanical Switches
Push Buttons, Keyboards, Switch Arrays Interfacing
Input
A
B
MECHANICAL INPUT

C Keypad
A
X
Microcontroller
Y
1 2 3 Z
B
Inputs

Output

4 5 6 Each Outputs X, Y, & Z is held

C LOW and Inputs A, B, & C is
checked if they are also low. If an
Input is found LOW for a specific
Output, then switch at the
7 8 9 intersection is pressed.

X Y Z
Example: If Switch 5 is pressed,
Outputs then Y = LOW, B = LOW.
Disadvantage:
A keyboard scanning routine had
to run continuously.
NOTE: If the I/O ports have Input Pull Up
resistor, they should be activated. Ideal should be to scan only after
keyboard interrupt.
 Input – Mechanical Switches
(Contd.) +VCC Interrupt based approach +VCC

RPU
MECHANICAL INPUT

RPU RPU RPU Outputs

RPU>> RPD
XYZ
RPU resistors are used to pull the
inputs up to logical HIGH.
Inputs
A ABC
RPD
RPD
1 2 3
B
RPD
4 5 6
C RPD resistors are used to pull the
inputs up to logical LOW.
RPD
7 8 9

Interrupt

RAND RAND constitute a three

X Y Z input wired AND.
RPD = RAND
 Input – Mechanical Switches
A debouncer eliminates
debouncing by using a delay
circuit. Debouncing needs
MECHANICAL INPUT

TBOUNCE atleast a few milli-seconds delay

from the first switching
occurance.

Hardware Debouncer

Bouncing – rapid
transition of states due to
mechanical switch's
friction and contact.
 DC Inductive Load
Normally Normally Single Pole
Open relay Closed Double Throw
relay

VCC
Snubbe
r Diode
ACTUATORS

Relay Relay Relay

RR
IR
RP Relay is a binary actuator that have two state: ON or OFF. If
relay activation causes the relay to turn ON, this type of
R relay is called Normally Open.
VCE(sat)
There is also Normally ON relay, which is Closed when it is
C not activated.

RR = Relay internal resistance

IR = Relay operating current
V CC=R R I R + R P I R +V CE(sat) RP = Relay current protection resistor
VCE(sat) = Collector to Emitter saturation voltage (usually
V CC−V CE(sat) −R R I R
 R P= 0.2V, see respective transistor datasheet)
IR
 Solenoid
ACTUATORS

Solenoid is a binary actuator Solenoid valve is a electrically

which moves a shaft. This type of powered valve which turns ON or
actuators are used extensively in OFF when electrical power is
electronic door locks. The circuit applied on the solenoid.
to drive a solenoid is same as the
relay circuit.
 IR = Relay current = v/RR

Snubber Diode Selection v = voltage across the relay.

Vbe = Back emf.
RR = Relay internal
Normally resistance
Open relay L = Relay inductance
v tHL

VR
VCC
Snubbe
r Diode RC
ACTUATORS

Relay
t

RR
IR RC = tHL
RP
Snubber diode is required to suppress the back-emf created
R by the Relay's inductor. The faster the Fall time (lower t HL)
VCE(sat)
the higher is the voltage.
v
C d( )
di RR L dv L VR
V be =−L R =−L =−  V be =−
dt dt R R dt R R t HL
To minimize Vbe, the fall time, tHL, should be increased. By
using the RC circuit at the base of the transistor, and
Example: choosing,  = RC (time constant) to 100 ms, reverse emf can
L = 10mH, RR = 10, VR = 1V, tHL = be significantly reduced.
1s
If,  = RC = tHL = 100ms,
−3
−(10 * 10 H)∗(1V)
V be = =1000 V
(10∗Ω ) * (1∗10−6 sec ) −(10 * 10−3 H )∗( 1V )
V be = =0.01V
( 10 Ω )∗(100∗10 -3 sec)
 DC Motors [Types] Brushless
DC Motor Parameters:
Voltage Rating
Current Rating
Starting Current
Horse Power
Torque Permanent Stepper
Magnet
DC
MOTOR

Motor Brushed
Separately
Excited
NOTE
1. DC motor generates reverse emf.
2. A snubber diode required during surge.
3. DC motor is like short circuit at startup. Stepper Motor
4. Brushed DC motor has high initial torque. Parameters:
Voltage Rating
Current Rating
Starting Current
Shunt Series Step Size
Torque
Polarity of Coil
See Videos:
DC Motor How it works - YouTube.mp4
Brushless DC Motor How it works - YouTube.mp4
 DC Motors [Types] Brushless
DC Motor Parameters:
Voltage Rating
Current Rating
Starting Current
Horse Power
Torque Permanent Stepper
Magnet
DC
MOTOR

Motor Brushed
Separately
Excited
NOTE
1. DC motor generates reverse emf.
2. A snubber diode required during surge.
3. DC motor is like short circuit at startup. Stepper Motor
4. Brushed DC motor has high initial torque. Parameters:
Voltage Rating
Current Rating
Starting Current
Shunt Series Step Size
Torque
Polarity of Coil
See Videos:
DC Motor How it works - YouTube.mp4
Brushless DC Motor How it works - YouTube.mp4
 AC Motors [Types] Induction Motor:
AC Motor Parameters: 1. Most common
Voltage Rating
Current Rating 2. Good initial torque
Starting Current
Horse Power
Induction 3. Single to 3 Phase
Torque
1-3 Phase
AC
MOTOR

Motor
Synchronous
3 Phase

Synchronous Motor:
1. Constant speed irrespective of load
2. Low initial torque
3. Usually 3 Phase
 Brushed DC Motor
N N N N
S S S S
A

X
N N N

A
MOTOR

N
S

S
S X S Y
S
B

Y
N N N N
S S S S
A Y

A
+ - + - + - + -
X

B
B

Y
In brushed DC motor turns on the coil that is perpendicular to the
magment
 Brushed Motor Pros/Cons
Less Expensive Periodic maintenance
Simpler Construction Brush friction reduce
Replaceable brush torque
No driver electronics Lower speed
MOTOR

Two wire only High noise

 Brushless DC Motor (BLDC)
Q
Y
1 Q
Y
2 Q
Y
3
N N

N N S N N N N
N A A A

N S S
P
S P
S P
MOTOR

S S

B B B

X X X

Polarity Reversed
1 2 3 4 5 6 1 The positions 4, 5 and 6 is
AB the repeat of 1, 2 and 3
with direction of current
PQ reversed.
XY
Some brushless motors
have Hall sensor to locate
the position of the rotor.
 BLDC Wiring
A
B B
N
N
N
N S
N

N
A S
N S S
S
MOTOR

C
C
Y Configuration
Delta Configuration
B B
BLDC typically have 3 wires
colored Red, Black and Blue, and
3 additional wires for motors with Series
A sensors.
Excitation

Parallel
C Excitation
C A
 BLDC Pros/Cons
High Torque/Speed Need sensors
Higher efficiency Complex driver
Low electrical noise circuits
Smaller size Costlier
MOTOR
 kV Rating

kV Rating is used as a measure of RPM per volt on a

motor. So, a 1000kV motor will turn at 1000 RPM when 1
volt is applied. So, for 12V, the motor will rotate at 12000
MOTOR

RPM.

A lower kV motor have more torque than a higher kV

motor.

A lower kV motor have thicker winding wires and lower

number of turns and can tolerate higher current.
 Uni Polar Stepper Motor

A
A

N
MOTOR

B
B
S
C

X Y Z
X Y Z

Unipolar Motor have six

wires
 Uni-Polar motor full-step
GND A A
N
1 2
+ S +
V
C V
C S N

B B
MOTOR

X Z Y X Z Y
+V +V GND

A 3 A 4
GND
+ +
V
C V
C N S
S
N
B B

X Z Y X Z Y
+V GND GND +V
 GND
A
GND
A A
1 A
2 3 4
N N
+ +V
+ S +
C VC S N C
V C
V N
N
B B B
B

Y Y X Z Y
X Z X Z +V Y X Z +V GND
GND GND
GND
MOTOR

A A A
5
A
6 7 8
+ + +
+
VC VC NS VC N
V
C N
S
N
B B B B

X Z Y Z Y X Z Y X Z Y
X
+V +
GND +V +
GND GND
V V

Uni-Polar motor half-step

 Bi Polar Stepper Motor

A
A

N
MOTOR

S C

X Z
X Y
Bipolar Motor have four
wires
 GND
A A
N
1 2
S
S S N

S
+V
B B
MOTOR

X Y X +V Y
GND
Bi-Polar motor full-step
A
+V A 4
3
S
N S S

S
N
GND B
B

X Y +V
X Y GND
 GND +V A
A A A
N
1 2 3 4
N
S
N S N

N
+V B B B
+V B

Y Y +V X Y
X +V X Y X
+V
MOTOR

+V A +V A A A
5 6 7 N 8
N NS N
S
N N
B B B +V B

X Y Y X Y X Y
X
+V +V +V

Bi-Polar motor half-step

 Bi-Polar: Half Step Sequence
A B X Y VAB VXY

1 0 +V 0 0 -V 0
2 0 +V +V 0 -V V
3 0 0 +V 0 0 V
4 +V 0 +V 0 V V
5 +V 0 0 0 V 0
6 +V 0 0 +V V -V
MOTOR

7 0 0 0 +V 0 -V
8 0 +V 0 +V -V -V
 Bi-Polar: Half Step Sequence
A B X Y

1 0 1 0 0

2 0 1 1 0

3 0 0 1 0

4 1 0 1 0

5 1 0 0 0

6 1 0 0 1
MOTOR

7 0 0 0 1

8 0 1 0 1
 Micro Stepping
IAB IXY

Micro-stepping is a way to increase 1 -I 0

number of steps by adjusting coil 2 -I +I/2
current
3 -I +I
A proper stepper motor controller with 4 -I/2 +I
micro-stepping feature must ensure 5 0 +I
that the torque is uniform at each step.
6 I/2 +I
7 I +I
MOTOR

8 I I/2
9 I 0
10 I -I/2
11 I -I
12 I/2 -I
13 0 -I
14 -I/2 -I
15 -I -I
16 -I -I/2
 Servo Motor
Servo motor is a geared motor with position detector and
command input to set the angle precisely.
Command input is typically
pulse width (or duty cycle)
variation at a fixed frequency
(e.g. 50Hz)
MOTOR

IN
Motor
POT
Gear Command
s Decoder

+
Typical angle
-
control
-90o to +90o
 MOSFET
N CHANNEL MOSFET
POWER ELECTRONICS

More Reading:
MotorController\NXP_APPCHP3.pdf
 MOSFET [Continued]
POWER ELECTRONICS

Snubber Diode, catches the

reverse emf built on a DC motor
when the motor is stopped and
protects the circuit.
 MOSFET [DC Motor Control]
POWER ELECTRONICS
 Using all P-Channel and
N-Channel MOSFETs Snubber
10K Diode 10K

H-Bridge P-Channel DC P-Channel

Motor

A B
MOTOR

N-Channel N-Channel

Using all N-Channel

MOSFETs
Snubber
10K Diode 10K
H-Bridge is widely used
to control the direction
of DC motors.
DC
MOSFET based H-Bridge Motor
is suitable for high
power, high voltage and
high current
applications.
A B
 Inter Integrated Circuit (I2C)
2 wire open drain
output bus shared by
+VCC all I2C devices.
SERIAL INTERFACING

Max bus capacitance:

SCL 400pF
RPU

SDA

I2C I2C I2C I2C I2 C

Master Master Slave Slave Slave
Address: 1 Address: 2 Address: 3 Address: 4 Address: n

Each device have

unique address in the
bus Types of Slaves:
Memory
RPU Value: A/D D/A converters
4.7K → 100KHz Types of Master: LCD Display
2.2K → Standard Mode Microcontrollers Sensors
1K → Fast Mode Bus Controllers Interfacing ICs
 I2C Signal
https://learn.sparkfun.com/tutorials/i2c
I2C Use:
SERIAL INTERFACING

Sensors
Serial Memory
Serial I/O
A/D D/A Converters
GPIO
 I2C Protocol State Machine
Starting Communication with Slave

Direction 0 =
128 Addresses master → slave
32 of them are 7-bit Address 1-bit Dir
reserved Data is sent in
command 8-bit blocks
SERIAL INTERFACING

D7 D6 D5 D4 D3 D2 D1 D0

Idle
ACK
Master
M SDA → 0 M SDA = 0 SDA = 0 S
SDA = 1 Slave
SCL → 0 SCL → ∏ SCL → ∏
SCL = 1

ACK is used by Ack = 0, slave

Master always acknowledged
slave to respond
initiates comm. Ack = 1, slave
to master
not
Start acknowledged
Stop
Restart Sent by master

SDA A6 A5 A4 A3 A2 A1 A0 Dir Ack

SCL

Master drives
Clock transition must happen when data is the clock at
stable initial
communication
 I2C Protocol State Machine
Master writes n bytes to the slave
Start
Restart Sent by master
Ack = 0, slave
acknowledged
Dir=0
Ack = 1, slave
SERIAL INTERFACING

A6 A5 A4 A3 A2 A1 A0 Ack not
acknowledged

Master drives
the clock at
initial
communication

Clock transition must happen when data is

stable
Ack = 0, slave Stop
Sent by master
acknowledged

D7 D6 D5 D4 D3 D2 D1 D0 Ack

SDA

SCL

Master drives
Clock sent by master the clock at
initial
Repeat n times
communication
With different data
 I2C Protocol State Machine
Master reads n bytes from the slave
Start
Restart Sent by master
Ack = 0, slave
acknowledged
Dir=1
Ack = 1, slave
A6 A5 A4 A3 A2 A1 A0 Ack not
SERIAL INTERFACING

acknowledged

Master drives
the clock at
initial
communication

Clock transition must happen when data is

§
stable
Ack = 0, master
Acknowledged.
in last packet Stop
Sent by master
Ack = 1, master
not acknowledge

D7 D6 D5 D4 D3 D2 D1 D0 Ack

SDA

SCL

Master drives
Clock sent by master the clock at
initial
Repeat n times
§ In the last data packet, master does not With different data
communication
acknowledge
 I2C Protocol Example
Slave Address is 9C. Master sends b6 (hex) to slave. Then reads 7a from slave
from same address.
9C = 1001 1100
Start Leading 1 will be
ignored
I2C uses 7 bit address B6 = 1011 0110
SERIAL INTERFACING

0=Write

SDA 0 0 1 1 1 0 0 1 0 1 1 0 1 1 0
0=Ack
0=Ack

SCL

Master Slave Slave

Restart Although master has
Sends address again Read received it, a high from Stop
9C (msb ignored)
7A = 0111 1010 master will stop slave from
sending further data to the
master
1=Read

0 0 1 1 1 0 0 0 1 1 1 1 0 1 0

SDA 0=Ack 0=Ack

SCL

Master Slave Master

 ATmega I2C features
I2C is supported by all
Atmega processors

TWPS1, TWPS0
SERIAL INTERFACING
 Serial Peripheral Interface (SPI)
https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi

SS – Slave Select
SCK – Serial Clock
MOSI – Master Out
SERIAL INTERFACING

MISO – Master In

Max SCK = ~100MHz

SPI Use:
LCD Display
Sensors
Input Device
 SPI Communication (contd).
SPI communication may use one edge for transmission,
other edge for reception.

Transmits at
Falling edge
T R T R T R T R
SERIAL INTERFACING

SCK

d0 d1 d2 d3

MOSI
MTx

d0 d1 d2 d3

MISO
MRx
Clock transition must happen when data is
stable

Receives at
Rising Edge
 UART – Universal Asynchronous Short range

Receiver Transmitter transmission

speed can be in
excess of 115K
UART usually refers to RS232, RS422, RS485 standards baud

The receiving Previous

ends clock sync Next
Stop
Start Stop Start
SERIAL INTERFACING

with the start bit

One frame

Tx 1 0 b0 b1 b2 b3 b4 b5 b5 b7 1 0

Rx 0 b0 b1 b2 b3 b4 b5 b6 b7 1
A6 A5 A4 A3 A2

Shift

The shift register contain the received data after 10 clocks

The receiving end use STOP →

START edge to sync with the
clock
 UART – Transmission Example
UART sends 3ba9 using 1 stop and 1 start bit

LSB is sent first

SERIAL INTERFACING

Previous
Stop 3ba9 = 0011 1011 1010 1001
Start Stop
One frame
1 0 0 1 0 1 0 1

Tx 1 0 1

b0 b1 b2 b3 b4 b5 b6
b7
MSB is sent next

3ba9 = 0011 1011 1010 1001

Start Stop
Second frame
1 1 0 1 1 1 0 0
Tx
(continued)
0 1

b0 b1 b2 b3 b4 b5 b6
b7

Two frames are needed to send 16 bit value

 RS485
SERIAL INTERFACING

●
RS485 is multi-drop, means that the same serial line can be used by
multiple RS485 channels. In a sense, RS485 acts like a serial bus.
●
RS495 is extensively used in industrial applications for connecting
electromechanical devices to the controller boards.
 RS485
Differential Pair wire
Distance 1200m
SERIAL INTERFACING
 Universal Serial Bus (USB)
Version 3.0: http://www.usb.org/developers/docs/
Version 2.0: http://www.usb.org/developers/docs/usb20_docs/

History:
SERIAL INTERFACING

USB 1.1 : 1.5 Mbps

USB 2.0 : 480 Mbps, 500mA
USB 3.0 : 5 Gbps, 900mA
USB 3.1 : 10 Gbps

Uses Differential Signals (D+ and D-), Power and GND.

Non Return to Zero Invert (NRZI) encoding with sync fields

Features
●
Host controlled → host regulates communication
●
One host per bus.
●
OTG → Host negotiation protocol allows two devices negotiate for
the role of host.
●
7 bit address → 127 devices can be connected
●
Driver Auto load/unload
●
Bandwidth allocation with guaranteed latency
 USB (contd) NRZi Encoding

0 1 0 0 1 1 0 0 0 1 1
SERIAL INTERFACING

Data

NRZi

D-

D+

Logic Level 1 causes transition. 0 causes no transition.

 USB – Universal Serial Bus
SERIAL INTERFACING

Token Packet Handshake Packet

Host base protocol

Start of Frame Packet
Host
Root Hub

Device Device
Hub

Data Packet
Hub

Device Device
 [USB] Protocol

One's Complement of 3..0

SERIAL INTERFACING
 Power Electronics
THYRISTOR
POWER ELECTRONICS

– SCR
– TRIAC
– DIAC
MOSFET
H BRIDGE
POWER TRANSISTOR
 SCR Photos
POWER ELECTRONICS

High Voltage High

Current SCR

General purpose Low

Voltage Low Current
SCR

High Voltage High Current SCR with High

Surge continuous output Industrial SCR
 SCR – Silicon Controlled
Rectifier
PNPN with a PN gate
POWER ELECTRONICS

More Reading:
http://www.allaboutcircuits.com/vol_3/chpt_7/5.html
POWER ELECTRONICS

SCR [Continued]
POWER ELECTRONICS

SCR [Continued]
POWER ELECTRONICS

SCR – AC Control
TRIAC Photos
High Voltage High Current

General purpose Low High Voltage High Current

Voltage Low Current SCR with High Surge
SCR continuous output Industrial
SCR
 TRIAC - TRIode for
Alternating Current
More Reading:
http://www.allaboutcircuits.com/vol_3/chpt_7/6.html
POWER ELECTRONICS
 TRIAC [Continued]
POWER ELECTRONICS

More Reading:
http://www.allaboutcircuits.com/vol_3/chpt_7/4.html
 TRIAC Characteristics
POWER ELECTRONICS

IH - Holding current is
the minimum current to
keep the TRIAC in ON
state.
 Brake
Rotary
Encoder
Simple 3 story elevator
M = We-Wc
Flywheel
Speed Control Motor
Speed
Control
Sensor
3 1 Horsepower = One metric
Hall Sensor horsepower is needed to lift 75
Accelerometer L1
kilograms (avg. body weight of a
person) by 1 meter (3.28 feet) in 1
second.
Pressure
Sensor
We F2
2
Work = Mg(3h)
L2 Magnet

Counterweight
F1
1
Wc
Alignment
Sensor
W1 h
F0
How many
W2
0 horsepower motor
Hydraulic Damper or is needed?
Shock Absorber

10hp
10 people
 GND
A A + A
A
N
1 2 3 4
N
S

S
S N

S
N
N
+ B B B
+ B

Y Y + X Y
X X Y X
+ +
MOTOR

+ A + A A A
5 6 7 N 8
NS N

S
N

S
S
S
N N
B B B + B

X Y Y X Y X Y
X
+ + +

1 2 3 45 6 78 1

XY

AB
Induction Motor
 AC Induction Motor -
Direction Control
POWER ELECTRONICS
 Opto Isolator based motor control
POWER ELECTRONICS
 Electronic Circuit Analysis - 3
RL RP
RL RP
VS
Before IGT
ELECTRICAL ANALYSIS

VS IT IGT
Trigger
AC VGT Diode
Drop,
0.7V
VGT Diode
Drop, VS = RL.IGT + 0.7 + RP.IGT + VGT
0.7V
→ RP.IGT = VS - RL.IGT – 0.7 -
How to calculate minimum and maximum
VGT
value of current limiting/protection V S −R L I GT −V GT −0 .7
resistor. R P=
I GT

R IGT = Gate Trigger Current

RP,min = RP for minimum trigger voltage VS
VGT = Gate Trigger Voltage
RP,max = RP for maximum trigger voltage VS
L
IH = Holding Current
V IT = Forward Current
Choose SCR that meets:
After I I = Forward Surge Current
S Trigger T TSM 1. ITSM > IL,max
VDRM = Forward Blocking
Voltage 2. VDRM ,VRRM> VS,max
VRRM = Reverse Blocking 3. IT > IL
Voltage
 Electronic Circuit Analysis - 4
RL RP
RL RP
VS
Diac Before IGT
ELECTRICAL ANALYSIS

VS Drop, +ve
IT VDIAC
Trigger
AC VGT Diac
Drop,
VDIAC

VGT IGT RL RP

RP , is computed the same way as SCR.

VS
A TRIAC triggers in both direction. Before -ve IGT
If there is no DIAC, VDIAC = 0V Trigger

R R VGT Diac
Drop,
VDIAC
L L VS = RL.IGT + VDIAC + RP.IGT + VGT
V IT V → RP.IGT = VS - RL.IGT – VDIAC - VGT
After After -ve
V S −R L I GT −V GT −V DIAC
S +ve S Trigger IT R P=
I GT
Trigger
RP,min & RP,max is also computed similarly.
 Electronic Circuit Analysis - 5
RL RP
Opto-TRIAC uses the same
equation for RP .
For Opto-TRIAC
VS
ELECTRICAL ANALYSIS

VTM = Get from

Datasheet,
AC otherwise use Choose Opto-TRIAC that
0V
meets:
1. IT > IGT,max
2. IGT,max = VS,max /RP,min
VGT IGT 3. VDRM ,VRRM> VS,max

IGT = Gate Trigger Current

VGT = Gate Trigger Voltage RED LED
Voltage
Opto-TRIAC
IH = Holding Current
IT = Forward Current
Drop, 2.0V RP,TRIAC
ITSM = Forward Surge Current IP < IK
VDRM = Forward Blocking Choose TRIAC that
IP < IS
Voltage meets:
VRRM = Reverse Blocking
1. ITSM > IL,max
Voltage
IK = Sink Current 2. VDRM ,VRRM> VS,max
IS = Source Current NOTE: LED voltage drop is higher 3. IT > IL
than diode voltage drop.
 RMS Value of Sinusoid
General Formula:
T 2π
A Period, T = 2 ∫ a (t)dt
2
∫ a 2 (θ)d θ
a 2rms = 0
a 2rms = 0
T 2π

0
AC CONTROL

An RMS value is a DC value that produce the

 = 2→t = T same power as the time varying signal.

θ= 2π 2πt
θ=
t T T 2π 2π 2 2π
21 2 1 2 A 2
a = ∫ a (t)d θ= ∫ ( A sin(θ) ) d θ= ∫ ( sin θ ) d θ
rms
2π 0 2π 0 2π 0

Applying the identity in trigonometry called

1
power reduction method: 2
sin ( θ)= ( 1−cos ( 2 θ ) )
2

2 2π 2 2π 2π 2π
A2
[ ]
2
2 A
rms
1
a = ∫ ( 1−cos ( 2 θ ) ) d θ=
2π 0 2
A
∫
4π 0
( 1−cos ( 2 θ ) ) d θ=
A
4π [1
θ− sin ( 2θ )
2 ]
0
a =
2
rms
4π
1
θ− sin(2 θ)
2 0
 RMS control with conduction angle

General Formula for Sinusoid RMS:

A Period, T = 2
2π
A2
0
 2

2
a =
rms
4π [ 1
θ− sin(2 θ)
2 ] 0
AC CONTROL

RMS value of a full sine wave:

A2
2
1 a = rms
2
2
π 2π
A2 A2
T/2 t2 T

a = 2
rms
4π
1
[
θ− sin(2 θ) +
2 θ 4π
1
]
θ− sin (2 θ)
2 1
[ ] θ2
=Pterm + N term

2
0 t1  21 Pterm =
A
4π
1
[
π−θ 1+ sin(2 θ 1)
2 ]
2 2

conduction angle
N term=
A
4π [
1
2 π−θ 2+ sin(2 θ 2) =
2
A
4π
1
] [
π−θ 1+ sin(2 π+2 θ1 )
2 ]
2 2
2
a =
rms
A
4π
[ 2(π−θ 1)+sin (2 θ1 ) =
A
2π
1
2
] [
(π−θ1 )+ sin(2θ 1)
]
2 2

( a rms
a rms | max ) [ 1 1
= π α− sin(2 α )
2 ] a =
A
2
rms
2π
1
α − sin(2 α )
2 [ ]
 RMS control with conduction angle

2
a rms
( ) [ 1 1
] At /2:
2
a rms
( a rms | max ) a rms | max
= π α− sin(2 α )
2
2
a rms
 ( a rms | max ) [ 1 1
]
= π π − sin(2 π ) =0.5
2 2 2
AC CONTROL




 
 Power Circuit Simulation
High power circuit should almost always be
simulated
POWER ELECTRONICS

Breadboard use should be avoided

TOP ANALOG CIRCUIT SIMULATORS
MULTISIM by National Instruments,
PROTEUS by Lab Electronics,
TINA by DesignSoft,
TINA-TI (FREE) by Texas Instruments,
NANOSPICE by ProPlus (large scale circuits),
 Standard Binary

Gray Code Higher Frequency

Lower Frequency
DATA ACQUISITION

O O O O

O O O I

O O I
I

O O I
O

O I I
O

O I I
I

O I
O I

O I
O O
Many optical readers are
R
designed to use gray code. O O O I I O O
Gray Code is reflected binary
number. R indicates Reflection. O O I I I O I
Imagine a folding along the thick O I
I
I I I
I
line, the top bits are folded (or
O I I I I
O O
reflected) at the bottom.
R
O O I I I O I
O O
Gray Coded data can be sent
O I I I I O I
I I
with less bandwidth.
R
O I I I O
I O I O I
R
I I I I O
O O O O O
Gray code use
Use
Rotary Switch
Mechanical Encoder
Low BW Transmit
 Gray Code +

+
Gray code to Binary Conversion

I I I O
O O
A B C X Y
DATA ACQUISITION

AB
O O O 00 01 11 10
O O O
C
0 O I O I 0
O O I O O I
X
O I O I 1 O I O I 1
+
I O

O I O I
O I
R AB+AB
I I I O
O O

I I
I
I O
I
C
+
0 1
I I X
O I
+
I O
0 O I 0
I
O O
I
I I Y
1 I O 1
Gray Binary

XC+XC I I O I I O O I
 Gray Code +
+
Binary to Gray code Conversion

I I I O
O I
X Y Z A B C
DATA ACQUISITION

XY
O O O 00 01 11 10
O O O
Z
0 O I O I 0
O O I O O I
B
O I
O
O I
I 1 O I O I 1

O I
I
O I
O +
R XY+XY
I O I I
O O

I O
I
I I
I +
XY
I I
I O O I
+
00 01 11 10
Z
I I
I I O O
0 O I I O 0
C
Binary Gray 1 I O O I 1

I I O I I O I I
YZ+ZY
 Gray Code
Gray to Binary code Conversion
I O I I O I I O I I O I I O I I
DATA ACQUISITION

+ + + + + + + + + + + + + + +

I I O I I O I I O I I O I I O I

Binary to Gray code Conversion

I I O I I O I I O I I O I I O I

+ + + + + + + + + + + + + + +

I O I I O I I O I I O I I O I I
 Op Amps (contd.)
OpAmp Integrator
C
V in −V n d (−V o−V n )
=C
R dt

Vin Vn i
R dV o V in For ideal OpAmp
 −C ( )=
OP AMP

dt R V p = V n & Vp = 0
Vo for integrator
i Vp
 dV o =−( 1 )V in dt
RC

 V o =−( 1 )∫ V in dt
RC

1
V o =−( )∫ V in dt
RC
 Op Amps (contd.)
OpAmp Differentiator

R
−V o −V n d (V in −V n )
=C
R dt
i
C Vn
Vin Vo dV For ideal OpAmp
 −( )=C ( in )
OP AMP

R dt V p = V n & Vp = 0
Vo for integrator
i  V =−RC dV in
Vp o
dt

dV in
V o =−RC
dt
 Passive Low Pass Filters (LPF)
Gain = Vo/Vin
Ideal Filter 1st Order
2 2
Power Gain, Pgain = Vo /V in
= Gdb
2
Gain
At cutoff frequency, Gain is half 0dB 2nd Order
(0.5). -3dB

Pass Band
Gdb=10 log 10 (P gain)
fc
FILTER

P output
GdBm=10 log 10 ( ) Attenuation

1mW R
Vin Vo

Gdb=20 log 10 (Gain) mW GdBm

C 1
G db 0.5 -3dB st
1 Order f c=
20 1 0dB 2πRC
Gain=10 2 3dB
Gain Gdb Gain Gdb 4 6dB R R
1/16 -24dB 16 24dB 8 9dB Vin Vo
1/8 -18dB 8 18dB 16 12dB
¼ -12dB 4 12dB 100 20dB C C
nd
2 Order
½ -6dB 2 6dB 500 27dB
1/√2 -3dB 1 0dB 1000 30dB
 Passive High Pass Filters
(HPF) Gdb
Ideal Filter

Attenuation
0dB
-3dB

1
f c= Pass Band

2πRC
fc
FILTER

1st Order 2nd Order

R

C C C
Vin Vo Vin Vo

R
st
R R
1 Order 2 nd
Order
 Active LPF
Glog
-3dB

OpAmp Low Pass Filter Pass Band

Attenuation

Unity-Gain Sallen-Key Low-Pass Filter

fc
+ fc = Cutoff Frequency
C
Beyond cutoff frequency
Gain = Vo/Vin gain is rapidly attenuated
Vin R R
Vo Glog = 20 Log10 (Gain)
+ C
At cutoff, Gain = 1/√2
FILTER

Glog = -3.01

fc
Q = Quality Factor
Pmax 0dB
Example: Design a low pass
audio filter to be used after DAC 1
with cutoff = 3kHz
P3db -3dB f c=
2πRC

R C=
1  R C= 1
=5.31∗10−5
Q
fC 1
Q=
3
2π f c 2 π 3.10
=
Choose C = 1nF BW 2
R = 5.31*10-5/1*10-9 =53.1K
You can also choose R first
BW
 Active HPF
Glog
-3dB
Attenuation
Pass Band

OpAmp High Pass Filter

fc

R fc = Cutoff Frequency
Beyond cutoff frequency
gain is rapidly attenuated

Vin C C
Gain = Vo/Vin
FILTER

Vo
R

Q = Quality Factor

Unity-Gain Sallen-Key High-Pass Filter 1 1

f c= Q=
Example: Design a high pass 2πRC 2
audio filter to be used after DAC
with cutoff = 50Hz
Choose C = 1F

R C=
1  R C= 1 =3.18∗10−3 R = 3.18*10-3/1*10-6 =3.2K
2π fc 2 π 50
You can also choose R first
 Audio Amplifier Example
RV RV RV
VCC RHP V o =−( V B+ V M + V T )
1 R2 CHP CHP RB RM RT
f F= A=1+ C
2 π RF C F R1
+

Rm RHP RT
CF High Pass
C Filter C
+ +
AUDIO

RF RM RV
+
CLP
R2 RLP RLP
C
R1 +
+
Mic CLP RB
RC High
Bias Audio Low Pass Audio
Pass Filter
Circuit Pre Amp Filter Mixer
Rm = Electret microphone bias resistor. Get from Microphone's datasheet. Typical value 1K
fFCutoff frequency of High Pass RC filter. Choose minimum fc equal to line frequency (50
Hz).
To ADC or
Pre-amp gain. Typical gain 100. Choose R2 = 100K. Find R1 from the gain equation.
Audio Amp
fCCutoff frequency of Bass and Treble filter. Usually (500 Hz).
RV = Master volume control. Choose RV = 100K. 1 1
RT, RM, RB = Treble and Bass boost. Can be equal to RV. f C= =
2 π R HP C HP 2 π RLP C LP
C = Coupling capacitor (1F for audio)
 Audio Power Amplifier Example
Stereo Power Amp
AUDIO

Datasheet: Lectures\PowerElectronics\AudioPowerAmp_tpa3121d2.pdf
 Nyquist Sampling Theorem
Given a signal, y(t) = A sin(2ft+
The signal can be fully reproduced without loss of
data if the signal is sampled at 2f.
DATA ACQUISITION

For proof, see

Lectures\DataAcquisition\NyquistSamplingTheorem.pdf

f, signal 2f, sampling

frequency frequency

These two samples can

reproduce the whole signal
 Data Acquisition A sample and hold circuit holds the sample
voltage at sample time until the voltage is
In analog data acquisition, data is sample at converted into digital data. The time during
the A/D converter through a sample and hold which the sample is held into the Capacitor is
circuit. called Hold Time.
DATA ACQUISITION

Vin
Sample Vout
Time, tS
C

T = Hold Time

Holding the sample into the Capacitor ensure

that the voltage will not change even if the
input changes.

Analog to Digital Converter

 circuit.

Data Acquisition (cont.)

DAC converts digital signal into analog
Digital to Analog Converter signal. A DAC is usually followed by Analog
filter to smooth the waveform.

Sample is held
until the next data
is available After Analog filtering the high
DATA ACQUISITION

frequency component is
removed resulting in a
smooth output

T = Hold Time

Holding the sample during DAC conversion

reduces noise.
 Data Acquisition (cont.)
Digital to Analog Converter DAC converts digital signal into analog
signal. A DAC is usually followed by Analog
The R-2R resistor ladder for DAC is a filter to smooth the waveform.
popular technique for Digital to Analog
conversion.
2R
2R V IN
VIN V OUT=
VOUT 2
DATA ACQUISITION

VIN
b2 b0 One Bit
2R b0 = 1
R
2R
VIN
b1
R 2R R Two Bit
V IN
2R VIN V OUT = b1b0 = 01
4
VIN
b0
b0 2R 2R
2R

R R This indicate that

V IN V IN at each stage
After applying superposition V OUT=
2 4 voltage is
theorem
b0 dropped by half
b0 b 1 b2 2R 2R
V OUT={ + + }V
8 4 2 IN
 Flash ADC
+VCC

R Combinational Logic

D2 0 0 0 0 1 1 1 1 D2
R
D1
DATA ACQUISITION

D1 0 0 1 1 0 0 1 1
D0 0 1 0 1 0 1 0 1 D0
R b6 0 0 0 0 0 0 0 1
b5 0 0 0 0 0 0 1 1
R b4 0 0 0 0 0 1 1 1
b3 0 0 0 0 1 1 1 1
b2 0 0 0 1 1 1 1 1
R
b1 0 0 1 1 1 1 1 1
b0 0 1 1 1 1 1 1 1
R
●
Very Fast: MAX104 Flash ADC is
1Gsps, 8-bit
R ●
Need 2N-1 fast comparators for
N bits
●
Very Expensive
●
Used only in special applications
R +Vin
[0..VCC ]
 Data Acquisition Z b7 b6 b5 b4 b3 b2 b1 b0

Analog to Digital conversion Init 1 1

Successive Approximation ADC
●
This is the most popular kind of ADC 1 1 1
technique.
●
Can convert to digital signal in N clocks for
DATA ACQUISITION

N bit ADC 0 1 0 1

Approximation Registers
1 1 0 1 1
Vin Z
Logic

1 1 0 1 1 1

0 1 0 1 1 0 1

DAC 0 1 0 1 1 0 0 1

1 1 0 1 1 0 0 1 1
Operation
The approximation is set with the current bit (msb) set to 1.
If Z → 0, the current bit is set to 0 (=Z) and the next bit becomes 0 1 0 1 1 0 0 1 0
the current bit (set to 1).
If Z → 1, Z becomes the current bit. Output
At each iteration, one bit of approximation is completed.
 Data Acquisition Z b7 b6 b5 b4 b3 b2 b1 b0

Analog to Digital conversion 128 1 1

Successive Approximation ADC

192 1 1 1
convergence
DATA ACQUISITION

160 0 1 0 1
178

176 1 1 0 1 1

184 1 1 0 1 1 1
192

184

180

179

178
178
176
160

180 0 1 0 1 1 0 1
128

178 0 1 0 1 1 0 0 1

0 1 2 3 4 5 6 179 1 1 0 1 1 0 0 1 1
7 8

178 0 1 0 1 1 0 0 1 0

Output
 Reconstruction from Pulse Width
Using Digital Filters, the original waveform can be reconstructed

See, digital-lpf.ods for more information.

FIFO
DATA ACQUISITION

S6 S5 S4 S3 S2 S1 S0

PWM signal

+
yout

yout [n]= a7•s[n-4]+a6•s[n-3]+a5•s[n-2]+a4•s[n-1]

+a3•s[n]+a2•s[n+1]+a1•s[n+2]+a0•s[n+3]

Reconstructed
waveform Digital Filter Example
Coefficients an determine the
behavior of the filter
 Data Acquisition (cont.) a

Delta Sigma A/D Converter ∫ a dt =at +C=aT +C

Extensively used in DSP Audio applications. Vin VO =Vin - VDAC Vint

Must be over sampled significantly higher to Vout
reproduce the wave form from pulses.
∫
VDAC
DATA ACQUISITION

1-bit
Sample is held DAC
until the next data
is available

7V

7
6
5
4
7 7 7
3 6 6 6
2 4 4 4
3
1 2 2
0
1 1
0
1 -2 -3 -2
2 -4
Oversamples -5
3
-7
4 Standard
5 Samples
6
7
1u
-7V

T = Hold Time
 Delta Sigma ADC (contd.)
yout = x[-3]+x[-2]+x[-1]+x[0]+x[1]+x[2]+x[3]
Max 1
Low pass filter using 3 past sample, 1
1
current sample, 3 future sample
Vin Vdac Vint Vout 2
DATA ACQUISITION

0 3 8
1.00 -1 2.00 1 4
4.00 1 3.00 1 5 6
6.00 1 5.00 1 6
4
7.00 1 6.00 1 7
7.00 1 6.00 1 7
2
7.00 1 6.00 1 7
6.00 1 5.00 1 7
0
4.00 1 3.00 1 5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
3.00 1 2.00 1 3
-2
2.00 1 1.00 1 1
0.00 1 -1.00 -1 -1
-4
-2.00 -1 -1.00 -1 -3
-3.00 -1 -2.00 -1 -5
-6
-5.00 -1 -4.00 -1 -7 1 current
-7.00 -1 -6.00 -1 -5 sample
-8
-4.00 -1 -3.00 -1 -3
-2.00 -1 -1.00 -1 -1 3 past 3 future
sample sample
1.00 -1 2.00 1 1
2.00 1 1.00 1 2
4.00 1 3.00 1 3 Pulses Values Samples
Delta Low Pass
6.00 1 5.00 1 4 Decimator
Sigma Digital Filter
 Saturation Arithmetic
Original signal Saturated signal
Max Max
DATA ACQUISITION

Distortion
Unsaturated signal caused by
saturation
Max
A processor with built in saturation arithmetic
will saturate the result to the highest positive or
negative value instead of overflowing.

Processors with saturation arithmetic has a

saturation flag, which is set at the time of
saturaiton.

Noise caused by
overflow
 Saturation Arithmetic (cont.)
Digital Signal Processors and some Microprocessors
have Saturation hardware and instructions
DATA ACQUISITION

Saturated Add: Saturated Mul:

Positive Numbers +ve * +ve numbers

6F + 7D = 7F (hex) 6F + 7D = FF (hex)
(largest positive 8 bit) (multiply with negative 8 bit)

Negative Numbers +ve * -ve numbers

6F + AD = 80 (hex) 6F + AD = 80 (hex)
(largest negative 8 bit) (multiply with negative 8 bit)

Saturated Shift:

Shift Right Shift Right

01110011 → 00111001 11110011 → 11111001
(positive number shift right) (negative number shift right)

Shift Left Shift Left

01000000 ← 01111111 11110011 ← 1110010
(positive number shift left) (positive number shift left)
 Negative and Positive Saturation
When saturating, make sure that the result does not
change the sign
DATA ACQUISITION

Positive Saturation: Negative Saturation:

2n-1 -2n

Positive saturation in binary: Negative saturation in

binary:
MSB bit is kept 0 all other bits
set to 1. MSB bit is kept 1 all other bits
set to 0.
For 16 bit register, the
maximum positive value For 16 bit register, the
possible is: maximum positive value
0x7FFF = 32767 (dec) possible is:
0x8000 = -32768

Computing 2's complement of positive number:

0x8000 = 32768 (positive number)

2's complement = 0x8000 (inverting the bits) + 1 = 0x7FFF + 1 = 0x8000 = -32768 (dec)
2's complement 1 = 0x0001 + 1 = 0xFFFE + 1 = 0xFFFF = -1 (dec)
 Fixed Point Numbers
If a fractional numbers range is known, fixed point
number may be used

n
DATA ACQUISITION

0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
2-n 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 0.00390625 0.001953125 0.0009765625

n -11 -12 -13 -14 -15

2-n 0.00048828125 0.000244140625 0.0001220703125 0.00006103515625 0.000030517578125

n -16 -17 -18 -19

2-n 0.0000152587890625 0.00000762939453125 0.000003814697265625 0.0000019073486328125

n -20 -21 -22

2-n 0.00000095367431640625 0.000000476837158203125 0.0000002384185791015625

n -23 See fixed-point.ods spreadsheet for full

2-n 0.00000011920928955078125 automatic conversion.
 Representing Fraction in Fixed Point
Convert 0.819820934 into fixed point representation
Conversion Example:
If this sum is negative, then use n = 0,
n Otherwise use n = 1 and find the
DATA ACQUISITION

fractional value of the remainder.

0.819820934 1 • 2-1 + 0.319820934 1

0.319820934 1 • 2-2 + 0.069820934 1 n

error =|a−∑ 2 |
n
-3
0.069820934 0 • 2 + 0.069820934 0
n=0
-4
0.069820934 1 • 2 + 0.007320934 1
Q-Point
0.007320934 0 • 2-5 + 0.007320934 0
Q-point is written as: Q[m.]n:
0.007320934 0 • 2-6 + 0.007320934 0 m (optional) number of integer bits,
0.007320934 0 • 2-7 + 0.007320934 0 n (last bits) number of fractional bits.

0.007320934 1 • 2-8 + 0.003414684 1 Q point defines the number format of a

fixed point. If m is not stated, then n
0.003414684 1 • 2-9 + 0.001461559 1 is the fractional bits and the remaining
0.001461559 1 • 2-10 + 0.0004849965 1 leading bits are integer bits.
Q9 means fixed point number with 9
0.0004849965 0 • 2-11 + 0.0004849965 0 fractional bits.
0.0004849965 1 • 2-12 + 0.000240855875 1

0.000240855875 1 • 2-13 + 0.0001187855625 1 See fixed-point.ods spreadsheet for

full conversion
 Fixed Point Adjustment (contd.)
n=10

A 0 1 0 1 0 0 1 1 0 0 1 0.6494140625 Q1.10
m=8
DATA ACQUISITION

B 0 0 0 1 1 0 0 1 0 1 1 0.79296875 Q3.8

Multiplication
n+m=18 Actual
Q4.18 0.5149650574 0.514965057373046875

A*B 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1

Divide
n+m=18 0.8189620972 Actual
Q4.18 0.8189655172413793103448275862069

A/B 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1 0
Before divide, shift left A by m bits to preserve precision

Addition/Subtraction
Must align the point. B ← (n-m) 0r A → (n-m) before addition
(← is shift left, → shift right)
 Floating Point Numbers
ANSI/IEEE Std 754-1985 is the most widely used
format for floating point
DATA ACQUISITION

31 30 23 22 0
S e7..e0 1.m1..m23

mantissa
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Conversion:

10 in floating point format:

f = (-1)S • 2e-127 • m

10 = (-1)0 • 10 (we need to find e & m)

10 = (-1)0 • 8 • (10/8)
10 = (-1)0 • 23 • 1.25
10 = (-1)0 • 2130-127 • 1.25 Single Precision Floating Point Number
10 = (-1)0 • 2130-127 • (1+0.25)
10 = (-1)0 • 2$82-127 • (1+$200000)
f = (-1)S • 2e-127 • m
 Atmega2560 Boot Sequence
in C C source code in Proteus
8 with WinAVR tool
chain ISR(INT0_vect)
{
Details at Section 14.1 /* ISR for INT0 */
ATmega2560 datasheet }
SOFTWARE

Page. 105
ISR(INT1_vect)
Program Memory {
/* ISR for INT1 */
Reset Vector,
Address of main() }
0x0000
int main(void)
0x0002 Address of ISR(INT0_vect) {
/* user code */
0x0004 }
Address of ISR(INT1_vect)
 MSP430 Boot Sequence in C

ISR(NMI_vect)
{
See MSP430F21x2 /* ISR for INT0 */
interrupt vector }
SOFTWARE

addresses
ISR(ADC10_vect)
Program Memory {
/* ISR for INT1 */
Reset Vector,
Address of main() }
0xFFFE
int main(void)
0xFFFC Address of ISR(NMI_vect) {
/* user code */
0xFFEA }
Address of ISR(ADC10_vect)
 ARM Cortex M3 Boot
Sequence in C
See Cortex M3 NVIC
interrupt vector ISR(GPIOC_vect)
SOFTWARE

locations {
/* ISR for GPIOC */
}

ISR(GPIOB_vect)
Program Memory {
/* ISR for GPIOB */
Reset Vector,
Address of main() }
0x0000 0004
int main(void)
0x0000 0048 Address of ISR(GPIOC_vect) {
/* user code */
0x0000 0044 }
Address of ISR(GPIOB_vect)
 Kahn Network - Introduction
Kahn Network is used to model distributed system (also used in
CONCURRENT SYSTEM MODELING

signal processing). Each NODE is a computational block, each

arrow is FIFO queue.
●
The Kahn process network does not
depend on communication delay or
computation
Computational Computational ●
Only One process can put token and
Block Block only One process can get the token.
●
Each FIFO is unbounded
FIFO A ●
Writing to FIFO is non-blocking
●
Reading from FIFO is blocking
●
Each FIFO holds the SAME TYPE of
data.
Place ●
Kahn Network is deterministic - for
same type of input produces same type
of output
●
One output token is fired when each
input FIFO has at least one token

P1 passes result to P2 through unbounded FIFO A

P1 •••
P2
Producer Consumer
Block Block
 Kahn Network – Elevator Example
Kahn Network – Elevator Switches
CONCURRENT SYSTEM MODELING

Identical processes.
ASC- Only one will be called.
FIFO Analogy with Threads
UP

K-FIFO
SW SRT

Internal Switches Sorter DSC-

Ignore FIFO ST
DN
Past

Stop elevator
and open door

ST

FL

Floor
Level
sensor

●
When an elevator's internal switch is pressed, the sequence must be ordered
such that, if the elevator is going up, then the sequence is ascending, or if going
down, its descending.
●
When a floor is reached, the elevator must stop
 Micro Kernel
Kernel functions:
A set of routines that does the init()
following: add_proc()
loop()

1. Inter Process Communication Co-operative multi-tasking

fifo_get()
2. Memory Management
SOFTWARE

fifo_put()
3. Virtual Memory (optional)
4. Scheduling
5. Messaging

Pre-emptive multi-tasking – Each process has its own

execution time slot.

Process1 Process2 Process3 Process1 Process2 Process3

Co-operative multi-tasking – A message driven multi-

tasking that shares the same common timeslot

Process1 Process2 Process3 Process1 Process2 Process3

Messages
 FIFO First In First Out
Producer

ISR(INT0_vect)
{
/* ISR for INT0 */
/* Call Device Driver */
FIFO Size = 3 /* Get Values */
Message *m;
INT0 INT1 message /* Create Message */
m = create_message(...);
fifo_put(m);
INT1 INT0 message }

.
µP ISR(INT1_vect)
SOFTWARE

.
. {
...
INTn /* Create Message */
m = create_message(...);
fifo_put(m);
}

INT1 message
Consumer
FIFO creates a queue to int main(void)
free ISR from blocking {
other interrupts. The Message *m;
main task is processed in while(fifo_wait()) {
the consumer thread or m = fifo_get();
process(m);
the main thread.
}
INT0 message }

consumed
 Kernel functions:

Kernel Functions int main(void)

{
init(); /* initialize processor */
loop: fifo_init(); /* initialize FIFO */
An infinite loop of FIFO fetch & dispatch add_procs(); /* add processes */
loop(); /* start main loop */
/* this line is never reached */
void loop(void) { return 0;
while(1) { }
message_t m;
if (fifo_get(&m) == SUCCESS) {
int i;
for(i=0;i<PROC_SIZE;i++) {
void* ret;
SOFTWARE

proc_t p;
p = process_pool[i];
if (p == NULL)
break;
ret = p(&m);
}
} add_proc:
proc_main(&m); Add function pointers of processes
}
}
void add_proc(proc_t p) {
int i = 0;
for(i=0;i<PROC_SIZE;i++) {
proc_t pi = process_pool[i];
init: if (pi == NULL) {
Initialize I/O ports direction registers process_pool[i] = p;
Initialize Interrupt registers process_pool[i+1] = NULL;
Initialize Timers return;
Initialize A/D D/A converters }
Initialize Device Driver }
}
Initialize Processes
Enable Interrupts
 Kernel Data Flow Hardware

main.c

Start Initialize
Processor
Init Read
Initialize Open
FIFO

Write
Device
SOFTWARE

interrupt.c Close Driver

Interrupts

Add
Processes

Create
Message Normal
Process 1 Processing

Put in Get from

FIFO FIFO

Process

Return from Process 2

Interrupt Process 3
proc.c
 Device Driver
Device Driver gets the data from the physical device. Device Driver interface should be portable.
No device could be accessed without appropriate device
driver.
General Interface
int open(int id);

void init(int id);

SOFTWARE

void close(int id);

int read(int id, void* device_struct);

User Program int write(int id, void* device_struct);

Device Driver
General Implementation
Hardware Device
int device_open();

int device_init();

void device_close(int id);

int device_read(int id, void* device_struct);

int device_write(int id, void* device_struct);

 Critical Section
Critical Section Implementation
Semaphore variable stores the
process id. If it is 0, then no
process is using the NAND flash
unsigned char semaphore;

int write_nand_flash(int id, char* bytes, int

size) {
SOFTWARE

if (semaphore > 0)
Device Driver return 1;
if (!semaphore)
semaphore = 1;
NAND Flash

Critical Section is used

nandf_write(int id, bytes, size);
to access shared
resources like NAND
Flash semaphore = 0;
return 0; /* success */
}

Critical Section
Critical Section is a part of code in a multi-
tasking software system when this part of
the code an be executed by one process
only.
 Inter Process Communication
Critical Section Implementation
Semaphore variable stores the
process id. If it is 0, then no
unsigned char mem_semaphore;
process is using the shared
memory typedef struct shared_mem {
Shared int from_id;
int to_id;
Memory
SOFTWARE

unsigned char[SHARED_MEM_SIZE];
int size;
} shared_t;
Device Driver
int send_data(int from_id, int to_id, char*
bytes, int size) {
Shared Memory
if (mem_semaphore && mem_semaphore != 1)
Critical Section is used return 1;
to access shared if (!mem_semaphore)
resources like Shared mem_semaphore = 1;
Memory
shared_write(int from_id, int to_id,
bytes, size);
Critical Section
Critical Section is a part of code in a mem_semaphore = 0;
multi-tasking software system which return 0; /* success */
}
an be executed by one process only
while other processes wait for its
chance.
 Petri Net - Introduction
Petri Net is used to model concurrent system of events in the form of
CONCURRENT SYSTEM MODELING

graph. From this graph, it is possible to determine the system

behavior.
●
Tokens are moved by the
firing of tokens
●
Each input must have at least
one token to fire
●
Tokens can be anything that
carry usable information.

Tokens Place Place

Transition
Tokens Example
Fired Tokens
After tokens are fired Interrupts
FIFO Event
Button Press
Touch
Keyboard
Place Place
Transition Switch
I/O Port Bit
 Petri Net – Design
A transition can have multiple places as OUTPUT and each OUTPUT
CONCURRENT SYSTEM MODELING

gets the output token

Each OUTPUT token may be different

Input Tokens may be different

than output tokens
Places

Input Place Transition

Tokens Fired Output
Tokens are Tokens Firing
different To fire transition:
Each input must
After tokens are fired have token.
Each output gets a
new token
Places

Place Transition
 Petri Net – Design
A transition can have multiple places as INPUT and each INPUT
CONCURRENT SYSTEM MODELING

must have a token to fire a transition

Each INPUT token may be different

Input tokens may or may not

have any relationships with
output token

Fired Output
Input Tokens are
Tokens different
After tokens are fired

Tokens Firing
Places If any input is empty
(i.e., without tokens,
no transition can be
fired.
 Petri Net – Conflict
Conflict occurs when a single token is shared by two transitions.
CONCURRENT SYSTEM MODELING

t1 and t2 are both ready to fire but the

firing of any leads to the disabling of This transition (t1) causes

the other transitions. conflict for t2.

t t1
1

t2 t2

Conflict visualization
Petri Net visualizes conflicts clearly and in a system
design, these conflicts could be avoided by eliminating
such conflicts from redesign.
 Petri Net – Elevator Example
Elevator Door Opening Petri Net
CONCURRENT SYSTEM MODELING

H1
1. Motor is OFF
2. Hall1 and Hall2 sensors are ON
Hall 1
3. Accelerometers indicate ZERO
Sensor
velocity

Elevator
H2 leveled with
floor

Hall 2 This token is

Sensor generated by
consuming tokens
from inputs
Door can be
opened
M

Motor Off
Indicator

Elevator not in Petri Net visualizes dynamic systems

motion The above Petri Net to open Elevator
Door clearly visualize that if not all
Accelerometer events (tokens) are present at each
Sensor – generates step of transition, the door will not
ZERO velocity token open.
 Petri Net – Elevator Example Runtime
Elevator Door Opening Petri Net Token flow
CONCURRENT SYSTEM MODELING

H1
2
H1

1
H22 H2

M M

3 4
H1 H1

H2 H2

M M
 Multi-Processing

µP 1 µP 2 µP n
MULTI PROCESSING

...

Multi-processing: Method of distributing

task to 2 or more processors.
1. Reduces processor overload
2. Dynamically allocate and connect to processors based on workload.
3. Aid in Parallel Processing.
 Multi-processing Inter processor
communication can be
message based. Each
processor
communicates through
messages.
µP 1 µP 2 µP n The message engine is
MULTI PROCESSING

... common to all the

communicating
processors.

I2C, SPI, UART,

Shared Memory

Connect

One processor initiate communication by using a ACK

protocol. The protocol is designed based on the Messages
system and application. Response
Close

µP 1 µP 2
 ARM Cortex
A Series

Geared toward Consumer Devices

1-4 Symmetric Multi Processing
High clock speed Banana PI
CORTEX M3

A20 ARM Coretx -A7 Dual-

SoC capability Core
Compromised power efficiency
Memory Cache (L2, I, D)
Multi Level Pipeline
Hardware Virtualization
Hardware Floating Point

Cortex M Series is suitable for Hard Real Time

systems.
Raspberry PI 2
ARM Cortex-A7

Lectures\ARM\cortex_a72_mpcore_trm_100095_0001_02_en.pdf
 ARM Cortex M3 Core

32 bit Harvard Architecture

M Series Low Power
3 Stage Pipeline
High Performance
Low Interrupt Latency
M0: M0+ 2 state pipeline ultra lower Memory Protection Unit
Power. M0 – 3 stage pipeline compact 32 bit. Bit Banding
CORTEX M3

Single Cycle Multiply Accumulate

Saturation Modes
M1: ARM M core targeted for the Low Price
FPGA and ASIC market RISC Instructions

M3: High Performance embedded

systems with lower power consumption.

M4: High Performance embedded

systems with lower power consumption.
Adds Floating Point and DSP specific
instructions

M7: Six stage pipeline embedded

processor with multi core option. Multiple
Cache.
CORTEX M3
 ARM Cortex M3
TI Stellaris L3S300

Datasheet:
Lectures\ARM\ATSAM3N.pdf
CORTEX M3

GPIO – 8..36
Analog Comparator – 3
DAC – 1
SPI – 4
I2C – 2
TIMER – 2
UART – 2
USART – 2
PWM – 4

Synchronous Serial Interface

 Instructions: ABCDEFGH
ARM Cortex M3

Executed Instructions
Fe De Ex

A
B A
C B A
CORTEX M3

D C B A
E D C B
F E D C
G F E D
H G F E
H G F
H G
H
 ARM Cortex M3
Nested Vectored Interrupt Controller (NVIC)

●
33 Interrupts in SAM3N (M3 core supports 240
interrupts)
CORTEX M3

●
16 priority levels (0 → high priority)
●
Level or pulse input
●
Low latency
●
Dynamic reprioritization
●
Grouping and sub-priority fields
●
Interrupt tail-chaining
●
External NMI (Non Maskable Interrupt)
 ARM Cortex M3 Interrupts
Timer count down
interrupt usually used to
create multi-tasking

Timer count down

interrupt usually used to
create multi-tasking

Pendable interrupt driven

lower level system service
usually used for context
CORTEX M3

switching

Caused by illegal or
undefined instruction,
invalid instruction state or
fault in exception return

Caused by faults during

bus fetching of program or
data caused by memory Exception produced by
Supervisor call cased by fault Memory Protection Unit.
SVC instruction. Used to Caused by access
access kernel functions or violation or other memory
device drivers protection.

Caused by hardware error

during exception The second highest
processing. Highest priority interrupt after
priority after NMI RESET, which is usually
activated by NMI interrupt
pint of the processor

Power up reset or soft

resent. Causes to restart
the processor
 ARM Cortex M3
4.0 GB

3.5 GB
CORTEX M3

2.5 GB

1.5 GB

1.0 GB

0.5 GB
 ARM Cortex M3

Process Stack
Pointer
CORTEX M3

Main Stack Pointer

MSR Instruction to
switch stack poiner

[1] SPSEL, 0 = MSP, 1 = PSP

[0] nPRIV, 0 = Priv, 1 = UnP
 CORTEX M4 Saturation Instructions

Cortex M4 has DSP

friendly instructions
suitable for Real
Time Signal
CORTEX M3

Processing
 CORTEX M3 Read Modify Write
Read-Modify-Write instructions are required for exclusive
locking. Cortex M3 have built in instructions for it.

Requirements of Exclusive Lock Cortex M3 Ex Lock Instructions

LDREX [32 bit]
CORTEX M3

Read → Read from memory to accumulator STREX [32 bit]

Modify → Modify accumulator with new value LDREXH [16 bit]
Write → Write new value into memory STREXH [16 bit]
LDREXB [8 bit]
STREXB [8 bit]
READ MODIFY WRITE CLREX

LDREX{cond} Rt, [Rn {, #offset}]

Loads from memory at Rn with optional
offset int Rt if the optional cond is met.

Interrupts occurring at these points may cause STREX{cond} Rd, Rt, [Rn {, #offset}]
lock failure. Therefore, interrupts must be Stores to memory location pointed by Rn
disabled to achieve locking in a multi-cycle with optional offset the value in Rt if the
exclusive lock request
optional cond is met.
 CORTEX M3 Read Modify Write with Bit Banding
Cortex M3 allows easy bit manipulation without using AND, OR and SHIFT. Flipping a
bit is simply accessing bit-band memory location and read/write new value.

This operation of reading the bit, modifying it and writing the bit is atomic.
CORTEX M3

m-addr X X X X X 1 X X x

0 0 0 0 0 0 0 1 y=1

1 0 0 0 0 0 1 0 0 y <<= n

2 0 1
1 0 1
0 1
0 1
0 0
1 1
0 1
0 y ~= y

3 X X X X X 0
1 X X y &= x

m-addr = memory address

 CORTEX M3 - Bit Banding
Bit banding operation makes use of special single bit addressable memory location
which is at a constant offset from m-addr (memory address of the variable). By adding
the offset to the m-addr, and then adding the bit number * 4, the value of the bit can be
directly read or written just like any variable.
SRAM bit band region
bit band region m-addr = 0x2000:0000
CORTEX M3

bb-addr = 0x2200:0000
m-addr
X X X X X 1 X X x 0ffset = 0x0200:0000
m-addr+1
X X X X X X
1 X X Peripheral bit band region
m-addr = 0x4000:0000
X
7 X
6 X
5 X
4 X
3 12 X
1 X
0 bb-addr = 0x4200:0000
0ffset = 0x0200:0000

bb-addr + 7*4 n=2 (x+offset+n*4) = 0

0x0200:0040 alias region 0x2200:0008

bb-addr = m-addr + offset

X X X X X 0
1 X X 0x2200:0000

X X X X X X
1 X X
X
7 X
6 X
5 X
4 X
3 12 X
1 X
0 bb-addr = m-addr + 8*4 + offset
0x2200:0040
 CORTEX M3 - Bit Banding regions and map
CORTEX M3

1 byte
 Cortex M3 – Memory Protection Unit
Memory Protection Unit divides memory into 0-7 overlapping
regions with individual and isolated read/write privilege.

Cortex M3 Memory
CORTEX M3

0 1 2 3 4 6 5 7

Region 6 is
inside Region
5
If memory is protected,
X
Address X
Size X
Type X
Access 1
Permission
unauthorized access will give rise
to Exception interrupt.
X
MPUBASEx X MPUATTRx

Example:
NULL Pointer exception is write
NOTE: Cortex M3 - ATSAM3N does not have MPU, but TI LM3S300 have it.
protected memory. Any write will
cause exception Interrupt.
See Datasheet: ARM\TI_ARM_Cortex3_lm3s300.pdf
 Pre-emptive Multi tasking
Cortex M3 have built-in hardware to support preemptive multi-
tasking with minimal overhead

PendSV Interrupt

~ 20ms
CORTEX M3

3 Process 1 Process 2 Process 3 1

S L E S L E S L E S L

Loads context from data structure. Continue executing the Saves the context
This includes, setting all the program using the last for later use.
registers, and Program Counter. used context.

During Preemptive multi-tasking, the

PendSV interrupt is used to generate
low priority interrupt. In the ISR, the
context of the next process is loaded.
PendSV → Causes Periodic Linked Interrupt When the next PendSV interrupt
Modify → Modify accumulator with new value occurs, the running process is saved
and the next process is loaded.
Write → Write new value into memory
 Direct Memory Access (DMA)
In Real Time
systems,
processors
should not be

Arbiter DMA disturbed if DMA

CPU is available.
Controller
DMA takes over
the bus without
halting processor
Data Bus
and transfer data
DMA

directly from
memory/IO to
Address Bus memory/IO.

DMA controller
can transfer
blocks of data
from one device
I/O  I/O to another at
very high speed
while the
processor is
Memory I/O Device ACK processing with
internal data.
Memory  Memory REQ
 Direct Memory Access (DMA)
Memory DMA I/O
Controller Device
Memory  I/O
Block Block
DMA

Single Single

Memory  Memory I/O  I/O

Block Block

Memory  Memory I/O  I/O

Single Single
Memory  I/O

DMA Controllers may be programmed to transfer data from memory to memory,

memory to I/O or I/O to I/O either single or block of bytes.
 DMA in ATSAM3N Cortex M3
Memory DMA I/O
Controller
Device
TPR RPR

Block TCR RCR Block

TNPR RNPR
TNCR RNCR
DMA

Single TXTEN RXTEN Single

TXTDIS RXTDIS

T[N]PR (Transfer PointeR)

T[N]CR (Transfer CounteR)
Block R[N]PR (Receive PointeR) Block
R[N]CR (Receive CounteR)
TXTEN (Transmit Enable)
TXTDIS (Transmit Disable)
Single TXTEN (Receive Enable) Single
TXTDIS (Receive Disable)
[N] Indicate Next

To setup DMA from memory to I/O, set TPR to start memory location and TCR to number of
bytes to transfer. Set RPR to the start I/O location and RCR to the number of bytes to transfer.
Enable Transmit by setting TXTEN and enable receive by setting RXTEN channel bit.
 LVDS Signal for Displays
Low Voltage Differential Signal CLOCK
LVDS
RED
LVDS LCD
1. Used by most LCD and OLED displays for I/O
OLED
2. In LVDS, the electric fields created by the differential are GREEN
coupled, which minimize loss due to radiation. LVDS Matrix
3. LVDS signal cancels induced noise by the receiver. BLUE
4. Controlled LVDS can be exceptionally fast: 6.4 Gbps is LVDS
tested. Typical speed: 100 MHz to 2 GHz.
DISPLAY

5. High resolution displays use LVDS to reduce pin count

Single line LVDS driver.

Coupled line reduces induced noise.

Coupled lines increase SNR.

For Details Read: \Lectures\Display\LVDS.pdf

 LVDS (Continued)
DISPLAY

LVDS application
 TMDS (Transition Minimized
Differential Signal)
DISPLAY

1. Introduced by Silicon Image, Inc. USA.

2. HDMI and DVI uses TMDS protocol
3. Supports display upto 3840x2400.
4. TMDS protocol minimizes transition by
bit swapping.
5. If transition is not present for many bits,
TMDS introduces transition to maintain DC
balance.
6. Transmission of each channel is
differential.

For Details Read: \Lectures\Display\TMDS_SiI-WP-007-A.pdf

 TMDS (Continued)
DISPLAY
 TMDS (Continued)

DC Signal
All 1s
DISPLAY

All 0s
 HDMI HDMI – High Definition Multimedia Interface

1. HDMI is backward compatible with DVI

2. Uses TMDS protocol for each line.
3. Integrates Audio and Video into a single
channel.
DISPLAY
 HDMI/DVI Connector
DISPLAY
 Digital Micromirror Device
Youtube Video: \Video\How Digital Light Processing DLP works - YouTube.mp4

Details:
Screen \Lectures\Display\DMD_101_dlpa008a.pdf
White
Light
Digital Micromirror Device
(DMD) works by directing
light toward or away from the
screen creating the image
DISPLAY

Opaque on the screen.

Mirror

Single Chip DMD

Substrate Shades of color is created by

frequency of ON/OFF pixels.
ON OFF Light Shade
OFF → mirror flat
ON → mirror not flipping
ON OFF ON Dark Shade Shading → control pulse width
 Frame Buffer Video Encoder
This type of Display driver converts the image stored in a frame buffer and outputs it through physical display
output. To view the output one must have to connect a monitor or other type of display which is compatible with the
output signal.
LVDS – Low Voltage Differential Signal

Output Driver – isolates and

converts to differential signal
(if needed) suitable for
DISPLAY

physical output.
Frame Buffer – The entire Video Encoder – Encodes
VGA
image is created in the frame the frame buffer into video
buffer memory. stream suitable for various HDMI
output specifications.

TV OUT
Output
Video Video
Driver LCD LVDS
Frame Buffer Encoder
Display Port

Single Chip Solution

Epson S1D13746 TV-Out Graphics Engine

 Semiconductor Laser (Light Emission by
Stimulated Emission of Radiation)
Semiconductor Laser Inventor:
General Electric's
Dr Robert N. Hall
LASER

(1) A typical P-N semiconductor laser diode.

(2) P-type region (blue).
(3) N-type region (red).
(4) P-N junction region (resonant cavity) where light is produced by stimulated emission. This
isn't drawn to scale! In Hall's original patent, it's described as being 0.1 micron (0.1 millionths
of a meter, 0.1μm, or 1000 Angstroms) thick.
(5) Upper electrode.
(6) Solder fixing upper electrode to p-type region.
(7) Lower electrode.
(8) Solder fixing lower electrode to n-type region. (This covers the whole of the base of the n-
type region, not just the gray outer outline shown here.)
(9) Upper electrode connector.
(10) Lower electrode connector.
(11) Highly polished front surface.
(12) Highly polished rear surface, which must be precisely parallel to the front surface to
ensure standing waves of electromagnetic radiation (laser light) are produced and emitted
efficiently in the resonant cavity between the p-type and n-type regions. Surfaces 11 and 12
Original Patent
may be covered with mirrors or a metallic coating to improve the resonant effect.
(13) Side surface cut at an angle (or roughened) to prevent waves of light forming in other
directions.
(14) Other side surface cut at a similar angle or roughened in a similar way.
 Laser Semiconductor Materials

Laser (Continued) GaAs (gallium arsenide)

AlGaAs (aluminum gallium arsenide)
GaP (gallium phosphide)
InGaP (indium gallium phosphide)
The double heterostructure is one of the GaN (gallium nitride)
most basic Laser structures InGaAs (indium gallium arsenide)
Typical 5 layer structure GaInNAs (indium gallium arsenide nitride)
InP (indium phosphide)
GaInP (gallium indium phosphide)
LASER
 Laser (Continued)
LASER
 Laser (Continued)
LASER

Laser Diodes with

integrated photodiode
UV 400-100 nm
Blue 445 nm
Green 532 nm
Red 650 nm
Infra Red 1064 nm
 Laser (Continued)
Laser+Photodiode & filter
LASER

Pre-Amp Sensitivity Difference Driver

& buffer adjustment Amplifier

Laser Diode Driver using Discrete components

Startup time 20ms
 Line of sight laser beam or fiber

Laser (Continued)
optic cable

Laser Laser
Transceiver Transceiver
Texas Instruments
11.3-Gbps LASER DRIVER Laser Diodes with
integrated photodiode
LASER
 [BUS] PCI

PCI = Peripheral Component Interconnect

Used on all desktop PCs and Macs
BUS INTERFACING


Transfer up to 528 MB/s, PCI-X up to 4 GB/s

Up to 256 devices per system

Supports 5V and 3.3V signaling

Optimized for transferring blocks of data

Any device on bus can initiate bus transactions

Little-endian byte ordering

Supports plug-and-play
 [BUS] SCSI - Small Computer
System Interface
A bus that uses SCSI communication
protocol
BUS INTERFACING

Max 640 MB/sec

Parallel (8/16 bit)
Versions SCSI-1, SCSI-2, SCSI-3
Serial Attached SCSI (SAS) – 3Gbps speed
(Example, SAS Hard drive)
 [BUS] ATA - Advanced
Technology Attachment
Parallel
Max speed 100MB/s (ATA-6)
BUS INTERFACING

Serial ATA (SATA) – 150MB/s (Example, Hard

drive)
Power Supply
 Home Automation ZWave
ZigBee
SENSOR NETWORK

Bridge

Range:
ZigBee = 150ft
ZWave = 300ft

Zigbee and Zwave are both low power wireless mesh

network protocol used primarily in sensor networking.
ZigBee is IEEE 802.15.4, ZWave is a proprietary
technology from Zensys.
 Mesh Network
ZWave ZigBee
900MHz @ 100kbps 2.4GHz @ 250kbps
232 devices per 868MHz @ 20kbps
network (EU)
The mesh network extends by
915MHz @ 40kbs (NA)
hopping through other nodes.
SENSOR NETWORK

Mesh creation Dynamic routing

Dynamic re-routing
 ZigBee
SENSOR NETWORK

Off the shelf ZigBee mesh module for

use with Arduino/Raspberry PI

Lectures\SensorNetwork\ds_xbeezbmodules.pdf

High performance On Chip ZigBee

implementation with SPI interface.
Lectures\SensorNetwork\atmel-8351-mcu_wireless-at86rf233_datasheet.pdf
 ZWave 900MHz @ 100kbps
232 devices per
network
SENSOR NETWORK

ZWave products are available from Sigma Designs: http://www.sigmadesigns.com

Surface Mount Technology
SMT Diode

SMT
Transistors Advantages
●
Small Size
Ball Grid
Array (BGA)
●
Low Inductance
●
Double Sided Boards
●
Low Price
●
Good Temperature
SMT
Capacitors
Tolerance
●
Small PCB
●
Mechanically Rigid
SMT
Resistors
●
Fast Assembly by Pick &
Place Machine

Quad Flat
Pack (QFP)

SMT
Tantalum
Capacitors
Surface Mount Processors

Ball Grid Array (BGA)

Highest pin density Quad Flat No-lead (QFN)
Medium pin density

Quad Flat Pack (QFP) Pin Grid Array (PGA)

Medium pin density High pin density
 Surface Mount Technology
Resistors & Capacitors
Metal Oxide Insulation Terminal
resistive film Tolerance: 5%, 2%, 1%, 0.5% & 0.1%

Package L x W, mm L x W, in Watt
SENSOR NETWORK

2512 6.30 x 3.10 0.25 x 0.12 0.50 (1/2)

W 2010 5.00 x 2.60 0.20 x 0.10 0.25 (1/4)

1812 4.6 x 3.0 0.18 x 0.12

1210 3.20 x 2.60 0.12 x 0.10 0.25 (1/4)

H
Side View 1206 3.0 x 1.5 0.12 x 0.06 0.125 (1/8)

0805 2.0 x 1.3 0.08 x 0.05 0.1 (1/10)

0603 1.5 x 0.08 0.06 x 0.03 0.0625 (1/16)

0402 1 x 0.5 0.04 x 0.02 1/16 - 1/32

0201 0.6 x 0.3 0.02 x 0.01 0.05

W
Top SMT Capacitor
View Construction

Packag Package
e 25 12 0.25 x 0.12 Dimension
Style
E24 Standard Resistor Values
Standard Resistor Values (  5%)
1.0 10 100 1.0K 10K 100K 1.0M
1.1 11 110 1.1K 11K 110K 1.1M
1.2 12 120 1.2K 12K 120K 1.2M
1.3 13 130 1.3K 13K 130K 1.3M 101/24 = 1.1
1.5 15 150 1.5K 15K 150K 1.5M
1.6 16 160 1.6K 16K 160K 1.6M
1.8 18 180 1.8K 18K 180K 1.8M Rnext = Rprev * 1.1
2.0 20 200 2.0K 20K 200K 2.0M
2.2 22 220 2.2K 22K 220K 2.2M
2.4 24 240 2.4K 24K 240K 2.4M
2.7 27 270 2.7K 27K 270K 2.7M
3.0 30 300 3.0K 30K 300K 3.0M
3.3 33 330 3.3K 33K 330K 3.3M
3.6 36 360 3.6K 36K 360K 3.6M
3.9 39 390 3.9K 39K 390K 3.9M
4.3 43 430 4.3K 43K 430K 4.3M
4.7 47 470 4.7K 47K 470K 4.7M
5.1 51 510 5.1K 51K 510K 5.1M
5.6 56 560 5.6K 56K 560K 5.6M
6.2 62 620 6.2K 62K 620K 6.2M
6.8 68 680 6.8K 68K 680K 6.8M
7.5 75 750 7.5K 75K 750K 7.5M
8.2 82 820 8.2K 82K 820K 8.2M
9.1 91 910 9.1K 91K 910K 9.1M
E12 Standard Capacitor Values
101/12 = 1.21

Rnext = Rprev * 1.21

Standard Capacitor Values ( ± 10%)

10pF 100pF 1000pF .010 µ F .10 µ F 1.0 µ F 10 µ F

12pF 120pF 1200pF .012 µ F .12 µ F 1.2 µ F
15pF 150pF 1500pF .015 µ F .15 µ F 1.5 µ F
18pF 180pF 1800pF .018 µ F .18 µ F 1.8 µ F
22pF 220pF 2200pF .022 µ F .22 µ F 2.2 µ F 22 µ F
27pF 270pF 2700pF .027 µ F .27 µ F 2.7 µ F
33pF 330pF 3300pF .033 µ F .33 µ F 3.3 µ F 33 µ F
39pF 390pF 3900pF .039 µ F .39 µ F 3.9 µ F
47pF 470pF 4700pF .047 µ F .47 µ F 4.7 µ F 47uF
56pF 560pF 5600pF .056 µ F .56 µ F 5.6 µ F
68pF 680pF 6800pF .068 µ F .68 µ F 6.8 µ F
82pF 820pF 8200pF .082 µ F .82 µ F 8.2 µ F
Advanced EDA Tools

Mentor Graphics:
http://mentorgraphics.com - Advanced
PCB Design (64 bit and above),
Simulation, Verification, IC Layout, etc.

Cadence: http://cadence.com - IC Design,
Layout, Advanced PCB Design (64 bit and
above), Simulation, etc. OrCad is owned
by Cadence.

Synopsys: http://synopsys.com - VLSI
Design, verification and synthesis. Not for
PCBs.
Intentionally Left Blank