High-Speed DSP and Analog System Design

Thanh T. Tran

High-Speed DSP and Analog

System Design
Thanh T. Tran
Texas Instruments Incorporated
12203 Southwest Freeway, MS 722
Stafford, TX 77477
USA

ISBN 978-1-4419-6308-6 e-ISBN 978-1-4419-6309-3

DOI 10.1007/978-1-4419-6309-3
Springer New York Dordrecht Heidelberg London

Library of Congress Control Number: 2010926196

© Springer Science+Business Media, LLC 2010

All rights reserved. This work may not be translated or copied in whole or in part without the
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To my family, Nga, Lily, Kevin and Robin
 Preface

This book covers the high-speed DSP and analog system design techniques
and highlights common pitfalls causing noise and electromagnetic interfer-
ence problems engineers have been facing for many years. The material in
this book originated from my high-speed DSP system design guide (Texas
Instruments SPRU 889), my system design courses at Rice University and
my experience in designing computers and DSP systems for more than 25
years. The book provides hands-on, practical advice for working engi-
neers, including:
• Tips on cost-efficient design and system simulation that minimize
late-stage redesign costs and product shipment delays.
• 11 easily-accessible chapters in 210 pages.
• Emphasis on good high-speed and analog design practices that mi-
nimize both component and system noise and ensure system de-
sign success.
• Guidelines to be used throughout the design process to reduce
noise and radiation and to avoid common pitfalls while improve
quality and reliability.
• Hand-on design examples focusing on audio, video, analog filters,
DDR memory, and power supplies.
The inclusion of analog systems and related issues cannot be found in oth-
er high-speed design books.

vii
Preface viii

This book is intended for practicing engineers and is organized as follows:

• Chapter 1: Highlights challenges in designing video, audio, and
communication systems.
• Chapter 2: Covers transmission line theories and effects. Dem-
onstrates different signal termination schemes by performing sig-
nal integrity simulations and lab measurements.
• Chapter 3: Shows the effects of crosstalk and methods to reduce
interference.
• Chapter 4: Provides an overview of switching and linear power
supplies and highlights the importance of having proper power se-
quencing schemes and power supply decoupling.
• Chapter 5: Covers the analytical and general power supply de-
coupling techniques.
• Chapter 6: Covers design considerations of analog phase-locked
loop (APLL) and digital phase-locked loop (DPLL) and how to
isolate noise from affecting APLL and DPLL jitter.
• Chapter 7: Presents an overview of data converter, sampling
techniques and quantization noise.
• Chapter 8: Covers analog active and passive filter design includ-
ing operational amplifier design with single-rail and dual-rail
power supplies.
• Chapter 9: Provides memory sub-system design considerations.
Includes DDR overview, signal integrity and design example.
• Chapter 10: Covers printed circuit board (PCB) stackup and sig-
nal routing considerations.
• Chapter 11: Describes sources of electromagnetic interference
(EMI) and how to mitigate them.
 ACKNOWLEDGMENTS
I would like to thank many of my colleagues at Texas Instruments Incor-
porated who encouraged me to write this manuscript, Kevin Jones for do-
ing the lab measurements to validate some of the theoretical concepts and
simulations and Cathy Wicks for her outstanding support in many ways.
Also special thanks to Jennifer Maurer and Jennifer Evans of Springer for
giving me this writing opportunity and for reviewing and providing great
suggestions. This book would not have been possible without the help and
support from all these great individuals.
And, I just can’t thank my brother, Nhut Tran, enough for tirelessly
spending weeks to review and edit every chapter in this book. As for my
daughter, Lily Tran, instead of relaxing over the Christmas break from
months of extremely hard work at Massachusetts Institute of Technology,
she voluntarily reviewed the entire manuscript and provided invaluable in-
puts. Again, sincere thanks to both Nhut and Lily for doing this!
Finally, for my wife, Nga, I am still amazed with how she can hold a
very demanding full-time job at HP and still find time to provide great
support to me and care to our kids. She is truly an amazing friend and a
remarkable soccer mom.

Thanh T. Tran
Houston, Texas, 2010

ix
 Contents

Chapter 1: Challenges of DSP Systems Design.............................1

1.1 High-Speed Dsp Systems Overview.......................................2
1.2 Challenges Of Dsp Audio System ..........................................5
1.3 Challenges Of Dsp Video System ..........................................6
1.4 Challenges Of Dsp Communication System ..........................8
References....................................................................................11

Chapter 2: Transmission Line (TL) Effects................................13

2.1 Transmission Line Theory....................................................14
2.2 Parallel Termination Simulations .........................................19
2.3 Practical Considerations Of TL ............................................21
2.4 Simulations And Experimental Results Of TL.....................22
2.4.1 TL Without Load Or Source Termination ..................22
2.4.2 TL With Series Source Termination ...........................24
2.5 Ground Grid Effects On TL..................................................27
2.6 Minimizing TL Effects .........................................................28
References....................................................................................30

Chapter 3: Effects of Crosstalk ....................................................31

3.1 Current Return Paths.............................................................31
3.2 Crosstalk Caused By Radiation ............................................36
3.3 Summary...............................................................................41
References....................................................................................43

xi
xii Contents

Chapter 4: Power Supply Design Considerations ......................45

4.1 Power Supply Architectures .................................................45
4.2 DSP Power Supply Architectural Considerations ................55
4.2.1 Power Sequencing Considerations..............................61
4.3 Summary...............................................................................64
References....................................................................................65

Chapter 5: Power Supply Decoupling .........................................67

5.1 Power Supply Decoupling Techniques.................................67
5.1.1 Capacitor Characteristics ............................................69
5.1.2 Inductor Characteristics ..............................................72
5.1.3 Ferrite Bead Characteristics........................................74
5.1.4 General Rules-Of-Thumb Decoupling Method ..........75
5.1.5 Analytical Method of Decoupling ..............................77
5.1.6 Placing Decoupling Capacitors...................................91
5.2 High Frequency Noise Isolation ...........................................94
5.2.1 Pi Filter Design ...........................................................95
5.2.2 T Filter Design ............................................................98
5.3 Summary.............................................................................102
References..................................................................................104

Chapter 6: Phase-Locked Loop (PLL) ......................................105

6.1 Analog PLL (APLL)...........................................................105
6.1.1 PLL Jitter ..................................................................107
6.2 Digital PLL (DPLL) ...........................................................111
6.3 PLL Isolation Techniques...................................................114
6.3.1 Pi and T Filters..........................................................114
6.3.2 Linear Voltage Regulator..........................................118
6.4 Summary.............................................................................119
References..................................................................................120

Chapter 7: Data Converter Overview .......................................121

7.1 Dsp Systems........................................................................121
7.2 Analog-To-Digital Converter (ADC) .................................122
7.2.1 Sampling ...................................................................124
7.2.1 Quantization Noise....................................................126
7.3 Digital-To-Analog Converter (DAC) .................................130
Contents xiii

7.4 Practical Data Converter Design Considerations ...............132

7.4.1 Resolution and Signal-to-Noise ................................133
7.4.2 Sampling Frequency .................................................134
7.4.3 Input and Output Voltage Range ..............................134
7.4.4 Differential Non-Linearity (DNL) ............................135
7.4.5 Integral Non-Linearity (INL)....................................137
7.5 Summary.............................................................................138
References..................................................................................140

Chapter 8: Analog Filter Design ................................................141

8.1 Anti-Aliasing Filters ...........................................................141
8.1.1 Passive and Active Filters Characteristics ................142
8.1.2 Passive Filter Design.................................................143
8.1.3 Active Filter Design..................................................146
8.1.4 Operation Amplifier (op amp) Fundamentals...........147
8.1.5 DC and AC Coupled .................................................155
8.1.6 First Order Active Filter Design ...............................164
8.1.7 Second Order Active Filter Design...........................169
8.2 Summary.............................................................................175
References..................................................................................176

Chapter 9: Memory Sub-System Design Considerations ........177

9.1 DDR Memory Overview ....................................................177
9.1.1 DDR Write Cycle......................................................179
9.1.2 DDR Read Cycle.......................................................181
9.2 DDR Memory Signal Integrity ...........................................181
9.3 DDR Memory System Design Example.............................183
References..................................................................................186

Chapter 10: Printed Circuit Board (PCB) Layout...................187

10.1 Printed Circuit Board (PCB) Stackup...............................187
10.2 Microstrip And Stripline...................................................190
10.3 Image Plane ......................................................................192
10.4 Summary...........................................................................193
References..................................................................................194
xiv Contents

Chapter 11: Electromagnetic Interference (EMI)....................195

11.1 FCC Part 15B Overview...................................................195
11.2 EMI Fundamentals............................................................197
11.3 Digital Signals ..................................................................199
11.4 Current Loops ...................................................................201
11.5 Power Supply....................................................................202
11.6 Transmission Line ............................................................204
11.7 Power And Ground Planes................................................206
11.8 Summary: EMI Reduction Guidelines.............................208
References..................................................................................210

Glossary .........................................................................................211

Index ..............................................................................................213
 About The Author

DR. THANH TRAN has over 25 years of experience in high-speed DSP,

computer and analog system design and is an engineering manager at Tex-
as Instruments Incorporated. He currently holds 22 issued patents and has
published more than 20 contributed articles. He is also an adjunct faculty
member at Rice University where he teaches analog and digital embedded
systems design courses. Tran received a BSEE degree from the University
of Illinois at Urbana-Champaign, Illinois in 1984 and Master of Electrical
Engineering and Ph.D. in Electrical Engineering degrees from the Univer-
sity of Houston, Houston, Texas in 1995 and 2001 respectively.

xv
 Challenges of DSP
Systems Design 1

As DSP performance levels and clock frequencies continue to rise at a

rapid rate, managing noise, radiation and power consumption becomes an
increasingly important issue. At high frequencies, the traces on a PCB car-
rying signals act as transmission lines and antennas that can generate sig-
nal reflections and radiations that cause distortion and create challenges in
achieving electromagnetic compatibility (EMC) compliance. These can of-
ten make it difficult to meet Federal Communication Commission (FCC)
Class A and Class B [1] requirements. Heat sinks and venting that may be
required to address the thermal challenges of high performance designs
can further exacerbate EMC problems. Many systems today have embed-
ded wireless local area network (WLAN) and Bluetooth which will create
further difficulties as intentional radiators are designed into the system.

With these difficulties, it’s necessary to rethink the traditional high speed
DSP design process. In the traditional approach, engineers focus on the
functional and performance aspects of the design. Noise and radiation are
considered only towards the later stages of the design process, if and when
prototype testing reveals problems. But today, noise problems are becom-
ing increasingly common and more than 70% of new designs fail first-time
EMC testing. As a result, it is essential to begin addressing these issues
from the very beginning of the design process. By investing a small
amount of time in the use of low-noise and low-radiation design methods

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_1, 1
© Springer Science+Business Media, LLC 2010
2 Chapter 1

at the beginning of the development cycle, this will generate a much more
cost efficient design by minimizing late-stage redesign costs and delays in
the product ship date.

1.1 HIGH-SPEED DSP SYSTEMS OVERVIEW

Typical DSP systems such as the one shown in Figure 1.1 consist of many
external devices such as audio CODEC, video, LCD display, wireless
communication (Bluetooth, GPS, UWB and IEEE 802.11), Ethernet
controller, USB, power supply, oscillators, storage, memory and other
supporting circuitries. Each of these components can either be a noise
generator or be affected by interferences generated by neighboring
components. Therefore, applying good high speed design practices are
necessary in order to minimize both component and system related noise
and to ensure system design success.

DDR

RGB888/
YUV422
HDMI
HD Camera VIDEO
Receive IN RGB888 HD
VIDEO
OUT
Panel
1000
GMII
BaseT SPI
Ethernet Touch-
PHY Screen
1000 HDMI
BaseT
GMII
DSP/SoC HD
Ethernet
PHY Display
EMIF
NOR or NAND USB Port1
FLASH USB Port2
Mic Array McASPs
AUDIO COMM SDIO
Audio
IN/OUT IN/OUT WLAN
CODECs
UART
GPS
PCI
WLAN/ PCI SPI
Serial
UWB
ROM

CORE
POWER
Power SUPPLY
PLL OSC
IO/DDR

Figure 1.1. Typical DSP System

Challenges of DSP Systems Design 3

The coupling between a noise source and noise victim causes electrical
noise. Figure 1.2 shows a typical noise path. The noise source is typically a
fast-switching signal and the noise victim is the component carrying the
signal. The noise victim’s performance will be impacted by the noise.
Coupling takes place through the parasitic capacitances and mutual induct-
ances of the adjacent signals and circuits. Electromagnetic coupling occurs
when the signal traces become effective antennas, which radiate and gen-
erate interferences to the adjacent circuitries.

Figure 1.2. A Typical Noise Path

There are many mechanisms by which noise can be generated in an elec-

tronic system. External and internal DSP clock circuits generally have the
highest toggle rates and the primary source of high frequency noise. Im-
properly terminated signal lines may generate reflections and signal distor-
tions. Also, improper signal routing, grounding and power supply decoup-
ling may generate significant ground noise, crosstalk and oscillations.
Noise can also be generated within semiconductors [2] themselves:

• Thermal Noise: Also known as Johnson noise is present in all re-

sistors and is caused by random thermal motion of electrons.
Thermal noise can be minimized in audio and video designs by
keeping resistance as low as possible to improve the signal-to-
noise ratio.

• Shot Noise: Shot noise is caused by charges moving randomly

across the gate in diodes and transistors. This noise is inversely
proportional to the DC current flowing through the diode or tran-
sistor, so the higher DC operating current increases the signal-to-
noise ratio. Shot noise can become an important factor when the
DSP system includes many analog discrete devices on the signal
paths, for example discrete video and audio amplifiers.
4 Chapter 1

• Flicker Noise: Also known as 1/f noise is present in all active de-
vices. It is caused by traps where charge barriers are captured and
released randomly, causing random current fluctuations. Flicker
noise is a factor of semiconductor process technologies, so DSP
system design cannot reduce it at the source but focus should be
on mitigating its effects.

• Burst Noise and Avalanche Noise: Burst Noise, also known as

popcorn noise, is caused by ion contamination. Avalanche Noise is
found in devices such as zener diodes that operate in reverse
breakdown mode. Both of these types of noise are again related to
the semiconductor process technology rather than system design
techniques.
Since government regulates the amount of electromagnetic energy that can
be radiated, DSP systems designers must also be concerned with the poten-
tial for radiating noise to the environment. The main sources of radiation
are digital signals propagating on traces, current return loop areas, inade-
quate power supply filtering or decoupling, transmission line effects and
lack of return and ground planes. It’s also important to note that at Giga-
hertz speeds, heat sinks and enclosure resonances can amplify radiation.
Noise in DSP systems cannot be eliminated but it can be minimized to en-
sure that it is not interfering with other circuits in the system. The three
ways to reduce noise are suppressing it at the source, making the adjacent
circuits insensitive to the noise and eliminating the coupling channel.
High-speed design practices can be applied to minimize both component
and system related noise and improve the probability of system design
success. This book will address all three areas by providing guidelines that
can be used from the very beginning of the design process through trouble-
shooting to reduce noise and radiation to acceptable levels. The noise-
sensitive interface examples shown in this document are focused on audio,
video, memory and power supply. The performances of these systems are
greatly affected by the surrounding DSP circuitries and how these circuits
interfaced to the DSP.
Challenges of DSP Systems Design 5

1.2 CHALLENGES OF DSP AUDIO SYSTEM

Audio systems represent one of the greatest challenges for high-speed
DSP design. Because of relatively small levels of noise often have a no-
ticeable impact on the performance of the finished product. In audio cap-
ture and playback, audio performance depends on the quality of the audio
CODEC being used, the power supply noise, the audio circuit board lay-
out, and the amount of crosstalk between the neighboring circuitries. Also,
the stability of the sampling clock has to be very good to prevent un-
wanted sounds such as pops and clicks during playback and capture. Fig-
ure 1.3 shows a typical signal chain of the DSP audio design. Most of
DSPs include a Multi-Channel Buffered Serial Port or McBSP [3] for in-
terfacing with external audio CODECs. Although this is a proprietary in-
terface, it is configurable to work with the industry standard I2S audio
CODECs.

Figure 1.3. DSP Audio System

All of the blocks shown in Figure 1.3 from the ADC to the Amp stage are
very sensitive to noise so any interference coupled to any of the blocks will
propagate and generate unwanted audible sounds. Common audio design
problems include:

• Noise coupled to the microphone input. Mic input typically

has a very high gain (+20dB) so a small amount of noise can
generate audible sounds.

• Not having an anti-aliasing filter at the audio inputs.

• Excessive distortion due to gain stage and to amplitude mis-

match.
6 Chapter 1

• Excessive jitter on audio clocks, bit clock and master clock.

• Lack of good decoupling and noise isolation techniques.

• Not using a linear regulator with high power supply rejection

to isolate noise from the audio CODEC.

• Not having good decoupling capacitors on the reference volt-

age used for ADC and DAC converters.

• Switching power supply noise coupled to the audio circuits.

• High impedance audio traces are adjacent to noisy switching

circuits and no shortest current return path is provided in the
printed circuit board (PCB) layout to minimize the current re-
turn loop between the DSP and the CODEC.

• Not having isolated analog and digital grounds.

In summary, having good audio performance requires proper design of the
ADCs, DACs, DSP interfaces, clocks, input/output filters, power supplies
and the output amplifier circuits. The performance of all these circuits not
only depends on how well the circuits are being designed, but also on how
the grounds and power being isolated and the PCB traces being routed.

1.3 CHALLENGES OF DSP VIDEO SYSTEM

Video processing is another important DSP application that is highly sen-
sitive to noise and radiation. One of the major challenges of video systems
design is to how to eliminate video artifacts such as color distortion, 60Hz
hum, visible high frequency interferences caused fast switching buses, au-
dio beat, etc. These issues are generally related to improper video board
design and PCB layout. For example, power supply noise may propagate
to the video DAC output, audio playback may cause transients in the
power supply, and the high frequency radiations may couple back to the
tuner. Here are some common video noise issues:

• Signal integrity, excessive overshoots and undershoots on the

HSYNC, VSYNC and pixel clocks caused by improper signal
terminations.
Challenges of DSP Systems Design 7

• Excessive radiations from high speed buses such as PCI, parallel

video ports (BT.1120, BT.656) and DDR memory.

• Excessive encoder, decoder and pixel clock jitter causes problems

with detecting the color information. For example, the color screen
only displays black and white images.

• The lack of video termination resistors will cause distortion of the

video image. A 75-ohm termination resistor must be used at the
input of the video decoder and the output of the video encoder.

• Audio playback may cause a flicker on the video screen. This can
be corrected by increasing the isolation of the video and audio cir-
cuits. The best method is by using high power supply rejection ra-
tio (PSRR) linear regulators to isolate the audio CODEC and the
video encoder/decoder supplies. Also, manually route the critical
traces away from any of the switching signals to reduce the
crosstalk and interferences.

• An isolated analog ground without a high-speed signal return path.

It’s important to remember that for a low speed signal, below 10
MHz, current returns on the lowest resistance, which usually is the
shortest path. High-speed current, on the other hand, returns on
the path with the least inductance, usually underneath the signal.
Figure 1.4 shows a typical DSP HD video system where the analog video
signals, high definition (HD) and standard definition (SD), are captured,
processed and then displayed. The quality of this video signal path deter-
mines the video performance of the display, especially at the input video
stages and at the output video stages. Since the system design and layout
are very critical, it is necessary to apply the high-speed design rules dis-
cussed in this book to reduce the negative effects of the switching noise,
crosstalk and power supply transients in order to reduce or eliminate video
artifacts. In this system, the digital video inputs and outputs such as High
Definition Media Interface (HDMI), Digital Video Interface (DVI) and
DisplayPort (DP) are also highly sensitive to system noise as noise causes
jitter which increases the bit error rate (BER). As in any electronic sys-
tems, it is not possible to eliminate the noise totally but applying good de-
sign techniques will reduce the risk of having a negative impact on per-
formance.
8 Chapter 1

In any HD video systems, there are many wide high speed busses switch-
ing at a rate of 66MHz or higher and these buses generating broadband
noise and harmonics that cause radiations in the Gigahertz range. This
type of interference is very difficult to control because there are so many
of these busses on the board and it is not practical to terminate every signal
trace being routed from one point to another. The good news is that there
are good design practices to follow in order to minimize the interference.

Figure 1.4. DSP HD Video System

1.4 CHALLENGES OF DSP COMMUNICATION SYSTEM

Like video and audio systems, communication is another important DSP
application that is highly sensitive to noise and radiation. One of many
challenges here is creating systems with multiple powerful and highly in-
tegrated DSPs that deliver high performance with very low bit error rate
and interference. In these systems, interference not only generates EMI
problems but also jams other communication channels and causes false
channel detection. These issues can be minimized by applying proper
board design techniques, shielding, RF and mixed analog/digital signals
isolation. In some cases, a spread spectrum clock generator may be re-
quired to further reduce the interference and to improve the signal-to-noise
ratio. Although spread spectrum clock reduces the peak level radiation,
the harmonics of this clock are spreading over a wider bandwidth and this
can cause inter-channel interference so engineers must be careful when us-
ing this type of clock generator circuit. Table 1.1 shows high speed buses
Challenges of DSP Systems Design 9

generating harmonics that interfering with embedded Wireless Local Area

Networks (WLAN). One example of the communication systems is
shown in Figure 1.5 where both Bluetooth and IEEE802.11 are being im-
plemented on the same motherboard and residing on the same 2.4GHz RF
spectrum. The most difficult tasks are how to prevent the two systems
from interfering with each other and how to prevent radiations from the
high speed busses (PCI Express, DDR2 and display) interfering with the
embedded antennas. By applying the rules outlined in this book, engi-
neers will improve and increase the probability for design success.

Table 1.1. High Speed Busses Interference [4]

Standards: Wireless Interfering Clocks and

Networking: Busses:

Bluetooth Personal Area Network Gigahertz Ethernet, PCI

(2.4GHz band) Express, Display clock har-
monics

IEEE 602.11b/g WLAN (2.4 GHz Gigahertz Ethernet, PCI

band) Express, Display clock har-
monics

IEEE 802.11n High Speed WLAN (5 Gigahertz Ethernet, PCI

GHz band) Express, Display clock har-
monics

IEEE 802.16e Mobile Broadband PCI Express, Display har-

(Wi-Max, 10GHz to monics
66GHz band)

IEEE 802.11a WLAN (5GHz band) PCI Express, Display clock

harmonics
10 Chapter 1

Figure 1.5. DSP Communication System

Challenges of DSP Systems Design 11

REFERENCES
[1] Federal Communication Commission (2005) Unintentional Radiators
Title 47 (47CFR), Part 15 B.
http://www.fcc.gov/oet/info/rules/part15/part15-91905.pdf
[2] Hiers T and Ma R (1999) TMS320C6000 McBSP: I2S Interface.
Texas Instruments Inc’s Application Report, SPRA595.
[3] Franco S (2002) Design with Operational Amplifiers and Analog Inte-
grated Circuits. McGraw-Hill, New York.
[4] Nassar M, Gulati K, DeYoung M, Evans B, and Tinsley K (2008)
Mitigating Near-field Interference in Laptop Embedded Wireless
Transceivers. IEEE Journal of Signal Processing Systems.
 Transmission Line (TL) Effects 2

Transmission line (TL) effects are one of the most common causes of
noise problems in high-speed DSP systems. When do traces become TLs
and how do TLs affect the system performance? A rule-of-thumb is that
traces become TLs when the signals on those traces have a rise-time (Tr)
less than twice the propagation delay (Tp). For example, if a delay from
the source to the load is 2nS, then any of the signals with a rise-time less
than 4nS becomes a TL. In this case, termination is required to guarantee
minimum overshoots and undershoots caused by reflections. Excessive TL
reflections can cause electromagnetic interference and random logic or
DSP false-triggering. As a result of these effects, the design may fail to get
the FCC certification or to fully function under all operating conditions
such as at high temperatures or over-voltage conditions.
There are two types of transmission lines, lossless and lossy. The ideal
lossless transmission line has zero resistance while a lossy TL has some
small series resistance that distorts and attenuates the propagating signals.
In practice, all TLs are lossy. Modeling of lossy TLs is a difficult chal-
lenge that is beyond the scope of this book. Since the focus of this book is
only on practical problem-solving methods, it assumes a lossless TL to
keep things simple. This is a reasonable assumption because in DSP sys-
tems where the operating frequency is less than 1GHz the losses on printed
circuit board traces are negligible compared to losses in the entire signal
chain, from analog to digital and back to analog.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_2, 13
© Springer Science+Business Media, LLC 2010
14 Chapter 2

2.1 TRANSMISSION LINE THEORY

A lossless TL is formed by a signal propagating on a trace that consists of
series parasitic inductors and parallel capacitors as shown in Figure 2.1.
L1 L2 L3 L4

C1 C2 C3 C4

Figure 2.1. Lossless Transmission Line Model

The speed of the signal, Vp, is dependant on properties such as characteris-

tic impedance, Zo, which is defined as an initial voltage V+ divided by the
initial current I+ at some instant of time. The Eqs. (2.1) and (2.2) for Vp
and Zo are

1
Vp = , (2.1)
LC

L
Zo = , (2.2)
C
where L is inductance per unit length and C is capacitance.
Another important property of the TL is the propagation delay, Td. The Eq.
(2.3) for Td is

1
Td = = LC . (2.3)
Vp
The source and load TL reflections depend on how well the output imped-
ance and the load impedance, respectively, are matched with the character-
istic impedance. The load and source reflection coefficients, Eq. (2.4) and
Eq. (2.5), are
Transmission Line (TL) Effects 15

Z S − ZO
ΓS = source _ reflections = , (2.4)
Z S + ZO

Z L − ZO
ΓL = load _ reflections = , (2.5)
Z L + ZO

where ZS and ZL are the source impedance and load impedance respec-
tively.
The following example shows the characteristics of a TL with no load and
with a 3V signal source driving the line.
Example 2.1: Calculate the voltage at the open ended load of the
transmission line below.

Figure 2.2. Open Ended Transmission Line

Zo 50
V initial = V clk =3 = 2V
Zs + Zo 25 + 50

Zs − Zo 25 − 50
ρs = = = −0.333
Zs + Zo 25 + 50
Z L − Zo
ρL = =1
Z L + Zo
16 Chapter 2

In Figure 2.3, the overshoot voltage can be calculated using a lattice dia-
gram [1] as follows.

At T1 = 1.8nS: VL= Vi + ρLVi = 2+2 = 4.0V,

At T2 = 3.6nS: VS=4.0V + ρSVi = 4.0V – 0.67V = 3.33V,

At T3 = 5.4nS: VL= 3.33V + ρL(ρSVi) = 3.33 – 0.67 = 2.66V,

At T4 = 7.2nS: Vs = 2.66V + ρS[ρL(ρSVi)] = 2.66 + 0.22 = 2.88V,

At T5 = 9.0nS: VL = 2.88 + ρL (0.22) = 3.1V

Figure 2.3. Lattice Diagram of Open Ended TL

Transmission Line (TL) Effects 17

Figure 2.4. Voltage Waveform at the Open Ended Load

As shown in Example 2.1, the reflections with a 3V source caused the sig-
nal to overshoot as high as 4V at the load as explained below:

• The initial voltage level at the load at time T1 depends on the

load impedance, which is infinite for an open load, and the
characteristic impedance of the TL.

• The voltage level at time T2, when the reflected signal arrives
at the source, depends on the source impedance and the char-
acteristic impedance of the TL.

• The voltage level at time T3, when the reflected signal arrives
at the load again, depends on the reflected voltage at T2 plus
the reflected voltage at time T3.

• This process continues until steady state is reached. In this ex-

ample, the steady state occurs at T5, which is 9nS from T1, as
shown in Figure 2.3.
18 Chapter 2

Figure 2.5 shows the waveforms at the load for both terminated and
unterminated circuits. As shown in the previous example, the terminated
TL has a zero reflection coefficient and therefore no ringing occurs on the
waveform as seen on the top graph of Figure 2.5. The problem is that in
high-speed digital design, adding a 50-ohm resistor to ground at the load is
not practical because this requires the buffer to drive too much current per
line. In this case, the current would be 3.3V / 50 = 66mA. A technique
known as parallel termination can be used to overcome this problem. It
consists of adding a small capacitor in series with the resistor at the load to
block DC. The RC combination should be much less than the rise and fall
times of the signal propagating on the trace.

Figure 2.5. Voltage Waveforms at the Terminated and

Unterminated Loads

Figure 2.6. Parallel Termination with Multiple Loads

Transmission Line (TL) Effects 19

Figure 2.6 shows a parallel termination technique. This method can be

used in the application where one output drives multiple loads as long as
the traces to the loads called L2 are a lot shorter than the main trace L1.
To use the parallel termination technique, it is necessary to calculate the
maximum allowable value for L2 according Eq. (2.6) below assuming the
main trace L1 and the rise-time Tr are known.

tr
L2 , max = L 1
10 (2.6)

2.2 PARALLEL TERMINATION SIMULATIONS

Parallel termination techniques become useful when designers have to use
a single clock output to drive multiple loads to minimize the clock skew
between the loads. In this case, having a series resistor at the source limits
the drive current to the loads and may cause timing violations by increas-
ing rise-times and fall-times. This simulation example includes one 6”
trace (L1) and two 2” stubs. The DSP [2] drives the main L1 trace and one
memory device connected to each end of the 2” trace. It is reasonable to
neglect the effects of the stubs as long as they are short and meet the crite-
ria shown in Figure 2.7. In this case, only one parallel termination (68
ohms and 10pF) is required at the split of the main trace to the loads. Re-
ferring to the simulation result in Figure 2.8, the waveforms at the loads
look good and meet all the timing requirements for the memory devices.
As expected for the “no series” termination case, the waveform at the
source does not look good but this does not affect the system integrity at
the load.

Figure 2.7. Parallel Termination Configuration

20 Chapter 2

OSCILLOSCOPE
Design file: 5912CLK.TLN Designer: TI
BoardSim/LineSim, HyperLynx
Comment: NOTE: The signals recorded at the terminating loads is identical therefore only the magenta signal is shown.

4500.0 Probe 1:U(A0)

Probe 2:U(D0)
4000.0 Probe 3:U(D1)

3500.0

3000.0
V
o
l 2500.0
t
a
g 2000.0
e
-
m 1500.0
V
-
1000.0

500.0

0.000

-500.0
0.000 5.000 10.000 15.000 20.000 25.000 30.000 35.000 40.000 45.000 50.000
Time (ns)

Date: Tuesday May 18, 2004 Time: 17:06:26

Show Latest W aveform = YES, Show Previous W aveform = YES

Figure 2.8. Parallel Termination Simulation Results

Figure 2.9 shows an example of one clock output driving two loads con-
nected using a daisy-chain topology. The distance from the source to the
first load (1st SDRAM) is the same as the distance from the first load to the
second load (2nd SDRAM). In this case, the reflections coming from the
second load distort the clock signal at the first load. The best way to mini-
mize this distortion is by adding a parallel termination at the second load to
reduce the impedance mismatch and therefore reduce the reflections as
shown in Figures 2.10 and 2.11. This system still requires a series termi-
nation at the source to control the edge rate of the whole signal trace. This
resistor needs to be small so that the source and sink currents are large
enough to drive two loads. In this example, the series termination resistor
is 10 ohms.

A d d e d R C
2 nd S D R A M P a r a ll e l
1 s t S D R A M T e r m i n a ti o n

D M 6 4 2 E V M

10 O h m s
S e rie s
T erm .

C L O C K
O U T F R O M D S P

Figure 2.9. DSP Clock Driving Two Loads

Transmission Line (TL) Effects 21

Figure 2.10. Clock Distortion Due to Reflections

Figure 2.11. Clock Waveform with a Parallel Termination

2.3 PRACTICAL CONSIDERATIONS OF TL

In general, high-speed DSP systems consist of many CMOS devices where
the input impedance is very high, typically in Mega ohms and the input
capacitance is relatively small, less than 20pF. In this case, with no load
termination, the TL looks like a transmission line with a capacitive load,
rather than an open circuit. The capacitive load helps reduce the rise-time
and allows the designers to use only a series termination at the source. This
approach is becoming very common in high-speed systems.
22 Chapter 2

Figure 2.12. Practical Model of TL

In Figure 2.12, the voltage at the load is slowly charged up to the maxi-
mum amplitude of the clock signal. Initially, the load looks like a short cir-
cuit. Once the capacitor is fully charged, the load becomes an open circuit.
The source resistor Zs controls the rise and fall-times. Higher source resis-
tance yields slower rise-time. The load voltage at any instant of time, t,
greater than the propagation delay time, can be calculated using the fol-
lowing equation:

VL = Vclk (1 − e − (t −Td ) / τ ) , (2.7)

where t is some instant of time greater than the propagation delay

and τ = CLZo , where CL and Zo are the load capacitor and charac-
teristic impedance respectively.

2.4 SIMULATIONS AND EXPERIMENTAL RESULTS OF

TL

2.4.1 TL Without Load or Source Termination

One of the well-known techniques to analyze the PC board is using a sig-
nal integrity software [3] to simulate the lines. Figure 2.13 shows a setup
used for the simulations.
Transmission Line (TL) Effects 23

Figure 2.13. Simulation Setup

The selected signal is FLASH.CLK which is a clock signal generated by a

DSP. Figure 2.14 shows an actual PC board designed with a DSP where
the clock is driven by U3 and is measured at U2.

Figure 2.14. PC Board Showing FLASH.CLK Trace

Figure 2.15 shows the simulation result at U2 and Figure 2.16 shows the
actual scope measurement in the lab.
24 Chapter 2

OSCILLOSCOPE
Des ign file: 507201C.HY P Des igner: TI
B oardS im/LineS im , Hy perLy nx

7.000 Probe 5:U2.E6

6.000

5.000

4.000
V
o 3.000
l
t
a 2.000
g
e
- 1.000
V
-
0.000

-1.000

-2.000

-3.000
0.000 40.00 80.00 120.00 160.00 200.00
Tim e (ns)

Date: Thurs day Jul. 1, 2004 Tim e: 14:16:59

Net nam e: FLAS H.CLK
S how Lates t W aveform = Y E S, Show P revious W aveform = Y E S

Figure 2.15. Simulation Result of FLASH.CLK

Figure 2.16. Lab Measurement of FLASH.CLK

2.4.2 TL with Series Source Termination

As discussed earlier, most high-speed system designs use this technique.
Since, it is possible to optimize the load waveforms simply by adjusting
the series termination resistors. This technique also helps reduce the dy-
namic power dissipation, since the initial drive current is limited to the
maximum source voltage divided by the characteristic impedance. Figure
2.17 shows the setup used for the simulation of the audio clock driven by
an audio CODEC external to the DSP.
Transmission Line (TL) Effects 25

Figure 2.17. Series Termination Clock Setup

Figure 2.18 shows an audio clock that transmits by U17 and receives by
U3. The design has a 20-ohm series termination resistor but no parallel
termination at the load. This demonstrates the concept discussed earlier.

Figure 2.18. Audio Clock with Series Termination

The simulation result is shown in Figure 2.19.

26 Chapter 2

OSCILLOSCOPE
Design file: 507201C.HYP Designer: TI
BoardSim/LineSim, HyperLynx

7.000 Probe 5:U3.G13

6.000

5.000

4.000
V
o 3.000
l
t
a 2.000
g
e
- 1.000
V
-
0.000

-1.000

-2.000

-3.000
0.000 40.00 80.00 120.00 160.00 200.00
Tim e (ns)

Date: Thursday Jul. 1, 2004 Time: 12:39:31

Net name: MCBSP1.CLKS
Show Latest W aveform = YES, Show Previous W aveform = YES

Figure 2.19. Series Termination Simulation Result

The lab measurement shown in Figure 2.20 correlates with the simulation
very well. The 22-ohm series resistor can be modified to lower the over-
shoots and undershoots. But since the overshoots are less than 0.5V, they
are acceptable in this case.

Figure 2.20. Series Termination Lab Measurement

Transmission Line (TL) Effects 27

2.5 GROUND GRID EFFECTS ON TL

In summary, the simulation results correlate very well with the actual lab
measurements. Designers need to understand the TL characteristics and
terminate traces to minimize reflections that may cause random circuit
failures, excessive noise injected into the power, ground planes and elec-
tromagnetic radiation.
One final comment about the TL is that the previous examples were based
on a model where a signal trace is on top of a ground plane known as a mi-
crostrip model. Other techniques, such as a ground grid, are also com-
monly used. Example 2.2 demonstrates the effects of the ground grid. In
this configuration, the designers need to understand the current flows and
their effect on the characteristic impedance.
Example 2.2:
Figure 2.21 shows an example of using a ground grid, instead of ground
plane for the PC board. As shown in this figure, the current path is not
immediately under the signal trace, so there is a large current return loop
that yields higher inductance and lower capacitance per unit length. In this
case, the characteristic impedance is higher than if a continuous ground
plane was used.

Ground
grid Current
Return

Input
Signal

Signal trace is routed between the two ground paths of the grid

Figure 2.21. Current Return Paths of Ground Grid

28 Chapter 2

Figure 2.22 also shows another example of using a ground grid where the
signal is being routed diagonally. As shown in this figure, the current re-
turn has to travel on a zig zag pattern back to the source and creates a large
current return loop that yields higher inductance and lower capacitance per
unit length. In this case, the characteristic impedance is higher than using a
continuous ground plane and higher than the case where the signal is
routed in parallel with the ground grid as shown in Figure 2.21.

Current
Ground
Return
gr id

Input
Signal
Signal trace is route d diagonally

Figure 2.22. Current Return Paths of Diagonal Grid

So, if ground grid is a required in a design, the best approach is to route the
high speed signals right on top of the grids and parallel to the grid to en-
sure the smallest current return loops. This lowers the characteristic im-
pedance to the level equivalent to the impedance of the continuous ground
plane. This is very difficult to accomplish since complex board has many
high speed traces. Therefore, continuous ground plane is still the best
method to keep characteristic impedance and EMI low.

2.6 MINIMIZING TL EFFECTS

As demonstrated in this chapter, transmission line effects cause signal dis-

tortions which may lead to digital logic failures and radiations. These ef-
fects can’t be eliminated totally but can be minimized by applying the fol-
lowing guidelines:

• Slow down the signal edge rate by lowering the buffer drive
strength if it is not affecting the timing margins. Remember a
Transmission Line (TL) Effects 29

trace becomes a TL if the rise-time of the signal propagating on it

is less than a roundtrip propagation delay.
• If the edge rate of the buffer is not configurable, add a series ter-
mination resistor as close to the source as possible. The value of
the resistor is equal to the characteristics impedance (Zo) of the
trace minus the buffer output impedance.
• When one clock is driving multiple loads as shown in Figure 2.9,
add a series termination at the source and a parallel termination at
the load.
• If ground grids have to be used, route the high speed signals in
parallel with the ground grids to reduce the current return loops.
Ground planes are always preferred over ground grids.
30 Chapter 2

REFERENCES

[1] Hall S, et al (2000) High Speed Digital System Design. John Wiley &
Sons, New York.

[2] Texas Instruments Inc (2003) OMAP5912 Applications Processor

Data Manual. http://focus.ti.com/lit/ds/symlink/omap5912.pdf.

[3] Mentor Graphics (2004) Hyperlynx Signal Integrity Simulation soft-

ware. http://www.mentor.com/products/pcb-system-design/circuit-
simulation/hyperlynx-signal-integrity/.
 Effects of Crosstalk 3

In any electronic systems, it is not practical nor is it necessary to eliminate

all the noise, as noise is not a problem until it interferes with the surround-
ing circuitries or radiates electromagnetic energy that exceeds FCC limits
and or degrades the system performance. When noise interferes with other
circuits it is called crosstalk. Crosstalk can be transmitted through electro-
magnetic radiation or electrically coupling, such as when unwanted signals
propagate on the power and ground planes or couple onto the adjacent cir-
cuits. One of the most challenging problems designers are facing in to-
day’s electronic systems is to determine the source of crosstalk, especially
in the case where crosstalk randomly causes system failures. Because
components are so tightly packed into a very small printed circuit board
(PCB). This chapter outlines the crosstalk mechanisms and design meth-
odologies to minimize the effects of crosstalk.

3.1 CURRENT RETURN PATHS

In designing a system, it is crucial for designers to understand the current
return paths as these current returns are the main sources of electromag-
netically and electrically coupling. For example, the digital signal current
return crosses the analog section of the design and causes noise on the ana-
log waveforms or the current return generates a large current loop area
which radiates onto the adjacent circuitries.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_3, 31
© Springer Science+Business Media, LLC 2010
32 Chapter 3

Current returns follow different paths depending on their frequency. A

high frequency current flow tends to concentrate on the surface of the con-
ductor as supposed to distribute uniformly across the conductor like a low
frequency current. This phenomenon is known as skin effect and it modi-
fies the current distribution and changes the resistance of the conductor.
Due to skin effect, signals above 10 MHz tend to follow one return path
while those below 10 MHz follow another. The low-speed signal current
returns on the path of least resistance, normally the shortest route back to
the source as shown in Figure 3.2. In Figure 3.1, the high-speed signal cur-
rent, on the other hand, returns on the path of least inductance, normally
underneath the signal trace. Knowing the current return paths is important
for designers to optimize the system design to reduce crosstalk.

Figure 3.1. High Frequency Current Return Paths (>10MHz)

Figure 3.2. Low Frequency Current Return Paths (<10MHz)

Effects of Crosstalk 33

The current return density and the amount of crosstalk can be estimated as
shown in Figures 3.3 and 3.4. Based on the equations shown in the figures,
the spacing between the traces and the distance that they run in parallel de-
termines the amount of crosstalk. Obviously, moving the traces further
from each other will reduce the crosstalk.

current
density curve
signal trace

H
Ground

Figure 3.3. Current Return Density

The return current density, ID, in Figure 3.3 [1] is

I 1
ID = , where I is the signal current. (3.1)
πH ⎛D⎞
2

1+ ⎜ ⎟
⎝H⎠

signal trace signal trace

H
Ground

Figure 3.4. Crosstalk Estimation

The crosstalk in Figure 3.4 [1] can be estimated as

K
Crosstalk = 2
, (3.2)
⎡D⎤
1+ ⎢ ⎥
⎣H ⎦
34 Chapter 3

where D is the distance between the traces, H is the height of the signal to
the reference plane and K is the coupling constant less than 1.
There are two types of crosstalk, forward and backward. Forward
crosstalk, also known as capacitive coupled crosstalk. This occurs when
the current flows in the same direction as the source. With backward
crosstalk, which is also called inductive coupled crosstalk, the coupling
current flows in the opposite direction of the source.
The following simulations [2] demonstrate the concept of reducing for-
ward and backward crosstalk by spacing the aggressor and victim traces.
The model simulates two parallel 5 mil wide, 12-inch long traces. The
source of the trace is connected to a DSP and the load to DDR memory. As
shown in Figure 3.5, D0 line is an aggressor and D1 line is a victim.

Figure 3.5. Crosstalk Simulation Setup

OSCILLOSCOPE
Des ign file: UNNA M E D0.TLN Des igner: TI
B oardS im /LineS im , Hy perLy nx

3000.0 Probe 3:U(B0).DQ0

Probe 4:U(B1).DQ1
2500.0

2000.0

1500.0

V
o 1000.0
l
t
a
g 500.0
e
-
m
V 0.000
-

-500.0

-1000.0

-1500.0

-2000.0
0.000 4.000 8.000 12.000 16.000 20.000
Tim e (ns)

Date: W ednes day A ug. 4, 2004 Tim e: 17:40:38

Curs or 1, V oltage = 2.3m V , Tim e = 2.915ns
Curs or 2, V oltage = 242.6m V , Tim e = 6.188ns
Delta V oltage = 240.3m V , Delta Tim e = 3.274ns
S how Lates t W aveform = Y E S

Figure 3.6. Crosstalk Simulation Results for 5 Mil Spacing

Effects of Crosstalk 35

Figure 3.6 shows simulation results. On the victim trace, the first negative-
going pulse, which has a –200mV peak, is the forward crosstalk. The posi-
tive-going pulse of 240mV is the backward crosstalk. The backward pulse
width is about 2 times the coupling region. In this case, the coupling region
is 3.54nS and the simulation also shows a 4nS backward crosstalk pulse.
The crosstalk Eq. (3.2) is

K
2
.
⎡D⎤
1+ ⎢ ⎥
⎣H ⎦
Let’s assume that K=1, D=5 mils and H=10 mils as in the simulation. The
maximum crosstalk is then calculated as follows:

K 1
Max. Crosstalk = 2
= 2
= 0.8V.
⎡D⎤ ⎡5⎤
1+ ⎢ ⎥ 1+ ⎢ ⎥
⎣H ⎦ ⎣10 ⎦

As expected, the simulations in Figure 3.6 showed that the peak-to-peak

crosstalk is 440mV, which is much less than the maximum crosstalk esti-
mated.
Now, let’s test the condition where the two traces are placed further away
from each other, by making D=15 mils. The maximum estimated crosstalk
is now 0.3V while the simulation in Figure 3.7 shows a forward crosstalk
of –100mV and a backward crosstalk of 90mV. The peak-to-peak crosstalk
is about 190mV, which is again much less than the calculated maximum of
300mV. This simulation demonstrates how the rule of thumb provided ear-
lier overestimates crosstalk.
O SCILLO SCO PE
Des ign file: UNNA M E D0. TLN Des igner: TI
B oardS im / LineS im , Hy perLy nx

3000.0 Probe 3:U(B0).DQ0

Probe 4:U(B1).DQ1

2500.0

2000.0

1500.0

1000.0

V
o
l
t
a
g 500.0
e
-
m
V
-

0.000

-500.0

-1000.0

-1500.0

-2000.0
0.000 2.000 4.000 6.000 8.000 10.000 12.000 14.000 16.000 18.000 20.000
Ti m e (n s)

Dat e: W ednes day A ug. 4, 2004 Tim e: 17:38: 41

Curs or 1, V olt age = -7. 3m V , Tim e = 3. 143ns
Curs or 2, V olt age = 90.5m V , Tim e = 6. 368ns
Delt a V olt age = 97. 8m V , Delt a Tim e = 3. 226ns
S how Lat es t W aveform = Y E S

Figure 3.7. Crosstalk Simulation for 15 mils Spacing

36 Chapter 3

In summary, accurately calculating and simulating the crosstalk of a sys-

tem is not possible due to many complex capacitive and inductive coupling
paths that are involved. The examples show how difficult it is to estimate
and simulate crosstalk and the effects of spacing on the adjacent signal.
The following points need to be considered before finalizing the design:

• When the PCB is designed, minimize the height, H, between

the high-speed signal routing layer and the ground plane.
Lower H yields lower crosstalk.

• Maximize the spacing, D, between the signals. Higher D

yields lower crosstalk.

• For board layout, analyze the critical signals and minimize the
coupling regions.

• Slow the edge rates if possible because this reduces crosstalk.

3.2 CROSSTALK CAUSED BY RADIATION

Crosstalk can also be caused by high-speed signals that are routed on
traces that form effective antennas. The first step in determining whether a
trace is acting as an antenna is to calculate the wavelength of the signal us-
ing the following equation:

C
λ= , (3.3)
f
where C is the speed of light or 3x108 m/s and f is the frequency in Hertz.
The equation shows that a 100MHz clock signal has a wavelength of 3 me-
ters or 9.84 feet. A good rule for minimizing radiation is making sure that
the trace length is not longer than the wavelength divided by 20. So in the
case of the 100MHz clock signal, the signal length should be kept below
0.15m or 0.492 feet. Keeping the traces below 0.5 feet is easy, but the
squarewave clock signal consists of multiple harmonics and each of the
harmonics can radiate even when the traces are very short. Here is an ex-
ample.
Example 3.1:
Let f = 500MHz, the 5th harmonic of the 100MHz clock,
Effects of Crosstalk 37

C 3x108
λ= = = 0.6m .
f 500 x106
A rule-of-thumb for determining when the clock trace becomes an effec-
tive antenna is taking the wavelength divided by 20. The maximum length
the 500MHz clock is

C 3x108
λ= = = 0.03m or 3cm which is 1.18 inches.
20 f 20(500 x106 )
What this means is that, depending on the rise and fall-times of the
100MHz signal, the energy of the 5th harmonic can radiate and interfere
with the adjacent circuits when this signal trace is longer than 1.18 inches.
The energy of the harmonics depends on the rise and fall-times of the sig-
nal as shown in Figure 3.8. In this figure, it is assumed that the clock
waveform has a 50% duty cycle and rise and fall-times are equal. With
these assumptions, only odd harmonics of the clock are present. The am-
plitude of the harmonics starts decaying at the first pole frequency, f1, at a
rate of 20dB/decade and then increases to 40dB/decade at the second pole
frequency f2. The equations for f1 and f2 are

1
f1 = , where Pw is the high-time of the waveform, (3.4)
Pw

1
and f2 = , where Tr is the rise-time of the waveform. (3.5)
πTr

T r P w

T
1
2 0 d B /d e c a d e
π Pw 1
Amplitude

π T r

4 0 d B /d e c a d e

H ig h e r T r r e d u c e s
a m p li t u d e o f h a r m o n i c s
1 /T (3 ) (5 )
F r e q u e n c y ( h a r m o n ic )

Figure 3.8. Radiation Caused by Clock Signal

38 Chapter 3

To illustrate how a digital clock waveform can generate crosstalk that de-
grades the video quality of a time shifting system [3], let’s take a look at a
system diagram shown in Figure 3.9 where many critical components are
placed on the same printed circuit board. In this design, the clock signals
ranging from 18.4MHz to 100MHz are being routed to all the subsystems
(modem, audio CODEC, video encoder/decoder, CPU, MPEG encode and
MPEG-2 decode).

Figure 3.9. Time Shifting System

The time shifting system in Figure 3.9 operates as follows:

• As shown in Figure 3.10, the Video Tuner receives a radio fre-

quency (RF) signal from an antenna and demodulates the RF sig-
nal and converts it down to the baseband frequency.

• The Video Decoder receives the baseband video signal from the
Tuner and digitizes the signal to prepare for digital signal com-
pression. This video data rate for an analog TV channel with
640x480 30 frames per second resolution is around 147Mbits/s
(data rate = 640 x 480 x 16 bits/pixel x 30 frames/second =
147Mbits/s).
Effects of Crosstalk 39

• The CPU is responsible for running a high level operating system

and for managing all the video and audio data. The digital video
data are captured by the CPU and are stored in external memories
such as DDR.
The CPU transfers the digital video data stored in the memories to
the MPEG-2 Encoder [4]. The Encoder compresses the data from
147Mbits/s to 2Mbits/s bit rate and sends the compressed bit rate
back to the external memories. The compressed data are then sent
to the hard drive for storage.

• The CPU then reads the compressed data from the hard drive and
sends the data to the MPEG-2 Decoder [4]. The Decoder decom-
presses the data from 2Mbits/s bit rate back to 147Mbits/s bit rate
and sends it to the Video Encoder. The Encoder converts the digi-
tal decoded data to analog signals and displays it on a TV screen.

• The Modem in the time shifting system is there for communicating

with the service provider server to request for TV guides and soft-
ware updates.

• The Audio CODEC is responsible for digitizing the analog audio

signals received from the Tuner or from an external audio device.
The digital audio data follows the same path as the digital video
signal in which the data are being compressed, stored and play-
back the same way. This CODEC also receives the digital audio
data from the CPU and converts it to analog signals for playing out
to the speakers.

Figure 3.10. Time Shifting System Data Flow

40 Chapter 3

In this time shifting system design, the crosstalk can occur anywhere
within a system even though the system was fully FCC certified, so it is
very difficult to find the root causes of the problem. For example, any of
clocks can generate harmonics that radiate to the antenna input and inter-
fere with the TV channel. To illustrate this effect, Figure 3.11 shows a
video screen with horizontal lines generated by the third harmonic
(55.2MHz) of the 18.4MHz clock radiating to the antenna input. 55.2MHz
harmonic happens to be within Channel 2 (54MHz to 60MHz) of the
NTSC spectrum [5] and causes interferences that can’t be rejected by the
Tuner because the Tuner can’t distinguish between the in-band noise and
the actual TV signal.

Figure 3.11. Clock Harmonic Interfered with Video

In this case, the best way to get rid of the interference is to reduce the en-
ergy radiated by the 3rd harmonic of the 18.4MHz clock. Figure 3.8 shows
that increasing the rise-time of the signal, assuming that this is not causing
any setup and hold time violations, attenuates the harmonic amplitude and
reduces the radiation. The two ways to reduce the rise-time are lowering
the clock buffer slew rate if possible or adding a series termination resistor
at the output of the clock buffer as shown in Figure 3.12.

Figure 3.12. 18.4MHz Clock Trace

Effects of Crosstalk 41

It is very difficult to calculate the value of the resistor R, so the best

method is to vary the resistance until the noise is longer appeared on the
display. At this point, measure the rise and fall-times of the 18.4MHz
clock and verify that reducing the rise and fall-times does not cause any
timing violations. Figure 3.13 shows a design example of having a 75 ohm
series termination resistor to reduce the rise-time and get rid of the inter-
ference as shown in Figure 3.11.

Figure 3.13. Interference Reduction by Increasing the Rise Time

3.3 SUMMARY

As highlighted in sections 3.1 and 3.2, the current return paths and the sig-
nal rise-time play the key role in generating crosstalk that interferes with
the adjacent circuits and causes random system failures and or system per-
formance degradation.

• Slow down the rise and fall-times if possible. Increasing the rise-
time reduces the power spectral density of the harmonics as shown
in Figure 3.8.

• Keep high speed signals as short as possible and make sure that
the wavelengths of the third and fifth harmonics of the signal are
much less than the wavelength divided by 20.

• Always add a series termination at the source of the clock signal as

demonstrated in Figure 3.12. This helps reduce the transmission
line effects and provides a way to reduce the rise-time if neces-
sary.
42 Chapter 3

• Always route the high speed signals away from any critical high
impedance traces. High impedance traces are the input traces to
the video and audio amplifiers. Also, space the traces at least one
width apart from each other to reduce the coupling; for example a
5 mil trace should have a gap of at least 5 mils to another trace.

• The best method to minimize crosstalk is to place the clock genera-

tor component in the middle of the system as shown in Figure 3.9.
This ensures minimum routing clock traces to all other sections.

• Using a spread spectrum clock generator is another way to reduce

the peak radiated power but be careful with the jitter generated by
these clock buffer devices. For example, in one spread spectrum
clock buffer [6], the amplitude of the 7th harmonic can be attenu-
ated by -13dB by setting the spread spectrum at +/-2%. The issue
with this setting is that the 100MHz clock output jitter will in-
crease by 529ps. If this increase in jitter is still within the allow-
able limits of the DSP clock input, then this solution is acceptable.
Effects of Crosstalk 43

REFERENCES

[1] Johnson H, Graham M (1993) High-Speed Digital System Design.

Prentice Hall, New Jersey.

[2] Mentor Graphics (2004) Hyperlynx Signal Integrity Simulation soft-

ware. http://www.mentor.com/products/pcb-system-design/circuit-
simulation/hyperlynx-signal-integrity/.

[3] TIVO DVR. http://www.tivo.com/dvr-products/tivo-hd-

dvr/index.html.

[4] International Organization for Standardization (2000) Information

Technology—Generic Coding of Moving Pictures and Associated Au-
dio Information: Video. ISO/IEC 13818-2:2000.

[5] Standard NTSC Channels & Frequencies.

http://radiotechnicalservices.com/tvchannels.pdf.

[6] Texas Instruments Inc (2009) Spread Spectrum Clocking Using the
CDCS502/503 Application Report, SCAA103.
http://focus.ti.com/lit/an/scaa103/scaa103.pdf.
 Power Supply Design
Considerations 4

Power supply design is perhaps the most challenging aspect of the entire
process of controlling noise and radiation in high-speed DSP design. This
is largely because of the complexity of the dynamic load switching condi-
tions. These include the DSP going into or out of low power modes, exces-
sive in-rush current due to bus contention and charging decoupling capaci-
tors, large voltage droop due to inadequate decoupling and layout,
oscillations that overload the linear regulator output, and high current
switching noise generated by switching voltage regulators. A clean and
stable power supply design is required for all DSP systems to guarantee
system stability. This chapter outlines the importance of proper power
supply design and the methods to minimize unwanted noise.

4.1 POWER SUPPLY ARCHITECTURES

The two types of power supplies commonly being used in DSP systems are
linear and switching power supplies. The linear power supply is the best
architecture for low noise designs such as analog audio, video and data
converter circuits. The disadvantages of this architecture are its power ef-
ficiency and dissipation. As shown in Figure 4.1, the linear power supply
consists of two main stages, input/output transistor and error amplifier.
The input DC voltage here has to be higher than the output voltage and the
minimum input voltage varies depending on the component selected. So,

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_4, 45
© Springer Science+Business Media, LLC 2010
46 Chapter 4

it is very important for designers to review the power supply’s specifica-

tions and set input and output voltage levels appropriately.

The circuit in Figure 4.1 works as follows:

• The transistor T1 operates in a linear region where the emitter cur-

rent, Ie, (output current) is controlled by the base current, Ib, and the
gain of the transistor, β.
Ie = Ic + Ib (4.1)
Ic = Ibβ (4.2)
Substitute Eq. (4.2) into Eq. (4.1)
Ie = Ibβ + Ib (4.3)

• If the output voltage drops due to higher current load, the error
amplifier configured as a negative feedback circuit compares the
Regulated Output divided by the resistors R1 and R2 to the Refer-
ence Voltage and drives higher base current Ib to maintain regula-
tion. As shown in Eq. (4.3), the output current Ie is increased with
the increase in the base current Ib.

• If the output voltage increases do to lighter current load, the error

amplifier sees more negative voltage at the input and lowers the
base current. This leads to lower output current and again the sys-
tem maintains regulation.

Ic Ie
DC Input T1 Regulated Output
R1

Ib Error Amp
C2

+
R2

Reference Voltage

R3

Figure 4.1. Linear Power Supply Architecture

Power Supply Design Considerations 47

Like any other feedback systems, if there are changes in the input voltage
and the load current, the system takes some time to stabilize and this time
typically is specified in the component data sheet under the transient re-
sponse section. The major issue with linear regulator is the power dissipa-
tion across the transistor T1 for high output current applications. The
power dissipation is
PT1 = (Vin – Vout) x Ie (4.4)
For example, if the input voltage is 12V and the output is regulated at 5V
as shown in the Design Example 4.1. For the 1A output current, the power
dissipation across the transistor T1 is
PT1 = (12 – 5) x 1 = 7 Watts.
This power dissipation generates a lot of heat and increases the device op-
erating temperature to the point where heatsink is required to keep the de-
vice temperature under the maximum allowable limits. As the current re-
quirement increases with higher performance DSP and the system becomes
smaller and smaller, it is no longer practical to use the linear regulators to
generate all the supply voltages. In this case, it is best to use switching
power supply for the main power and linear regulators to provide clean
low noise supplies to the noise sensitive circuits such as analog and mixed
analog/digital data converter circuits as shown in Figure 4.2.

Figure 4.2. DSP System Power Supply Architecture

48 Chapter 4

Design Example 4.1:

Let’s design a low noise high ripple rejection linear regulator to provide a
+5V to the audio circuit assuming +12V is available on the board.
Design Steps:

• Audio circuits are very sensitive to low frequency noise, so it is

best to select a regulator with high power supply rejection ratio
and with an external adjust pin to allow for additional decoupling.
So, let’s use LM317.

• As shown in the LM317 data sheet [1], this device has a Ripple
Rejection specification of 62dB minimum when using a 10uF ca-
pacitor to decouple the Adjust pin.

• Figure 4.3 shows the complete LM317 circuit as recommended in

the data sheet.

D1 1N4002

U1 LM317
+12V IN +5V ANALOG
IN OUT
ADJ

D2 1N4002
C1 100n R1 240 C3 1u

C2 10u R2

Figure 4.3. Linear Regulator Circuit

• In Figure 4.3, C1 prevents high frequency noise from affecting the

LM317 performance. D1 and D2 are diodes needed to discharge
the currents in C2 and C3 to avoid these currents discharging into
the output of LM317 during powering up and down of the regula-
tor. These diodes are reverse based in normal operation. C2 is re-
quired to get better Ripple Rejection specification and C3 is a
typical decoupling capacitor. Keep in mind that C3 does not need
to be a large decoupling capacitor because LM317 is already doing
a good job rejecting low frequency noise.
Power Supply Design Considerations 49

• R1 is fixed at 240 ohms and R2 is to be calculated as follows.

From the LM317 data sheet,

⎛ R ⎞
Vout = Vref ⎜⎜1 + 2 ⎟⎟ + (I adj R2 ) , (4.5)
⎝ R1 ⎠

where Iadj is 50uA and Vref is 1.25V. Vout is 5V and R1 is 240

ohms.

⎛ R ⎞
(
5 = 1.25⎜1 + 2 ⎟ + 50 x10− 6 xR2 )
⎝ 240 ⎠

For this application, it is acceptable to neglect 50uA and solve for

R2. Therefore,

⎛ R ⎞
5 = 1.25⎜1 + 2 ⎟ ,
⎝ 240 ⎠
R2 = 720 ohms. Put the complete circuit shown in Figure 4.3 in the
circuit simulator [2] and the results are shown in Figure 4.4 where
the output is regulated at +5V when the input is +12V.

Figure 4.4. LM317 Circuit Simulation Results

50 Chapter 4

As indicated earlier, for high current consumption circuits, it is best to go

with switching power supply architecture. Because it provides much better
power efficiency and lower power dissipation as compared to linear power
supply. However, this architecture generates excessive output switching
noise that can degrade system performance and cause EMI failures if de-
signers are not carefully controlling the switching noise by applying proper
design, PCB layout and isolation techniques.
The two types of switching power supplies are “buck” and “boost” con-
verter. The buck converter requires the input voltage to be higher than the
output voltage; it is also know as a step down converter. And the Boost
converter generates an output that is higher than the input voltage; this is
also known as a step up converter. For DSP systems as many different
voltages are required and these voltages can easily and economically be
derived from the highest input voltage, a buck converter is preferred. In a
buck converter as shown in Figure 4.5, the three main stages are: 1. The
power transistor stage; 2. The error amplifier stage; and 3. The pulse width
modulator or PWM stage. The converter operates as follows:

• The power transistor T2 operates in a saturation region where the

transistor is being driven fully on or off. When the transistor is
on, there is only a small resistance, Rdson in milli-ohms range, in
series with the input and the output LC filter. This leads very low
power dissipation and high efficiency.

• The emitter output of the T2 transistor is a digital waveform with

variable duty cycle controlling by the PWM circuit. This emitter
output is filtered by the L1 and C1 and the output of the filter is a
regulated DC output with some switching noise modulated on it.

• The regulated DC output is fed back to the error amplifier circuit

through the resistor divider R4 and R5. This is a negative feed-
back loop so if the DC voltage increases, the error amplifier out-
put will be driven more negative. If the DC voltage decreases, the
error amplifier output will go more positive.
Power Supply Design Considerations 51

• The output of the error amplifier is an input to the PWM stage.

This PWM compares the error amp voltage to a sawtooth wave-
form. If the error amp voltage increases, lower regulated DC out-
put voltage, the PWM generates a higher duty cycle waveform to
drive the power transistor. This leads to an increase in the regu-
lated output voltage to maintain regulation. If the error amp volt-
age decreases, higher regulated DC output voltage, the PWM
generates a lower duty cycle waveform to drive the power transis-
tor. This leads to a decrease in the regulated output voltage to
maintain regulation.

• The regulated output voltage is

⎛T ⎞
Vout = Vdc ⎜ on ⎟ , where Ton is the high time and T is the period.
⎝T ⎠

DC Input 1 T2 2 L1 3 Regulated Output

R4
C1
D1

Error Amp
Pulse Width Modulator (PWM)
- 4 +
+
5 6
R5

Reference Voltage Triangular Wave In

R6

Figure 4.5. Buck Converter Architecture [3]

Figure 4.6 demonstrates how the system compensates for higher output
voltage. Higher output voltage leads to lower duty cycle signal and there-
fore lower the output voltage back to the regulated level.
52 Chapter 4

Figure 4.6. Timing Diagrams for Higher Error Voltage

Figure 4.7 shows that the duty cycle of the signal increases when there is a
decrease in the output voltage. This again forces the system back into
regulation.

Figure 4.7. Timing Diagrams for Lower Error Voltage

Power Supply Design Considerations 53

Design Example 4.2:

Let’s design a buck converter power supply for a DSP system that has the
design specifications shown in Table 4.1 [4].

Table 4.1. Buck Converter Design Specifications

Parameter Test Conditions Min Typ Max Unit

INPUT:
VIN (input voltage) 10.8 12.0 13.2 V

IIN (input current) Vin=12V, Iout=10A 1.7 1.8 A

UVLO_OFF (VIN 0A ≤Vout≤10A 5.4 6.0 6.6 V

undervoltage lockout
turn off)

UVLO_ON (VIN 0A ≤Vout≤10A 6.6 7.0 7.6 V

undervoltage lockout
turn on)

OUTPUT:

Vout (input voltage Vin=12V, Iout=5A 3.1 3.3 3.5 V

range)

Line Regulation 10.8 ≤Vin≤13.2V 0.5 %

Load Regulation 0A ≤Iout≤10A 0.5 %

Vripple (Output rip- Vin=12V, Iout=10A 100 mVp

ple) p

Iout (output current) 10.8 ≤Vin≤13.2V 0 5.0 10 A

Iocp (output over- Vin=12V, 14 20 43 A

current inception Vout=(Vout-5)
point)

Transient Response 10A≤Iout(max)≤0.2x 8 A

Load Step (Iout(max))

Switching 240 300 360 kHz

Frequency
54 Chapter 4

Peak Efficiency Vin=12V, 90%

0 ≤ Iout ≤ 10A

Efficiency at Full Vin = 12V 87%

Load Iout = 10A
o
Operating 10.8 ≤ Vin ≤ 13.2V -40 25 85 C
Temperature 0 ≤ Iout ≤ 10A

Refer to [4] to calculate all the component values shown in Figure 4.8.
The performance of this buck converter depends on the component values,
the component placements and the layout. Here are some important points
to remember;

• Always follow the manufacture design guidelines and layout.

• Place the switching power supply circuit at a corner of the PCB

away from the rest of the system components.

VCC_12V

C1 C2a C2b
+ R3 R20
100K 1% 100K, 1% 22uF 25V 22uF 25V
9
5
6
7
8

25uF C7
U54A
S1 D 1
S2 D 2
S3 D 3
D4
PAD

100nF 1 16 4 Q1
EN HDRV G
2 15 Si7860DP
FB SW C6 VCC_3.3V
3 14
1
2
3

COMP BOOT L1
4 13 100nF
VDD LDRV 800nH
5 12
UVLO BP
6 11 C9a C9b C9c
RT SS_SEL
9
5
6
7
8

R9 + + +
100K 1% 7 10
ILIM PGOOD
S1 D 1
S2 D 2
S3 D 3
D4
PAD

4
P w rP d

Q2 47uF 47uF 47uF

C13 8 9 G
GND SYNC C12 Si7868DP
R6 100nF R7 TPS40195RGYR
17

1
2
3

100K 7.5K 1% 4.7uF

C4 R2

R11
8.2nF 2.32K 1% 10K, 1%

R10 C14
C5

49.9 1% 1nF
220pF

R5
2.2K 1%

Figure 4.8. 3.3V Output Buck Converter Schematic

Power Supply Design Considerations 55

• Keep all the switching current loops as small as possible. Refer to

the manufacture data sheet to figure out the possible current loops.

• In general, switching power supplies like Buck converter have very

high current switching characteristics and this generates harmonics
as high as 10 to 100 times the fundamental frequency. Proper
shielding, decoupling and isolating methods outlined in the manu-
facture data sheet and in this book have to be taken into considera-
tions in order to increase the probability for success.

4.2 DSP POWER SUPPLY ARCHITECTURAL

CONSIDERATIONS
Designing DSP power supply is not just designing the power supply itself,
but is necessary to implement a DSP power system to guarantee minimum
noise and radiation that will lead to higher performance, higher reliability
and lower cost. The system with low noise yields lower cost because
noisy system tends to fail at a higher rate in manufacturing. In many cases,
system designers have to take an expensive approach to solve noise and
EMI issues by unnecessarily redesigning the mechanical chassis to add
better shielding in order to prevent radiation instead of changing the elec-
trical design to solve the problems.
This is understandable as redesigning electrical system for low noise and
EMI is very difficult for engineers who are not familiar with the latest high
speed design techniques outlined in this book.
Assuming that the DSP power supply itself was done properly as shown in
the previous sections, the power integrity depends on how far the DSP is
placed away from the power supply module and how well the DSP is being
decoupled. Figures 4.9 and 4.10 show two circuits, in Figure 4.10, has a
decoupling capacitor close to the DSP. Assuming the same power supply
trace inductance, Figure 4.9 has a larger dynamic current return path lead-
ing to larger power supply voltage droop and greater electromagnetic ra-
diation. This may cause random system failures that are very difficult to
debug.
56 Chapter 4

Power wiring or trace inductance

Power Supply

14
+ 1
3
2
-
Load C

7
Current return path

Figure 4.9. Power Supply Current Return Path Example 1

Power wiring or trace inductance

Power Supply
14

+ 1
3
2
-
Load Ca
7

Current return path

Figure 4.10. Power Supply Current Return Path Example 2

One of the most challenging tasks for system designers is determining an

acceptable noise level for a DSP in a particular application. DSP data
manuals clearly specify the operating conditions but cannot account for the
dynamic nature of high-speed systems. This is because the dynamic
switching characteristics very much depend upon on the actual system de-
sign and layout. The following are some of the important issues that must
be addressed during the power supply design process:

• Power supply transient response, such as load regulation, line

regulation, power supple ripple, power supply noise rejection,
and power sequencing for multiple rails.

• Power supply decoupling to ensure minimum voltage droop at

the pins of the DSP.
Power Supply Design Considerations 57

• Linear regulator versus switching regulator.

• Power supply planes versus power supply traces.

• DSP in-rush currents during power supply ramp and at steady

state.

• Power cycling: no residual voltage during DSP startup.

• Power supply rails sequencing: Core before IO or IO before

Core.

• Be cautious with using a switching regulator to power the

PLLs, audio CODECs and video encoders and decoders.

• Always asserting reset during power supply ramp to reduce

the probability of internal DSP bus contention.
Excessive power supply noise can have the following harmful effects:

• Voltage droop, inadequate decoupling capacitors, or current

starvation may cause random logic failures. This is very diffi-
cult to debug and may even require a re-design of the system
to get rid of the noise.

• Inadequate voltage regulation can cause reliability problems

or unintentional system shutdown.

• Excessive jitter may appear on clock circuits, especially the

PLL.

• Radiation may rise to a level that makes it difficult to pass

EMC tests.

• Visible and audible artifacts on video and audio systems.

58 Chapter 4

Designers have three primary methods to overcome these problems: volt-

age regulator design (linear versus switcher), decoupling techniques and
PCB layout. One of the most important decisions made by designers is
whether to use linear regulators or switching regulators. This decision re-
quires a good understanding of the characteristics of the power supply and
the impact of the supply on the system noise performance. The design of
the power supply itself was covered in the previous sections. Let’s look at
the differences between linear and the switch regulators:

Table 4.2. LDO versus Switching Regulators

Linear or Low Drop Out Switching Regulators

(LDO) Regulators

Low noise with high power sup- Switching noise may cause EMI
ply rejection ratio problems or video and audio arti-
facts

Fast response to load changes, Slow response to load changes

typical 1 μs

Low efficiency, typically 56%, High efficiency, typically 92%,

may increase power dissipation, provides low power dissipation
heatsinks may be required

Unstable if the total decoupling DSP decoupling capacitor has a

capacitance is higher than the little or no impact on the supply
maximum allowable limit stability. On the other hand, PCB
layout is critical.

Excellent choice for video, au- Excellent choice for the core CPU
dio, analog and PLL circuits. and the IO power.

Low cost Higher cost due to need for exter-

nal filter components such as an
LC filter at the output of the
switch
Power Supply Design Considerations 59

Table 4.2 helps determine which power supply solution is a better fit for
the application. The next step is to determine the current consumptions and
whether or not power sequencing is required. In general, DSPs have a
minimum of two power supply rails, Core and IO. The sequence of ramp-
ing the Core and IO voltages can affect the startup current consumption so
refer to the device data manuals to help design a robust power supply for a
particular DSP. Here are recommended rules for selecting/designing a DSP
power supply.
CORE Voltage Regulator Design:

• Refer to the device data manual to get the maximum current

consumption for the Core supply. Many of the DSPs come
with a Power spreadsheet that can be used to estimate the cur-
rent consumption of a particular CPU operating condition.

• Select a regulator with at least two times the maximum Core

current capability. This provides adequate margin to handle
the dynamic current conditions.

• Be cautious with the current starvation condition. During

startup, the surge current may exceed the maximum limit of
the regulator for a short period of time. The selected regulator
should have a soft-start capability to prevent thermal or over-
current shutdown conditions from occurring.

• The final design step for the Core voltage regulator is whether
or not a heatsink is required.
IO Voltage Regulator Design:
IO voltage regulator design depends on the external loads in the specific
application. For fast switching signals, the IO currents are supplied by the
decoupling capacitors, not by the regulator itself due the parasitic induc-
tance associated with the power supply trace or plane. The dynamic cur-
rent calculation will be shown in the decoupling section. The following
guidelines provide a conservative method to design an IO voltage regulator
for the DSP itself. It should be noted that this method applies to the DSP
power alone as opposed to the entire system.

• Count the number of outputs from the DSP. All GPIOs should
be considered as outputs.
60 Chapter 4

• Multiply the number of outputs by the source current specified

in the data manual.

• Add the total source current using the maximum IO current

consumption specified in the data manual.

• Then, multiply the result by 2 to provide a 100% margin.

• Due to transmission line effects, IO current may surge during

switching but this condition will be absorbed by the local DSP
decoupling capacitors.

• The final step is to determine if heatsink is required or not.

Once designers complete the power supply architecture for a particular
DSP, the next step is to determine if the DSP requires sequencing. The
supply rails may be sequenced, for example, to ramp up the Core before
the IO or vice versa. Proper sequencing is necessary to avoid internal con-
tention.

• Improper reset during power-up. Reset must be asserted

longer than the minimum reset pulse specified in the data
manual.

• Core and IO not coming up within the specified time limits.

Typically, DSPs do not require a power sequence but there is
a time limit for one supply rail to be on while the other is off.

• Improper reset of the JTAG emulation port. For example,

TRST needs to be stable low. Excessive noise coupled to this
signal may cause a startup problem or bus contention.

• Boot mode configuration pins not being driven to proper states

before releasing reset. Refer to the device data manual to
make sure that the configuration pins have proper pull-ups and
pull-downs and these pins have reached a stable logic level
before releasing reset.
Figures 4.11 and 4.12 show two DSP power supply architectures [5], in
Figure 4.11, the Core and IO rails are powered up synchronously and in
Figure 4.12 the Core supply rail is ramped up before the IO. Refer to the
[6] to obtain more details about power management architectures.
Power Supply Design Considerations 61

Figure 4.11. Synchronous Core and IO Supply Rails Example

Figure 4.12. Before IO Example

4.2.1 Power Sequencing Considerations

The number of power supply rails required for DSP or SoC is increasing
constantly as more and more peripherals are being integrated. And manag-
ing these rails during powering-up or down of the DSP is a very difficult
task. Typically, a high performance DSP or SoC consists of at least 3
power supply rails, +1.8V for DDR2, +3.3V for data converters, +1.2V for
core. The internal logic has many voltage translations to enable all the
blocks communicating to each other. During power-up, if one power sup-
ply rail goes up before another for some period of time, the internal logic
can get to an unknown state which can cause internal bus contention and
the system to go unstable. Designers must refer to the DSP data sheet and
design in the power sequence if it is required. The problem is that the
62 Chapter 4

power supply sequence circuits shown in Figures 4.11 and 4.12 can only
guarantee the power up sequence of the power supply itself, not the whole
system. This is because the decoupling capacitors used around the DSP as
shown in Figure 4.10 affecting the time it takes for the power supply to
ramp up to the final operating voltage. This time can be calculated as fol-
lows:

⎛ dV ⎞
I power = Cdecoupling ⎜ ⎟,
⎝ dt ⎠

⎛ dV ⎞
dt = Cdecoupling ⎜ ⎟, (4.6)
⎜I ⎟
⎝ power ⎠
where Cdecoupling is the total decoupling capacitance, Ipower is the current
sourced from the power supply, dV is the change in voltage and dt is the
time it takes to get to the dV value.
As shown in the Eq. (4.6), for a given power supply, the time it takes to
reach the final voltage level depends on the total decoupling capacitance.
So, to guarantee a particular sequence, it is very important for designers to
do the following:

• Refer to the DSP data sheet and determine whether or not power
sequencing is necessary.

• If the selected DSP requires a power up sequence, then use a topol-

ogy similar to the one shown on Figure 4.12 to develop the power
supply system.

• Use Eq. (4.6) and calculate the ramp time for each power supply
rail and verify that the power up sequence was achieved at a system
level with all the decoupling capacitors installed on the board.

• Use a current probe and measure the power up currents (Core and
IO) to make sure that there are no bus contentions. Keep in mind
that all capacitors appear like a short circuit to ground when they
start from a zero volt state, so the surge current may be higher than
expected during start-up. Be sure to provide adequate margin in
the power supply design to avoid false-triggering the over-current
protection circuits. A good rule-of-thumb is adding a 50% margin
to the maximum current consumed in the design.
Power Supply Design Considerations 63

• If there was excessive current consumption during power-up, de-

signers need to check the following.
[1] Is the system reset active? Reset signal should be asserted
during this time.
[2] Is the power-up sequence correct?
[3] Are any of the inputs left floating? All the inputs need to
be pulled-up or down but they can’t be floating. Some of
the DSPs have internal pull-ups or downs integrated but
not all of them, so make sure to check the data sheets and
enable the pull-ups and downs appropriately.
[4] Is the clock output of the DSP started running immediately
after the power supply reaches its operating range? If not,
check the emulation reset signal to make sure that this in-
put is being driven correctly. If not, noise can couple to
this input and randomly put the device in some kind of test
modes.
Figure 4.13 summarizes the steps to verify the power sequencing and to
debug the system start-up over-current conditions.

Figure 4.13. Power Sequencing Verification

64 Chapter 4

4.3 SUMMARY
As demonstrated in this chapter, selecting the right power supply architec-
tures for the DSP system including surrounding analog/digital circuits and
doing the system floorplan design are the two most important critical tasks
for designers to get done first before getting started on the actual imple-
mentation. Good power integrity is key for achieving a low noise and low
EMI system design and here is a list of recommendations to improve the
probability of success:

• Develop a detailed system block diagram showing all the power-

supply requirements for all the components (DSP, ADC, DAC,
video, audio, PLLs, DDR, etc.)

• Apply the techniques described in this chapter and calculate the

current requirements for all the blocks. It is recommended to add
a 50% margin to the overall current budget as this helps the system
to better-handle dynamic situations.

• Highlight the noise sensitive circuits such as ADC, DAC, analog

video/audio and PLL and isolate these circuits by using high
power supply rejection linear regulators if possible. Avoid power-
ing these circuits with switching regulators.

• Do the floorplan design. Place the switching power supplies far

away from analog and high speed circuits. The best place for
noisy power supplies is at the corner of the PCB.

• Select the power supply topologies and begin circuit implementa-

tion and layout. Refer to Section 4.2.1 for power sequencing.
Power Supply Design Considerations 65

REFERENCES

[1] Texas Instruments Inc (2008) LM317 3-Terminal Adjustable Regula-

tor. http://focus.ti.com/lit/ds/symlink/lm317.pdf.

[2] Texas Instruments Inc (2008) Spice-Based Analog Simulation Pro-

gram. http://focus.ti.com/docs/toolsw/folders/print/tina-ti.html.

[3] Pressman Abraham (1991) Switching Power Supply Design. McGraw-

Hill, New York.

[4] Texas Instruments Inc (2008) TPS40195 4.5-V to 20-V Synchronous

Buck Controller with Synchronization and Power Good.
http://focus.ti.com/lit/ds/symlink/tps40195.pdf.

[5] Texas Instruments Inc (2009) SM320C6713-EP Floating Point Digital

Signal Processors. http://focus.ti.com/lit/ds/symlink/sm320c6713b-
ep.pdf.

[6] Texas Instruments Inc (2008) Power Management Guide.

http://focus.ti.com/lit/sg/slvt145h/slvt145h.pdf.
 Power Supply
Decoupling 5

The number one root cause of system related problems is due to inade-
quate power supply decoupling around the DSP and or other surrounding
circuits such as DDR, clocks, analog-to-digital and digital-to-analog con-
verters etc. The most challenging task for designers is to determine the
best decoupling techniques to achieve low noise and high performance. In
general, component manufactures provide a conservative recommendation
for power supply decoupling, but in many cases, it is not practical to fol-
low this recommendation because of PCB space availability, power con-
sumption, EMI or safety requirements. Also, component manufactures
always provide development platforms for designers to evaluate and these
platforms typically are a lot larger than the actual design and are not re-
quired to be FCC certified, so copying what was done on the development
platform is not a guaranteed that the design will be successful. This chap-
ter will discuss three important topics for designers: 1. a general rule-of-
thumb decoupling method, 2. an analytic decoupling method and 3. how
to make design tradeoffs to achieve the best noise performance possible.

5.1 POWER SUPPLY DECOUPLING TECHNIQUES

Once designers select and design a power supply for the DSP, the next step
is to determine the decoupling capacitors needed to ensure that the power
supply droop under all dynamic operating conditions is lower than the

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_5, 67
© Springer Science+Business Media, LLC 2010
68 Chapter 5

specified limits. For example, a 5% tolerance rating on a 3.3V IO supply

requires the ripple to be less than 165mV. Let’s first consider the situation
where no decoupling capacitor is used as shown Figure 5.1.

Power wiring inductance

U19A

14
+ 1
3
2
-
Load Cap
7
14081/SO

Current for charging the capacitor load

Figure 5.1. DSP Power w/o Decoupling Capacitor

In Figure 5.1, the DSP labeled U19A is driving a capacitive load and is
switching at a fast rate. Now, let’s assume that the regulator is placed 5
inches away from the DSP and is routed with a 5 mil trace to the DSP.
During fast switching, the power supply trace becomes an open circuit be-
cause of the parasitic inductance associated with the trace. This generates a
large voltage droop at the pin of the DSP which can be estimated as fol-
lows [1].

dI
Droop = L( Max ) (5.1)
dt
where L is the parasitic inductance.

dI 1.52ΔV
Max = C (5.2)
dt (Tr ) 2

where ΔV is a switching voltage, C is a load capacitor and Tr is a risetime.

For a 5 inch trace, the inductance is estimated by the signal integrity simu-
lator [2] to be 600nH/m. The inductance L is
L = 5 in x 2.5 cm/in x 1m/100cm x 600nH/m = 75nH.
Power Supply Decoupling 69

Let Tr = 2nS, C=50pF (load capacitance) and ΔV = 80% of 3.3V or 2.64V.

The maximum calculated droop is

dI 1.52ΔV
Droop= L(Max ) = L[ C]
dt (Tr )2
⎡1.52(2.64) ⎤
= 75x10−9 ⎢ −9 2
x50x10−12 ⎥ = 3.76V .
⎣ (2x10 ) ⎦
This example demonstrates that for a 5 inch trace, 2ns signal, 50pF load
and 3.3V IO, the maximum power supply droop is 3.76V. This level of
droop is certain to cause random system failures. To compensate, decoup-
ling capacitors are placed close to the DSP to provide the required charge
during switching. What is the best method to filter the noise from the DSP
system? Noise characteristics differ so much from system to system that no
one method guarantees low noise and low radiation for all cases. However,
designers can apply best practices outlined here to minimize the noise and
to improve the probability for success. Before going into the decoupling
techniques, it is important to understand the characteristics of the common
components (capacitors, inductors and ferrite beads) being used to filter
out the power supply noise.

5.1.1 Capacitor characteristics

The key specification of a capacitor used for decoupling is the self-
resonant frequency. The capacitor remains capacitive below and starts to
appear as an inductor above this frequency. Here is a series equivalent cir-
cuit representing the capacitor.

CAP+

ESR

ESL

CAP-

Figure 5.2. Capacitor Equivalent Circuit

70 Chapter 5

The series equivalent circuit for a capacitor has three different compo-
nents: equivalent series resistance (ESR), equivalent series inductance
(ESL) and the capacitance itself. The self-resonant frequency happens at
the point where the impedance of the capacitor, C, is equal to the imped-
ance of the inductor, L.

1
Z C
, capacitor =
ωC
,

where C is capacitance and ω is 2π times the frequency, f.

Z L
, inductor = ωL, where L is inductance.

At resonance, ZL is equal to Zc or

1
= ωL ,
ωC
1
ω
2
= ,
LC
1
ω= , where ω = 2πf.
LC
Therefore, the self-resonant frequency is

1
fR = . (5.3)
2π LC
As shown in the self-resonance equation, lower capacitance and lower in-
ductance yield a higher resonant frequency. For a given capacitance value,
choosing a smaller surface mount component achieves a higher self-
resonant frequency. Because a smaller component package typically has
lower parasitic and lead inductance. The whole decoupling concept is to
provide a low impedance path from the power supply to ground and to
shunt the unwanted RF energy. This means that choosing a capacitor with
high capacitance but with low inductance is very important. The problem
with this concept is that higher capacitance comes in a larger package
which yields higher parasitic inductance. In many cases, it is better to use
many capacitors with different values to decouple the DSP.
Power Supply Decoupling 71

Figure 5.3 shows the capacitor frequency response. For a particular ca-
pacitor, the impedance decreases with frequency and reaches the lowest
impedance point at resonant frequency, fR. For frequencies above the
resonant frequency, the impedance of the capacitor is dominated by the
parasitic inductor, ESL. This causes the impedance to increase with fre-
quency. It is recommended to operate in the capacitive region of the curve
as this region guarantees a close to ideal impedance response of the capaci-
tor.

Figure 5.3. Capacitor Impedance Response

There are many different types of capacitors and which type to use de-
pends on the voltage, temperature and frequency of the design. For exam-
ple, low frequency filtering requires a large electrolytic aluminum or tanta-
lum capacitor with a value of 10uF or higher, while high frequency
filtering needs a small film or ceramic capacitor with a value of less than
10uF. Selecting the wrong capacitor type can negatively affect the per-
formance of the system, so designers must carefully review the component
specifications and the applications before making the selection. Table 5.1
shows the electrical characteristics of different types of capacitors com-
monly being used.

Table 5.1. Capacitor Characteristics [6]

Capacitor Type: Capacitance Characteristics: Typical

Range: ESR:

Ceramic: Good temperature

stability
¾ NPO/COG 0.5pF - 0.1uF 0.12 ohms at
72 Chapter 5

1MHz for
¾ X7R/Y5R 1pF – 3.3uF Non-linear varia- 0.1uF sur-
tion with tempera- face mount
ture capacitor
¾ Z5U/Y5U 0.001pF – 10uF Poor temperature
and voltage
stability

Film: Good temperature

stability
¾ Polypropylene 0.5pF - 0.1uF 0.11 ohms at
1MHz for
¾ Polystyrene 100pF – 0.1uF Best overall 1uF surface
specifications mount ca-
pacitor
¾ Polycarbonate 0.001uF – 10uF Average tempera-
ture stability

¾ Polyester 100pF – 10uF High temperature

coefficient, lowest
cost

Electrolytic: Good overall 0.6 ohms at

specifications, 100KHz for
¾ Aluminum 0.1uF – 2.0F high ESR and 100uF
leakage current capacitor

0.001uF – Best overall speci- 0.12 ohms at

¾ Tantalum 8,000uF fications, low ESR 100KHz for
and leakage cur- 100uF
rent, less tempera- capacitor
ture sensitive than
aluminum

5.1.2 Inductor characteristics

The inductor also has a self-resonant frequency. The inductor remains in-
ductive below and starts to appear as a capacitor above this frequency.
Here is a series equivalent circuit of the inductor:
Power Supply Decoupling 73

IND+

DCR

IND-

Figure 5.4. Inductor Equivalent Circuit

The formula for calculating the resonant frequency of an inductor is the

same as for a capacitor.

1
fR = .
2π LC

Figure 5.5. Inductor Impedance Response

Figure 5.5 shows the inductor frequency response. For a particular induc-
tor, the impedance increases with frequency and reaches the highest im-
pedance point at resonant frequency, fR. For frequencies above the reso-
nant frequency, the impedance of the inductor is dominated by the
parasitic capacitor, C, and this causes the impedance to decrease with fre-
quency. It is recommended to operate in the inductive region of the curve
as this region guarantees a close to ideal impedance response of the
74 Chapter 5

inductor. Like capacitors, there are different types of inductors and the
two main ones are air core and magnetic core. Air core is the coil with air
or insulating core and magnetic core is the coil wrapped around magnetic
materials such as iron and ferrite. Inductors are commonly being used in
RF and high power circuits but are rarely being designed in high speed
DSP systems. Because it is better and lower cost to use ferrite beads to
isolate and filter the noise in DSP systems.
Here are general rules for using inductors to filter noise in a DSP system:

• Inductors are expensive and are sensitive to noise. Depending

on the switching speed of the signals propagating through it,
an inductor can also generate and radiate noise.

• Inductors are commonly used to filter low frequency noise in

high current applications. In this case, designers need to add a
high frequency filter in series with the inductor to reject the
high frequency noise. Because inductors behave like a short
circuit for noise with frequency higher than the inductor reso-
nant frequency.

5.1.3 Ferrite Bead Characteristics

Ferrite beads have electrical characteristics that are similar to ideal induc-
tors. The key difference is that the ferrite bead has no or negligible para-
sitic capacitance until the frequency reaches GHz range as shown in Figure
5.7. So the ferrite bead behaves like an inductor over a very wide fre-
quency range. As shown in Figure 5.6, ferrite bead always has a small DC
resistance so review the specifications carefully and select a component
that has the right AC impedance and low IR drop for the design. The fer-
rite bead generally performs very well at frequencies higher than 30MH. It
is commonly used to isolate power supplies and noise sensitive circuits
such clocks, video and audio CODECs.
Some manufactures provide free design tools to help engineers selecting
and simulating the ferrite bead circuits. Figure 5.7 shows an impedance
response provided by one of ferrite bead design tools [3].
Power Supply Decoupling 75

Ferrite+

DCR

Ferrite-

Figure 5.6. Ferrite Bead Equivalent Circuit

Figure 5.7. Ferrite Bead Electrical Characteristics

Two important parameters to select a ferrite bead are DC resistance and

AC impedance at a given frequency. In general, assuming no issues with
PCB space, it is best to select a device with the lowest DC resistance and
highest impedance at the operating frequency. This yields the lowest IR
drop across the ferrite bead while provides the highest noise rejection.

5.1.4 General Rules-Of-Thumb Decoupling Method

The ideal way to decouple the supply noise is having one capacitor be-
tween each of the power and ground pins of the DSP. Normally, this is
physically not practical because the DSP package area is too small. So, de-
signers have to compromise by reducing the number of decoupling capaci-
tors to fit in the general area underneath or above the DSP. Refer to the
device data manual for a recommended method. But in general, here are
the important considerations for decoupling:
76 Chapter 5

• Add as many decoupling capacitors as space allows but do not

put more capacitors than the DSP power pins.

• Add 8 bulk capacitors, 4 for Core and 4 for IO supplies. Place

each bulk capacitor at each region of the DSP, with region be-
ing defined as an edge or a corner of the DSP. Bulk capacitors
act as a low frequency noise filter and a charge storage device
for the smaller decoupling capacitors. The use of four bulk ca-
pacitors is preferable to one large discrete component because
this guarantees a shorter recharge path and a lower parasitic
inductance path between the bulk and the decoupling capaci-
tors.

• Keep in mind that all capacitors have equivalent series induc-

tance (ESL) and equivalent series resistance (ESR). ESL and
ESR reduce filtering effectiveness. So, select the smallest sur-
face mount capacitors that can be used.
Figure 5.8 demonstrates a good scheme for decoupling a particular DSP.
Refer to the device data manual to find more details. As shown in this fig-
ure, 0.01uF ceramic capacitors are used for the decoupling capacitors and
10uF tantalum capacitors are used as low frequency filtering components.
Typically, designers have to go back and change the values to optimize
them for their applications. A good approach is changing the capacitor
values to achieve less than 50mV power supply ripple for the IO rail and
less than 20mV for the Core rail. Another good rule is to use ceramic ca-
pacitors for high frequency decoupling and tantalum capacitors for low
frequency filtering. This is because tantalum capacitors come in higher
values than ceramic capacitors as shown in Table 5.1. These two types of
capacitors provide the low ESR and ESL which are needed for low noise
and low EMI designs operating over a wide range of voltages, tempera-
tures and frequencies.
These general rules are only applied to the digital Core and IO power pins
of the DSP. PLL and other analog power pins need to include better filter-
ing schemes (Pi filters and or linear voltage regulators) to prevent the low
and high frequency noise from affecting the performance of these circuits.
Refer to the PLL (Chapter 6) and data converters (Chapter 7) for more de-
tails.
Power Supply Decoupling 77

10uF 10uF
0.01 0.01 0.01 0.01

0.01 uBGA
0.01

0.01 0.01 10uF

10uF
0.01 0.01 10uF
10uF
0.01 0.01

0.01 0.01 0.01 0.01

10uF 10uF

Figure 5.8. General Rules for Decoupling

5.1.5 Analytical Method of Decoupling

Another method of decoupling power supply noise from a DSP system is
calculating the total capacitance required to keep the power supply ripple
under a certain limit. Similar to the general rules of decoupling, this
method provides a starting value that must typically be optimized. The
large ball grid array (BGA) package typically used for DSPs behaves like a
PCB itself with long traces routing from the die out to the balls. These
traces can generate interference and are susceptible to crosstalk, power
supply droop and other electrical noise. The asymmetry analytical decoup-
ling technique begins by dividing the DSP into 4 regions and then decoup-
ling each region separately. Providing fewer decoupling capacitors in the
low speed section leads to a uniform reduction in noise and electromag-
netic radiation. The rules for this decoupling technique are:

A. Core Voltage Decoupling Steps:

• Divide the DSP package into 4 regions by drawing two diago-

nal lines across the 4 corners of the DSP as shown in Figure
5.10. Be sure to keep a group of signals together, for example
78 Chapter 5

keeping all the DDR signals in one region. The boundaries do

not have to be diagonally divided as shown in Figure 5.10.

• Conservatively estimate the current consumption of the Core

voltage in the region, ICRegion, as shown in the equation below
by taking the maximum device current, ICoreMax, multiplied by
2 (adding 100% margin) divided by the total number of Core
voltage pins, N, and multiplied by the number of Core voltage
pins, M, within a region.

2 xI CoreMax
I C Re gion = xM (5.4)
N
If the maximum current specification is not available in the
data sheet, then estimate the maximum current by multiplying
the typical current by 2 as in Eq. (5.5).

4 xI CoreTyp
I C Re gion = xM (5.5)
N
• Calculate the total decoupling capacitance for the region by
applying Eq. (5.7) below.

dVCore
I C Re gion = CCore , (5.6)
dt
dt
CCore = I C Re gion , (5.7)
dVCore
where dt is the fastest rise-time in the region and dV is the
maximum ripple allowed for the Core voltage, assuming
10mv ripple.

• Now, calculate the total bulk capacitance for the region by

multiplying the total decoupling capacitance by 40. The rule
recommended for bulk capacitance is at least 10 times the to-
tal decoupling capacitance [4]. Use one bulk capacitor per re-
gion to minimize the parasitic inductance between the bulk
and the decoupling capacitors.
Power Supply Decoupling 79

• To figure out the number of decoupling capacitors, review the

PCB area to see how many capacitors can be placed within 0.5
inches or 1.25 cm of the power supply pins. It is preferable to
use smaller size capacitors in order to have more capacitors in
a region. If the DSP package is a full grid array as shown in
Figure 5.9, escape all the signals uniformly out in 4 different
directions (Northwest, Northeast, Southwest and Southeast) to
create two lanes across the package. Now, use these two lanes
to place the capacitors near the DSP Core and IO power pins.
To find the decoupling capacitor value, divide the total capaci-
tance by the number of capacitors allowed for the region. It is
good to select a capacitor with the self-resonant frequency
equal to the maximum frequency of the particular region. For
example, if the SDRAM port runs at 100MHz, then add at
least one capacitor with the resonant frequency of 100MHz in
this region. The other capacitors within each region should
have the highest possible resonant frequency. This helps miti-
gate EMI over a wide frequency range.

Figure 5.9. Full Ball Grid Array Signal Routings

80 Chapter 5

Figure 5.10. Analytical Decoupling Technique

B. IO Voltage Decoupling Steps:

• Divide the DSP package into 4 regions by drawing two diago-

nal lines across the 4 corners of the DSP as shown in Figure
5.10. Be sure to keep the signal groups together as indicated
in Core voltage decoupling section.

• Count the number of IO voltage, inputs and outputs of each

region.

• Conservatively estimate the IO current consumption of the

DSP itself in the region, IIORegion, as shown in Eq. (5.8) below
by taking the maximum device current specification, IIO, di-
vided by the total number of IO voltage pins, K, and multi-
plied by the number of IO voltage pins, J, within a region. Do
not need to add margin to the IO current consumption here as
the margin will be added in the next step.

I IO
I IO Re gion = xJ (5.8)
K
• The total IO current is not equal to the IO current sourcing and
sinking defined in the DSP data sheet. The majority of the to-
tal IO current depends on the external loads, for example re-
Power Supply Decoupling 81

sistive, capacitive or transmission line. In this design, let’s add

a lot of margin by assuming a worse case scenario where all
the IOs are outputs and are loaded with transmission lines. In
this case, each output current, IIOTrans, is equal to the output
voltage divided by the characteristic impedance of the trans-
mission line, Zo , as shown in Eq. (5.9).

VIO
I IOTrans = (5.9)
Zo
• In Eq. (5.10), the total IO current for the region is equal to the
IO current of the DSP itself plus the IO current driving the
transmission lines.

I IOTotal = I IO Re gion + JxI IOTrans (5.10)

Substitute Eq. (5.9) into Eq. (5.10),

VIO
I IOTotal = I IO Re gion + Jx (5.11)
Zo
• Calculate the total decoupling capacitance for the region by
applying Eq. (5.13) below.

dVIO
I IOTotal = C IO , (5.12)
dt
dt
C IO = I IOTotal , (5.13)
dVIO
where dt is the fastest rise-time in the region and dV is the
maximum ripple allowed for the IO voltage, assuming
50mv ripple.

• Now, calculate the total bulk capacitance for the region by

multiplying the total decoupling capacitance by 40. The rule
recommended for bulk capacitance is at least 10 times the to-
82 Chapter 5

tal decoupling capacitance [4]. Use one bulk capacitor per re-
gion to minimize the parasitic inductance between the bulk
and the decoupling capacitors.

• To figure out the number of decoupling capacitors, review the

PC board area to see how many capacitors can be placed
within 0.5 inches of the pins. If the DSP package being used is
a full ball grid array, then apply the same technique outlined
in the Core decoupling section to create two lanes for placing
the decoupling capacitors nearby the power pins. To find the
decoupling capacitor value, take the total capacitance value
just calculated and divide it by the number of capacitors al-
lowed for the region. It is good to select a capacitor with the
self-resonant frequency equal to the maximum frequency of
the particular region. For example, if the video port IO runs at
100MHz, then add at least one capacitor with the resonant fre-
quency of 100MHz at this region. For the rest of the capaci-
tors within that region, select a highest possible resonant fre-
quency value.
This analytical decoupling method provides designers with a good starting
point. As mentioned earlier, designers need to optimize the decoupling ca-
pacitors to ensure low noise and EMI during the board characterization
process. The following example shows how this process can be applied to
a typical design.
Example 5.1:
Lets use a 289-pin BGA (Ball Grid Array) DSP [5]. Now, divide the 289-
pin package into four regions by drawing two symmetry lines across the
part as shown in Figure 5.11. Then count the number of Core voltage pins,
I/O voltage pins and signals, not including the ground pins, in each region.
Also, pay special attention to the critical sections, such as external memory
interface fast (EMIFF), phase-locked loop (PLL) and other high-speed se-
rial/parallel ports. Assume all IOs outputs driving a 60 ohm transmission
line and all the signal groups falling within a region. These are reasonable
assumptions but there are cases where the boundaries of the regions had to
be altered in order to keep the signal groups together. For the PLL and
other analog power pins, the decoupling schemes are covered in Chapters
6 and 7.
Power Supply Decoupling 83

AA1 AA21

REGION 2

REGION 1 REGION 3
(digital PLL) (analog PLL, Y21)

REGION 4

A1 A21

Figure 5.11. Bottom View of the DSP [5] Package

REGION 1: 3 Core voltage pins, 8 I/O voltage pins and 54 in-

put/output pins
REGION 2: 3 Core voltage pins, 4 I/O voltage pins and 59 in-
put/output pins
REGION 3: 3 Core voltage pins, 3 I/O voltage pins, and 59 in-
put/output pins
REGION 4: 4 Core voltage pins, 6 I/O voltage pins and 55 in-
put/output pins
The next step is to conservatively estimate the switching current require-
ments for each Region.
Table 5.2 shows the calculations of switching currents for all four Regions.
The conservative assumptions used to calculate the capacitors on Table 5.2
are:
- Maximum Core current = Typical Current x 2 plus 100% mar-
gin = 170mA x 2 x2 = 680mA.

- Device IO current = Typical IO current x 2 plus 100% margin

= 45mA x 2 x 2 = 180mA.
84 Chapter 5

- Total IO Current = Device IO Current plus IO Current Driving

a Transmission Line.
- Assuming that half of the inputs and outputs in the Region
switching at the same time driving 60-ohm transmission lines,
this is a very conservative assumption since many of the sig-
nals in the 4 regions are too slow to be considered as transmis-
sion lines.

Table 5.2. Switching Current Estimation

Region Total Peak Device IO IO Current Total IO

Core Cur- Current, for Driving Current,
rent, IIOTotal IIORegion Transmis- IIORegion plus
sion Lines, IIOTrans
IIOTrans

Region 1 680mA 180mA 3.3 69mA+

x3 x8 x54 2.97A= 3A
13 21 60
= 157 mA = 69mA = 2.97 A
Region 2 Same as 1, 180mA 3.3 3.3A +
157mA x4 x60 34mA =
21 60
3.3A
= 34mA = 3.3 A
Region 3 Same as 1, 180mA 3.3 3.3A+26mA
157mA x3 x59 = 3.3A
21 60
= 26mA = 3.3 A
Region 4 680mA 180mA 3.3 3A + 51mA
x4 x6 x55 = 3.1A
13 21 60
= 209mA = 51mA = 3A
Power Supply Decoupling 85

Since the Core and I/O voltage operate at different frequencies, they re-
quire separate decoupling calculations. The following shows the steps
needed to calculate and select the decoupling capacitors for both Core and
I/O supplies.
To find the decoupling capacitance, plug the peak current, the rise-time
and the maximum ripple voltage parameters into Eq. (5.7) below and solve
for C. It is acceptable to assume that the maximum ripple voltage is 10mV
for Core and 50mV for IO and the typical rise-time is 2nS.

dt
CCore = I C Re gion
dVCore

Use the capacitor Eq. (5.13) below to calculate the total capacitance for the
IO voltage decoupling:

dt
C IO = I IOTotal
dVIO

Now lets calculate the total capacitance required for each region.
Region 1: Total Core capacitance,
(2nS )
CCore = 157 mA = 0.03uF
(10mV )

Total I/O capacitance,

(2nS )
CIO = 3 A = 0.08uF
(50mV )
86 Chapter 5

There are 3 Core voltage pins operating at 150MHz (CPU frequency) and
8 I/O voltage pins operating at 40MHz (EMIFS frequency). It would be
desirable to use multiple capacitors for the multiple supply pins, but there
is a physical limitation due to the limited space available around the de-
vice. For the DSP [5] package, there is enough board space to place about
4 or 5 capacitors per region. In this case, select two capacitors with the to-
tal capacitance of around 0.03uF. At least one of the capacitors should
have a self-resonant frequency around 150MHz to decouple the Core volt-
age pins in Region 1. Then, select three capacitors with a total capacitance
of around 0.08uF with at least one of the capacitors having the self-
resonant frequency around 75MHz to decouple the I/O voltage pins in Re-
gion 1.
In summary, for Core voltage in Region 1, use two 0.022uF (0.044uF to-
tal) ceramic capacitors and, for the I/O voltage, use three 0.033uF
(0.099uF total) ceramic capacitors.
The next step is calculating the bulk capacitors for both Core and IO. Bulk
capacitor placement is not as critical as decoupling capacitor placement.
But bulk capacitors are needed to filter the low frequency ripple typically
generated by switching power supply and to recharge the decoupling ca-
pacitors.
A rule of thumb is to select bulk capacitors with at least ten times the total
decoupling capacitance. Lets use 40 times to be conservative. For the Core
voltage,
40 x total Core capacitance = 40 x (0.03uF) = 1.2uF for Region 1 of
the Core voltage
and 40 x total IO capacitance = 40 x 0.08uF = 3.2uF for Region 1
of the IO voltage
As mentioned earlier in this chapter, the best technique is adding 4 bulk
capacitors to 4 regions of the DSP and the smallest tantalum capacitor
available is 4.7uF. In this case, select 4.7uF tantalum bulk capacitors for
both IO and Core voltages in Region 1.
In summary, Figure 5.12 shows the complete schematic diagram for de-
coupling Region 1 of the DSP. Next is to repeat the same steps for Re-
gions 2, 3 and 4.
Power Supply Decoupling 87

Figure 5.12. Region 1 Decoupling Capacitors

Region 2: Total Core capacitance,

(2nS )
CCore = 157 mA = 0.03uF
(10mV )

Total I/O capacitance,

(2nS )
CIO = 3.3 A = 0.13uF
(50mV )

There are 3 Core voltage pins operating at 150MHz (CPU frequency) and
4 I/O voltage pins operating at 40MHz (EMIFS frequency). For the DSP
[5] package, there is enough board space to place about 4 or 5 capacitors
per region. In this case, select two capacitors with the total capacitance of
around 0.03uF. At least one of the capacitors should have a self-resonant
frequency around 150MHz to decouple the Core voltage pins in Region 2.
Then, select three capacitors with a total capacitance of around 0.13uF
with at least one of the capacitors having the self-resonant frequency
around 75MHz to decouple the I/O voltage pins in Region 2.
In summary, for Core voltage in Region 2, use two 0.022uF (0.044uF to-
tal) ceramic capacitors and for the I/O voltage, use three 0.047uF (0.14uF
total) ceramic capacitors.
88 Chapter 5

The next step is calculating the bulk capacitors for both Core and IO. A
rule of thumb is to select bulk capacitors with at least ten times the total
decoupling capacitance. Lets use 40 times to be conservative. For the Core
voltage,
40 x total Core capacitance = 40 x (0.03uF) = 1.2uF for Region 2.
For the IO voltage,
40 x total IO capacitance = 40 x 0.13uF = 5.2uF for Region 2 of the
IO voltage
In this case, select 4.7uF tantalum capacitor for the Core voltage and 6.8uF
tantalum capacitor for the IO voltage in Region 2. Figure 5.13 shows the
complete decoupling schematic of Region 2.
6.8uF

4.7uF
0.047uF

0.022uF

0.047uF

0.022uF

0.047uF

Figure 5.13. Region 2 Decoupling Capacitors

Region 3: Region 3 has the same Core and IO currents as Region

2. Therefore, the Core and IO capacitors have the same values as
the capacitors in Region 2; there are two 0.022uF capacitors and
three 0.047uF capacitors. And for the bulk capacitors, one 4.7uF
tantalum capacitor is for the Core voltage and one 6.8uF tantalum
capacitor is for the IO voltage as shown in Figure 5.14.
Power Supply Decoupling 89

Figure 5.14. Region 3 Decoupling Capacitors

Region 4: Total Core capacitance,

(2nS )
CCore = 209mA = 0.042uF
(10mV )

Total I/O capacitance,

(2nS )
CIO = 3.1A = 0.124uF
(50mV )

There are 4 Core voltage pins operating at 150MHz (CPU frequency) and
6 I/O voltage pins operating at 40MHz (EMIFS frequency). For the DSP
[5] package, there is enough board space to place about 4 or 5 capacitors
per region. In this case, select two capacitors with the total capacitance of
around 0.042uF. At least one of the capacitors should have a self-resonant
frequency around 150MHz to decouple the Core voltage pins in Region 4.
Then, select three capacitors with a total capacitance of around 0.124uF
with at least one of the capacitors having the self-resonant frequency
around 75MHz to decouple the I/O voltage pins in Region 4.
In summary, for Core voltage in Region 4, use two 0.027uF (0.054uF to-
tal) ceramic capacitors and for the I/O voltage, use three 0.047uF (0.14uF
total) ceramic capacitors.
90 Chapter 5

The next step is calculating the bulk capacitors for both Core and IO. A
rule of thumb is to select bulk capacitors with at least ten times the total
decoupling capacitance. Lets use 40 times to be conservative. For the Core
voltage,
40 x total Core capacitance = 40 x (0.054uF) = 2.16uF for Region
4.
For the IO voltage,
40 x total IO capacitance = 40 x 0.14uF = 5.64uF for Region 4 of
the IO voltage
In this case, select 4.7uF tantalum capacitor for the Core voltage and 6.8uF
tantalum capacitor for the IO voltage in Region 4 as shown in Figure 5.15.

Figure 5.15. Region 4 Decoupling Capacitors

Table 5.3 shows a summary of all the capacitors calculated for the 4 re-
gions of the DSP and Figure 5.16 shows the complete schematic.

Table 5.3. Summary of Decoupling Capacitors

Region: Ceramic Bulk Caps Ceramic Bulk Caps

Caps for for Core: Caps for IO: for IO:
Core:

Region 1 2 x 0.022uF 1 x 4.7uF 3 x 0.033uF 1 x 4.7uF

Power Supply Decoupling 91

Region 2 2 x 0.022uF 1 x 4.7uF 3 x 0.047uF 1 x 6.8uF

Region 3 2 x 0.022uF 1 x 4.7uF 3 x 0.047uF 1 x 6.8uF

Region 4 2 x 0.027uF 1 x 4.7uF 3 x 0.047uF 1 x 6.8uF

Figure 5.16. DSP Decoupling Schematic

5.1.6 Placing Decoupling Capacitors

It is very important to place all the decoupling capacitors as close as possi-
ble to the pins, no more than 0.5 inches most cases. The bulk capacitors
should be placed as close as possible to the decoupling capacitors. This re-
duces the trace lengths, reducing the current loops and in turn lowering ra-
diation while minimizing parasitic inductance. The best strategy is placing
the decoupling capacitors on the bottom of the PCB and the bulk capaci-
tors on top or bottom of the PCB close to decoupling capacitors.
92 Chapter 5

In summary, there should be two bulk capacitors per region, one for Core
and one for IO, and as many decoupling capacitors as space allows. Figure
5.17 shows a very good example of the capacitors placement on the bottom
side of the PCB. The Core decoupling capacitors and four large bulk ca-
pacitors are placed on the interior of the BGA package in the open space
right under the DSP. The IO decoupling and bulk capacitors are placed on
the perimeter of the BGA package. This is possible because this particular
BGA package is not a full BGA package where all the balls are fully popu-
lated on the bottom of the package.

Figure 5.17. Good Decoupling Capacitors Placement

If the package being used is a full BGA package, then it is necessary to

route the signals from the DSP package out to external circuits as demon-
strated in Figure 5.18 that creates two lanes underneath the DSP for de-
coupling capacitors. Now, use these two lanes and populate as many de-
coupling capacitors as the lanes allow. In this case, the bulk and some of
the IO capacitors can be placed on the perimeter of the DSP package. The
recommended rules for creating the lanes are as follows:

• Power and ground pins need to be closest to the lanes. This allows
the shortest connection paths to the capacitors.
Power Supply Decoupling 93

• The lanes do not have to be symmetrical as shown in Figure 5.18.

• Designers can replace the lanes with capacitor islands underneath

the DSP as long as this allows placing the decoupling capacitors
near the power pins. For example, instead of having two lanes, de-
signers may want to create many islands and each island can hold
one or more decoupling capacitors.

Figure 5.18. Full Grid Layout Example (DSP bottom view)

94 Chapter 5

5.2 HIGH FREQUENCY NOISE ISOLATION

The decoupling methods described up to now filter noise locally at the

DSP. There are cases where the whole power supply plane for some criti-
cal sections needs to be isolated. This may be required to prevent external
noise from entering these sections or to prevent noisy circuits such oscilla-
tors from coupling onto the power plane. The power supply plane is gener-
ally isolated using either Pi or T filters. A Pi filter is constructed with two
capacitors and one ferrite bead while a T filter requires one capacitor and
two ferrite beads. Each of these filters is commonly used in series with the
signals exiting and entering the system or the power supply to reduce the
radiated emissions. The pass-band of the filter has to be calculated pre-
cisely to ensure that the bandwidth is wide enough to pass the desired sig-
nals without degrading signal quality, especially critical parameters such
as rise and fall-times and amplitude.
14

1
Ferrite Bead, Z Output
3
2

C1 C2
7

DSP

Figure 5.19. Pi Filter Circuit for High Speed Signals

14

1
Ferrite Bead, Z1 Ferrite Bead, Z2 Output
3
2

C1
7

DSP

Figure 5.20. T Filter Circuit for High Speed Signals

Power Supply Decoupling 95

Ferrite Bead

VDD
Power TI DSPA

14
+ 1
3
C1 C2 2
-
Load Cap

7
Figure 5.21. Pi Filter Circuit for Power Supply Isolation

5.2.1 Pi Filter Design

The filter bandwidth is calculated as follows:
For Pi filter in Figure 5.19, starting from the DSP output, the first parallel
component is C1, second series component is Z and third parallel compo-
nent is C2. Therefore, the bandwidth of this filter is determined by the
three poles formed by C1, ferrite bead and C2 assuming that the output
impedance of the DSP is matched with the load impedance and is equal to

Lz
, where Lz is the inductance of the ferrite bead Z. (5.14)
2xC1

For this special Pi filter assuming C1 equal to C2, the corner frequency of
the 3-pole filter [6] is

1
fC = . (5.15)
π Lz C1
Figure 5.22 shows the frequency response of this special Pi filter.
96 Chapter 5

Figure 5.22. Pi Filter Frequency Response

Pi Filter Design Example:

Lets design a Pi filter for a graphic controller’s Red, Green and Blue
(RGB) analog signal outputs driving a computer monitor. Assuming that
RGB signals have a 100MHz analog bandwidth, calculate the filter com-
ponents as follows.
Let fc = 200MHz. Setting the filter at 200MHz provides a 100MHz margin
(200MHz minus 100MHz) to make sure that the filter is not affecting the
video signal bandwidth.
The filter corner frequency is

1
fC = = 200MHz.
π Lz C1
Lets select a ferrite bead with 100 ohms impedance at 100MHz and calcu-
late Lz. The impedance, Z, of the ferrite bead is
Z = 2πfL = 100 ohms,

100 100
Lz = = = 0.16uH .
2πf 2π (100 x106 )
Now, calculate C1 by substituting Lz and fc into the Eq. (5.15) and solve for
C1.
Power Supply Decoupling 97

1
fC = = 200MHz,
π Lz C1

1
200 x106 = ,
π (0.16 x10− 6 )C1

C1 = 15.8pF.
Therefore, the Pi filter has two 15.8pF capacitors and one 0.16uH inductor.
Now, lets use an analog circuit simulator [7] to verify the design.

VF1
VF2

R1 71 L1 160n
C2 15.8p

C1 15.8p

VG1
+

R2 71

Figure 5.23. Pi Filter Circuit Model for Simulation

To match the source and load impedance, use Eq. (5.14) and calculate R1
and R2 values. In this case, R1 = R2 = 71 ohms for C1 = 15.8pF and
Lz=0.16uH.

Figure 5.24. Pi Filter Circuit Simulation Results

98 Chapter 5

Figure 5.24 shows the simulation results of the circuit model shown in
Figure 5.23. In the pass-band from DC to 100MHz, the circuit shows a
-6dB attenuation. This is because the voltage divider formed by the 71
ohm source resistor and 71 ohm load resistor. In this case, the attenuation
is

VF 2
= 20 log10 , where (5.16)
VF 1

71
VF 2 = VF 1 . (5.17)
71 + 71
Now, substitute Eq. (5.17) into Eq. (5.16) and solve calculate the attenua-
tion.

71
Attenuation = 20 log10 = −6dB .
71 + 71
This correlates with the simulation results showing a -6dB signal attenua-
tion within the pass-band.
For the filter corner frequency, the simulation results show that the signal
starts rolling off at 100MHz with a slope of 60dB/decade. This is correct
as this is a 3-pole low-pass filter and each pole has a 20dB/decade slope.
Since the -3dB corner frequency of each pole is at 200MHz and the Pi fil-
ter has 3 poles (2 capacitors and 1 ferrite bead), the combined corner fre-
quency at 200MHz has a -9dB attenuation as shown in the simulation.

5.2.2 T Filter Design

The filter bandwidth is calculated as follows:
For the T filter in Figure 5.20, starting from the DSP output, the first series
component is L1, second parallel component is C1 and third series compo-
nent is L2. Therefore, the bandwidth of this filter is determined by the
three poles formed by the two equal inductance ferrite beads and C1 as-
suming that the output impedance of the DSP is matched with the load im-
pedance and is equal to
Power Supply Decoupling 99

Lz
, where Lz is the inductance of the ferrite bead Z. (5.17)
2xC1

For this special T filter assuming L1 equal to L2, the corner frequency of
the 3-pole filter [6] is

1
fC = . (5.18)
π Lz C1
Figure 5.25 shows the frequency response of this special Pi filter.

Figure 5.25. T Filter Frequency Response

T Filter Design Example:

Lets design a T filter for a graphic controller’s Red, Green and Blue
(RGB) analog signal outputs driving a computer monitor. Assuming that
RGB signals have a 100MHz analog bandwidth, calculate the filter com-
ponents as follows:
Let fc = 200MHz. Setting the filter at 200MHz provides a 100MHz margin
(200MHz minus 100MHz) to make sure that the filter is not affecting the
video signal bandwidth.
The filter corner frequency is
100 Chapter 5

1
fC = = 200MHz.
π Lz C1
Lets select a ferrite bead with 100 ohms impedance at 100MHz and calcu-
late Lz. The impedance, Z, of the ferrite bead is
Z = 2πfL = 100 ohms,

100 100
Lz = = = 0.16uH .
2πf 2π (100 x106 )
Now, calculate C1 by substituting Lz and fc into the Eq. (5.18) and solve for
C1 .

1
fC = = 200MHz,
π Lz C1

1
200 x106 = ,
π (0.16 x10− 6 )C1

C1 = 15.8pF.
Therefore, the T filter has two 0.16uH ferrite beads and one 15.8pF capaci-
tor. Now, lets use an analog circuit simulator [7] to verify the design.

VF1
VF2

R1 71 L1 160n L2 160n
C1 15.8p

VG1
+

R2 71

Figure 5.26. T Filter Circuit Model for Simulation

Power Supply Decoupling 101

To match the source and load impedance, use Eq. (5.17) and calculate R1
and R2 values. In this case, R1 = R2 = 71 ohms for C1 = 15.8pF and
L1=L2=0.16uH.

Figure 5.27. Pi Filter Circuit Simulation Results

Figure 5.27 shows the simulation results of the circuit model shown in
Figure 5.26. In the pass-band from DC to 100MHz, the circuit shows a -
6dB attenuation. This is because the voltage divider formed by the 71 ohm
source resistor and 71 ohm load resistor. In this case, the attenuation is

VF 2
= 20 log10 , where (5.19)
VF 1

71
VF 2 = VF 1 . (5.20)
71 + 71
Now, substitute Eq. (5.20) into Eq. (5.19) and solve calculate the attenua-
tion.

71
Attenuation = 20 log10 = −6dB .
71 + 71
This correlates with the simulation results showing a -6dB signal attenua-
tion within the pass-band.
102 Chapter 5

For the filter corner frequency, the simulation results show that the signal
starts rolling off at 100MHz with a slope of 60dB/decade. This is correct
as this is a 3-pole low-pass filter and each pole has a 20dB/decade slope.
Since the -3dB corner frequency of each pole is at 200MHz and the T filter
has 3 poles (2 ferrite beads and 1 capacitor), the combined corner fre-
quency at 200MHz has a -9dB attenuation as shown in the simulation.
Table 5.4 shows a comparison between T and Pi filters.

Table 5.4. Pi and T Filters Comparison

Pi Filter T Filter
1. Components Two capacitors and one ferrite Two ferrites and
Required one capacitor

2. Cost Slightly lower because capaci- Slightly higher

tors are less expensive than fer-
rites

3. Effectiveness Slightly better because having a Difficult to layout

capacitor to ground next to the the capacitor
RGB connector reduces RF cur- close to the con-
rent loops and ESD susceptibil- nector
ity

4. Power Supply Recommended for power sup- Not as effective

Isolation ply filtering because the capaci- as the Pi filter, the
tor can be placed close to the capacitor can’t be
power supply pin placed as close

5.3 SUMMARY

Power supply decoupling and noise isolation techniques discussed in this

chapter provide practical design considerations and theoretical approaches
to design the optimum filters for noise isolation. Poor decoupling tech-
niques are the number one root cause of random DSP system failures. So,
to improve the probability of design success and to prevent random logic
failures caused by excessive system noise, designers need to do the follow-
ing:
Power Supply Decoupling 103

• Apply the General Rules for decoupling or the Analytic Decoup-

ling methods described in this chapter.

• Follow the guidelines shown in this chapter to place the decoup-

ling capacitors properly. Select the right components (ferrite
beads, inductors, capacitors or resistors) for the design.

• Use Pi filters to isolate noise and place the capacitor as close to

the connector as possible. This minimizes the RF current loops
while providing some ESD protection.

• Use an analog simulator [7] and simulate the design to verify all
the calculations before going into layout.
104 Chapter 5

REFERENCES

[1] Johnson H, Graham M (1993) High-Speed Digital Design – A Hand-

book of Black Magic. Prentice Hall PTR, New Jersey.

[2] Mentor Graphics (2004) Hyperlynx Signal Integrity Simulation soft-

ware. http://www.mentor.com/products/pcb-system-design/circuit-
simulation/hyperlynx-signal-integrity/.

[3] Murata Manufacturing Co. (2009) Murata EMI Filter Selection Simu-
lator.

[4] Ott Henry (2009) Electromagnetic Compatibility Engineering.

John Wiley and Sons, New Jersey.

[5] Texas Instruments Inc (2002) OMAP5910 Dual-Core Processor Data

Manual. http://focus.ti.com/lit/ds/symlink/sm320c6713b-ep.pdf.

[6] Kaiser Kenneth, (2005) Electromagnetic Compatibility Handbook.

CRC Press, Florida.

[7] Texas Instruments Inc (2008) Spice-Based Analog Simulation Pro-

gram. http://focus.ti.com/docs/toolsw/folders/print/tina-ti.html.
 Phase-Locked Loop (PLL) 6

PLL is the heart of practically all electronic components and or modules

where different clock frequencies are required to synchronize the data
transmitting and receiving to and from externals respectively. The input
clock to the PLL is much lower than the DSP maximum clock frequency.
PLL is typically being used as a frequency synthesizer to generate the
clock for the DSP core. For example, the input clock to the 1.2GHz DSP
[1] is 66MHz.
PLL is an analog circuit that is very sensitive power supply noise. Noise
causes jitter and excessive jitter causes timing violations which lead to sys-
tem failures. The two main PLL architectures are analog PLL (APLL) and
digital PLL (DPLL). Understanding the differences help to make the de-
sign tradeoffs often required for minimizing noise and jitter caused by ex-
ternal circuitries, such as the power supply and other noisy switching de-
vices.

6.1 ANALOG PLL (APLL)

As stated, PLL generally functions as a frequency synthesizer, multiplying
the input clock by an integer. This integer is a ratio of the feedback counter
M divided by the input counter N as shown in Figures 6.1.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_6, 105
© Springer Science+Business Media, LLC 2010
106 Chapter 6

fREF fOUT
/N PFD CP VCO
R
C
C

/M

M
f OUT = f IN
N

Figure 6.1. Analog PLL

The following table provides a brief description of each block shown Fig-
ure 6.1 for the APLL.

Table 6.1. Analog PLL Description

Name: Description: Function:

/N Divide-by-N Divide-by-N counter scales down the

input frequency

PFD Phase-Frequency PFD compares the frequency and the

Detector phase of the input and the feedback
clock signals and generates an error sig-
nal.

CP Charge Pump This is typically a constant current

source controlled by the error signal
output from the PFD block.

VCO Voltage Con- This VCO oscillates at a frequency con-

trolled Oscillator trolled by the DC input voltage derived
from integrating the error signal.

/M Divide-by-M Divide-by-M counter scales down the

output frequency.
Phase-Locked Loop (PLL) 107

The following provides an overview of how the PLL functions as a fre-

quency synthesizer:
1. The reference clock is connected to the PDF input. The Divide-by
N counter reduces the input frequency.
2. The PDF compares the output of the Divide-by-M counter with the
reference clock and generates an error signal.
3. Base on the error signal, the CP charges or discharges the current
store on the loop filter, an RC filter shown in Figure 6.1. This in-
creases or decreases the VCO control voltage. For some PLL archi-
tectures, increasing the VCO control voltage increases the clock
frequency and decreasing the voltage lowers the clock output fre-
quency.
4. The phase correction continues until both the feedback signal from
the Divide-by-M counter and the reference clock are synchronized.
At this point, the error voltage should be zero.
5. The output clock frequency is equal to the ratio of the Divide-by-M
counter and the Divide-by-N counter multiply by the input clock
frequency. As a rule of thumb, a higher multiplier ratio yields
higher jitter, so keep the M and N ratio as low as possible when de-
signing with PLLs. The PLL output frequency, fout, for a given in-
put frequency, fin, is

M
f out = fin , where M is the PLL
N (6.1)

feedback counter and N is the input counter.

6.1.1 PLL Jitter

Jitter in PLL design is defined as the signal timing displacement from a
reference clock. The three main sources of DSP PLL jitter are jitter gener-
ated by the reference clock itself, power supply noise and noise coupling
from external and internal circuitries. The following lists important tech-
niques for designers to minimize the DSP PLL jitter:
108 Chapter 6

• Select a reference clock oscillator with the lowest jitter speci-

fication possible.

• Heavily filter the clock circuit to reduce the effect of noise on

output jitter. See the following section on PLL isolation.

• Use a series termination resistor at the output of the reference

clock to control the edge rate.

• Distribute the clock differentially if possible. Differential sig-

nals reject common mode noise and crosstalk.

• Set the multiplier as low as possible to achieve maximum DSP

operating frequency. Keep in mind that a higher multiply ratio
yields higher output jitter.
In all cases, jitter can be minimized but cannot be eliminated. The three
types of deterministic jitter [2] important for frequency synthesizers and
DSP performance are long term jitter, cycle-to-cycle jitter and period jitter.
Long Term Jitter: See Figure 6.2 where long-term jitter is defined as a
time displacement from the ideal reference clock input over a large number
of transitions. Long term jitter measures the deviation of a rising edge over
a large number of cycles (N) after the first rising edge.
Peak-to-Peak Jitter = Max Period (N cycles) – Min Period (N cycles),
where Max Period is the maximum period equal to 1 divided by the operat-
ing frequency measured at N number of cycles and Min Period is the
minimum period equal to 1 divided by the operating frequency measured
at N number of cycles.

Figure 6.2. Long Term Jitter

Phase-Locked Loop (PLL) 109

The long jitter can be measured using an automatic jitter measurement

equipment [3] or using a high speed digital sampling scope. Here are the
steps to measure long term jitter using a scope:

• Use a high-speed 10GHz sampling oscilloscope.

• Use the input clock to trigger the scope and set the scope in
the Infinite Persistence mode.

• The deviation is measured from the first rising edge to the Nth
cycle. The “fuzz” shown on the scope in Figure 6.3 is the long
term jitter.

Figure 6.3. Jitter Measured by Digital Scope

Cycle-To-Cycle Jitter: See Figure 6.4 where cycle-to-cycle is defined as

the deviation of the clock period between two consecutive clock cycles.

Figure 6.4. Cycle-To-Cycle Jitter

In Figure 6.4, the cycle-to-cycle is measured by subtracting t2 from t1, t3

from t2, and so on.
110 Chapter 6

Cycle-To-Cycle Jitter Measurement:

This is a difficult parameter to accurately measure with the high-speed
sampling scope. Because the sampling scopes on the market today are not
capable of measuring jitter in a few picoseconds range. The best way is to
use a Timing Interval Analyzer (TIA) which captures one cycle at a time
and compares the timing differences between two consecutive cycles. An-
other method is to use a scope with a cycle-to-cycle jitter measurement op-
tion. This method is outlined as follows:

• Use a high-speed 10GHz sampling oscilloscope [4] with cy-

cle-to-cycle jitter option.

• Trigger the PLL output clock and measure the cycle-to-cycle

jitter. Use the windowing method to measure the changes
from one cycle to another.
Period Jitter: See Figure 6.5 where period jitter is defined as the maxi-
mum deviation in the clock’s transition from its ideal position. These peri-
ods are non-successive.

Figure 6.5. Period Jitter

Period Jitter Measurement:

• Use a high-speed 10GHz sampling oscilloscope [4].

• Set the scope in the Infinite Persistence mode and trigger the
PLL clock output on the rising edge.

• Measure the “fuzz” shown on the screen at the next rising of

the clock.
Phase-Locked Loop (PLL) 111

In summary, the jitter measurements can either be done using a high-speed

digital sampling scope, Timing Interval Analyzer (TIA) or an automatic
jitter measurement system [3].

6.2 DIGITAL PLL (DPLL)

The main differences between the APLL and DPLL are that the DPLL re-
places the analog filter with a digital controller block that filters the phase
error in the digital domain and replaces the VCO with a Digital Controller
Oscillator (DCO). The advantages of the DPLL are:

• The DPLL supports a wide range of input frequency from

30KHz to 65MHz or higher.

• The DPLL design requires a smaller silicon area to implement

and consumes less power than the APLL.

• The DPLL does not have analog filter components such as ca-
pacitors which can cause leakage current. This leads to lower
power consumption.

• The DPLL block is scalable and portable. The same design

can be implemented on different process technology nodes.

• The DPLL design can be optimized for low jitter. But it may
not be acceptable for jitter sensitive designs such as USB, au-
dio and video clocks.
The disadvantages of the DPLL are:

• It is very sensitive to external and internal power supply noise.

Use of a linear regulator plus a Pi filter to isolate the power
supply from the DPLL is recommended.

• Low power supply rejection ratio.

• In addition to power supply sensitivity, quantization noise and

phase detector dead zone are the major sources of output jitter.

• Requiring a DAC block to control the oscillator. This makes

the DPLL more sensitive to noise.
112 Chapter 6

Figure 6.6 shows a typical DPLL architecture [6] and Table 6.2 describes
the function of each block in the architecture.

fREF Digital fOUT

/N PFD DAC OSC
Controller
DCO

/M

M
f OUT = f IN
N

Figure 6.6. Digital PLL

Table 6.2. Digital PLL Description

Name: Description: Function:

/N Divide-by-N Divide-by-N counter scales down the

input frequency

PFD Phase- PFD compares the frequency and the

Frequency De- phase of the input and the feedback
tector clock signals and generates an error
signal.

Digital Digital Control- This digital filter block detects the

Controller ler phase error information and digitally
controls the oscillator.

DCO Digital con- This DCO converts the control code

trolled oscillator to analog levels and generates a stable
clock output.

/M Divide-by-M Divide-by-M counter scales down the

output frequency.
Phase-Locked Loop (PLL) 113

APLL and DPLL Jitter Characterization

Table 6.3 shows a jitter comparison between an analog and a digital PLL
that shows the effects of process variation where Hot is fast, Cold is slow
and Baseline is typical. In this DSP design, the DPLL power supply is iso-
lated by an internal low dropout regulator (LDO) while the APLL is con-
nected directly to the common power supply plane. To test the noise sensi-
tivity, 100mV of noise modulating from 100Hz to 1MHz is injected into
the power supply rails. The results showed that the peak-to-peak period jit-
ter is less than 3% for the DPLL and is less than 2% for the APLL. With
the LDO, the DPLL jitter is less than 4% up to 50mV of noise on the
power supply.

Table 6.3. APLL and DPLL Jitter Comparison

Designers need to be careful when injecting a signal onto the power supply
to do jitter measurements. The nature of the signal used for simulating a
noisy power supply condition can have a major impact on the PLL jitter. A
squarewave signal with a frequency less than the PLL bandwidth charac-
terizes the worst case PLL jitter. As far as the amplitude of the noise, the
peak-to-peak voltage has to be within the power supply limits. For exam-
ple, for a 1.6V +/-3% Core, the maximum acceptable peak-to-peak noise is
96mV (-48mV min and +48mV max).
114 Chapter 6

6.3 PLL ISOLATION TECHNIQUES

As shown in previous sections, both an APLL and a DPLL are sensitive to
noise, especially to noise frequency within the PLL bandwidth. PLL isola-
tion is needed in order to prevent the high frequency PLL signal from
propagating out of the PLL section and affecting other circuits. PLL isola-
tion can also attenuate the external noise propagating to the PLL circuit
which causes excessive jitter. In many cases, external power supply noise
causes the PLL to go unstable and the DSP to lock-up randomly.

6.3.1 Pi and T Filters

The two important filter schemes discussed in this document to isolate the
PLL are low frequency filtering and high frequency filtering. For high fre-
quency filtering, a Pi or T network filter can be used as shown in Figures
6.7 and 6.8:

VDD_3V3 VDD_PLL
L

FERRITE BEAD

C1 C2

Figure 6.7. Pi Filter Circuit

The Pi filter circuit consists of one ferrite bead, L and two capacitors, C1
and C2. This circuit provides both input and output isolation where noise
from the 3.3V supply is attenuated by the ferrite bead and the C2 capacitor
and noise generated by the PLL circuit is isolated by the ferrite bead and
the C1 capacitor. Refer to Chapter 5 for the filter design and simulation in-
formation.
Phase-Locked Loop (PLL) 115

VDD_3V3 VDD_PLL
L1 L2

FERRITE BEAD FERRITE BEAD

C1

Figure 6.8. T Filter Network

A T filter consists of two ferrite beads and one capacitor as shown in Fig-
ure 6.8. Just like in a Pi filter, 3.3V supply noise is attenuated by the L1
ferrite bead and the C1 capacitor and PLL noise is isolated by the L2 ferrite
bead and C1 capacitor. Refer to Chapter 5 for the filter design and simula-
tion information.
Both Pi and T circuits are good for filtering high frequency noise but they
are not as effective for low frequency filtering since ferrite beads have al-
most zero AC impedance at low frequency. The Pi circuit has an advantage
over the T circuit. Because this topology makes it possible to place the ca-
pacitor closer to the PLL voltage pin that ensures low impedance to ground
and also the smallest current loop area, which reduces noise and EMI.
For low frequency isolation, there are two common techniques, Pi filter
with large bulk capacitor and linear voltage regulator.

VDD_3V3 VDD_PLL
R

+
C1 C2 C3
10uf

Figure 6.9. Low Frequency Pi Filter

116 Chapter 6

One method for low frequency filtering is shown in Figure 6.9, where a re-
sistor R replaces the ferrite bead and a bulk capacitor C3 (10uF to 33uF) is
added to the circuit. Low frequency noise is attenuated by the resistor R
and the bulk capacitor C3. The resistor needs to be selected such that the
voltage drop across the resistor is negligible. The low frequency -3dB cor-
ner for this filter is approximated by Equation 6.2. Notice that C1 and C2
are negligible in this case, since its value is a lot lower than the bulk ca-
pacitor C3.

1
f−3dB =
2πRC3 (6.2)

Design Example 6.1:

Design a PLL power supply filtering circuit that provides a 20dB attenua-
tion at 15KHz. The tolerance for the PLL power supply is +/-5% and the
maximum current consumption is 10mA.
Design steps are:

• The Pi filter circuit in Figure 6.9 is a single pole filter ne-

glecting C1 and C2. For a single pole filter, the attenuation
is -20dB/decade starting at the -3dB corner frequency as
shown in Equation 6.2.

• f-20dB = 10xf-3dB , slope is 20dB/dec so the frequency at -

20dB is equal to 10 times the frequency at -3dB. There-
fore, f-3db = (15KHz)/10 = 1.5KHz.

• From Equation 6.2,

1
f−3dB = = 1.5KHz,
2πRC3
RC3 = 1.06x10-4,
Let R = 10 ohms,
Phase-Locked Loop (PLL) 117

C3 = 10.6uF or 10uF.

• The voltage drop across the resistor is

o V = IR = 10x10-3 = 0.01V. This is very small
and is way within the power supply limits of
3.3V±5%.

• The resistor power dissipation is

o P=VI where V=IR -> P=I2R =(10mA)2x10 =
0.01mW. This small power dissipation allows
designers to use a very small size resistor for
this filter.

• Let C1 and C2 be a 0.01uF capacitor since this is a

good high frequency decoupling capacitor as discussed
in Chapter 5. The final circuit and simulation are
shown in Figure 6.10 and Figure 6.11 respectively.

VDD_3V3 R3 10 VDD_PLL
C2 10n

C1 10n

C3 10u

Figure 6.10. Final Pi Filter Circuit for PLL

Figure 6.11. Final Pi Circuit Simulation

118 Chapter 6

As shown in Figure 6.11 simulation, the -3dB corner frequency is at

1.5KHz and the -20dB attenuation is at 15KHz. These are the design
specifications.
In this design example, there is an IR voltage drop across the resistor R so
it is very important to select the resistance to guarantee that the PLL sup-
ply voltage range are within the specified limits for worst case PLL current
consumption.

6.3.2 Linear Voltage Regulator

Another method of low frequency filtering is to use a linear voltage regula-
tor. This method has the least effect on PLL performance. The linear regu-
lator typically has good line regulation and power supply rejection charac-
teristics which prevent low frequency transients and high frequency noise
from entering the PLL circuit. The method shown in Figure 6.12 is more
expensive to implement than other methods described previously. But it is
extremely effective in keeping the PLL voltage as clean as possible to
guarantee lowest PLL jitter. Refer to Chapter 4 for design considerations.

VDD_5V VDD_PLL
Linear
Reg
+
C1 C2 C3
10uf

Figure 6.12. Noise Isolation with Voltage Regulator

One issue with using a linear regulator is that it does not reject high fre-
quency very well. As shown in Figure 6.13, the ripple rejection is ap-
proaching 0dB (no rejection at all) for noise that is higher than 1MHz.
This high frequency noise can cause more jitter in the PLL.

In summary, the best way to isolate PLL is using a combination of Pi filter

and linear regulator. In this case, the Pi filter can be implemented with fer-
Phase-Locked Loop (PLL) 119

rite bead and capacitors so there is no IR drop across the resistor as shown
in the previous example. The final circuit is shown in Figure 6.14.

Figure 6.13. Linear Regulator Ripple Rejection

L1
VDD_5V LINEAR VDD_PLL

REGULATOR
+
C3 C4
C2 C1

Figure 6.14. Linear Regulator Pi Filter Circuit

6.4 SUMMARY

Because of low power consumption and fast response time, most of the
PLL designs integrated in the DSP today are based on digital PLL con-
cepts. As discussed, DPLL is very sensitive to power supply and input
noise, so proper design noise isolation filters are required to achieve the
lowest jitter possible. The best approach is using a combination of Pi filter
and linear regulator as shown in Section 6.3.2. This may not be possible
due to PCB space limitation so designers have to make design compro-
mises. If there is not enough room for the regulator circuit, then imple-
menting a Pi filter using a resistor instead of a ferrite bead is the second
best approach. This has low frequency and high frequency filtering char-
acteristics as demonstrated in Section 6.3.1.
120 Chapter 6

REFERENCES

[1] Texas Instruments Inc (2008) SM320C6455-EP Fixed-Point Digital

Digital Signal Processor. SPRS462B. http://focus.it.com/lit/ds/symlink/
sm320c6455-ep.pdf.

[2] Cypress Semiconductor Corporation (1997) Jitter in PLL-Based Sys-

tems: Causes, Effects and Solutions.

[3] Wavecrest (2002) Examining Clock Signals And Measuring Jitter with
the WAVECREST SIA-300. Application Note No. 142.

[4] Agilent Technologies (2003) Jitter Generation and Jitter Measure-

ments with the Agilent 81134A Pulse Pattern Generator & 54855A In-
finiium Oscilloscope.

[5] Lin J, Haroun B, Foo T, Wang J, Helmick B, Mayhugh T, Barr C,

Kirkpatrick J (2004) A PVT Tolerant 0.18MHz to 600MHz Self-
Calibrated Digital PLL in 90nm CMOS Process. ISSCC.
 Data Converter Overview 7

This chapter provides an overview of analog-to-digital and digital-to-

analog converters and their applications to audio and video systems design.
There are many factors affecting the performance of the converters and
these can be minimized if designers understand the converter’s sampling
techniques and quantization noise, the necessity of having input and output
filters and the proper system design and layout.

7.1 DSP SYSTEMS

Figure 7.1 shows a typical DSP system where the input and output are ana-
log and data converters plus processing elements reside in the middle of
the signal chain. The theories and applications of the input Gain Stage,
Anti-Aliasing Filter (ADC input) and Reconstruction Filter (DAC output)
are covered in Chapter 8. This chapter focuses on the ADC and DAC
blocks of the DSP Signal Chain in Figure 7.1.
In general, a DSP system captures an analog input, amplifies the signal,
band-limits the signal for sampling, converts it to digital, processes the
data in digital domain, converts it back to analog and filters the sampling
noise to reconstruct the analog signal.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_7, 121
© Springer Science+Business Media, LLC 2010
122 Chapter 7

Figure 7.1. DSP Signal Chain

The design goal is to maintain or improve the signal quality as it propa-

gates through all the blocks shown in Figure 7.1. The question is why is it
necessary to convert the analog signal to digital and process it in digital
domain? It is because:

• There are no linear and non-linear distortions.

• Data compression is possible in digital domain. This is key for

video, audio and communication as these systems have limited
transmission bandwidth.

• It is easy to upgrade the system by replacing the software and or

DSP algorithms.

7.2 ANALOG-TO-DIGITAL CONVERTER (ADC)

An ADC converts the analog input to the digital output word by sampling
and comparing the analog level to the digital word. This sampling point to
decide what digital code is equivalent to this analog value. For example in
Figure 7.2, sampling point 0 occurs at 1V analog level translating to 001
digital output word, sampling point 1 occurs at 2V analog level translating
to 010 digital output word and so on.
Data Converter Overview 123

Figure 7.2. Analog-to-Digital Converter

In Figure 7.2, 1 LSB is defined as one Least Significant Bit and at every
sampling point; the analog level can vary from ±1/2LSB from the center.
This is known as a quantization error. The LSB voltage, VLSB, is equal to

Vref
V LSB = , where Vref is the reference voltage (7.1)
2N
and N is the number of bits.
For the 3-bit ADC and Vref of 8V, the VLSB is equal to 1V. Table 7.1
shows an example of a 3-bit ADC sampling an 8V analog input signal.

Table 7.1. ADC Input and Output

Digital Code: Analog Range: Quantization Error:

000 0 to 0.5V 1/2LSB or 0.5V

001 0.5V to 1.5V 1 LSB or 1V

010 1.5V to 2.5V 1 LSB or 1V

011 2.5V to 3.5V 1 LSB or 1V

100 3.5V to 4.5V 1 LSB or 1V

101 4.5V to 5.5V 1 LSB or 1V

110 5.5V to 6.5V 1 LSB or 1V

111 6.5V to 7.5V 1 LSB or 1V

124 Chapter 7

Overall, the equation for calculating the voltages of the ADC [1] is as fol-
lows:
Vref(b12-1 + b22-2 + b32-3 + …… + bN2-N) = Vin ± Vx, (7.2)
where Vx is

1 1
− V LSB ≤ V X ≤ V LSB and b1 is the most significant
2 2
bit and bN is the least significant bit.
Figure 7.3 shows a practical ADC block diagram where the analog input
has to be band-limited before being converted to digital word. This is be-
cause the Nyquist sampling theory defined that the sampling clock has to
be at least two times the analog bandwidth to prevent aliasing. Aliasing is
the image of the analog signal folded back into the frequency of interest;
aliasing degrades the ADC performance. Therefore, an anti-aliasing filter
must be placed at the input of the ADC.

ANALOG ANALOG-TO-
ANTI-ALIASING DIGITAL
INPUT DIGITAL
FILTER OUTPUT
CONVERTER

Sampling
Clock, fS

Figure 7.3. Analog-to-Digital Block Diagram

7.2.1 Sampling
An ADC utilizes the sampling clock, fS, to sample the analog input and
represents the level in a digital word as shown in the previous section.
Sampling is equivalent to amplitude modulating the signal, fA, into a car-
rier equal to the sampling frequency and generates a frequency spectrum
shown in Figure 7.4.
Data Converter Overview 125

Figure 7.4. Frequency Spectrum of a Sampled Signal

Nyquist Theorem states that the sampling frequency fs must be equal to or

greater than 2 times the signal bandwidth fA or
fs ≥ 2fA. (7.3)
If the sampling frequency is less than 2 times the signal bandwidth, then
the sampled signal aliases back into the signal bandwidth causing the dy-
namic range degradation. Figure 7.5 shows an aliasing region when this is
the case. So, to guarantee compliant to Nyquist Theorem, the ADC must
have an anti-aliasing filter at the input to limit the signal bandwidth and a
sampling frequency greater than 2 times the signal bandwidth. One impor-
tant rule-of-thumb for selecting an anti-aliasing filter is that higher sam-
pling frequency ADC requires a lower order anti-aliasing filter. This is
because higher sampling frequency pushes the noise spectrum further
away from the analog spectrum and enables the lower order filter to pre-
vent the noise image from aliasing back into the band of interest. Figure
7.5 and Figure 7.6 demonstrate this phenomenon.

Figure 7.5. Aliasing

126 Chapter 7

Figure 7.6. Higher Sampling Frequency

Today’s technologies enable very high sampling frequency ADC so it is

not necessary to have higher than a 2nd order anti-aliasing filter at the input
of the ADC.

7.2.2 Quantization Noise

Quantization process is a process of sampling an analog signal and repre-
senting the signal in a sequence of digital bits. The issue is that the input
signal varies rapidly and generates a quantization error where a particular
bit oscillates back and forth between two digital levels. For example in
Figure 7.7 at the Sample 2 and Sample 3 points, the digital word for these
two levels could be 000 or 001, since these points are at half way between
two levels and at a given sample time, the quantizer can interpret this level
as a 000 or 001. Therefore, the quantization error is ±q/2 where q is a
quantization step equal to 1 LSB.

Figure 7.7. Quantization Error

Data Converter Overview 127

Now assume that the quantization error voltage between the quantized lev-
els and the sampled voltage is uniformly distributed between –q/2 and +q/2
where q is equal to 1 LSB voltage. In this case, the Probability Density
Function, fQ(x), is shown in Figure 7.8 where the area under the curve is
equal to one.

Figure 7.8. Probability Density Function, fQ(x)

The quantization noise in RMS value is

1/ 2
⎡ q/2 2 ⎤
VQ(rms) = ⎢ ∫ x f Q ( x ) dx ⎥
⎣⎢ − q / 2 ⎥⎦
1/ 2 1/ 2
⎡1 q /2
⎤ ⎡1 q /2
⎤
∫ ∫
2 2
=⎢ x dx ⎥ = ⎢ x dx ⎥
⎢⎣ q −q / 2 ⎥⎦ ⎢⎣ q −q / 2 ⎥⎦
1/ 2 1/2
⎡1 q /2
⎤ ⎡ 1 ⎡ 1 3 ⎤ +q /2 ⎤
∫
2
=⎢ x dx ⎥ = ⎢ ⎢ x ⎥⎦ ⎥
⎢⎣ q −q / 2 ⎥⎦ ⎢⎣ q ⎣ 3 −q / 2 ⎥
⎦
q
= . (7.4)
12
The RMS value of a sinusoidal signal is
128 Chapter 7

1/2
⎡1 T
⎤
∫0 V ( t ) dt ⎥⎦
2
VIN(rms) = ⎢ , where V(t) = Acos(2πfct)
⎣T
and A is the zero-to-peak voltage as shown in Figure 7.9.

Figure 7.9. Sinusoidal Input Waveform

Therefore,
1/2
⎡1 T
⎤
∫A ( 2 π f c t ) dt ⎥
2 2
VIN(rms) = ⎢ cos . Since
⎣T 0 ⎦
1 + cos( 4 π f c t )
cos 2
( 2π f ct ) = ,
2
1/ 2
⎡ A2 T
1 + cos( 4 π f c t ) ⎤
VIN(rms) = ⎢
⎣ T
∫0 2
dt ⎥
⎦
1/ 2
⎡ A2 T ⎤ A
= ⎢ ⎥ = . (7.5)
⎣ T 2⎦ 2
A is equal 1/2VREF since VREF is equal to the peak-to-peak voltage of a si-
nusoidal wave as shown in Figure 7.10 and A is the zero-to-peak value.
Data Converter Overview 129

Figure 7.10. VREF and Peak-to-Peak Voltage

Now, substitute A=1/2VREF into Eq. (7.5),

V REF
VIN(rms)= . (7.6)
2 2
Or
VREF = Vpeak-to-peak = 2.828VIN(rms).

The signal-to-noise or SNR is defined as the log of the ratio of the input
RMS voltage over the quantization noise.

V IN ( rms )
SNR = 20log10 . (7.7)
V Q ( rms )
Substitute Eqs. (7.6) and (7.4) into Eq. (7.7),

⎛ V REF 12 ⎞
SNR = 20log10 ⎜⎜ ⎟ .
⎟
⎝2 2 q ⎠
Since q = VLSB and from Eq. (7.1)

Vref
V LSB = ,
2N
130 Chapter 7

⎛ 3 N ⎞
SNR = 20log10 ⎜⎜ 2 ⎟
⎟
⎝ 2 ⎠
= 6.02N + 1.76 dB. (7.8)
Eq. (7.8) indicates that the performance of an ADC depends on the number
of bits used to quantize the analog signal. It is roughly 6dB per bit. This
equation was derived assuming that the only error in the system is quanti-
zation error. In the real world, other factors such as power supply noise
and clock jitter generate additional errors that degrade the signal-to-noise
significantly. So, another equation to measure the overall performance of
the ADC is

SNR − 1 . 76
ENOB, Effective Number of Bits = . (7.9)
6 . 02
For example, if a 16-bit ADC has an SNR specification of 86dB, the Effec-
tive Number of Bits is

86 − 1 . 76
ENOB = = 14 .
6 . 02
What this means is that the 16-bit ADC only performs at a 14-bit level due
to quantization noise and other system related noise, such as power sup-
plies, clocks and others degrading its performance.

7.3 DIGITAL-TO-ANALOG CONVERTER (DAC)

A DAC converts the digital input codes to the analog output values and its
transfer function is shown in Figure 7.43 [1]. Eq. (7.29) shows the rela-
tionship between the digital word, Bin, and the analog output signal, Vout.
Vout = Vref(b12-1 + b22-2 + b32-3 + …… + bN2-N) = VrefBin , (7.29)
where
Bin = b12-1 + b22-2 + b32-3 + …… + bN2-N.
Data Converter Overview 131

Figure 7.11. Digital-to-Analog

Similarly to ADC, for the 3-bit DAC and Vref of 8V, the V LSB is equal to
1V. Table 2 shows an example of a 3-bit DAC taking a digital word and
converting it to an equivalent analog level assuming that the sampling er-
ror is ±0.5LSB.

Table 7.2. DAC Input and Output

Digital Input Code: Analog Output: Error:

000 0V 0.5V

001 1V ±0.5V

010 2V ±0.5V

011 3V ±0.5V

100 4V ±0.5V

101 5V ±0.5V

110 6V ±0.5V

111 7V ±0.5V
132 Chapter 7

Figure 7.12 shows a practical DAC block diagram where the digital input
is being converted to analog and the Reconstruction Filter eliminates the
sampling noise modulated on the analog waveform. The design of this fil-
ter depends on which DAC is being used and how much noise suppression
is necessary to achieve a certain signal-to-noise specification. The filter
topologies and design methodologies are covered in Chapter 8 of this
book.

Figure 7.12. Practical Digital-to-Analog

The filter requirements for the DAC are analog bandwidth, fA , samples per
second input, fs , and stop band attenuation. As shown in Figure 7.4, the
sampled data has an image closest to the band of interest at
Image = fs – fA.
For example, a video signal has a bandwidth of 6MHz and the DAC input
is 27 MSPS (Mega Samples Per Second). The image of this video signal is
Image = 27MHz – 6MHz = 21MHz.
If the system needs a 60dB signal-to-noise performance, then the image
needs to be attenuated at least 60dB at 21MHz. The details of the filter de-
sign are in Chapter 8.

7.4 PRACTICAL DATA CONVERTER DESIGN

CONSIDERATIONS
A typical high level block diagram shown in Figure 7.13 consists of input
ADC [2], DSP and DAC [3]. Here are the important parameters to con-
sider when selecting ADCs and DACs:

• Resolution and Signal-to-Noise (SNR)

Data Converter Overview 133

• Input and Output Voltage Range

• Sampling Frequency

• Differential Non-linearity

• Integral Non-linearity

S S

Figure 7.13. DSP System Block Diagram

7.4.1 Resolution and Signal-to-Noise

ADC or DAC resolution determines the number of digital bits to represent
an analog signal. Higher resolution always yields higher SNR. Here is an
SNR specification of ADC [2].
For a 10-bit ADC, SNR = 55dB for fA = 10MHz Sand f = 110
MSPS.
Lets calculate the Effective Number of Bits or ENOB using Eq. (7.8).

SNR − 1 . 76 55 − 1 . 76
ENOB= = ≅ 9 .
6 . 02 6 . 02
ENOB indicates that the performance of this 10-bit ADC is equivalent to
the performance of an ideal 9-bit ADC. Achieving the theoretical resolu-
tion is very difficult so getting a 9-bit performance out of a 10-bit ADC is
considered as a very good ADC.
134 Chapter 7

7.4.2 Sampling Frequency

Sampling frequency determines the frequency spacing between the analog
signal and its images as shown in Figure 7.4. So, a higher sampling fre-
quency is preferred. This allows lower order input and output filters. The
disadvantage of higher sampling frequency is that it tends to radiate more
effectively as discussed in Chapter 2.
In the ADC [2] data sheet, the SNR specification shows a sampling fre-
quency of 110MHz for a 10MHz signal. The minimum sampling fre-
quency is
at Nyquist, fs = 2fA = 2(10MHz) = 20MHz.
Oversampling = 110MHz/20MHz = 5.5.
The oversampling ratio of 5.5 indicates that the ADC samples the input
signal at the rate 5.5 times higher than the minimum sampling frequency
required by the Nyquist Theorem. In general, oversampling ADC or DAC
has higher performance than the non-oversampling one.

7.4.3 Input and Output Voltage Range

ADC and DAC data sheets specify a maximum input voltage and a mini-
mum output voltage respectively. To maximize the performance of the
system, it is recommended to amplify or attenuate the signal to get the
maximum symmetrical swing. For example,
An ADC has two inputs and each input has a maximum input specification
of 2 volts peak-to-peak. The two outputs from the previous stages measure
1 volts and 4 volts peak-to-peak. To balance the ADC inputs, one input
path has to include a gain circuit and the other has an attenuator as shown
in Figure 7.14.

Figure 7.14. Inputs to ADC

Data Converter Overview 135

The gain stages of 2 and 0.5 can be implemented using op amps as shown
in Chapter 8. Another option to design a gain of 0.5 is using a resistor di-
vider to divide the input voltage by half. Here is an example.

Figure 7.15. Voltage Divider

For the voltage divider shown in Figure 7.15, the output voltage is

R2
VO= V IN . (7.30)
R1 + R 2
If R2 = R1, then Vo is half of VIN.
Regarding the gain circuit of 2, refer to Chapter 8 for more details.
Similarly, for the DAC output voltage range, if the DAC being used has a
low level voltage output that is not compatible with the next stage or not
compliant to some input and output standards, then a gain circuit at the
DAC output is required. Refer to Chapter 8 to design this amplifier circuit.

7.4.4 Differential Non-Linearity (DNL)

The Differential Non-Linearity (DNL) error [4] occurs on both ADC and
DAC and is defined as the difference between the step width and one LSB.
From Figure 7.16 [4], the ADC DNL errors occur at 1V and 4V analog
levels. Ideally, the 001 code is centered at 1V with ±1/2LSB tolerance and
the 100 code is centered at 4V with ±1/2LSB, but due to DNL errors, the
001 code is at 1V with -1/2LSB tolerance and the 100 code is at 4V with -
1/2LSB to +1LSB tolerance.
136 Chapter 7

Figure 7.16. ADC Differential Non-Linearity

Figure 7.17 [4] shows a DAC DNL error where the input 010 code has an
analog range larger than 1 LSB voltage. In this case, the error is +1/4LSB.

Figure 7.17. DAC Differential Non-Linearity

Data Converter Overview 137

7.4.5 Integral Non-Linearity (INL)

The Integral Non-Linearly (INL) is defined as the maximum deviation of
the actual transfer function from an ideal straight line. Like DNL, both
ADC and DAC have INL errors. For ADC, the amount of error is meas-
ured at the transition from one digital code to another and compared it to
the ideal transition point as shown in Figure 7.18 [4]. For example, the ac-
tual transition from 001 code to 010 code happens at the 1V point instead
of 1.5V point. This early transition produces a -1/2LSB INL error.

Figure 7.18. ADC Integral Non-Linearity

Figure 7.19 [4] shows an INL error caused by the DAC. In this case, the
maximum deviation from the ideal curve happens at the 011 input digital
code and the error is equal to 1/2LSB.
138 Chapter 7

Figure 7.19. DAC Integral Non-Linearity

7.5 SUMMARY

Important points to remember in this chapter are:

• Proper sampling and filtering are key to achieving high perform-

ance data converter system design. Understanding Nyquist and
oversampling techniques are crucial for making the right data con-
verter selection for the targeted application.

• The derivation of SNR in this chapter was assumed that there is

only quantization noise in the system. This is an ideal case and is
not practical in the real world design. ENOB is a good measure-
ment of the actual data converter performance,

• DNL and INL errors occurred in ADC and DAC can not be elimi-
nated using system design techniques. These are inherent in the
data converter itself. Choose the converters with the lowest DNL
and INL specifications if possible.
Data Converter Overview 139

Overall, the design goal for the data converter system is to match the per-
formance specified in the converter data sheet. For example, if the con-
verter has an 80dB SNR specification, the system performance target
should be 80dB SNR. This is the best performance that can be achieved
because all other components (anti-aliasing filters, amplifiers, power sup-
plies, and reconstruction filters) around the converter tend to generate ad-
ditional noise and errors to the system.
140 Chapter 7

REFERENCES

[1] Johns D, Martin K (1997) Analog Integrated Circuit Design. John

Wiley & Sons, USA.

[2] Texas Instruments Inc (2007) TVP7002 Triple 8-/10-Bit 165-/110-

MSPS Video And Graphics Digitizer With Horizontal PLL,
SLES205A.

[3] Texas Instruments Inc (2009) THS8200 All-Format Oversampled

Component Video/PC Graphics D/A System with Three 11-Bit DACs,
CGMS Data Insertion, SLES032B.

[4] Texas Instruments Inc (1995) Understanding Data Converters, Mixed-

Signal Products, SLAA013.
 Analog Filter Design 8

This chapter presents passive and active filter topologies and design tech-
niques, including practical design examples and system simulations. In
DSP systems, there are analog filters required for signal conditioning and
limiting the bandwidth before sampling. To design these filters, designers
need to be knowledgeable of operational amplifiers, DC biasing circuits,
AC coupling techniques and traditional passive components like inductors,
capacitors and resistors.

8.1 ANTI-ALIASING FILTERS

There are many different types of anti-aliasing filters (Butterworth, Cheby-
shev, Inverse Chebyshev, Cauer and Besser-Thomson) [1], but for video,
audio and communication applications, it is best to use the Butterworth fil-
ter because it has the best passband performance; it is known as a maxi-
mally flat passband filter. A Butterworth filter can be implemented in two
ways; 1. With passive components such as resistors, inductors and capaci-
tors. 2. Active components such as operational amplifiers, resistors and
capacitors. There are advantages and disadvantages with the two ap-
proaches, so selecting the right topology requires designers to understand
the basic differences and how one filter works better than the other. One
important rule-of-thumb is the higher sampling frequency, the lower order
anti-aliasing filter needed as shown in Chapter 7.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_8, 141
© Springer Science+Business Media, LLC 2010
142 Chapter 8

8.1.1 Passive and Active Filters Characteristics

Table 8.1 shows characteristic of passive and active filters and highlights
the advantages and disadvantages of each type.

Table 8.1. Passive and Active Filters

Electrical Passive Filter: Active Filter:

Characteristic:

• Power Supply Not Required Required

• Voltage Gain No Yes

• Filter Compo- Inductors, Capacitors, Op Amps, Resistors,

nents Resistors Capacitors

• Radiation Yes, Inductors Tend to No, Proper Decoup-

Radiate ling is Required

• Circuit Stability Very Good Good, Proper Analy-

sis is required

• Dynamic Range No Yes (power supply

Limitation and op amp)

• Depending on Yes (filter characteris- No (op amp has very

Source and tics are affected by the high impedance in-
Load Imped- source and the load) puts)
ance

• Reliability Very Good (passive Good (active circuits

components are very like op amps are not
reliable) as reliable as passive
components)

• Frequency Very Good Good (limited by the

Range op amp bandwidth)

• Cost More Expensive (in- Less Expensive

ductors)
Analog Filter Design 143

In summary, if gain is not required and source and load impedances are
known, then it is better to go with passive filters. Now, if impedance isola-
tion and gain are required, then active filters would be better.

8.1.2 Passive Filter Design

A. 1st Order Passive Lowpass Filter:

The 1st order passive filter can easily be realized by one resistor and one
capacitor as shown in Figure 8.1.

Vin R1 Vout

C1 Rload

Figure 8.1. 1st Order Passive Filter

Assuming Rload is much higher than R1, the -3dB corner frequency for the
filter in Figure 8.1 is
1
f − 3 dB = . (8.1)
2 π R 1C 1

Example 8.1: An audio ADC has a bandwidth of 20Hz to 20KHz

and requires a 1st order anti-aliasing filter at its input. Design and
simulate [3] this filter.
Answer: Let f-3dB = 20KHz,
1
20 KHz = . Now, let C1 = 0.001uF and solve for
2πR1C1
R1 .
-> R1 = 8K ohms. As shown in Figure 8.2, the -3dB corner
frequency is at 20KHz.
144 Chapter 8

Figure 8.2. 1st Order Passive Filter Simulation

B. 2nd Order Passive Filter Design:

The 2nd order lowpass circuit requires one inductor and one capacitor. In
general, the order of the filter circuit is equal to the number of capacitors
and inductors in the circuit. As mentioned in the previous section, the pas-
sive filter depends on the source and load impedances, so lets assume that
the source impedance, RS, is much higher than the load impedance, RL, as
shown in Figure 8.3.

Vin Rs L1 Vout

C1 RL

Figure 8.3. 2st Order Passive Filter Circuit

Analog Filter Design 145

The frequency response of the 2nd order filter circuit has amplitude peaking
at the -3dB corner and the amount of this peaking depends on the ratio of
RL and RS. This peaking typically does not affect the circuit performance
as long as the noise at the corner frequency is very low, so it is crucial for
designers to verify that the frequency response and signal-to-noise over the
passband are as expected. It is very common to fine tune RL and RS to get
the frequency response needed for the application.

For RL >> RS, the -3dB corner frequency for the circuit in Figure 8.3 is

R + R
f − 3 dB = L S
. (8.2)
2π L 1C 1 R L

Example 8.2: An audio ADC has a bandwidth of 20Hz to 20KHz

and requires a 2st order anti-aliasing filter at its input. Design and
simulate [3] this filter.
Answer: Let f-3dB = 20KHz, RS = 70Ω and RL = 7K Ω.

7 K + 70 .
20 KHz =
2π ( 7 K ) L 1C 1

Now, solving for L1 and C1

L1C1 = 6.388e-11, let C1 = 0.001uF,
L1 = 0.064H. Figure 8.4 shows the final circuit diagram
and Figure 8.5 shows the simulation.

Vin Rs 70 L1 64m Vout

C1 1n RL 7k

Figure 8.4. 2st Order Passive Filter Circuit Design

146 Chapter 8

Figure 8.5. 2st Order Passive Filter Simulation

As shown in Figure 8.5, the -3dB corner is approximately at 20KHz. The

amplitude peaking at this corner is determined by the source and load re-
sistors. This is a major disadvantage of a 2nd order passive filter since it is
not practical to control the load impedance. The input impedance of an
ADC or load impedance varies greatly with the silicon process and the
range is not specified in the data sheet. The data sheet typically only
shows a minimum input impedance specification. One method to mini-
mize the effect of the input impedance is selecting an ADC with high im-
pedance and adding an external load resistor with the resistance much
lower than the ADC input impedance, so that the parallel combination of
the two resistors will not vary widely over the silicon process.

8.1.3 Active Filter Design

For practical purposes, active filter designs in this section are focused only
on 1st and 2nd order Butterworth, as these are the most popular topologies
being implemented in audio, video and communication systems today. To
be able to design active filters, designers need to understand operational
amplifier or op amp and how to bias the op amp to get the maximum dy-
namic range.
Analog Filter Design 147

8.1.4 Operational Amplifier (op amp) Fundalmenta

An op amp circuit has 3 terminals, inverting input and non-inverting input
and output, as shown in Figure 8.6 and has the following electrical charac-
teristics;

• Very high impedance: For an ideal op amp, it is assumed infinite

input impedance. The input currents are very small and are negli-
gible.

• Very low output impedance: It is zero for an ideal op amp.

• Virtual ground: The voltages at the negative and positive inputs are
equal.

• Very high open loop gain: It is infinite for an ideal op amp.

U1 LM318
VN, Inverting Input
- VO, Output

+
+
VP, Non Inverting Input

Figure 8.6. Operational Amplifier

The relationships of the inputs and output of the op amp are

VD = VP – VN, (8.3)
where VD is the differential input, VP is the non-inverting input and
VN is the inverting input.
VO = aVD, where a is the open loop gain. (8.4)
Substitute Eq. (8.3) into Eq. (8.4),
VO = a(VP – VN). (8.5)
As shown in Eq. (8.5), the open loop op amp works like a comparator
where the output voltage is the difference of the input multiplied by the
open loop gain.
148 Chapter 8

Op amp typically being implemented in a linear circuit such as filters

works in a closed loop system where the output has a feedback to the input
to control the signal or AC gain. In this case, the inverting and non-
inverting inputs are equal; this is also known as virtual ground. The gain
equations are derived as follows.
A. Non-Inverting Amplifier

R2

I2

R1
- VO
I1 VN
+
+
VP
U1 LM318
+

VIN

Figure 8.7. Non-Inverting Amplifier

Applying Kirchhoff’s Current Law at node VN,

I2 = IN + I1, (8.6)
where IN is the negative input current and is equal to zero
since op amp has infinite input impedance.
V − V
I 2 = O N ,
R2

V N
I1 = ,
R1

Substitute I2 and I1 into Eq. (8.6),

V − V V N
O N
= . (8.7)
R2 R1

Due to virtual ground rule,

VN = VP and VP = VIN as shown in the circuit.
Analog Filter Design 149

Substitute VIN into Eq. (8.7) and solve for the gain,
VO/VIN.
VO R2
Gain = = + 1 . (8.8)
V IN R1

B. Inverting Amplifier

R2

I2

R1
- VO
I1 VN
+
+

+
VIN
U1 LM318

Figure 8.8. Inverting Amplifier

Applying Kirchhoff’s Current Law at node VN,

I2 + I1= IN, (8.9)
where IN is the negative input current and is equal to zero
since op amp has infinite input impedance.
V − V
I 2 = O N ,
R2

V − V
I1 = IN N ,
R1

Substitute I2 and I1 into Eq. (8.9),

V − V V − V
O N
+ IN N
= 0 . (8.10)
R2 R1

Due to virtual ground rule,

VN = VP = 0 as shown in the circuit.
150 Chapter 8

Replace VN with zero in Eq. (8.9) and solve for the gain,
VO/VIN.
VO R2
Gain = = − . (8.11)
V IN R1

8.1.4.1 Biasing Op Amps

Op amp can either be powered by a dual rail supply (±VDD) or a single
rail supply (+VDD). For the dual rail supply, the signal is centered around
zero volts and swings between the positive and negative rails as shown in
Figure 8.9. In this case, the op amp needs to be biased at zero volts as this
allows the maximum symmetrical swing.

Figure 8.9. Dual Rail Signal Swing

R2

-VDD

VIN R1
- VO
VN
+
+ U1 LM318

+VDD

Figure 8.10. Op Amp with Dual Supply Rails

Analog Filter Design 151

The rule is to always bias the positive terminal of the op amp as shown in
Figures 8.10 and 8.12 and the bias voltage must be set at the level where
the output has the maximum swing as shown in Figure 8.11.
For the op amp with a single rail power supply, the bias voltage must be
half of the power supply to guarantee maximum symmetrical swing as
demonstrated in Figure 8.11. The circuit shown in Figure 8.12 has a volt-
age divider formed by two equal resistors, R3 and R4, to generate a bias
voltage at half of the power supply rail, +VDD. For an ideal op amp, the
positive and negative input voltages are equal. But this is not the case in
the real word where there is always some small offset voltage between the
two inputs. This offset voltage is in the range of micro volts and can be an
issue for small signal detection and processing applications. In general,
this offset voltage is not a concern for video, audio and communication de-
signs, but it is good to keep it as low as possible. To minimize the offset
voltage, set the parallel combination of R3 and R4 equal to R2.

R3R4
R2 = R3//R4 = ,
R3 + R4
2
R3
and R3 = R4 so R2 = .
2 R3

Therefore, R3 = R4 = 2R2 (8.12)

This bias voltage can also be generated by a voltage regulator. The advan-
tage of the regulator is that it rejects the power supply noise. But the dis-
advantages are adding more cost and making the design and layout more
complicated.

Figure 8.11. Single Rail Signal Swing

152 Chapter 8

R2

V IN R1
- VO
VN
+
+ U1 LM318

R3 +VDD

+VDD/2

R4

Figure 8.12. Op Amp with Single Rail Supply

Again, only the positive terminal of the op amp needs to be biased at half
of the power supply. Due to virtual ground rule, the negative DC voltage
is at +VDD/2 and this also sets the output at +VDD/2. Now the whole cir-
cuit is DC balanced, which enables the signal to swing symmetrically
around +VDD/2.
Another important rule to remember is that if a point in the circuit is con-
nected to a DC voltage, the connection point becomes an AC or signal
ground. So for a resistor divider circuit in Figure 8.12, it is good to add a
bypass capacitor C1 in parallel with R4 to provide a good AC ground as in
Figure 8.13. This capacitor does not affect the signal path at all, since the
capacitor is on the positive input of the op amp which only has a DC bias
voltage.
R2

VIN R1
- VO
VN
+
+ U1 LM318

R3 +VDD

+VDD/2

R4
C1

Figure 8.13. Op Amp with Single Rail Supply

Analog Filter Design 153

For AC signals, C1 bypasses R4 and provides a very low impedance path to

ground. In this case, an RC filter is formed by R3 and C1 and the corner
frequency is
1
f − 3 dB = . (8.13)
2π R 3C 1

In Eq. (8.13), it is preferable to select C1 such that the -3dB corner fre-
quency is low enough to filter out the power supply noise. Now, let’s bias
a non-inverting amplifier circuit. The rule is the same as in the inverting
case where only the positive input of the op amp needs to be biased. Fig-
ure 8.14 shows the biasing circuit where R3 is connected to ground which
is in the middle +VDD and –VDD rails. Again, to minimize the offset
voltage, set R3 equal to the parallel combination of R1 and R2. So,

R1R 2
R3 = R1//R2 = , (8.14)
R1 + R 2

where R1 and R2 determine the AC gain of the circuit as shown in

Eq. (8.8).

R2

-VDD

R1
- VO
VN
VIN
+
+ U1 LM318
VP

R3
+VDD

Figure 8.14. Biasing Op Amp with Dual Rail Supply

154 Chapter 8

Similarly, Figure 8.15 shows a biasing circuit for the single rail supply
non-inverting amplifier. The resistors R3 and R4 bias the positive input at
half of the supply voltage. To minimize the offset voltage, set the parallel
combination of R3 and R4 equal to R2, since DC current does not flow
through R1 because of the DC blocking capacitor C3.
R3//R4 = R2,

R3R4
= R2. Since R3 = R4,
R3 + R4

R3 = R4 = 2R2, where R1 and R2 determine (8.15)

the gain of the non-inverting amplifier circuit.

R2

C3 R1
R4
- VO
VN
VIN
+
+ U1 LM318
VP
Rload
R3

VDD

Figure 8.15. Biasing Op Amp with Single Rail Supply

Analog Filter Design 155

8.1.5 DC and AC Coupled

The next step is to isolate the DC bias voltages of the op amp to ensure
that the input and output loadings do not change the DC voltages of the
circuit. This is done by adding a DC blocking capacitor in series with the
input and the output as shown in Figures 8.16. The DC blocking or AC-
coupling capacitor affects the frequency response of the circuit, so design-
ers must perform the analysis to select the capacitor value such that the
corner frequency is outside of the band of interest.

R2

C3 R1
R4
- C2 VO
C1 VN
VIN
+
+ U1 LM318
VP
Rload
R3

VDD

Figure 8.16. Non-Inverting AC-Coupled Input and Output

From the input VIN looking into the circuit, the C1 capacitor and resistors
R3 and R4 in Figure 8.17 form a highpass filter and the corner frequency is

1
f − 3 dB = ,
2π (R 2 // R 3 ) C 1

R2 + R3
f − 3 dB = . (8.16)
2π ( R 2 R 3 )C 1

The frequency response of the highpass filter is shown in Figure 8.17.

156 Chapter 8

Figure 8.17. Non-Inverting Highpass Filter Response

the role of this capacitor C3 is to block DC current from flowing through

the resistor R1 in order to keep all the DC voltages around the op amp
equal. For AC signal, C3 and R1 also form a highpass filter and its -3dB
corner is
1
f − 3 dB = . (8.17)
2 π R 1C 3

For the output AC-coupling capacitor C2, looking out from the op amp
output, the capacitor C2 and the resistor Rload form a highpass filter and its -
3dB corner frequency is
1
f − 3 dB = . (8.18)
2π R load C 2

Again, C2 must be selected to ensure that the corner frequency is lower

than the lowest frequency of the band of interest.

Design Example 8.3:

Design a non-inverting audio amplifier having the following specifica-
tions:
o Gain = 2
o Input -3dB corner frequency = 20Hz
o Output -3dB corner frequency = 20Hz
Analog Filter Design 157

o From the input to output, there is a -6dB attenuation at

20Hz. This is due to cascading -3dB input and -3dB output
stages.
o Input impedance is 10K ohms
o Output load impedance is 20K ohms
o AC-coupled input and output
o +12V single rail power supply
Simulate [3] the circuit to verify the results.
Solution:
Use the circuit diagram in Figure 8.16 and calculate all the component val-
ues.
VO R2
Gain = = + 1 = 2,
V IN R1

So, R2 = R1.
Let R2 = R1 = 20KΩ, reasonable value for audio design.
From Eq. (8.15),
R3 = R4 = 2R2= 2(20K) = 40KΩ.
The input impedance is R3 in parallel with R4 which is

( 40 K )( 40 K )
= 20KΩ.
40 K + 40 K

From Eq. (8.13), the -3dB corner is

R2 + R3
20 Hz = ,
2π ( R 2 R 3 )C 1

40 K + 40 K
C = = 0 . 4 uF
2 π ( 20 )( 40 K )( 40 K )
1
158 Chapter 8

Let C1 to be 0.47uF for 0.47uF being a standard capacitor value.

Calculate the output AC-coupling capacitor C2 using Eq. (8.18).
1
20 Hz = , where Rload is 20KΩ.
2π R load C 2

1
C = = 0 . 4 uF
2 π ( 20 )( 20 K )
2

Let C2 be 0.47uF for 0.47uF being a standard capacitor value.

Calculate the DC blocking capacitor C3 using Eq. (8.17).
1
20 Hz = ,
2 π R 1C 3

1
C = = 0 . 4 uF .
2 π ( 20 )( 20 K )
3

Let C3 be 0.47uF for 0.47uF being a standard capacitor value.

The final circuit is shown in Figure 8.18 and simulation in Figure 8.19.
R2 20k

C3 470n R1 20k
R4 40k
- C2 470n VO
C1 470n VN
VIN
+
+ U1 LM318
VP
Rload 20k
+

R3 40k
VG1

VDD 12

Figure 8.18. Final Circuit for Example 8.1

The simulation in Figure 8.19 verified that there is a -6dB attenuation at

20Hz; the overall circuit has a gain of 2 or +6dB and, at 20Hz, the gain is
+6dB minus 6dB attenuation. Therefore, the graph in Figure 8.19 shows a
0dB gain at 20Hz.
Analog Filter Design 159

Figure 8.19. Final Circuit Simulation For Example 8.1

Now for the inverting circuit shown in Figure 8.20, from the input VIN
looking into the circuit, the gain of the circuit is modified by the imped-
ance of the capacitor and is equal to R2 divided by R1 plus the impedance
of the capacitor C2.
VO R2
= − , where Z2 is the (8.19)
V IN R1 + Z 2
impedance of C2 and is equal to
1
and f is frequency.
2 π fC 2

Substitute Z2 into Eq. (8.19). The magnitude of the gain, ignoring the
negative sign as the sign only indicates the output is inverted, is
VO 2 π fC 2 R 2
= . (8.20)
V IN 2 π fC 2 R 1 + 1

For the corner frequency of

160 Chapter 8

1
f corner = , where C2 and R1 (8.21)
2 π R 1C 2
is the input impedance looking into the circuit. Substitute the corner fre-
quency into Eq. (8.20) and the magnitude of the gain at this frequency be-
comes
VO R2
= . (8.22)
V IN 2 R1

For R2 equal to R1, the gain at the corner frequency is

20log (0.5) = -6dB.
So, the AC-coupling capacitor at the input of the inverting amplifier forms
a highpass filter where the corner frequency shown in Eq. (8.21) is at -
6dB as demonstrated in Figure 8.21. As frequency gets higher and higher,
the gain in Eq. (8.20) is dominated by the resistors R2 and R1, which lead
to the same response as the inverting amplifier without the AC-coupling
capacitor. Again, designers need to select C2 so that the corner frequency
is lower than the lowest frequency of the signal.
C3 in Figure 8.20 is calculated the same way as in the non-inverting case.

R2

VIN C2 R1
- C3 VO
VN
+
+ U1 LM318

R5
R3 +VDD

+VDD/2

R4
C1

Figure 8.20. Inverting AC-Coupled Input and Output

Analog Filter Design 161

Figure 8.21. Inverting Highpass Filter Response

Design Example 8.4:

Design an inverting audio amplifier having the following specifications:
o Gain = -2
o Input -3dB corner frequency = 20Hz
o Output -3dB corner frequency = 20Hz
o From the input to output, there is a -9dB attenuation at
20Hz. This is due to cascading -6dB input and -3dB output
stages.
o Input impedance is greater than 10KΩ.
o Output load impedance is 20KΩ.
o AC-coupled input and output
o +12V single rail power supply
Simulate [3] the circuit to verify the results.
Solution:
Use the circuit diagram in Figure 8.20 and calculate all the component val-
ues.
162 Chapter 8

VO R2
Gain = = = 2 (neglect minus sign as it only indicates
V IN R1
the phase),
So, R2 =2R1.
Let R1 = 20K so R2 = 2(20K) = 40K.
From Eq. (8.12),
R3 = R4 = 2R2= 2(40K) = 80K.
The input impedance is equal to R1 which is 20K since the positive
and negative inputs of the op amp are equal, AC ground.
From Eq. (8.21), the input corner frequency (-6dB) is
1
20 Hz = ,
2 π R 1C 2

1
C = = 0 . 2 uF
2 π ( 20 )( 40 K )
2

Let C2 to be 0.22uF for 0.22uF being a standard capacitor value.

Calculate the output AC-coupling capacitor C3 using Eq. (8.18).
1
20 Hz = , where R5 (load) is 20K ohms.
2π R 5C 3

1
C = = 0 . 4 uF
2 π ( 20 )( 20 K )
3

Let C3 be 0.47uF for 0.47uF being a standard capacitor value.

Calculate the bypass capacitor C1 using Eq. (8.13).
1
f − 3 dB = = 20Hz, this is the filter corner for the
2π R 3C 1
bias voltage.
Analog Filter Design 163

1
C = = 0 . 1 uF .
2 π ( 20 )( 80 K )
1

The final circuit is shown in Figure 8.22 and simulation in Figure

8.23.
R2 40k

VIN C2 220n R1 20k

- C3 470n VO
VN
+
+ U1 LM318
+

VG1
R5 20k
R3 80k

V1 12

C1 100n
R4 80k

Figure 8.22. Final Circuit for Example 8.2

The simulation in Figure 8.23 verified that there is a -9dB attenuation at

20Hz; the overall circuit has a gain of 2 or +6dB and, at 20Hz, the gain is
+6dB minus 9dB attenuation. Therefore, the graph in Figure 8.23 shows
roughly a -3dB gain at 20Hz.

Figure 8.23. Final Circuit Simulation For Example 8.2

164 Chapter 8

8.1.6 First Order Active Filter Design

Lets assume that the active filters are running on a single rail power sup-
ply. This is more common in today’s electronics as it is more expensive to
implement a design powered by a dual rail power supply.
There are two topologies for the 1st order lowpass filter design, inverting
lowpass and non-inverting lowpass. For the non-inverting topology, the
gain has to be greater than 1 as shown in the previous section, and, for the
inverting topology, the output is 180 degrees phase shifted from the input.
To create an inverting lowpass filter, simply take the circuit in Figure 8.22
and add a capacitor in parallel with the resistor R2. The new circuit shown
in Figure 8.24 has the upper -3dB corner of
1
f − 3 dB = . (8.23)
2π R 2C 4

All other design parameters and methodologies are the same as those
shown in the previous op amp design sections.

C4

R2

VIN C2 R1
- C3 VO
VN
+
+ U1 LM318
+

VG1
R5
R3

V1 12

C1
R4

Figure 8.24. 1st Order Active Lowpass Filter

Design Example 8.5:

Design a 1st order inverting audio filter having the same specifications as
in Design Example 8.4 but adding an upper frequency limitation at 20KHz.
Simulate the circuit to verify the results.
Analog Filter Design 165

Solution:
Use the circuit in Figure 8.24. From Eq. (8.23), the upper -3dB frequency
is

1
20 KHz = .
2π R 2C 4
From Design Example 8.2, R2 is 40K ohms. So,

1
C4 = = 200 pF .
2 π ( 40 K )( 20 KHz )
The final circuit and simulation are shown in Figure 8.25 and Figure 8.26
respectively. It is verified that the circuit frequency response has an upper
frequency limitation at 20KHz. This is the 1st order filter circuit with the
-3dB frequency at 20KHz and the slope decaying at 20dB per decade.
As mentioned earlier, the output of the inverting lowpass filter has a 180
degrees phase-shift as compared to the input. Figure 8.27 shows the simu-
lated gain of 2 and phase relationship of the input and output waveforms.

C4 200p

R2 40k

VIN C2 220n R1 20k

- C3 470n VO
VN
+
+ U1 LM318
+

VG1
R5 20k
R3 80k

V1 12

C1 100n
R4 80k

Figure 8.25. Final 1st Order Active Lowpass Circuit

166 Chapter 8

Figure 8.26. Final 1st Order Active Filter Simulation

Figure 8.27. Input Versus Output Waveforms

Now to realize the non-inverting 1st order lowpass filter circuit, take the
non-inverting amplifier circuit and add a capacitor in parallel to R2 to limit
the op amp bandwidth and an RC filter at the positive input of the op amp
as shown in Figure 8.28. Op amp typically has a high gain bandwidth
product and can go unstable if the bandwidth is not limited to the operating
frequency range. Doing stability analysis is beyond the scope of this book
but designers can learn more in [2]. This new circuit is shown in Figure
8.28 and the -3dB corner is dominated by the resistor R5 and the capacitor
C5 ,

1
f − 3 dB = . (8.24)
2π R 5C 5
Analog Filter Design 167

With C4 connected in parallel with resistor R2, the op amp bandwidth is

limited to the -3dB corner set by this RC filter. The corner frequency is

1
f − 3 dB = . (8.25)
2π R 2C 4

Also, in Figure 8.28, the filter resistor R5 needs to be one tenth of the par-
allel combination of the resistors R3 and R4. This is to minimize the ef-
fects of the voltage divider formed by R5 and the parallel combination of
R3 and R4.

C4

R2

C3 R1
R4
- C2 VO
C1 R5 VN
VIN
+
+ U1 LM318
VP
Rload
R3
+

VG1 C5

VDD 12

Figure 8.28. Non-Inverting 1st Order Lowpass

Design Example 8.6:

Design a 1st order non-inverting audio filter having the same specifications
as in Design Example 8.3 but adding an upper frequency limitation at
20KHz. Simulate the circuit to verify the results.
Solution:
Use the circuit in Figure 8.28. From Eq. (8.24), the upper -3dB frequency
is

1
20 KHz = .
2π R 5C 5
168 Chapter 8

From Design Example 8.3, R3 = R4 = 40K ohms. So,

1 1 R3R4
R5 = ( R 3 // R 4 ) = = 2K ,
10 10 ( R 3 + R 4 )

1
C = = 0 . 00398 uF .
2 π ( 20 K )( 2 KHz
5
)

Now, since the maximum upper frequency is 20KHz, lets limit the op amp
at 40KHz which is two times the signal bandwidth. This provides plenty
of bandwidth margins.
From Eq. (8.25),

1
40 KHz = ,
2π R 2C 4

In Design Example 8.3, R2 = 20K so

1
C = = 200 pF .
2 π ( 20 K )( 40 KHz )
4

The final circuit and simulation are shown in Figure 8.29 and Figure 8.30
respectively. It is verified that the circuit frequency response has an upper
frequency limitation at 20KHz. This is the 1st order non-inverting filter
circuit with the -3dB frequency of 20KHz and the slope of -20dB/decade.
Figure 8.31 shows the simulated gain of 2 and phase relationship of the in-
put and output waveforms. The simulation results are correct and corre-
lated with the calculations very well.
C4 200p

R2 20k

C3 470n R1 20k
R4 40k
- C2 470n VO
C1 470n R5 2k VN
VIN
+
+ U1 LM318
VP
Rload 20k
+

R3 40k
VG1 C5 3.98n

VDD 12

Figure 8.29. Final Non-Inverting 1st Order Lowpass

Analog Filter Design 169

Figure 8.30. Final Non-Inverting 1st Order Response

Figure 8.31. Non-Inverting Input Versus Output Waveforms

8.1.7 Second Order Active Filter Design

The best and the most popular topology for a 2nd order lowpass design is
Sallen-Key circuit [4]. The three different Sallen-Key circuits are unity
gain, gain of 2 and gain of higher than 2. The higher the gain the more un-
stable the circuit becomes, so it is best to keep the overall gain of 2 or less.
If more gain is required for the design, then use another op amp as a gain
stage to boost the overall gain. This guarantees good stability.
170 Chapter 8

Sallen-Key Circuit with Gain = 1:

Figure 8.32 shows a 2nd order lowpass filter with a gain of 1 [4]. The resis-
tor and capacitor values are normalized to 1 and Q where Q determines the
gain peaking or GP at the corner frequency as shown in Figure 8.33. The
gain peaking or GP equation is
2
2Q
GP = 20 log 10 , for Q>0.707. (8.26)
4Q 2
−1

There is no gain peaking for Q = 0.707.

C1

2Q
- VO
VIN R1 R2
+
+ U1 LM318
1 1
+

VIN C2 1/2Q

Figure 8.32. Sallen-Key Circuit with Gain =1

Figure 8.33. Sallen-Key Response and GP

Analog Filter Design 171

To calculate the values of the capacitors and resistors, use the following
equations.
Rnew = KmRold , where Km is the new resistance (8.27)
and Rold is the normalized resistance shown in Figure 8.32.

1
Cnew = C old , where Kf is the (8.28)
K fK m
corner frequency in Rad/s, K
f = 2πf; f is the corner fre-
quency in Hertz.

Sallen-Key Circuit with Gain = 2:

Since R3 and R4 are equal in Figure 8.34 [4], the overall circuit gain is 1
plus the ratio of resistor R4 over resistor R3 or 2 as shown in the non-
inverting amplifier section. All the values in the circuit are calculated by
the same methods in the Sallen-Key Circuit with Gain = 1 section.

C1

R4
1
1
1
- VO
VIN R1 R2 R3
+
+ U1 LM318
1 Q
+

VIN C2 1/Q

Figure 8.34. Sallen-Key Circuit with Gain = 2

Sallen-Key Circuit with Gain = 3-1/Q:

The overall gain in Figure 8.35 [4] is

R4 2 −1/Q 1
1+ = 1+ = 3 − . (8.28)
R3 1 Q
172 Chapter 8

All the values in the circuit are calculated by the same methods demon-
strated in the Sallen-Key Circuit with Gain = 1 section.

C1

R4
1
2-1/Q
1
- VO
VIN R1 R2 R3
+
+ U1 LM318
1 1
+

VIN C2 1

Figure 8.35. Sallen-Key Circuit with Gain = 3-1/Q

Design Example 8.7:

Design a non-inverting 2nd order Sallen-Key lowpass filter having the fol-
lowing specifications:
o Gain = 2
o Corner frequency = 20KHz
o Gain peaking = 5dB
o Output load impedance = 20K ohms
o +12V single rail power supply
o Use the same input and output coupling capacitors as in
Design Example 8.3.
Simulate [3] the circuit to verify the results.
Solution:
For Gain =2, use the circuit in Figure 8.34.
For corner frequency = 20KHz,
Kf = 2πf = 2π(20KHz) = 125663.7 rads/s.
Analog Filter Design 173

Let Km = 2x104.
For gain peaking = 4dB,
2
2Q
4 dB = 20 log 10 ,
4Q 2
−1

Now, solve for Q and Q is 1.5.

Rnew = KmRold = 2x104 = R1 = R3 = R4.
R2 old = Q = 1.5,
R2 = KmRold = 2x104 (1.5) = 30K.
C1 old = 1,

1 1
C1 new = C old =
K fK m (125663.7 )(2x104 )

= 398pF.
C2 old = 1/Q = 0.667,

1 0.667
C2 new = C old =
K fK m (125663.7 )(2x104 )

= 265pF.
The final circuit is shown in Figure 8.36 where C3, C5 and C4 came from
the Design Example 8.3. R6 and R7 form a voltage divider to bias the op
amp at half of the power supply voltage. The parallel combination of the
resistors R6 and R7 is selected to be 10 times larger than the total resistance
of R1 and R2. This guarantees that the bias resistors will not affect the
overall gain.
The simulations in Figures 8.36 and 8.37 show the following results:
o Gain peaking = 4dB
o Corner frequency = 20KHz
o Slope = -40dB/decade, 2nd order lowpass filter
174 Chapter 8

o Passband signal gain = 1.85 instead of 2. This is due to the bias re-
sistors R6 and R7 loading the signal down. Increasing the total R6
and R7 resistance reduces the effect but will cause problems with
not having adequate bias current required for the op amp. Another
option is reducing the total resistance of R1 and R2. This is a better
option but it requires a total redesign of the filter.

C1 398p

R4 20k

C5 470n
- C4 470n VO
VIN C3 470n R1 20k R2 30k R3 20k
+
+ U1 LM318

C2 265p R5 20k
+

VIN

R6 1M

V1 12
R7 1M

Figure 8.36. Final Sallen-Key Circuit with Gain = 2

Figure 8.37. Final Sallen-Key Circuit Simulation

Analog Filter Design 175

Figure 8.38. Final Sallen-Key Input Versus Output

8.2 SUMMARY
As demonstrated throughout this chapter, filter designs are very compli-
cated and require to do thorough system analysis using a circuit simulator
such as [3]. A filter topology is selected base on the following criteria:

• Is the gain greater than 1? If yes, then an active filter is needed. If

no, then either an active or a passive filter can be selected.

• How much attenuation is needed to prevent aliasing for the ADC

input and to reject the sampling noise for the DAC output? This
determines 1st, 2nd or higher order filter topology.

• Is maintaining the input and output phase important? If yes, then

only a non-inverting filter can be used.

• For active filters, is the circuit running on a single or dual rail

power supply? Refer to the DC and AC Couple and Biasing Op
Amp sections, and bias the circuit to allow for a maximum sym-
metrical swing.

• For passive filters, is inductor shielding required? Inductors tend to

radiate high frequency noise, so shielding may be required to con-
tain the radiation.
In summary, DSP systems require analog filters to limit the signal band-
width before sampling, to reconstruct the analog signal from the DAC out-
put and to eliminate analog noise modulated on the signal. These filters
are very critical, and proper design techniques outlined in this chapter
should be followed to achieve the performance goals.
176 Chapter 8

REFERENCES

[1] Texas Instruments Inc (1995) Understanding Data Converters, Mixed-

Signal Products, SLAA013.

[2] Franco Sergio (2002) Design with Operational Amplifiers and Analog
Integrated Circuits. McGraw-Hill, New York.

[3] Texas Instruments Inc (2008) Spice-Based Analog Simulation Pro-

gram. http://focus.ti.com/docs/toolsw/folders/print/tina-ti.html.

[4] Valkenburg M.E. Van (1982) Analog Filter Design. Holt, Rinehart and
Winston, New York.
 Memory Sub-System
Design Considerations 9

The most critical bus in a DSP system today is the memory bus where a
large amount of ultra high speed data is being transferred from the DSP to
the physical memory devices and vice versa. The data on this bus are
switching very fast. The rise and fall times of the data, memory clocks,
control signals are approaching sub-nanosecond range. These fast tran-
sients generate noise, radiation, power supply droops, signal integrity, and
memory timing issues. This chapter covers memory sub-system design
techniques to minimize the effects of the high speed data propagating.

9.1. DDR MEMORY OVERVIEW

It is assumed in the chapter that the memory is DDR memory, since DDR
design presents many challenges as DDR transmits and receives data at
both edges of the memory clock. These include a noise sensitive analog
circuit called Delay Locked Loop or DLL. In this case, the internal and
external noise can cause excessive DLL jitter which leads to memory fail-
ures.
The three different types of DDR memories shown in Table 1 are DDR1,
DDR2 and Mobile DDR or mDDR.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_9, 177
© Springer Science+Business Media, LLC 2010
178 Chapter 9

Table 9.1. DDR SDRAM Overview

Parameter: DDR1: DDR2: mDDR:

Clock Speed Up to 200MHz Up to 400MHz Up to 200MHz

Power Con- High Moderate, dy- Low (popular in

sumption namic power is mobile devices)
40% lower

Differential Yes Yes Yes

Clock

Differential No Yes (optional) No

Strobe, DQS

External VREF Yes, 0.49xVdd Yes, 0.49xVdd No

Min, 0.51xVdd Min, 0.51xVdd
Max Max

DLL for DQ Yes Yes No

and DQS
Alignment

Figure 9.1 shows the basic DSP and DDR interface and the signal defini-
tions are in Table 2.

Figure 9.1. DDR Interface

Memory Sub-System Design Considerations 179

Table 9.2. DDR Signal Definition

CLK DDR Clock

CLK# Inverted DDR Clock

DQS Data Strobe: A bi-directional signal, output from DSP

for write and input from memory for read.

DQM Data Mask: Input data is masked when DQM is high

along with that input data during a Write access.

WE# Active Low Write Enable

CAS#, RAS# Active Low Column Address and Row Address

Strobes

VREF Reference Voltage: Half the supply voltage.

ADDRESS Address Bus: Provide the Row Address for

ACTIVATE commands and the Column Address for
READ/WRITE commands.

DATA [32:0] 32-bit Bi-directional data bus

9.1.1. DDR Write Cycle

Figure 9.2 shows a memory Write Cycle where D0 is the least significant
data bit and DQS is the Data Strobe. The data transfers happen at both
edges of DQS and DQS is typically 90 degree phase-shift from the first
data burst. Figure 9.3 shows an oscilloscope capture of the actual memory
bus.
180 Chapter 9

Phase shift for write

DQS

1 0 1 0 1 0 1 0
D0

Data transfers from memory at rising and falling edges

Figure 9.2. DDR Write Cycle

Figure 9.3. DDR Write Cycle Scope Captured

Memory Sub-System Design Considerations 181

9.1.2. DDR Read Cycle

Figure 9.4 shows a memory Read Cycle where D0 is the least significant
data bit and DQS is the Data Strobe. The data transfers happen at both
edges of DQS and DQS is synchronized with D0. In the Read Cycle,
memory device outputs DQS and drives the data bus synchronously.

DQS

1 0 1 0 1 0 1 0
D0

Data transfers from memory at rising and falling edges

Figure 9.4. DDR Read Cycle

9.2. DDR MEMORY SIGNAL INTEGRITY

As covered in Chapter 2 and 3, transmission line effects and crosstalk are
results of bad signal integrity design. Since memory timing is so critical,
the excessive overshoots, undershoots and glitches on the signal can false
trigger and cause memory read and write failures. The worst part is that
the memory controller such as DDR controller relies on a noise sensitive
analog circuit such as DLL to synchronize and delay the strobes to read the
incoming data from external memory devices.
Simulated Figures 9.5, 9.6 and 9.7 [2] demonstrate good, bad and ugly sig-
nal integrity designs respectively. The bad case in Figure 9.6 has a glitch
right a the switching threshold which may cause false clocking; the system
may see this glitch as a high and low transition just like a clock input and
respond to it.
182 Chapter 9

For the ugly case in Figure 9.7, the overshoots and undershoots are so ex-
cessive that the peak of the overshoot crosses over the minimum input high
voltage, Vih, and causes false clocking. Also, these overshoots and under-
shoots generate a lot of noise and radiation. The rule-of-thumb is to fine
tune the signal until all the overshoots are much lower than the threshold
voltage, Vih.

Figure 9.5. Good DDR Clock Waveform

Figure 9.6. Bad DDR Clock Waveform

Memory Sub-System Design Considerations 183

Figure 9.7. DDR Clock with Excessive Overshoots

9.3. DDR MEMORY SYSTEM DESIGN EXAMPLE

The following design rules for good memory signal integrity are:

• Apply good decoupling techniques as shown in Chapter 5. It is

highly recommended to have one high frequency capacitor (0.01uF
to 0.22uF) per DDR power pin and one bulk capacitor (10uF) for
the DDR region. These decoupling techniques are also required for
the memory devices in the design.

• Add termination resistors on the data bus and the control signals.
Where to place the resistors on the bi-directional bus depends on
which device has higher drive strength. Place the resistors nearby
the device with the higher drive strength. For example, DDR
memory devices typically have strong buffers to allow for non-
embedded designs such as PC. In this case, always put the termi-
nation resistors right by the memory devices. Ideally, add termina-
tion resistors at the output of the device driving the bi-directional
bus. See the design examples in Figures 9.8 [3] and 9.9.
184 Chapter 9

• Isolate and decouple the DLL power supply and the VREF voltage
pins. For the DLL, follow the rules described in the PLL chapter,
Chapter 6. To generate VREF, use a resistor divider and divide the
memory power supply voltage, VDD, required for both DSP and
memory devices. See the design example in Figure 9.9 [1].

Figure 9.8. DDR Design Example at the DSP

Memory Sub-System Design Considerations 185

VREF
GENERATOR

TERMINATION
RESISTORS ON
THE DATA BUS
NEAR DDR
MEMORY

TERMINATION RESISTORS
DQS’s NEAR DDR MEMORY

Figure 9.9. DDR Design Example at the DDR Memory

186 Chapter 9

REFERENCES

[1] Micron (2009) DDR2 SDRAM 1Gb: x4, x8, x16 DDR SDRAM.
http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf.

[2] Mentor Graphics (2004) Hyperlynx Signal Integrity Simulation soft-

ware. http://www.mentor.com/products/pcb-system-design/circuit-
simulation/hyperlynx-signal-integrity/.

[3] Texas Instruments Inc (2007) TMS320DM6467 Digital Media Sys-

tem-on-Chip, SPRS403F.
 Printed Circuit
Board (PCB) Layout 10

Once all the circuits have been designed, the next step is board layout. This
is a very critical step in the development process because the effectiveness
of the filtering circuits depends on where the components are placed rela-
tive to the DSP pins. Also, the board layout has a big effect on noise,
crosstalk and transmission line effects so optimizing the layout can mini-
mize these effects. This chapter covers the printed circuit board stackup
and layout techniques for low noise and EMI.

10.1. PRINTED CIRCUIT BOARD (PCB) STACKUP

First, designers need to determine the minimum number of PCB layers and
then configure the board stackup. Here are some general guidelines:

• Perform layout experiments and refer to the DSP reference de-

sign package to find the minimum number of layers required
to route the signals out from the DSP. Typically, DDR layout
guidelines dictate the number of PCB layers to allow for es-
caping all the signals out from the DSP.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_10, 187
© Springer Science+Business Media, LLC 2010
188 Chapter 10

• Consider the need for high-speed signals to be shielded be-

tween the ground and power planes.

• Are there buses, such as USB, Ethernet, and RapidIO, that re-
quire a tight differential impedance specification? If so, de-
signers need to follow the industry guidelines to control the
differential impedance of these buses.

• Does the PCB manufacture require a certain trace width and

spacing? This determines whether or not a trace can be routed
between the balls of a small pitch BGA package. For good
signal integrity with minimum skin effect losses, keep the
trace width between 4 mils and 12 mils. A common choice is a
5-mil trace and 5-mil spacing.

• Is one power plane and one ground plane sufficient?

• Does the DSP system require a controlled impedance board?

This is more expensive but allows the board to be optimized
from a signal integrity standpoint.
Two PCB stackup topologies are commonly used, adjacent power and non-
adjacent power and ground planes. Figure 10.1 [1] shows what can or can-
not be done with each layer when the design is implemented on a 6 layer
PCB for the adjacent power and ground topology.

Figure 10.1. Adjacent Power and Ground Board Stackup

Printed Circuit Board (PCB) Layout 189

The parallel capacitance, Cpp, between the power and ground planes is
calculated as
ε rA
C pp = k , (10.1)
d
where k is 0.2249 inches or 0.884cm,
εr, dielectric constant = 4.1 to 4.7 for FR4 type PCB,
A is area of the power and ground planes, and
d is the distance between the power and ground planes.
When using this topology, designers need to consider these points:

• As shown in the equation for Cpp, the distance, d, between the

power and ground planes determine the board capacitance.
Reducing the distance increases the capacitance and also re-
duces high frequency impedance. The limiting factor is how
closely the layers can be packed together while still maintain-
ing the quality and reliability of the design. Refer to the speci-
fications from PCB manufactures to understand the minimum
requirements between the layers.

• Route the high-speed signals on the planes next to the power

and ground planes. If possible, route all the high speed signals
next to the ground plane. If not, then it is also acceptable to
route them next to the power plane.

• In Figure 10.1, the best routing layer is Layer 2 because it is

next to the ground plane. This provides optimal current return
paths which helps reduce radiation. This is why the adjacent
power and ground topology is recommended for DSP systems
operating at very high frequency.

• The adjacent power and ground topology are not useable for
DSP systems that require many layers to route the signals out
from the DSP and interface with other circuits.
Figure 10.2 [1] shows a typical PCB stackup for the non-adjacent power
and ground topology. The power and ground planes are placed in Layer 5
and Layer 2 respectively. Layer 3 is best for routing high-speed traces
while Layer 1, Layer 4 and Layer 6 are acceptable. As shown in the figure,
190 Chapter 10

each of the routing layers is next to either a ground or power plane. Layer
3 is best because it is not only next to a ground plane but is also guarded
by a power plane below it. This scheme is best for difficult-to-route DSP
systems that don’t operate at very high frequencies. One thing to keep in
mind is that board capacitance becomes important for systems operating
above 300MHz [2].

Figure 10.2. Non-Adjacent Power and Ground Board Stackup

Here are rules for doing non-adjacent board stackup design:

• For non-adjacent topology, the board capacitance, as shown in

capacitance equation Cpp, is low and the board impedance is
high between the power and ground planes. This is the oppo-
site of what is needed for systems to have low noise and low
EMI.

• This topology requires more high frequency decoupling ca-

pacitors to compensate for the board characteristics.

10.2. MICROSTRIP AND STRIPLINE

Table 1 shows the advantages and disadvantages of the two main signal
routing technologies, Microstrip shown in Figure 10.3 where H is the
height, W is the width of the signal trace, W1 is the width including the
outside edge, T is the thickness of the trace and εr is the dielectric constant.
The Stripline is shown in Figure 10.4.
Printed Circuit Board (PCB) Layout 191

Figure 10.3. Microstrip Topology

Figure 10.4. Stripline Topology

Tabl le 1. Microstrip and Stripline Comparison

Microstrip Topology Stripline Topology

1. Number of No special require- Requires signals to route

PCB layers ments between the ground planes
so it is more expensive

2. Routability Easy and can route Difficult to route with lim-

with minimum num- ited number of PCB layers.
ber of vias Also, vias are required
which can cause signal
quality degradation.

3. Signal Quality Acceptable Very good

4. EMI Acceptable but an im- Very good because high-

age plane is needed speed signals are shielded
just below the routing between the planes.
layer.
192 Chapter 10

Designers generally make compromises by using both topologies where

some of the critical signals are routed between the ground and power
planes.

10.3. IMAGE PLANE

Image plane concept demonstrated in [3] is defined as having a ground
plane right underneath the signal routing layer. This provides a shielding
layer which greatly reduces the radiated emissions as shown in Figure 10.6
The system actually failed EMI initially when there was no image plane
inserted in the PCB stackup as shown in Figure 10.5.

Figure 10.5. PCB Radiated Emissions without Image Plane

Printed Circuit Board (PCB) Layout 193

Figure 10.6. PCB Radiated Emissions With Image Plane

10.4. SUMMARY
PCB routing and board stackup are major contributors to EMI so designers
need to apply best practices to reduce radiated emissions. An example is
the use of an Image Plane, a ground plane located next to the routing layer
that provides low inductance current return paths for high-speed signals.
An Image plane helps reduce the current loop areas and minimizes the po-
tential differences on the ground plane. Experiments conducted in [3]
compare the EMI for PCBs with and without an image plane. They dem-
onstrate that a PCB with an image plane shows around 15dB reduction in
EMI across the frequency spectrum.
194 Chapter 10

REFERENCES

[1] Montrose Mark (2000) Printed Circuit Board Design Techniques for
EMC Compliance. The Institute of Electrical and Electronics Engi-
neers, New York.

[2] Texas Instruments Inc (2000) Design Guidelines: Integrated Circuit

Design For Reduced EMI. Application Note.

[3] Montrose Mark (1996) Analysis on the Effectiveness of Image Planes

within a Printed Circuit Board. The Institute of Electrical and Elec-
tronics Engineers.
 Electromagnetic
Interference (EMI) 11

Radiated emissions in high-speed DSP systems are caused by fast-

switching currents and voltages propagating through printed circuit board
traces. As DSP speed increases, printed circuit board traces are becoming
more effective antennas, and these antennas are radiating unwanted ener-
gies that interfere with other circuitry and with other systems located
nearby. This section outlines different ways to design for low EMI and
find the root cause of EMI problems when they occur. It only covers the
electrical design aspects of EMI even though shielding, cabling and other
mechanical fixes can also be used to help reduce the emissions below the
maximum allowable limits. In general, mechanical solutions are very ex-
pensive for high volume designs. Even worse, the mechanical solutions
may have to change when the DSP speed increases.

11.1. FCC PART 15B OVERVIEW

To prevent systems from interfering with each other, the FCC sets maxi-
mum limits known as FCC Part 15 A for commercial products and FCC
Part 15 B [1] for consumer devices as shown in Figure 11.1.

T.T. Tran, High-Speed DSP and Analog System Design, DOI 10.1007/978-1-4419-6309-3_11, 195
© Springer Science+Business Media, LLC 2010
196 Chapter 11

Measuring Distance = 10 Meters

55
Field Strength (dBuV/m)

50
Class A
48
45
43
Class B
40
37
35
34 960
216
30
88
25

100 300 1000 5000

Frequency in MHz

Figure 11.1. FCC Radiated Emissions Limits

The following lists some of the most common sources of EMI in high
speed DSPs:

• Fast switching digital signals such as clocks, memory buses,

PWM (switching power supplies)

• Large current return loops

• Not having an adequate power supply decoupling scheme

around large DSPs

• Transmission lines

• Printed circuit board layout and stackup, lack of power and

ground planes

• Unintentional circuit oscillations

Electromagnetic Interference (EMI) 197

11.2. EMI FUNDAMENTALS

The five main sources of radiation are digital signals propagating on trac-
es, current return loop areas, inadequate power supply filtering or decoup-
ling, transmission line effects, lack of power and ground planes.
Radiation is classified in two modes, differential mode radiation and com-
mon mode radiation. It is important for engineers to understand the differ-
ences between the two modes in order to develop an effective scheme to
mitigate the problem. In DSP systems, all electrical currents propagate
from the source to the load and return back to the original source. This me-
chanism generates a current loop which creates differential mode radiation
as shown in Figure 11.2 [4].

High-Speed Current, I
DSP

Current, I
SDRAM

Figure 11.2. Differential Mode Radiation

Differential mode radiation is directly related to the length of the signal

trace, the driving current and the operating frequency. The electric field
caused by differential mode radiation is

E = 87.6 x10−16 [ f 2 AI ] , (11.1)

where f is the operating frequency; A is the current loop area created by

the trace length and the board stackup; and, I is the driving source current.
Common mode radiation is generated by a differential voltage between
two points on a ground plane. It typically radiates from cables connected to
198 Chapter 11

the board or chassis. In theory, 100% of the source current returns back to
the source but a small portion of the current spreads over the entire plane
before finding its way back to the source. This current creates an imbal-
ance in the ground potential and causes common mode radiation as shown
in Figure 11.3 [4].

Cable
System
ground
plane Vgnd

Figure 11.3. Common Mode Radiation

The electric field generated by common radiation is directly related to the

frequency propagating on the cable, the length of the cable, and the current
driving the cable. Here is an equation to calculate the common mode radia-
tion in an open field.

E = 4.2 x10 −7 [ fLI ] , (11.2)

where f is the frequency; L is the length of the cable in meter,; and, I is

the source current.
The relationship between the common mode and differential mode radia-
tion for a given signal is shown in Figure 11.4 [4]. In general, the differen-
tial mode dominates at a higher frequency spectrum while the common
mode radiates more energy around the operating frequency.
Electromagnetic Interference (EMI) 199

dB C om m on M ode

D if f e r e n tia l M o d e
Emission
e
ad
ec
/D
dB 20
20 dB
/D
ec
ad
e

fo fre q u e n c y f

1
f = , w h e r e T r is r is e tim e
π Tr

Figure 11.4. Relationship Between Common and

Differential Mode Radiation

11.3. DIGITAL SIGNALS

A digital or squarewave signal consists of a series of sine and cosine sig-
nals superimposed on one another. In the frequency domain, a squarewave
consists of many higher frequency harmonics, and the harmonic radiated
energy directly depends on the risetime and the pulsewidth of the signal as
shown in Figure 11.5.

Tr Pw

T
1
20dB/decade
π Pw 1
plitude

π T r
Am

40dB/decade

1/T (3) (5)

Figure 11.5. Frequency Spectrum of a Squarewave

200 Chapter 11

In Figure 11.5 assuming a 50% duty cycle signal where only odd harmon-
ics are present, the amplitudes of the harmonics decay slowly as frequency
increases. The first pole frequency is at

1
f −3dB = , (11.3)
πPW
and a second pole is at

1
f − 3dB = ⋅ (11.4)
πTr
Pw and Tr are the width and the risetime of the signal respectively. There-
fore, increasing the risetime increases attenuation of the harmonics which
leads to lower radiation. This method is not always practical because the
slower risetime reduces the timing margin and may violate electrical re-
quirements such as setup and hold times.
The best technique to minimize EMI generated by digital signals is keep-
ing the high-speed signal traces as short as possible. It is a good practice
for engineers to go through a design and analyze the traces to see if they
are effective antennas or not. A good rule-of-thumb is keeping the length
of the trace less than the wavelength (λ) divided by 20. Here is the equa-
tion.

λ c
max_ trace _ length = = , (11.5)
20 20 f

where C is a speed of light, 3x108 m/s, and f is the frequency.

For example, a 1.18 inch trace becomes an effective radiator when it is be-
ing driven by a 500MHz signal. The 500MHz signal is a 5th harmonic of a
100MHz clock, a very common frequency in DSP systems today.
Electromagnetic Interference (EMI) 201

11.4. CURRENT LOOPS

Current loops are the dominant sources of EMI, so it is very important for
designers to understand high-speed and low-speed current return paths and
optimize the design to reduce the loop areas. Figure 11.6 shows two pos-
sible current return paths from points A and B; for high speed current
(>10MHz), the return is right underneath the signal and, for low speed cur-
rent, the return is the shortest path back to the source.

High speed current A trace routed

return (green) from A (source) to B

A B

Load
Signal Low speed current
return (purple)

Figure 11.6. High Speed and Low Speed Current Loops

As shown in Figure 11.7 [6], current return creates a loop area that is di-
rectly related to the radiated electric field, so reducing the loop area lowers
radiation. Skin effect modifies the current distribution within a conductor
and increases resistance, so the high speed current return is right under-
neath the signal. Skin effect is negligible at lower frequencies but increases
as frequency rises. For a typical conductor used in DSP systems, a 10MHz
or higher trace is considered to be a high-speed signal. Providing a con-
tinuous ground plane right underneath a high-speed signal is the most ef-
fective way to achieve the lowest current loop area.
202 Chapter 11

Figure 11.7. High Speed Current Return on Continuous

Ground Plane

If the ground plane is not continuous underneath the high speed signal, all
crosstalk, reflections, and EMI will increase due to the impedance mis-
match and larger current loop return area as shown in Figure 11.8 [6].

Figure 11.8. High Speed Current Return on a

Discontinuous Ground Plane

11.5. POWER SUPPLY

The power supply is another major source of EMI because:

• The power supply is common to many high-speed sections in

a design. RF signals may propagate from one section to an-
other generating excessive EMI.
Electromagnetic Interference (EMI) 203

• A switching power supply generates fast current transients

with a large amount of radiated energies. A 1MHz switching
power supply can radiate enough energy to fail EMI testing at
the 100MHz frequency range.

• Inadequate power supply decoupling may lead to excessive

voltage transients on the power supply planes and traces.

• The power supply board layout can be a root cause of oscilla-

tions.

U19A U19A
14

14
1 1
+ 3 + 100nF 3
2 2

- -
7

7
14081/SO 14081/SO

I I

Figure 11.9. Power Supply Decoupling Reduces Current

Loop Area

As shown in Figure 11.9, decoupling the power supply reduces transients

and provides a smaller current loop area. If the power supply trace in Fig-
ure 11.9 is long and has no decoupling capacitor, the parasitic inductance
is large and requires some time to charge up. This delay is a root cause of
the power supply droop problem. Power supply droop occurs when the
output buffer switches at a fast rate, but is starved for the current needed to
drive the load, since the parasitic inductance between the power supply
and the DSP becomes an open circuit.
Example 1:
- A DSP BGA (ball grid array) package has a trace inductance of
1.44nH.
- This output is driving a 3” trace with 1nS risetime signal.
204 Chapter 11

- This trace is being routed on a typical FR4 printed circuit

board.Line characteristic impedance and IO voltage are 68 ohms
and 3.3V respectively.
To estimate the power supply droop caused by the parasitic inductance,
first let’s estimate the *as follows. The dynamic IO current is the current
transient for transmission line load, not steady state resistive load.

ΔV 3 . 3V
I ( peak ) = = = 48 . 5 mA
Zo 68
Since the package inductance is 1.44nH for 1nS risetime signal, the inter-
nal voltage droop is

dI 48 . 5 mA
V ( droop ) = L = (1 . 44 nH ) = 70 mV
dt 1 nS
Typically, one DSP power supply pin is shared by many output buffers.
This creates larger droop and leads to higher radiation. This helps explain
why good power supply decoupling is required for low EMI design.

11.6. TRANSMISSION LINE

To combat TL effects, use simulation tools to fine-tune the series termina-
tion resistors to eliminate overshoots and undershoots caused by imped-
ance mismatch explained in the Transmission Line chapter. Improving
signal integrity design helps reduce EMI. But to minimize EMI, the series
termination resistors should also be as large as possible without violating
AC timing. A parallel termination resistor as shown in Figure 11.10 is
commonly used in RF and analog designs, but is not practical for digital
signals due to the amount of DC current drained by the 50 ohm resistor. If
parallel termination is required, use a DC blocking capacitor in series with
the resistor as demonstrated in the Transmission Line section.
Electromagnetic Interference (EMI) 205

Figure 11.10. Terminated and Un-Terminated Transmission

Lines

Table 1 [5] shows the source current for different values of the series ter-
mination resistor. Changing the value from 10 ohms to 39 ohms does not
have much effect on the waveform, [5] showing about 1nS degradation,
but dramatically reduces the source current which greatly lowers the radi-
ate emissions. Figure 11.11 shows a DSP board with a 47 ohm series re-
sistor added to the memory clock, reducing the radiated emissions 3dB
compared to the emissions of the signal without termination.
Overall, if slower risetime signals are acceptable and do not violate AC
timing specifications, designers should use the largest resistor value to
terminate high speed signals to optimize the design from an EMI stand-
point.

Table 11.1. Source Current For Different Series Termination

Series Termination Re- Peak Source Current:

sistor Value:

10 ohms ~ 40mA

22 ohms ~ 10mA

25 ohms ~ 5mA

30 ohms ~ 10mA

33 ohms ~ 9mA

39 ohms ~ 8mA
206 Chapter 11

Figure 11.11. DSP Board with Terminated Clock

11.7. POWER AND GROUND PLANES

For high-speed DSP systems, it is getting more and more difficult to meet
EMI regulations without using multiple layer PCBs and dedicating some
of the layers as power and ground planes. Compared to a trace, a power or
ground plane has a lower parasitic inductance and provides a shielding ef-
fect for high-speed signals. Power and ground planes also provide natural
decoupling capacitance. As described in the PCB layout section of this
document, natural decoupling capacitance occurs when power and ground
planes are spaced very closely, yielding higher capacitance. This effect be-
comes very important at 300MHz speed or higher. So, adding power and
ground planes simplifies PCB routing and reduces the number of high-
frequency decoupling capacitors required for the DSP.
Another important consideration for the PCB is layer assignment. Refer to
the board layout chapter, Chapter 10, to determine the best board stackup
for your application. Keep in mind that adding a ground plane directly un-
derneath the high-speed signal plane creates an image plane that provides
the shortest current return paths. Studies in [2] and [3] show that image
planes greatly reduce radiated emissions. The comparison between PCB
with and without image plane are shown Figures 11.12 and 11.13.
Electromagnetic Interference (EMI) 207

Figure 11.12. Radiated Emissions Without Image Plane

Figure 11.13. Radiated Emissions With Image Plane

208 Chapter 11

11.8. SUMMARY: EMI REDUCTION GUIDELINES

In summary, here are the guidelines for low EMI system design:

• Add image planes wherever possible.

• Create ground planes if there are spaces available on the rout-

ing layers. Connect these ground areas to the ground plane
with vias. Creating a quarter-inch via grid is ideal.

• Add guard traces to high-speed signals if possible.

• Reduce the risetime of the signal if timing is not critical. This

can be accomplished by including series termination resistors
on high-speed buses and fine-tuning the resistors for optimal
signal integrity and EMI. Series termination resistors lower
the source current, increase the signal risetime and reduce
transmission effects. Substantial benefits can be achieved with
this approach at a low cost.

• Keep the current loops as small as possible. Add as many de-

coupling capacitors as possible. Always apply current return
rules to reduce loop areas.

• Keep high-speed signals away from other signals and espe-

cially away from input and output ports or connectors.

• Avoid isolating the ground plane. If this is required for per-

formance reasons, such as with audio ADCs and DACs, apply
current return rules to connect the grounds together.

• Avoid connecting the ground splits with a ferrite bead. At high

frequencies, a ferrite bead has high impedance and creates a
large ground potential difference between the planes.

• Use multiple decoupling capacitors with different values.

Every capacitor has a self-resonant frequency so be careful.
Refer to the Power Supply Decoupling Techniques section for
more information.

• For PC board stackup, add as many power and ground planes

as possible. Keep the power and ground planes next to each
Electromagnetic Interference (EMI) 209

other to ensure low impedance stackup or large natural capaci-

tance stackup.

• Add an EMI pi filter on all the signals exiting the box or enter-
ing the box.

• If the system fails EMI tests, find the source by tracing the
failed frequencies to their source. For example, assume the de-
sign fails at 300MHz but there is nothing on the board running
at that frequency. The source is likely a 3rd harmonic of a
100HMz signal.

• Determine if the failed frequencies are common mode or dif-

ferential mode. Remove all the cables connected to the box. If
the radiation changes, it is common mode, if not, then it is dif-
ferential mode. Then, go to the clock source and use termina-
tion or decoupling techniques to reduce the radiation. If it is
common mode, add pi filters to the inputs and outputs. Adding
a common choke onto the cable is an effective but expensive
method of reducing EMI.
210 Chapter 11

REFERENCES

[1] Federal Communication Commission (2005) Unintentional Radiators,

Title 47 (47CFR), Part 15 B.
http://www.fcc.gov/oet/info/rules/part15/part15-91905.pdf.

[2] Montrose Mark (2000) Printed Circuit Board Design Techniques for
EMC Compliance. The Institute of Electrical and Electronics Engi-
neers, New York.

[3] Montrose Mark (1996) Analysis on the Effectiveness of Image Planes

within a Printed Circuit Board. The Institute of Electrical and Elec-
tronics Engineers.

[4] Ott Henry (1988) Noise Reduction Techniques in Electronic Systems.

Prentice-Hall, New Jersey.

[5] Johnson, H, Graham, M (2003) High-Speed Signal Propagation. Pren-

tice-Hall, New Jersey.

[6] Renolds J (2003) DDR PCB Routing Tutorial. Texas Instruments Inc
Tutorial.
 Glossary

AC Alternating current
ADC Analog-to-Digital Converter
APLL Analog phase-locked loop
BER Bit Error Rate
BGA Ball Grid Array
CODEC COmpression/DECompression
CP Charge pump
CPU Central Processing Unit
DAC Digital-to-Analog Converter
DC Direct Current
DCO Digital controlled oscillator
DDR Dual Data Rate
DLL Delay-Locked Loop
DNL Differential Non-Linearity
DP Display Port
DPLL Digital phase-locked loop
DSP Digital Signal Processing
DVI Digital Video Interface
ENOB Effective number of bits
EMC Electromagnetic Compatibility
EMI Electromagnetic Interference
EMIFF External memory interface fast
EMIFS External memory interface slow
ESL Equivalent Series Inductance
ESR Equivalent Series Resistance
FCC Federal Communication Commission
GP Gain peaking
GPS Global Positioning System
211
212 Glossary

IEEE Institute of Electrical and Electronics Engineers

HD High Definition
HDMI High Definition Media Interface
HSYNC Horizontal Synchronization
INL Integral Non-Linearity
IO Input/Output
JTAG Joint Test Action Group
LCD Liquid Crystal Display
LDO Low dropout regulator
LSB Least significant bit
McBSP Multi-Channel Buffered Serial Port
MPEG Moving Picture Experts Group
PCI Peripherals Component Interface
PCB Printed Circuit Board
PFD Phase frequency detector
PLL Phase-Locked Loop
PSRR Power Supply Rejection Ratio
PWM Pulse Width Modulation
RF Radio Frequency
SD Standard Definition
SDRAM Synchronous Dynamic Random Access Memory
SNR Signal-to-noise
SoC System-on-Chip
TL Transmission Line
USB Universal Serial Bus
UWB Ultra-Wide Band
VCO Voltage controlled oscillator
VSYNC Vertical Synchronization
WLAN Wireless local area network
 Index

AC timing, 204 Differential Non-Linearity,

Active Filter Design, 146, 164 133, 135
Dynamic Range Limitation, DNL, 138
142 INL, 138
Adjacent power and ground, 189 Integral Non-Linearly, 133,
Algorithms, 122 137
Amplifier circuit, 135 Antenna, 40, 195
Amplitude modulating, 124 Artifacts, 6
Analog circuit simulator, 97 Attenuation, 98, 101, 132, 163,
Analog Filter Design, 141 175, 200
Butterworth, 141, 146 Audio, 5, 42, 121
Cauer and Besser, 141 Audio filter, 167
Chebyshev, 141
Filter topology, 96, 175 Backward crosstalk, 35
Highpass filter, 160 Ball grid array, 77, 82
Inverse Chebyshev, 141 Bandwidth, 94, 96, 98
Inverting lowpass, 164 BER, 7
Non-inverting lowpass, 164 BGA package, 92, 188
Sallen-Key, 171, 172, 169 Biasing, 150, 151, 175
Analog-to-digital, 121 Bluetooth, 9
ADC, 5, 121, 138 Board capacitance, 190
Anti-aliasing filter, 5, 121, Boost converter, 50
126, 141 Broadband, 8
BT.1120, 7

213
214 Index

BT.656, 7 Digital controlled oscillator, 112

Buck converter, 50 Digital Controller, 112
Bulk capacitor, 78 Digital Controller Oscillator, 111
Digital-to-analog, 121
Capacitance, 27 DAC, 6, 121, 130, 138
Capacitive load, 21 Distortion, 5
Capacitor characteristics, 69 DLL, 181
Ceramic, 89, 71 DLL power supply, 184
Characteristic impedance, 17, 14, DSP, 1, 23, 45
24, 29, 27 Dual rail supply, 150
Charge Pump, 106 Duty cycle, 37, 51, 52, 200
Clock oscillator, 108 DVI, 7
Clock Speed, 178 Dynamic current, 55
CODEC, 6, 24, 39
Common mode, 209 Effective Number of Bits, 130
Common mode radiation, 197 ENOB, 130, 133, 138
Communication system, 8, 10 Effective radiator, 200
Controlled impedance, 188 Effects of crosstalk, 31
Corner frequency, 98, 99, 102, Electric field, 197, 198
145, 159, 162 Electrolytic, 71, 72
Cosine, 199 Electromagnetic interference, 13
Coupling, 3 EMI, 28, 50, 79, 187, 191,
CPU, 39 195
Crosstalk, 5, 7, 31, 33, 36, 40, EMC, 1, 57
41, 187, 202 EMIFF, 82
Current consumption, 80 EMIFS, 89
Current loops, 201 Equivalent series inductance, 70
Current return, 31, 201 ESL, 71, 76
Current return density, 33 Equivalent series resistance, 70
ESR, 76
Daisy-chain topology, 20 Error amplifier, 45, 46
Data compression, 122 Ethernet, 9, 188
DDR, 78, 177
Decoupling, 6, 80, 203 FCC, 31, 40
Analytical decoupling, 82 FCC Part 15 A, 195
Analytical Decoupling, 77 Ferrite bead, 74, 94, 95, 208
Design methodologies, 31 Forward crosstalk, 35
Dielectric constant, 189 FR4 printed circuit board, 204
Differential Clock, 178 Frequency Range, 142
Differential mode radiation, 197 Frequency response, 95, 99
Differential signals, 108 Frequency spectrum, 124, 198
Differential Strobe, 178 Full Grid Layout, 93
Index 215

Gain peaking, 170 Linear regulator, 6, 45, 47, 57,

General Rules-Of-Thumb, 75 59, 76, 118
Ground grid, 27, 29, 28 LM317, 48
Ground plane, 188 Load regulation, 53, 56
Low dropout regulator, 113
Harmonic, 36, 37, 40, 199, 209 Low Frequency Current Return,
HDMI, 7 32
High Frequency Current Return, Lowpass filter design, 164
32
High frequency noise, 94 Magnitude, 159, 160
Maximum crosstalk, 35
IEEE802.11, 9 Maximum dynamic range, 146
Image plane, 192, 193, 206 Maximum swing, 150, 151
Imbalance, 198 McBSP, 5
Impedance, 96 Memory sub-system, 19, 177
Impedance mismatch, 202 Read Cycle, 181
Inductance, 27, 68 SDRAM, 20
Inductor characteristics, 72, 74 Write Cycle, 179
Initial voltage, 17 Memory signal integrity, 183
Input impedance, 157, 161, 162 Methodologies, 164
Insulating core, 74 Microphone, 5
Interference Reduction, 2, 40, 41 Microstrip, 190
Isolation, 102 Minimizing radiation, 36
MPEG-2 decode, 38, 39
Jitter, 6, 107 MPEG-2 Encoder, 39
Cycle-To-Cycle Jitter, 109
Long Term Jitter, 108 Noise characteristics, 69
Period Jitter, 110 Avalanche Noise, 4
Burst Noise, 4
Kirchhoff’s Current Law, 148, Flicker Noise, 4, 7
149 Shot Noise, 3
Non-adjacent topology, 189, 190
Lattice diagram, 16 Non-embedded designs, 183
LC filter, 50 NTSC spectrum, 40
LDO versus Switching
Regulators, 58 Open ended load, 15
Least Significant Bit, 123 Operating frequency, 166, 198
Line regulation, 56 Operational Amplifier, 141, 147,
Line Regulation, 53 148
Linear and non-linear distortions, AC Couple, 155, 160, 175
122 AC gain, 148
AC ground, 152
216 Index

DC and AC Coupled, 155 Power efficiency and dissipation,

Inverting amplifier, 160 45
Inverting input, 147 Power plane, 188
Non-inverting amplifier, 147, Power Sequencing, 61
154 Power Sequencing Verification,
Virtual ground rule, 148, 149 63
Oscillations, 45 Power spectral density, 41
Oversampling, 134 Power supple ripple, 56
Oversampling ADC or DAC, Power supply architectures, 45,
134 60
Overshoot, 16, 17, 181 Power supply decoupling, 67
Power supply droop, 204
Parallel capacitance, 189 Printed circuit board, 187
Parallel combination, 154, 167 Probability Density Function,
Parallel termination, 19, 25, 29, 127
204 Propagation delay, 14, 22, 29
Parasitic inductance, 68, 206 PSRR, 7
Passband, 101, 174 PWM, 50, 51, 196
Passive and active filters, 142,
146 Quantization, 126
Passive filter, 144, 146 Quantization error, 123, 126
Passive Lowpass Filter, 143 Quantization step, 126
Pi filter, 94, 114
T filter, 94, 100, 115 Radiated emissions, 94, 192,
PCB, 6, 31, 91, 187 195, 206
PCB manufacture, 188 RapidIO, 188
PCI, 7 Reconstruction Filter, 121
PCI Express, 9 Reflected voltage, 17
Phase relationship, 165 Reflections, 13, 14, 202
Phase-Frequency Detector, 106 Reliability, 142
Phase-shift, 179 Reset, 60
Pixel clock, 7 Resolution, 133
Placing Decoupling Capacitors, RF spectrum, 9
91 Ripple rejection, 48, 118
PLL, 57, 76, 82, 105 Rise and fall-times, 37
APLL, 106 RMS, 127
Digital PLL, 105 Routability, 191
Divide-by-M counter, 107 Routing layer, 189
DPLL, 111
PLL isolation, 114 Sampling, 124
Power Consumption, 178 Aliasing, 125
Power dissipation, 47, 50 Nyquist, 124, 125, 134
Index 217

Sampling frequency, 125, Threshold voltage, 182

134, 141 Time shifting, 39, 40
Sampling noise, 121, 132 Timing Interval Analyzer, 110,
Self-resonant frequency, 70, 72, 111
79, 208 Timing violations, 41
Series termination, 20, 21, 24, Transient Response, 53, 203
40, 41, 208 Transistor, 46
Shielding, 175 Transmission line, 13, 15, 81,
Shielding layer, 192 196, 204
Signal integrity, 6 Lossy TL, 13
Signal Quality, 191 Transmission line effects, 28,
Signal-to-noise, 129 187
SNR, 133, 138
Simulation, 145, 146, 158, 163 Undershoots, 181
Single rail supply, 150 Unstable, 166
Sinusoidal, 127, 199 USB, 188
Skin effect, 32, 201
Spread spectrum, 8, 42 VCO, 107
Squarewave, 199 Video, 6, 38, 42, 121
Stability analysis, 166 Voltage Controlled Oscillator,
Stackup, 187, 206 106
Standard definition, 7 Voltage droop, 55
Stripline, 190 VREF, 128, 179
Switching Current Estimation,
84 Waveforms at the Terminated
Symmetrical, 93 and Unterminated Loads, 18
System start-up, 63 Wavelength, 200, 41
WLAN, 9
Tantalum capacitor, 71, 76
Termination, 7, 13, 183 Zero-to-peak voltage, 128
Thermal Noise, 3 Zig zag pattern, 28