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Experiment-5: Aim: To Write VHDL Code For 4 To 1 MUX and Observe The Waveform and Synthesize The Code

The experiment aims to write VHDL code for a 4 to 1 multiplexer (MUX) and observe the waveform and synthesize the code. A 4 to 1 MUX has 4 inputs, 2 control bits, and 1 output. The control bits determine which input is transmitted to the output. VHDL code for a 4 to 1 MUX is written using a case statement to select the output based on the control bits. The code is simulated and synthesized successfully.

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Yidnekachwe Mekuria
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67 views

Experiment-5: Aim: To Write VHDL Code For 4 To 1 MUX and Observe The Waveform and Synthesize The Code

The experiment aims to write VHDL code for a 4 to 1 multiplexer (MUX) and observe the waveform and synthesize the code. A 4 to 1 MUX has 4 inputs, 2 control bits, and 1 output. The control bits determine which input is transmitted to the output. VHDL code for a 4 to 1 MUX is written using a case statement to select the output based on the control bits. The code is simulated and synthesized successfully.

Uploaded by

Yidnekachwe Mekuria
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment-5

Aim: To write VHDL code for 4 to 1 MUX and observe the waveform and synthesize the code
with technological library with given Constraints.
Apparatus: Modelsim PE Student Edition 10.1 Software.
Theory:
A multiplexer is a circuit that accept many inputs but give only one output. A multiplexer is a
circuit used to select and route any one of the several input signals to a signal output. A simple
example of a non-electronic circuit of a multiplexer is a single pole multiposition switch. The
multiplexer used for digital applications, also called digital multiplexer, is a circuit with many
input but only one output. By applying control signals, we can steer any input to the output. Few
types of multiplexer are 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexer.
4-to-1 Multiplexer:
The 4-to-1 multiplexer has 4 input bit, 2 control bits, and 1 output bit. The four input bits are D0,
D1, D2 and D3. only one of this is transmitted to the output Y. The output depends on the value of
S0, S1 which is the control input. The control input determines which of the input data bit is
transmitted to the output.
For instance, as shown in figure 5.1 when S0 and S1 = 00, the upper AND gate is enabled while
all other AND gates are disabled. Therefore, data bit D0 is transmitted to the output, giving Y =
Do. If the control input is changed to S0 S1 =11, all gates are disabled except the bottom AND
gate. In this case, D3 is transmitted to the output and Y = D3.

Figure 5.1 Schematic diagram of 4:1 MUX


Figure 5.2 Block diagram of 4:1 MUX

Table 5.1 Truth table of 4:1 MUX

VHDL Code for 4:1 MUX Logic:


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX IS
PORT (A,B,C,D: IN STD_LOGIC_VECTOR(3 DOWNTO 0); S: IN STD_LOGIC_VECTOR(1
DOWNTO 0); Y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END MUX;

ARCHITECTURE BEHAVIOUR OF MUX IS


BEGIN
PROCESS(A,B,C,D,S)
BEGIN
CASE S IS
WHEN "00" => Y <= A;
WHEN "01" => Y <= B;
WHEN "10" => Y <= C;
WHEN "11" => Y <= D;
END CASE;
END PROCESS;
END BEHAVIOUR;

Figure 5.3 Simulation waveform results of 4:1 MUX


Results: VHDL code for the 4 to 1 MUX circuits is written, the waveform is observed and the
code is synthesized with the technological library and is verified.

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