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Ee6301 Digital Logic Circuits: Question Bank - R2013 Part A (April/May 2010), (April/May 2015) (Nov/Dec 2015)

This document contains a question bank for the course EE6301 - Digital Logic Circuits divided into two parts. Part A contains 24 multiple choice questions related to digital logic families, logic gates, flip-flops, sequential circuits, VHDL. Part B contains 7 multi-part design and analysis questions related to logic gates, counters, PLA, asynchronous circuits, and VHDL modeling. The document provides a set of practice questions for students to test their knowledge of key concepts taught in a digital logic circuits course.

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Krishnandrk 5577
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131 views2 pages

Ee6301 Digital Logic Circuits: Question Bank - R2013 Part A (April/May 2010), (April/May 2015) (Nov/Dec 2015)

This document contains a question bank for the course EE6301 - Digital Logic Circuits divided into two parts. Part A contains 24 multiple choice questions related to digital logic families, logic gates, flip-flops, sequential circuits, VHDL. Part B contains 7 multi-part design and analysis questions related to logic gates, counters, PLA, asynchronous circuits, and VHDL modeling. The document provides a set of practice questions for students to test their knowledge of key concepts taught in a digital logic circuits course.

Uploaded by

Krishnandrk 5577
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE6301‐ DIGITAL LOGIC CIRCUITS 

QUESTION BANK - R2013


PART A
1. Which IC family offers low propagation delay and low power dissipation?
[April/May 2010], [April/May 2015]
2. Define fan in and fan out characteristics of digital logic families. [April/May 2011],
[Nov/Dec 2015]
3. Compare totem pole output with open collector output. [Nov/Dec 2014]
4. What is advantages of ECL over TTL? [Nov/Dec 2014]
5. Convert (475.25)8 to its decimal equivalent & (549.B4)16 to its binary equivalent.
[April/May 2015]
6. Draw the logic diagram of an half adder. [Nov/Dec 2014]
7. What are the applications of multiplexer? [Nov/Dec 2014]
8. Convert the given expression in canonical SOP form Y = A B + A’ C + B C’ .
[Nov/Dec 2015]
9. Draw the logical diagram of EX-OR gate using NAND gates. [Nov/Dec 2015]
 
10. Simplify the expression Z  AB  A B. A.C . [April/May 2015]
11. What is meant by state assignment? State the rules for state assignment. [April/May
2015], [Nov/Dec 2013]
12. Differentiate between Melay and Moore models. [Nov/Dec 2014]
13. Show how the JK flipflop can be modified into a D flipflop or a T flipflop.
[Nov/Dec 2014]
14. Draw the truth table and state diagram of SR Flipflop. [Nov/Dec 2015]
15. What is edge triggered flipflops? [Nov/Dec 2015]
16. State the hazards in asynchronous sequential circuit. [April/May 2011], [Nov/Dec
2011], [Nov/Dec 2013]
17. Draw the block diagram of PLA. [Nov/Dec 2014]
18. What are the disadvantages of asynchronous sequential circuit? [Nov/Dec 2014]
19. Define racing. [Nov/Dec 2014]
20. What is PROM? [Nov/Dec 2015], [April/May 2015]
21. What are the operators present in VHDL? [Nov/Dec 2011], [Nov/Dec 2014],
[Nov/Dec 2015]
22. Write a VHDL code for 2 x 1 MUX. [Nov/Dec 2014]
23. Write the behavioural model of D Flipflop. [Nov/Dec 2015], [April/May 2015]
24. What is package in VHDL? [April/May 2015]
PART B
1. (i) With circuit schematic, explain the operation of a two input TTL NAND gate
with totem pole output. [April/May 2015]
(ii) Compare totem pole and open collector outputs. [April/May 2015]
2. (i) Encode the binary word 1011 into seven bit even parity Hamming code.
[April/May 2015]
(ii) Perform the following addition using BCD and Excee-3 addition (205 + 569).
Prepared by G.Padmavathi  Page 1 
 

EE6301‐ DIGITAL LOGIC CIRCUITS 

[April/May 2015]
3. (i) Design a Full Subtractor and implement it using logic gates. [Nov/Dec 2014]
(ii) Design a 4 Bit binary to gray code converter and implement it using logic gates.
[Nov/Dec 2014]
4. (i) Reduce the following function using K-Map.
F(A,B,C,D) = πM(0,2,3,8,9,12,13,15). [April/May 2015]
(ii) For the given circuit, derive an algebraic expression in SOP form. [April/May
2011]

5. (i) Describe an asynchronous Modulo-8 down counter using JK Flipfops. [Nov/Dec


2014]
(ii) Explain the various types of triggering with suitable diagrams. Compare their
merits & demerits. [Nov/Dec 2014]
6. (i) Implement the following function using PLA. A (x, y, z) = ∑m (1, 2, 4, 6)
[April/May 2015]
(ii) Describe with reasons the effect of races in asynchronous sequential circuit
design. Explain its types with illustrations. Show the method of race free state
assignments with examples. [Nov/Dec 2014]
7. (i) Explain the concept of Behavioural modelling & Structural modelling in
VHDL.Take the example of full adder design for both and write the coding
[Nov/Dec 2014]
(ii) Write a VHDL Code for a 4-bit universal shift register. [Nov/Dec 2014]

Prepared by G.Padmavathi  Page 2 

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