Features

• Low-voltage and Standard-voltage Operation

⎯ 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized as 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility Two-wire
• Write Protect Pin for Hardware and Software Data Protection
Serial EEPROM
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
256K (32,768 x 8)
• High Reliability
⎯ Endurance: One Million Write Cycles
⎯ Data Retention: 40 Years ATMLH412
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small
Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers

Description
The ATMLH412 provides 262,144 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits
each. The device’s cascadable feature allows up to eight devices to share a common
two-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices
are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra
Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is
available in a 1.8V (1.8V to 5.5V) version.

Table 1. Pin Configurations

Pin Name Function 8-lead PDIP 8-lead SOIC
A0 1 8 VCC A0 1 8 VCC
A0 – A2 Address Inputs
A1 2 7 WP A1 2 7 WP
SDA Serial Data A2 3 6 SCL A2 3 6 SCL
GND 4 5 SDA GND 4 5 SDA
SCL Serial Clock Input

WP Write Protect 8-ball dBGA2 8-lead TSSOP

VCC 8 1 A0 A0 1 8 VCC
GND Ground WP 7 2 A1 A1 2 7 WP
SCL 6 3 A2 A2 3 6 SCL
SDA 5 4 GND GND 4 5 SDA
Bottom View
8-lead Ultra-Thin SAP
VCC 8 1 A0
WP 7 2 A1
SCL 6 3 A2
SDA 5 4 GND
Bottom View 8568A–SEEPR–11/08
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute
Operating Temperature ........................... • 55°C to +125°C
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
Storage Temperature ............................ • 65°C to + 150°C
and functional operation of the device at these or
any other conditions beyond those indicated in
Voltage on Any Pin
the operational sections of this specification are
with Respect to Ground................................ • 1.0 V +7.0V
not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
Maximum Operating Voltage..................................... 6.25V
device reliability.
DC Output Current .................................................. 5.0 mA

Figure 1. Block Diagram

VCC
GND
WP
SCL START
STOP
SDA LOGIC SERIAL
EN
CONTROL H.V. PUMP/TIMING
LOGIC
LOAD

DEVICE COMP DATA RECOVERY

ADDRESS
COMPARATOR LOAD INC
A2
X DEC

A1 R/W DATA WORD EEPROM

A0 ADDR/COUNTER

Y DEC SERIAL MUX

DIN DOUT/ACK
LOGIC
DOUT

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1. Pin Descriptions
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and
negative-edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired
(directly to GND or to VCC) for compatibility with other ATMLHxx devices. When the pins are hardwired, as many as eight
256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device
Addressing”) A device is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP
is connected directly to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications,
Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel
recommends using 10kΩ or less.

8568A–SEEPR–11/08
2. Memory Organization
ATMLH412, 256K SERIAL EEPROM : The 256K is internally organized as 512 pages of 64 bytes each. Random word
addressing requires a 15-bit data word address.
(1)
Table 2. Pin Capacitance
Applicable over recommended operating range from:
TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics
Applicable over recommended operating range from:
TAI = − 40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
ICC1 Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA
ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

Standby Current VCC = 1.8V 1.0 μA

ISB1 VIN = VCC or VSS
(1.8V option) VCC = 5.0V 6.0 μA
Input Leakage
ILI VIN = VCC or VSS 0.10 3.0 μA
Currentt VCC = 5.0V
Output Leakage
ILO VOUT = VCC or VSS 0.05 3.0 μA
Currentt VCC = 5.0V
Ӎ0.6
(1)
VIL Input Low Level VCC x 0.3 V
(1)
VIH Input High Level VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

Note: 1. VIL min and VIH max are reference only and are not tested.

8568A–SEEPR–11/08
 Table 4. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from:
TAI = − 40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.8-volt 2.5, 5.0-volt
Symbol Parameter Units
Min Max Min Max
fSCL Clock Frequency, SCL 400 1000 kHz
tLOW Clock Pulse Width Low 1.3 0.4 μs
tHIGH Clock Pulse Width High 0.6 0.4 μs
(1)
tI Noise Suppression Time 100 50 ns

tAA Clock Low to Data Out Valid 0.05 0.9 0.05 0.55 μs
μs
(1)
tBUF Time the bus must be free before a new transmission can start 1.3 0.5
tHD.STA Start Hold Time 0.6 .25 μs
tSU.STA Start Set-up Time 0.6 0.25 μs
tHD.DAT Data In Hold Time 0 0 μs
tSU.DAT Data In Set-up Time 100 100 ns
μs
(1)
tR Inputs Rise Time 0.3 0.3
(1)
tF Inputs Fall Time 300 100 ns
tSU.STO Stop Set-up Time 0.6 0.25 μs
tDH Data Out Hold Time 50 50 ns
tWR Write Cycle Time 5 5 ms

(1) Write
Endurance 25°C, Page Mode, 3.3V 1,000,000
Cycles

Note: 1. This parameter is ensured by characterization and is not 100% tested.

2. AC measurement conditions:
RL (connects to VCC): 1.3 kΩ (2.5V, 5.5V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC

8568A–SEEPR–11/08
3. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (refer to Figure 2). Data changes during SCL high periods will indicate a
start or stop condition as defined below.

Figure 2. Data Validity

SDA

SCL

DATA STABLE DATA STABLE

DATA
CHANGE
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other
command (refer to Figure 3).

Figure 3. Start and Stop Definition

SDA

SCL

START STOP
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (refer to Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE:
receipt of the stop bit and the completion of any internal operations.

8568A–SEEPR–11/08
 SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset
by following these steps:
a) Create a start bit condition,
b) Clock 9 cycles,
c) Create another start bit followed by stop bit condition as shown below.
The device is ready for next communication after above steps has been completed.

Figure 4. Software Reset

Start bit Dummy Clock Cycles Start bit Stop bit

SCL 1 2 3 8 9

SDA

Figure 5. Bus Timing

tHIGH
tF tR

tLOW tLOW
SCL

tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO

SDA IN

tAA tDH tBUF

SDA OUT

Figure 6. Write Cycle Timing

SCL

SDA 8th BIT ACK

WORDn
(1)
twr

STOP START
CONDITION CONDITION

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the
internal clear/write cycle.

8568A–SEEPR–11/08
Figure 7. Output Acknowledge

SCL 1 8 9

DATA IN

DATA OUT

START ACKNOWLEDGE

8568A–SEEPR–11/08
4. Device Addressing
The 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or
write operation (refer to Figure 8). The device address word consists of a mandatory “1”, “0” sequence for the first four
most significant bits as shown. This is common to all two-wire EEPROM devices.

Figure 8. Device Addressing

1 0 1 0 A2 A1 A0 R/W

MSB LSB

The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on the same bus. These
bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary
circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high,
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return
to a standby state.
DATA SECURITY: e that allows the user to write protect the
whole memory when the WP pin is at VCC.

8568A–SEEPR–11/08
5. Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as
a microcontroller, must then terminate the write sequence with a stop condition. At this time the EEPROM enters an
internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the
EEPROM will not respond until the write is complete (refer to Figure 9).

Figure 9. Byte Write

Note: * = DON’T CARE bit

PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller
can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word received. The
microcontroller must terminate the page write sequence with a stop condition (refer to Figure 10).

Figure 10. Page Write

Note: * = DON’T CARE bit

The data word address lower six bits are internally incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If
more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will
be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same
page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a “0”, allowing the read or write sequence to continue.

8568A–SEEPR–11/08
6. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to “1”. There are three read operations: current address read, random address read, and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the
last read or write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte
of the first page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does
generate a following stop condition (refer to Figure 11).

Figure 11. Current Address Read

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller does not respond with a “0” but does generate a following stop condition. (Refer to
Figure 12)

Figure 12. Random Read

Note: * = DON’T CARE bit

8568A–SEEPR–11/08
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When
the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a
following stop condition (refer to Figure 13).

Figure 13. Sequential Read

8568A–SEEPR–11/08