DEVICES AND COMMUNICATION

BUSES FOR DEVICES NETWORK–

Lesson-22: PARALLEL BUS

DEVICE PROTOCOLS – PCI Bus

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 1
Publs.: McGraw-Hill Education
 PCI Parallel Bus
λ Parallel bus enables a host computer or
system to communicate simultaneously
32-bit or 64-bit with other devices or
systems, for example, to a network
interface card (NIC) or graphic card

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 2
Publs.: McGraw-Hill Education
 Computer system PCI
• When the I/O devices in the distributed
embedded subsystems are networked all
can communicate through a common
parallel bus.
• PCI connects at high speed to other
subsystems having a range of I/O devices
at very short distances (<25 cm) using a
parallel bus without having to implement
a specific interface for each I/O device.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 3
Publs.: McGraw-Hill Education
 PCI bus Applications
connects
λ display monitor,

λ printer,

λ character devices,

λ network subsystems,

λ video card,

λ modem card,

λ hard disk controller,

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 4
Publs.: McGraw-Hill Education
 PCI bus
connects
λ thin client,

λ digital video capture card,

λ streaming displays,

λ 10/100 Base T card,

λ Card with 16 MB Flash ROM with a router

gateway for a LAN and
λ Card using DEC 21040 PCI Ethernet LAN
controller.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 5
Publs.: McGraw-Hill Education
 Computer system PCI
• When the I/O devices in the distributed
embedded subsystems are networked, all
can communicate through a common
parallel bus.
• PCI connects at high speed to other
subsystems having a range of I/O devices
at very short distances (<25 cm) using a
parallel bus without having to implement
a specific interface for each I/O device.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 6
Publs.: McGraw-Hill Education
 PCI Bus Feature
λ 32- bit data bus extendible to 64 bits.
λ PCI protocol specifies the ways of
interaction between the different
components of a computer.
λ A specification version 2.1─
synchronous/asynchronous throughput
is up to 132/ 528 MB/s [33M × 4/ 66M
× 8 Byte/s], operates on 3.3V to 5V
signals.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 7
Publs.: McGraw-Hill Education
 PCI bus feature
λ PCI driver can access the hardware
automatically as well as by the
programmer assigned addresses.
λ Automatically detects the interfacing
systems and assigns new addresses
λ Thus, simplified addition and deletion
(attachment and detachment) of the
system peripherals.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 8
Publs.: McGraw-Hill Education
 FIFO in PCI device/card

λ Each device may use a FIFO controller

with a FIFO buffer for maximum
throughput.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 9
Publs.: McGraw-Hill Education
 Identification Numbers

λ A device identifies its address space by

three identification numbers, (i) I/O
port (ii) Memory locations and (iii)
Configuration registers of total 256B
with a four 4-byte unique ID. Each PCI
device has address space allocation of
256 bytes to access it by the host
computer
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 10
Publs.: McGraw-Hill Education
 PCI device identification
λ A sixteen16-bit register in a PCI device
identifies this number to let that device
auto- detect it.
λ Another sixteen16-bit register
identifies a device ID number. These
two numbers let allow the device to
carry out its auto-detection by its host
computer.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 11
Publs.: McGraw-Hill Education
Peripheral Component Interconnect (PCI) Bus
λ Independent from the IBM
architecture.
λ Number of embedded devices in a
computer system use PCI
λ Three standards for the devices
interfacing with the PC

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 12
Publs.: McGraw-Hill Education
Peripheral Component Interconnect (PCI)
Standards
λ PCI 32bit/33 MHz, and 64bit/66 MHz
λ PCI Extended (PCI/X) 64 bit/100 MHz ,

λ Compact PCI (cPCI) Bus

Two super speed versions

λ PCI Super V2.3 264/528 MBps 3.3V (on
64- bit bus), and 132/264 (on 32-bit bus)
and
λ PCI-X Super V1.01a for 800MBps 64- bit
bus 3.3Volt.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 13
Publs.: McGraw-Hill Education
 PCI bridge
λ PCI bus interface switches a processor
communication with the memory bus to PCI
bus.
λ In most systems, the processor has a single
data bus that connects to a switch module
PCI bridge
λ Some processors integrate the switch
module onto the same integrated circuit as
the processor to reduce the number of chips
required to build a system and thus the
system cost.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 14
Publs.: McGraw-Hill Education
 PCI bridge/switch
λ Communicates with the memory
through a memory bus (a set of
address, control and data buses), a
dedicated set of wires that transfer data
between these two systems.
λ A separate I/O bus connects the PCI
switch to the I/O devices.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 15
Publs.: McGraw-Hill Education
 Advantage of Separate memory and I/O
buses
λ I/O system generally designed for
maximum flexibility, to allow as many
different I/O devices as possible to
interface to the computer
λ Memory bus is designed to provide the
maximum-possible bandwidth between
the processor and the memory system.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 16
Publs.: McGraw-Hill Education
 PCI Bridge and Buses

DRAM ROM
Memory Bus
Address bus PCI bus Bridge
Processor
Data bus
of system
Control bus
A

PCI Bus

LAN Graphic Interface IO device IO Expansion

Interface Interface Interface
Graphic
SCSI Expansion bus
LAN Controller
controller
system B With LCD IO IO device
monitor or device
2008
CRTL22: "Embedded Systems - " , Raj Kamal,
Chapter-3
17
Publs.: McGraw-Hill Education
 PCI
• 32-bit 33 MHz throughput = 133 MBps,
• full component level, Connector (94-pin
connector with 50 signals)
• 64-bit bus, 66 MHz option

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 18
Publs.: McGraw-Hill Education
 PCI 2.2
Board specifications
• Board specifications, multiplexed
AD0-AD31 bus, dual address 64-bit
support,
• An un-terminated bus,
• Signal relay reflected on signal to
attain the final value

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 19
Publs.: McGraw-Hill Education
 PCI-X (PCI extended)
• 133 MBps to as much as 1 GBps
• Backward compatible with existing
PCI cards
• Used in high bandwidth devices
(Fiber Channel, and processors that
are part of a cluster and Gigabit
Ethernet)

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 20
Publs.: McGraw-Hill Education
 PCI-X (PCI extended) option

• Maximum 264 MBps throughput, uses 8,

16, 32, or 64 bit transfers
• 6U cards contain additional pins for user
defined I/Os
• Live insertion support (Hot-Swap),
• Supports two independent buses on the
back plane (on different connectors)

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 21
Publs.: McGraw-Hill Education
 PCI-X (PCI extended) option

• Supports Ethernet, Infiniband, and Star

Fabric support (Switched fabric based
systems) Compact PCI (cPCI)

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 22
Publs.: McGraw-Hill Education
 Each PCI device on Bus
λ Perform a specific function,
λ May contain a processor and software to
perform a specific function.
λ Each device has the specific memory
address-range, specific interrupt-vectors
(pre-assigned or auto configured) and the
device I/O port addresses.
λ A bus of appropriate specifications and
protocol interfaces these to the host
computer system or compute
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
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Publs.: McGraw-Hill Education
 Configuration address space

λ Unique feature of PCI bus unique

feature is its configuration address
space.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 24
Publs.: McGraw-Hill Education
 PCI controller Features
• Accesses one device at a time
• All the devices within host device or
system can share the I/O port and
memory addresses, but cannot share
the configuration registers
• Device cannot modify other
configuration registers but can access
other device resources or share the
work or assist the other device
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 25
Publs.: McGraw-Hill Education
 PCI driver Features
• If there are reasons for doing it so, a
PCI driver can change the default boot
up assignments on configuration
transactions.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 26
Publs.: McGraw-Hill Education
 PCI Device Initialization
• A device can initialize at booting time
• Avoids any address collision
• Device on boot up disables its interrupt
and closes its door to its address space
except to the configuration registers
space

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 27
Publs.: McGraw-Hill Education
 PCI BIOS (Basic Input-Output System)
• Performs the configuration transactions
and then, memory and address spaces
automatically map to the address space
in the device hosting system

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 28
Publs.: McGraw-Hill Education
 PCI device Interrupt Handling
λ A uniquely assigned interrupt type (a
number) handles an interrupt.
λ For example, interrupt type 3 has the
interrupt vector address 0x0000C and
four bytes at the address specify the
interrupt service routine address.
λ Interrupt type can be a number
between 0x00 and 0xFF.
Chapter-3 L22: "Embedded Systems - " , Raj Kamal,
2008 29
Publs.: McGraw-Hill Education
 Configuration register number 60

λ Stores the one byte for the interrupt

type n (pci)
λ The PCI device when interrupted
handles the interrupt of type n(pci)

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 30
Publs.: McGraw-Hill Education
 64 bytes at the standard device independent
configuration registers in a PCI device
Min-GNT

IRQ IRQ HT Max-

EXP ROM Reserved Line
OX30 GNT
BA pin
OX20
BA4 BA5 CBCISP SSVID SSDID

OX10 BA0 BA1 BA2 BA3

OX00 VID DID CR SR RID CC CL LT HT BIST

Ox0 0xI OxF

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 31
Publs.: McGraw-Hill Education
 Meaning of Terms in Figure

λ VID: Vendor ID.

λ DID: Device ID.
λ RID: Revision ID.
λ CR: Common Register.
λ CC: Class Code.
λ SR: Status Register.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

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Publs.: McGraw-Hill Education
 Meaning of Terms in Figure

λ CL: Cache Line.

λ LT: Latency Timer.
λ BIST: Base Input Tick.
λ HT: Header Type.
λ BA: Base Address.
λ CBCISB: Card Base CIS Pointer.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

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Publs.: McGraw-Hill Education
 Meaning of Terms in Figure

λ SS: Sub System.

λ ExpROM: Expansion ROM.
λ MIN_GNT: Minimum Guaranteed time
λ MAX_GNT: Maximum Guaranteed
Time.

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

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 Summary

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 35
Publs.: McGraw-Hill Education
We learnt
• PCI a parallel bus
• PCI 32/33 MHz, and 64/66 MHz
• PCI/X buses 64/100 MHz transfers
• Independent from the IBM
architecture.
• New versions have been introduced for
the PCI bus architecture

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 36
Publs.: McGraw-Hill Education
 End of Lesson 22 of Chapter 3

Chapter-3 L22: "Embedded Systems - " , Raj Kamal,

2008 37
Publs.: McGraw-Hill Education