Implementation of Different Flip-Flop Circuits (S-R, JK, D Flip Flop) Using Logic Gates.
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Mohayminul Al-HamimImplementation of Different Flip-Flop Circuits (S-R, JK, D Flip Flop) Using Logic Gates.
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Mohayminul Al-HamimName: Mohayminul Al-Hamim
ID: 153402032
Experiment No: 14
Experiment Name: Implementation of different Flip-Flop circuits (S-R, JK, D flip flop) using
logic gates.
Objective:
To learn about different types of flip flops.
To implement the obtained equation using different logic gates in the simulator and observe
the outputs.
To verify the outputs using the truth table.
Required Apparatus:
Logic gate simulator app.
NAND gates IC types 7400 Quadruple 3 input.
NOT gates IC types7404 Quadruple.
NOR gates IC types 7402 Quadruple 3 input
Input and output gates.
Theory:
SR Flip Flop: This simple flip flop circuit has a set input (S) and a reset input (R). In this circuit
when you Set “S” as active the output “Q” would be high and “Q‘‘” will be low. Once the
outputs are established, the wiring of the circuit is maintained until “S” or “R” go high, or power
is turned off. As shown above, it is the simplest and easiest to understand. The two outputs, as
shown above, are the inverse of each other. The truth table of SR Flip Flop is highlighted below.
JK Flip-flop: The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both inputs S
and Rare equal to logic level “1”. Due to this additional clocked input, a JK flip-flop has four
possible input combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a
JK flip flop is similar to that of an SR Bastable Latch as seen in the previous tutorial except for
the addition of a clock input.
D Flip Flop: D flip-flop operates with only positive clock transitions or negative clock
transitions. Whereas, D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal.
T Flip Flop: This is a much simpler version of the J-K flip flop. Both the J and K inputs are
connected together and thus are also called a single input J-K flip flop. When clock pulse is
1
Name: Mohayminul Al-Hamim
ID: 153402032
given to the flip flop, the output begins to toggle. Here also the restriction on the pulse width can
be eliminated with a master-slave or edge-triggered construction. Take a look at the circuit and
truth table below.
Circuit Diagram Simulation and Truth Table:
SR Flip Flop:
S R Q Q’
0 0 0 1
0 1 0 1
1 0 1 0
1 1 undefine undefine
Fig: Truth Table for SR flip flop
Fig: Implemented Circuit for SR flip flop
2
Name: Mohayminul Al-Hamim
ID: 153402032
JK Flip-flop:
CLK J K Q Q’
1 0 0 No Change
1 0 1 0 1
1 1 0 1 0
1 1 1 Toggle
Fig: Circuit diagram for JK flip flop.
Fig: Implemented Circuit for JK flip flop.
3
Name: Mohayminul Al-Hamim
ID: 153402032
D Flip Flop:
clock D Q Q’
0 0 Q Q’
0 1 Q Q’
1 0 0 1
1 1 1 0
Fig: Truth Table for D flip flop.
Fig: Implemented Circuit for D flip flop.
4
Name: Mohayminul Al-Hamim
ID: 153402032
Procedure:
At first, in the Simulator Application the logic gates and other components should be placed.
The logic gates and other components should be connected with connectors.
Finally, using the Toggle Switches the outputs can be observed and compared with the truth
table in the monitor.
Discussion:
Connectors should be connected properly with the proper logic gates and other components.
The hand cursor should be disabled to receive uninterrupted assistance from the simulator
application.
