DIVINE WORD COLLEGE OF CALAPAN

ENGINEERING AND ARCHITECTURE DEPARTMENT

FINAL EXAMINATION

NAME: ________________________________________________ SCORE: ____/____ RATING: _________

ID NUMBER: _________ COURSE: _________________

I. Multiple Choice: Write the letter on the space provided

_____1. The output will be a LOW for any case when _____14. Convert the decimal number 151.75 to
one or more inputs are zero in a(n) binary.
a. OR b. NAND c. NOT d. AND a. 10000111.11 b. 11010011.01 c. 10010111.11
_____2. A single transistor can be used to build which d. 00111100.00
of the following digital logic gates? _____15. The number of bits used to store a BCD digit.
a. OR b. NOT c. AND d. NAND a. 4 b. 1 c. 2 d. 8
_____3. Exclusive-OR (XOR) logic gates can be _____16. Which statement below best describes a
constructed from what other logic gates? Karnaugh map?
a. OR gates and NOT gates a. It is simply a rearranged truth table. b. A Karnaugh
b. AND gates, OR gates, and NOT gates map can be used to replace Boolean rules.
c. AND gates and NOT gates d. OR gates only c. The Karnaugh map eliminates the need for using
_____4. If a signal passing through a gate is inhibited NAND and NOR gates. d. Variable complements can
by sending a low into one of the inputs, and the output be eliminated by using Karnaugh maps.
is HIGH, the gate is a(n): _____17. Logically, the output of a NOR gate would
a.NAND b.AND c.NOR d.OR have the same Boolean expression as a(n):
_____5. How many NAND circuits are contained in a a. NOR gate immediately followed by an INVERTER
7400 NAND IC? b. NAND gate immediately followed by an INVERTER
a. 2 b. 1 c. 4 d. 3 c. AND gate immediately followed by an INVERTER
_____6. How many truth table entries are necessary d. OR gate immediately followed by an INVERTER
for a four-input circuit? _____18. Identify the logic function performed by the
a. 4 b. 8 c. 12 d. 16 circuit shown in the given figure (see fig 1)
_____7. The logic gate that will have HIGH or “1” at its a.XOR b. XNOR c. NAND d.NOR
output when any one of its inputs is HIGH is a(n): _____19. The number of full and half-adders required
a. AND b. NOR c. OR d. NOT to add 16-bit numbers is
_____8. What input values will cause an AND logic gate a. 8 half-adders, 8 full-adders
to produce a HIGH output? b. 1 half-adder, 15 full-adders
a. At least one input is LOW. c. 16 half-adders, 0 full-adders
b. At least one input is HIGH. d. 4 half-adders, 12 full-adders
c. All inputs are HIGH. _____20. Output of the following circuit (fig 2) is
d. All inputs are LOW. a. 0 b. 1 c. x d. x’
_____9. The basic logic gate whose output is the _____21. The characteristic equation of D flip-flop is:
complement of the input is the: a. Q = 1 b. Q = 0 c. Q = D’ d. Q= D
a. Inverter b. Comparator c. OR d. AND _____22. Each "1" entry in a K-map square represents:
_____10. 3428 is the decimal value for which of the a. a HIGH for each input truth table condition that
following binary coded decimal (BCD) groupings? produces a HIGH output. b. a HIGH output on the truth
a. 11010001001000 b. 11010000101000 table for all LOW input combinations. c. a LOW output
c. 110100001101010 d. 011010010000010 for all possible HIGH input conditions. d. a DON'T CARE
_____11. What is the decimal value of the hexadecimal condition for all possible input truth table
number 777? combinations.
a. 191 b. 19111 c. 1911 d.19 _____23. Looping on a K-map always results in the
_____12. What is the result when a decimal 5238 is elimination of:
converted to base 16? a. variables within the loop that appear only in their
a. 12166 b. 327.375 c. 1388 d.1476 complemented form. b. variables that remain
_____13. What is the difference between binary coding unchanged within the loop. c. variables within the
and binary coded decimal? loop that appear in both complemented and
a. Binary coding has a decimal format. uncomplemented form. d. variables within the loop
b. BCD is pure binary. c. Binary coding is pure binary. that appear only in their uncomplemented form.
d. BCD has no decimal format.

SUBJECT: Logic DATE OF EXAMINATION: March 23, 2017

TIME: 5:00PM – 8:00PM DAY: TTH TIME OF EXAMINATION: 5:00PM – 8:00PM
Page 1
PREPARED BY: Engr. Gerald U. Tiocson NOTED BY: Engr. Ariel M. de Roma
 _____24. Convert the following SOP expression to an _____41. Which statement BEST describes the
equivalent POS expression: operation of a negative-edge-triggered D flip-flop?
ABC + AB’C’ + AB’C+ ABC’ + A’B’C a. The logic level at the D input is transferred to Q on
a. (A’+B’+C’)(A’+B+C’)((A’+B+C) NGT of CLK. b. The Q output is ALWAYS identical to
b. (A+B+C)(A+B’+C)(A+B’+C’) the CLK input if the D input is HIGH. c. The Q output is
c. (A’+B’+C’)(A+B’+C)(A+B’+C) ALWAYS identical to the D input when CLK = PGT.
d.(A+B+C)(A’+B+C’)(A+B’+C) d. The Q output is ALWAYS identical to the D input.
_____25. Derive the Boolean expression for the logic _____42. How is a J-K flip-flop made to toggle?
circuit shown (fig 3): a. J = 0, K = 0 b. J = 1, K = 0
a.C(A+B)DE b.[C(A+B)D+E’] c. [[C(A+B)D]E’] d.ABCDE c. J = 0, K = 1 d. J = 1, K = 1
_____26. How many gates would be required to _____43. How many flip-flops are required to produce
implement the following Boolean expression before a divide-by-128 device?
simplification? XY + X(X + Z) + Y(X + Z) a. 1 b. 4 c.6 d.7
a.1 b.2 c.4 d.5 _____44. Which of the following is correct for a gated
_____27. How many gates would be required to D flip-flop? a. The output toggles if one of the inputs
implement the following Boolean expression after is held HIGH. b. Only one of the inputs can be HIGH
simplification? XY + X(X + Z) + Y(X + Z) at a time. c. The output complement follows the
a.1 b.2 c.4 d.5 input when enabled. d. Q output follows the input D
_____28. Use Boolean algebra to find the most when the enable is HIGH.
simplified SOP expression for F = ABD + CD + ACD + ABC _____45. If an input is activated by a signal transition,
+ ABCD. a. F = ABD + ABC + CD b. F = CD + AD it is ________. a. edge-triggered b. toggle triggered
c. F = BC + AB d. F = AC + AD c. clock triggered d. noise triggered
_____29. Converting the Boolean expression LM + _____46. What is one disadvantage of an S-R flip-flop?
M(NO + PQ) to SOP form, we get ________. a. It has no enable input. b. It has an invalid state.
a. LM + MNOPQ b. L + MNO + MPQ c. It has no clock input. d. It has only a single output.
c. LM + M + NO + MPQ d. LM + MNO + MPQ _____47.To convert an binary counter to a bcd
_____30. A Karnaugh map is a systematic way of counter, what must be added?
reducing which type of expression? a. or b. and c. xor d. not
a. product-of-sums b. exclusive NOR _____48. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz
c. sum-of-products d. those with overbars clock input. The Q output is ________.
_____31. Mapping the standard SOP expression ABCD’ a. constantly LOW b. constantly HIGH
+ A’B’CD + AB’C’D + A’B’C’D’, we get: c. a 40 kHz square wave d. a 10 kHz square wave
(see fig 4 for choices) _____49.In an R-S Flip-flop, when does the “hold“
_____32. Applying DeMorgan's theorem to the condition happen?
expression [(W+X+Y)Z]’, we get ________. a. only S is active b. only R is active
a.W’X’Y’Z’ b. (WXY)’Z c.WXYZ’ d.W’X’Y’+Z’ c. both S and R is active d. none of the above
_____33. To perform product of maxterms Boolean _____50. A gated S-R latch and its associated
function must be brought into waveforms are shown (fig 6). What, if anything, is
a. and terms b. or terms c. not terms d. nand terms wrong and what could be causing the problem?
_____34. Simplify the Boolean expression a. The Q’ output is always low; the circuit is defective.
(A+B+C)(D+E)' + (A+B+C)(D+E) b. The Q output should be the complement of the Q’
a. A+B+C b. D+E c. A'B'C' d. D'E' output; the S and R terminals are reversed.
_____35. Simplification of the Boolean expression (A + c. The Q should be following the R input; the R input is
B)'(C + D + E)' + (A + B)' yields which of the following defective. d. There is nothing wrong with the circuit.
results?
a.A+B b.A’B’ c.C+D+E d.AB’ BONUS LOGIC PUZZLE (5pts)
_____36. Simplification of the Boolean expression AB + At the local games evening, four boys were competing
ABC + ABCD + ABCDE + ABCDEF yields which of the in the checkers and chess competitions.
following results?
a.ABCDEF b.AB c.AB+CD+EF d.A+B(C+D(E+F)) Jack beat Mark in chess, Felix came third and the 16
_____37. The simplified form of the Boolean year old won. Jack came second in checkers, the 15
expression (X+Y’+Z)(Z+Y’+Z’)(X+Y+Z) is year old won, Felix beat the 18 year old and the 19 year
a. X’Y + Z’ b. X+Y’Z c. X d. XY+Z’ old came third. Ken is 3 years younger than Mark. The
_____38. The minimum Boolean expression for the person who came last in chess, came third in checkers
circuit (fig 5) is and only one boy got the same position in both games.
a. AB+AC+BC b.A+BC
c.A+B d.A+B+C Can you determine the ages of the boys and the
_____39. Reduce A’BC+AB’C+ABC’+ABC to its simplest positions in the two games?
form. a. A’BC+AB’C+AB b.A’BC+AC+AB
c.AB+AC+BC d.Cannot be reduced further
_____40. Determine the output frequency for a
frequency division circuit that contains 12 flip-flops
with an input clock frequency of 20.48 MHz.
a. 10.24khz b. 5khz c. 30.24khz d. 15khz

SUBJECT: Logic Page 2