Adaptive Hysteretic Comparator with

Opamp Threshold Level Setting

Ndubuisi Ekekwe, Ralph Etienne-Cummings
Department of Electrical & Computer Engineering
Johns Hopkins University
Baltimore, MD, USA
{nekekwe1, retienne} @jhu.edu

Abstract— This paper presents the design of an adaptive reduction of delay by adding a linear predictor and adaptive
hysteretic comparator optimized for noisy environment. It control to a comparator while Mikkola [7] developed a
features an input rail-to-rail opamp which uses feedback means to mitigate single event transients in comparators
networks to set varying hysteretic thresholds while maintaining
a constant hysteretic band for increased noise immunity and
through auto-zeroing techniques. In [3], hysteretic
stability. The chip which can resolve up to 9bits consumes a comparator is used as a building block for a synchronous
total power of 3.8mW and takes an active area of 0.021mm2 in a buck regulator that operates within few hundreds kilo-hertz.
2P3M 0.5 μ m CMOS process with 20ns propagation delay. In some applications, bias voltages could be externally
modulated to change the hysteresis band of the comparator,
I. INTRODUCTION but at the expense of changing its bandwidth, gain and speed.
The need for high performance comparators has always None of these implementations examined external hysteretic
resulted to the addition of hysteresis to improve their configuration which can adapt to changes in the input signal
stabilities and noise immunities when used in noisy while mitigating noise from the environment.
environments. Intrinsically, most comparators have In this paper, we present the addition of external hysteresis
hysteresis with a value of 5mV to 10mV [1, 2]. With internal to a comparator through opamp and resistors. Our goal is to
hysteresis, comparators avoid oscillations arising from vary the hysteresis thresholds while maintaining a constant
parasitic feedbacks. Though efficient in preventing self- hysteretic band. The hysteresis is implemented around the
oscillation, internal hysteresis fails in noisy environment. opamp and its output used as non-inverting input of the
Consequently, hysteresis must be implemented externally to comparator in a positive feedback arrangement. This
prevent rapid output changes and oscillations which may architecture enhances the system stability and improves
arise from noise. This is necessary since comparators have overall immunity to noise.
very high open loop gain with poor noise immunity. This paper is organized as follows: chip architecture is in
In designing external hysteretic comparator, positive section II and circuit techniques and operations in section III.
feedback is applied to the comparator. Positive feedback Section IV presents and discusses results while section V
guarantees a fast output transition state thereby minimizing gives the final conclusions.
the time the comparator stays in the intermediate state [1].
This feature prevents multiple switching. In applications like II. CHIP ARCHITECTURE
battery cells balancer and DC-to-DC converters [3], the
feedback network is used to set the threshold values for the
Vin Vout
comparator. In many cases, these networks, made up of
resistors and MOSFETS offer only static hysteresis band R1
which cannot adapt to input signal variations. Comparator
Xinquan [4] presents the design of a hysteretic comparator
by utilizing the bandgap structure of silicon in a bipolar
R2
junction transistor (BJT) process. The drawback of this
design is the dependence of the threshold voltage on Vcm
temperature. It would readily fail with marginal change in
operating temperature. In [5], Xiao presents a programmable Fig.1. A simple circuit with hysteresis
analog window comparator which can adjust its error Consider the circuit of a simple (yet popular) external
threshold based on the input voltage. The programmability hysteretic comparator shown in Fig.1 [1, 10]. In this design,
and integration complexities to circuit architectures which the positive and negative threshold voltages, respectively
incorporate comparators as building blocks are key given by (1) and (2), are set (primarily) by the output signal.
drawbacks to this circuit. Many different comparators have The resistors determine the hysteresis band, given by (3) if
been presented with features which enable them perform in Vss = 0V.
varieties of conditions [3, 6-9]. MeVay [6] focused on

978-1-4244-2167-1/08/$25.00 ©2008 IEEE 121

 R2 overcome this, a switching network shown in Fig.4 could be
VTH + = (Vcc − Vcm ) + Vcm (1) used. In this circuit, the two resistors are used to set the
R1 + R2 hysteresis band based on the value of Vset. Appropriate state
R2 of Vo completes the positive feedback connecting the
VTH − = (Vss − Vcm ) + Vcm (2) comparator positive input to the threshold levels. The penalty
R1 + R2
of using Fig.4 is the limited input voltage swing of the
R2 system. In this paper, we focused on the opamp based
ΔVTH = VTH + − VTH − = Vcc (3)
architecture.
R1 + R2
The hysteretic thresholds provided by Fig.1 are static. In vm
some applications like battery cells balancer and dc-dc
converters, a more dynamic threshold setting which will take
into consideration the general state of the system is required.
Vset
This state may be changes in the battery cells. In this case,
having access to the non-inverting input (NIV) of the
Σ
Vp
comparator becomes very important. Furthermore, it is also
Comparator
desirable not to load the comparator directly with a feedback
network as shown in Fig.1
We propose a hysteretic comparator architecture which
has elements of adaptation to its input. Shown in Fig. 2, it
relies on a feedback network around a summer to set the Fig.2. Chip concept
threshold bands for the comparator. This arrangement Rf vm
ensures that the comparator has no feedback network around
it and can operate much faster.
There are many ways this summer could be implemented. R1
One way is to use an opamp to obtain the Vset
summation/difference (see Fig.3). Equation 4 gives the
Vp
relationship between the threshold voltage (Vp), resistors and R2
the common mode voltage (Vcm). Depending on the value of Vo Rf Opamp Comparator
Vo, we have either positive (Vth+) threshold when Vo = Vcc
or negative threshold (Vth-) when Vo = Vss. The hysteresis vcm
band, given by (5) and comparable to (3), reduces to (6)
when R1 = R2 and Vss = 0
Fig.3. Chip architecture with opamp

R1 + R f Vo R f + Vcm R2 R f Vset
V p = Vth ± = − (4)
R1 R f + R2 R1
R f R1 + R f
ΔVth = Vth + − Vth − = Vcc (5)
R1 R f + R2
Rf
ΔVth = Vth + − Vth − = Vcc (6)
R1
The total gain of the system is given by (7) where G and A
are respectively the gain of the opamp and the comparator.

A(GVset − Vm)
Vo = (7) Fig.4. Chip architecture with switching network
AG − 1
Based on the expected level of noise and the comparator III. CIRCUITS TECHNIQUES AND OPERATIONS
inverting input (vm), the hysteresis band is set by R1 and R2. Owing to positive feedback from the comparator to the
We designed for ΔVth = 2V. This value is constant though opamp, the opamp is designed with input rail-to-rail common
mode voltage. For the same reason, the comparator has its
Vth + and Vth − can change as a result of Vset. input common mode voltage extending to the power supply
Depending on application, one potential drawback to Fig.3 rails. Further discussions of the circuits are provided in the
is the speed limitation which is introduced by the opamp. To following sections.

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A. Rail-to-rail input opamp
Fig. 5 shows the design of the opamp [11-13]. It uses
NMOS and PMOS differential pairs to increase the input
common voltage range. By combining these pairs, input
voltage can swing from ground to power supply. In this
design, the zero-nulling resistor for compensation is
implemented with MOSFETs thereby making zero-nulling
process independent. One major drawback to this opamp
architecture is the gain fluctuation. As the input voltages
change, the total input transconductance varies. This makes
the opamp compensation very challenging. The voltages
biases (Bia1 to and Bia4) are wide swing to enable high
swing operation at the output. Fig.7 Rail-to-rail comparator
Fig.6 shows the measurement result when the opamp is
configured as a voltage follower. The result shows that the
output is nearly rail-to-rail.

Vout

Vp
Fig.8 Measured comparator result
The opamp and the comparator were designed and tested
separately. Table 1 presents the summary of other
measurements results.

Fig.5 Rail-to-rail opamp C. Layout

Centroid layout was used to reduce systematic offsets and
variations across the chip. The die microphotograph, shown in
Fig. 9, is the complete chip with all the components together.

Output
Input

Opamp
Fig.6 Measured opamp result. (Both axes are 2/division)

B. Rail-to-rail input comparator Bias Comparator

Fig.7 shows the design of the comparator [11, 13]. In this

circuit, both NMOS and PMOS differential pairs are Fig. 9 Chip microphotograph
combined to enable rail-to-rail input common mode range.
Table 1: Measured results for opamp and comparator
The circuit contains a pre-amplification stage (the two
differential pairs), the decision stage and finally the post- Parameter Opamp Comparator
amplification (the output buffer). Bias voltages (vbiasn and DC-gain 51dB
vbias) provide the biases for the input stage differential pairs Unity-gain frequency 23.2MHz
and the post-amplification differential pair. Fig. 8 shows Supply voltage 3.3-5V 3.2-5V
measurement result when an input voltage of 2V dc and 1Vpp Power dissipation 1.75mW 1.3mW
@ 2V offset are applied respectively to the inverting and Input voltage range 0-5V 0-5V
non-inverting inputs of the comparator. Input offset voltage 3.2mV
Slew rate 15.2V/us 41.7V/us
Output voltage swing 0.5-4.53V 0-5V

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 IV. RESULTS 4
Fig.10 shows the measured result when Vset = 2.2V, Vdd = 3.5
Vth+
Vth-
5V, Vcm = 2.5V and Vmpp = 4V @ offset of 2.3V. The delta-Vth
3
measured ΔVth is 1.99V which differs slightly from the
2.5
simulated 2V, maybe, partly due to resistor mismatch. The

Vth[V]
2
value remains the same as Vset is varied though Vth + and
1.5
Vth − could change. In our high level application, ability to 1

change Vth + and Vth − with constant ΔVth enables us to 0.5

adaptively and precisely balance energy cells. Because of the 0

0.5 1 1.5 2 2.5 3 3.5 4
way Vm is generated, keeping Vth + and Vth − static would Vset [V]
Fig.12 Values of Vth+ and Vth- for different Vset
severely degrade the performance of the system. This is the
advantage of our proposed system over circuit of Fig.1. Fig.
Table 2: Summary of chip characteristics
11 shows a triangular Vmpp of 4V @ offset of 2.3V with Vset
Parameter Measured
= 3.6V. Notice the constant ΔVth of 1.99V. Fig.12 presents Technology CMOS 0.5μ m
measured relationships between Vset and the threshold Power supply 3.6-5V
voltages. Other measured results are presented in Table 2. Input range 0-5V
Power dissipation 3.8mW
Propagation delay 20ns
Active area 0.021mm2
Vo Resolution >9 bits
Vm
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