NuMicro

PWM Generator & Capture Timer

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Agenda
What’s PWM Output
PWM Timing Control
What’s Capture Input
Capture Timing Control
Interrupt Architecture
Sample Code

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What’s PWM?
PWM: Pulse Width Modulation
PWM Frequency
How to set and change frequency?
PWM Duty
How to set and change duty cycle?
PWM Output Channels
How to select PWM output channel? PWM
Interrupt
PWM Resolution
How many bits? PWM period
(frequency)
Complementary Paired PWM (CNR+1)
Needs dead-zone insertion? Duty
How to set dead-zone?
Other Functions (CMR+1)

Single-shot pulse
PWM Interrupt

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Features of PWM Generator
Four PWM Generators, each generator supports
One 8-bit prescaler
One clock divider
Two PWM-timers for two outputs, each timer includes
A 16-bit PWM down-counter
A 16-bit PWM reload value register (CNR)
A 16-bit PWM compare register (CMR)
One dead-zone generator
Two PWM outputs.
8 PWM channels or 4 PWM paired channels.
16 bits resolution.
PWM Interrupt synchronized with PWM period.
Single-shot or Continuous mode PWM.

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PWM/Capture Clock Source

PWM01_S(CLKSEL1[29:28])

PWM01_EN(APBCLK[20])

22M
11 PWM01_CLK
HCLK 10
32K
01
12M
00

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 Configure PWM Generator
Insert dead-zone for
paired-PWM
DZI01 Dead Zone
Generator 0
CSR0(CSR03[2:0])
CNR0, CMR0,
PCR
1 100
POE.PWM0

1/2 000 1
PWM- 1 1
PA.12/PWM0
1/4 001 Timer0 0
0 0
Clock 1/8 010 Logic
Divider GPIOA_DOUT[12]
1/16 011 CH0INV
GPIOA_MFP[12]
1 PWMIE0 PWMIF0
8-bit 1/2
PWM01_CLK DZEN01
(from clock
Prescaler 1/4
controller)
PPR.CP01 1/8 CNR1, CMR1,
1/16
PCR Select
1 100
Paired-PWM POE.PWM1

1/2 000 1
PWM- 1 1
PA.13/PWM1
1/4 001 Timer1 0
0 0

Select proper PWM 1/8 010 Logic

GPIOA_DOUT[13]
clock input 1/16 011 CH1INV
GPIOA_MFP[13]
PWMIE1 PWMIF1
CSR1(CSR03[6:4])

Configure PWM
PWM Interrupt output channel
Set PWM frequency( CNR)
Set PWM duty (CMR)
Configure PWM setting (PCR)
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 PWM Frequency & Duty Control
 PWM Frequency =
PWMxy_CLK/(prescale+1)*(clock divider)/(CNR+1);
where xy = 01, 23, 45 or 67, the selected PWM channel.
 Duty ratio = (CMR+1)/(CNR+1).
Start Update
Initialize new CMRx
PWM

CMRx+1 + PWM-Timer CMRx

Comparator
CNRx - Output CNRx

PWM
Ouput
CMRx+1 >= CNR: PWM output high.
CMRx+1 < CNR: PWM output low CNR+1
CMR+1

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 PWM Double Buffering Illustration
Why does need the double buffer?
To output the whole PWM cycle without any destroying.

S/W write new period (CNR)

And new duty (CMR)

CNR=150 CNR=199 CNR=99 CNR=0

CMR=50 CMR=49 CMR=0 CMR=XX

Start Stop
PWM
Waveform

51 50 1

write a nonzero number to

prescaler & setup clock 151 200 100
dividor

First cycle Second cycle

New period (CNR)
New duty (CMR) 8
 Operation oftheDead
Why does need dead zone Zone
control? Generator
To avoid a paired-PWM outputs overlapping on duty-on duration.
For example, in Motor Driver application, it needs to avoid the upper and
lower power switch turn on simultaneously.
Insert a delay time (dead zone) before duty on at each channel of paired-PWM.
8-bit dead-zone timer by PWM clock.

PWM-Timer (Internal signal)

Output 0/2/4/6

PWM-Timer
Inversed output
(Internal signal)
1/3/5/7

Dead-Zone
Generator (Port pin signal)

output 0/2/4/6

Dead-Zone
Generator
(Port pin signal)
output 1/3/5/7

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Dead zone interval
What’s Capture Input
Interrupt

Captured by Rising or Falling Edge

Measure Pulse Width W1
Rising to Falling (W2) Pulse width
(falling to rising)
Falling to Rising (W1)
Rising to Rising (W1+W2) W2
Falling to Falling (W1+W2)
Capture Input Channel Sampling Pulse width
(rising to falling)
How to set and change input channel?
Sampling Frequency
How to set and change frequency?
Capture Function Interrupt
Captured pulse width data
Rising Latch Register (CRLR)
Falling Latch Register (CFLR)

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Features of Capture Input

Timing control logic shared with PWM Generators.

(therefore up to 16 bits data length)
8 Capture inputs shared with PWM outputs
Each channel supports
One rising latch register (CRLR)
One falling latch register (CFLR)
Capture interrupt flag (CAPIFx)

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 Operation Timing of Capture Input
PWM Counter 3 2 1 8 7 6 5 8 7 6 5 4
Reload Reload
(If CNRx = 8) No reload due to
no CAPIFx
Capture Input x

The PWM counter will be

CAPCHxEN
reloaded with CNRx when
CFLRx 1 7
a capture interrupt flag
(CAPIFx) is set
CRLRx 5 The channel low pulse
width is (CNR+1 - CRLR).
CFL_IEx The channel high pulse
width is (CNR+1 - CFLR).
CRL_IEx
Clear by S/W
CAPIFx Set by H/W

Set by H/W Clear by S/W

CFLRIx
Set by H/W Clear by S/W
CRLRIx

Note: X=0~7
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 Interrupt Architecture
Two PWM/Capture Interrupt Vectors
Channel0~Channel3 share one
interrupt vector
PWMIF0 PWM0_INT
CAPIF0

PWMIF1 PWM1_INT
CAPIF1
PWMA_INT
PWMIF2 PWM2_INT
CAPIF2

PWMIF3 PWM3_INT
Each PWM/ CAPIF3
Capture Channel4~Channel7 share one
channel has interrupt vector
its own PWMIF4 PWM4_INT

interrupt flag CAPIF4

PWMIF5 PWM5_INT
CAPIF5
PWMB_INT
PWMIF6 PWM6_INT
CAPIF6

PWMIF7 PWM7_INT
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CAPIF7
PWM Sample Code

PWM Sample Code with Driver

Operation mode: DRVPWM_TOGGLE_MODE
Frequency: 250 Hz
Duty: 33/100=33%

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PWM Sample Code with Driver(1/2)
/*----------------------------------------------------------------------------
MAIN function
----------------------------------------------------------------------------*/
uint8_t volatile g_u8PWMCount = 100;
int32_t main (void)
{
S_DRVPWM_TIME_DATA_T sPt;
UNLOCKREG();
SYSCLK->PWRCON.XTL12M_EN = 1;
SysTimerDelay(5000);
SystemFrequency = 12000000;
DrvSYS_SetHCLKSource(0);
LOCKREG();
/* Enable PWM clock */
DrvPWM_Open();
/* Set PWM pins */
DrvGPIO_InitFunction(FUNC_PWM01);
/* PWM Timer property */
sPt.u8Mode = DRVPWM_TOGGLE_MODE;
sPt.u32Frequency =250;
/* High Pulse peroid : Total Pulse peroid = 33 : 100 */
sPt.u8HighPulseRatio = 33;
sPt.i32Inverter = 0;
/* Select PWM engine clock */
DrvPWM_SelectClockSource(DRVPWM_TIMER0, DRVPWM_HCLK);
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 PWM Sample Code with Driver(2/2)
/* Set PWM Timer0 Configuration */
DrvPWM_SetTimerClk(DRVPWM_TIMER0, &sPt);
/* Enable Output for PWM Timer0 */
DrvPWM_SetTimerIO(DRVPWM_TIMER0, 1);
/* Enable Interrupt Sources of PWM Timer0 and install call back function */
DrvPWM_EnableInt(DRVPWM_TIMER0, 0, DRVPWM_PwmIRQHandler);
/* Enable the PWM Timer 0 */
DrvPWM_Enable(DRVPWM_TIMER0, 1);
while (g_u8PWMCount);
/* Disable the PWM Timer 0 */
DrvPWM_Enable(DRVPWM_TIMER0, 0);
}
void DRVPWM_PwmIRQHandler()
{
if (g_u8PWMCount==1 )
{
DrvPWM_SetTimerCounter(DRVPWM_TIMER0, 0);
}
g_u8PWMCount--;
}

g_u8PWMCount 100 99 98 97 1 0

PWM output 33%

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4 ms
(250Hz)
Condition
Capture0
Input Channel:GPA12
Counter unit: 1usec (((11+1)*1)/12M)
Capture capability: 32 bits (hardware 16bits+ firmware 16bits)
PWM1
Output Channel:GPA13
Period: 1.049 sec (((11+1)*16*(65535+1))/12M)
High level: 262msec, Low level: 786msec
PWM2
Output Channel:GPA14
Period: 1365.3 usec (((1+1)*1*(8191+1))/12M)
High level: 682usec, Low level: 682usec
LCD
Display Capture0 result
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 Capture+PWM Block Diagram
LCD Panel
Capture demo
SPI High:683usec
Flash
Low: 683usec

Capture0

Cortex-M0
PWM1

PWM2
NUC140V3AN

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 Run “Smpl_Capture” Code

Customer_CD Readme.txt

NUC1xx BSP
NUC1xx_BSP Driver Reference Guide

NuvotonPlatform_Keil

Sample

NUC1xx-LB_002

Smpl_Capture Smpl_Capture.uvproj

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Q&A

Thank You

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