University of Engineering and Technology, Lahore

Department of Electrical Engineering

EE 213: Analog and Digital Electronics Circuits

Experiment 9
Roll No:2018-EE-317 Name: Hafiz Muhammad Sameer Jameel
Objective:
To design and study the operation of multi-vibrators using 555 timer IC.

Components Required:
IC 555 timer, Resistors (1KΩ×2, 10KΩ×2, 2.7KΩ), Variable resistor (10KΩ), Capacitors
(0.01uF, 0.047uF, 0.1uF, 1uF), and Diodes IN 4148×2.

Procedure:
Part 1: Astable Multi-vibrator
(a) For duty cycle more than 50%

1. Configure the circuit as per the circuit diagram.

2. Use RA=RB= 10KΩ, RL=1KΩ, CT= 0.1uF, C=0.01uF, and Vcc=10V.
3. Compute the expected values of fosc and duty cycle (%). Use the formulas given below.

4. Connect the output terminal (pin 3) to channel 1 of oscilloscope. Also feed the voltage
across capacitor to channel 2.
5. Power on the circuit. Determine the values of fosc and duty cycle (%) from your simulated
design observations and compare with theoretical values.
Theoretical Duty Cycle Calculation:
Time period:
Tosc = 0.693(𝑅𝐴 + 𝑅𝐵 )𝐶 + 0.692𝑅𝐵 𝐶
Tosc = 0.693(10𝑘 + 10𝑘)(0.1𝜇𝐹) + 0.693(10𝑘)(0.1𝑢𝐹)
Tosc = 2.079𝑚𝑠
Frequency:
1 1.44 1.44
𝑓𝑜𝑠𝑐 = = =
𝑇𝑜𝑠𝑐 (𝑅𝐴 + 2𝑅𝐵 )𝐶 (10𝑘 + 2(10𝑘))(0.1𝜇𝐹)
1
𝑓𝑜𝑠𝑐 = = 481𝐻𝑧
𝑇𝑜𝑠𝑐
On-Time:
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) = 0.693(𝑅𝐴 + 𝑅𝐵 )(𝐶)
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) = 0.693(10𝑘 + 10𝑘)(0.1𝜇𝐹)
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) = 1.386𝑚𝑠
Off Time:
𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 ) = 0.693(𝑅𝐵 )(𝐶)
𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 ) = (0.693)(10𝑘)(0.1𝜇𝐹)
𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 ) = 0.693𝜇𝑆
Duty-Cycle:
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 )
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) + 𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 )
1.386𝑋10−3
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
1.386𝑋10−3 + 6.93𝑋10−4
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 66.66%(𝑀𝑜𝑟𝑒 𝑇ℎ𝑎𝑛 50%)
Proteus Simulated Circuit:
Vcc
RA
10k
RL
A 1k
U1

8
B
3 4

VCC
Q R
C
7
DC
D
5
CV
RB
10k
C

GND
6 2 0.01uF
TH TR

1
CT 555
0.1uF

Simulated Output Waveform:

Duty-Cycle By Simulation:
Time Period = T = 2.04ms
1 1
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 = = = 485𝐻𝑧
𝑇 2.06𝑚𝑠
Pulse width
DutyCycle = 𝑋100
Time period
1.35𝑋10−3
𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 𝑋100
2𝑋10−3
𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 67.7%

(b) For duty cycle less than 50%

1. Configure the circuit as per the circuit diagram.

2. Use RA=2.7KΩ, RB= 10KΩ, RL=1KΩ, CT= 0.1uF, C=0.01uF, and Vcc=10V.
3. Compute the expected values of fosc and duty cycle (%). Use the formulas given
below.

4. Connect the output terminal (pin 3) to channel 1 of oscilloscope. Also feed the
voltage across capacitor to channel 2.
5. Power on the circuit. Determine the values of fosc and duty cycle (%) from your
simulated design observations and compare with theoretical values.
Theoretical Duty Cycle Calculation:
Time-period:
Tosc = 0.693(𝑅𝐴 + 𝑅𝐵 )𝐶
Tosc = 0.693(10𝑘 + 2.7𝑘)(0.1𝜇𝐹)
Tosc = 0.88𝑚𝑠

Frequency:
1 1.44 1.44
𝑓𝑜𝑠𝑐 = = =
𝑇𝑜𝑠𝑐 (𝑅𝐴 + 𝑅𝐵 )𝐶 (2.7𝑘 + 10𝑘)(0.1𝜇𝐹)
1
𝑓𝑜𝑠𝑐 = = 1133.85
𝑇𝑜𝑠𝑐

On-Time:
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) = 0.693(𝑅𝐴 + 𝑅𝐷 )(𝐶)
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) = 0.693(2.7𝑘 + 212)(0.1𝜇𝐹)
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) = 0.2018𝑚𝑠

Off Time:
𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 ) = 0.693(𝑅𝐵 )(𝐶)
𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 ) = (0.693)(10𝑘)(0.1𝜇𝐹)
𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 ) = 0.693𝑚𝑠

Duty-Cycle:
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 )
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
𝑂𝑛 𝑇𝑖𝑚𝑒(𝑇1 ) + 𝑂𝑓𝑓 𝑇𝑖𝑚𝑒(𝑇2 )
0.2018𝑋10−3
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
0.2018𝑋10−3 + 6.93𝑋10−4
𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 22.55%(𝐿𝑒𝑠𝑠 𝑇ℎ𝑎𝑛 50%)

𝑺𝒐 𝑫𝒖𝒕𝒚 𝑪𝒚𝒄𝒍𝒆 𝒊𝒔 𝒎𝒐𝒓𝒆 𝒕𝒉𝒂𝒏 𝟓𝟎%.

Proteus Simulated Circuit:
U1(VCC)

RL
RA 1k
U1

8
2.7k
3 4

VCC
A Q R
7
B DC
5
C CV
RB
D 10k D1 C
1N4007 0.01uF

GND
6 2
TH TR

D2

1
1N4007 555

CT
0.1uF

Simulated Output Waveform:

Duty-Cycle By Simulation:
Time Period = 𝑇 = 0.90ms
1 1
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 = = = 1111.11𝐻𝑧
𝑇 0.90𝑚𝑠

Pulse width
DutyCycle = 𝑋100
Time period
0.20𝑋10−3
𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 𝑋100
0.90𝑋10−3
𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 22.2%

(c) For duty cycle variable from 0 to 100%

1. Configure the circuit as per the circuit diagram.

2. Use R1=1KΩ, R2= 2.7KΩ, Rx=10KΩ, RL=1KΩ, CT= 0.047uF, C=0.01uF, and
Vcc=10V.
3. Calculate RA and RB for different values of potentiometer. Use the formulas given
below.
Theoretical Duty Cycle Calculation:
Time Period:
Tosc = 0.693(𝑅𝐴 + 𝑅𝐵 )𝐶
Tosc = 0.693(1𝑘 + 12.7𝑘)(0.047𝜇𝐹)
Tosc = 0.446𝑚𝑠

Frequency:
1 1.44 1.44
𝑓𝑜𝑠𝑐 = = =
𝑇𝑜𝑠𝑐 (𝑅𝐴 + 𝑅𝐵 )𝐶 (1𝑘 + 12.7𝑘)(0.047𝜇𝐹)
1
𝑓𝑜𝑠𝑐 = = 2236.37𝐻𝑧
𝑇𝑜𝑠𝑐

Minimum-Duty-Cycle:
𝑅1
𝑀𝑖𝑛𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
𝑅1 + 𝑅𝑋 + 𝑅2
1𝑘
𝑀𝑖𝑛𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
1𝑘 + 10𝑘 + 2.7𝑘
𝑀𝑖𝑛𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 7.299%(𝐿𝑒𝑠𝑠 𝑇ℎ𝑎𝑛 50%)

So Duty-Cycle is Less than 50%.

Maximum-Duty-Cycle:
𝑅1 + 𝑅𝑋
𝑀𝑎𝑥𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
𝑅1 + 𝑅𝑋 + 𝑅2
1𝑘 + 10𝐾
𝑀𝑎𝑥𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 𝑋100
1𝑘 + 10𝑘 + 2.7𝑘
𝑀𝑎𝑥𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦 𝐶𝑦𝑐𝑙𝑒 = 80.291%(𝐺𝑟𝑒𝑎𝑡𝑒𝑟 𝑇ℎ𝑎𝑛 50%)

So Duty Cycle is more than 50%.

Circuit For Maximum Duty Cycle:
R4(2)

R4
1k
RV1

R2

0%
1k
10k U1

8
3 4

VCC
A Q R
7
B DC
5
C CV
R3 D1
D 2.7k 1N4007

GND
6 2
TH TR
D2
1N4007 C1

1
555 0.01uF

C2
0.047uF

Simulated Output Waveform:

Circuit for Minimum Duty Cycle:
R4(2)

R4
1k
RV1

100%
R2
1k
10k U1

8
3 4

VCC
A Q R
7
B DC
5
C CV
R3 D1
D 2.7k 1N4007

GND
6 2
TH TR
D2
1N4007 C1

1
555 0.01uF

C2
0.047uF

Simulated Output Waveform:

Duty-Cycle By Simulation:
Time Period = 𝑇 = 0.50ms
1 1
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 = = = 2000𝐻𝑧
𝑇 0.50𝑚𝑠

Minimum. Pulse width

DutyCycle = 𝑋100
Time period
0.07𝑋10−3
𝑀𝑖𝑛𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 𝑋100
0.98𝑋10−3
𝑀𝑖𝑛𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 7.14%

Maximum. Pulse width

DutyCycle = 𝑋100
Time period
0.80𝑋10−3
𝑀𝑎𝑥𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 𝑋100
1𝑋10−3
𝑀𝑎𝑥𝑖𝑚𝑢𝑚. 𝐷𝑢𝑡𝑦𝐶𝑦𝑐𝑙𝑒 = 80%