PCF8833 1
PCF8833 1
DATA SHEET
PCF8833
STN RGB - 132 × 132 × 3 driver
Objective specification 2003 Feb 14
Philips Semiconductors Objective specification
2003 Feb 14 2
Philips Semiconductors Objective specification
3 ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
PCF8833U/2DA/1 − chip with bumps in tray −
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Philips Semiconductors Objective specification
4 BLOCK DIAGRAM
256/64 KBYTES
256
TO 4 KBYTES
COLOUR MPU INTERFACES
COLOUR
LUT
MAPPING
556 579, 624 518 549 551 550 552 553 554 548 547 545 543 541 546 544 542 540 497
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Philips Semiconductors Objective specification
5 PINNING
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Philips Semiconductors Objective specification
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Philips Semiconductors Objective specification
6 INSTRUCTIONS
The PCF8833 communicates with the host using an 8-bit parallel interface or a 3-line serial interface. Processing of
instructions and data sent to the interface do not require the display clock. The display clock and interface clock are
independent from each other. The display clock is derived from the built-in oscillator.
The PCF8833 has 2 types of accesses; those defining the operating mode of the device (instructions) and those filling
the display RAM. Since writing to the RAM occurs more frequently, efficient data transfer is achieved by
autoincrementing the RAM address pointers.
There are 3 types of instructions:
1. For defining display configuration
2. For setting X and Y addresses
3. Miscellaneous.
Commands in the range of 00H to AFH not defined in Table 1 and command DDH have the same effect as no operation
(NOP).
All commands in range B0H to B9H and DEH to FFH are forbidden.
2003 Feb 14 7
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Philips Semiconductors
STN RGB - 132 × 132 × 3 driver
D/C 7 6 5 4 3 2 1 0 DEFAULT OTP DESCRIPTION SECTION
0 0 0 0 0 0 0 0 0 00H − no operation (NOP) 6.2.1
0 0 0 0 0 0 0 0 1 01H − software reset (SWRESET) 6.2.3
0 0 0 0 0 0 0 1 0 02H − booster voltage off (BSTROFF) 6.2.4
0 0 0 0 0 0 0 1 1 03H − booster voltage on (BSTRON) 6.2.5
0 0 0 0 0 0 1 0 0 04H − read display identification 6.2.6
(RDDIDIF)
0 0 0 0 0 1 0 0 1 09H − read display status (RDDST) 6.2.7
0 0 0 0 1 0 0 0 0 10H − Sleep_IN 6.2.8
0 0 0 0 1 0 0 0 1 11H − Sleep_OUT 6.2.9
0 0 0 0 1 0 0 1 0 12H − Partial mode on (PTLON) 6.2.10
0 0 0 0 1 0 0 1 1 13H − normal Display mode on 6.2.11
(NORON)
0 0 0 1 0 0 0 0 0 20H − display inversion off (INVOFF) 6.2.12
0 0 0 1 0 0 0 0 1 21H − display inversion on (INVON) 6.2.13
0 0 0 1 0 0 0 1 0 22H − all pixel off (DALO) 6.2.14
8
Objective specification
0 0 0 1 0 1 1 0 0 2CH − memory write (RAMWR) 6.2.21
−
PCF8833
1 D7 D6 D5 D4 D3 D2 D1 D0 XXH write data 6.2.21
0 0 0 1 0 1 1 0 1 2DH − colour set (RGBSET) 6.2.22
1 X X X X R3 R2 R1 R0 00H − red tone 000 6.2.22
1 6 bytes for 6 red tones − 6 red tones 6.2.22
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2003 Feb 14
Philips Semiconductors
D/C 7 6 5 4 3 2 1 0 DEFAULT OTP DESCRIPTION SECTION
Objective specification
1 X X X X X P2 P1 P0 03H − colour interface format 6.2.30
x (2) set VOP (SETVOP) 6.2.31
PCF8833
0 1 0 1 1 0 0 0 0 B0H
1 X X X X VPR8 VPR7 VPR6 VPR5 08H x VOP 6.2.31
1 X X X VPR4 VPR3 VPR2 VPR1 VPR0 01H x VOP 6.2.31
0 1 0 1 1 0 1 0 BRS B4H x Bottom Row Swap (BRS) 6.2.32
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2003 Feb 14
Philips Semiconductors
D/C 7 6 5 4 3 2 1 0 DEFAULT OTP DESCRIPTION SECTION
Objective specification
1 X X X X VB3 VB2 VB1 VB0 0BH x bias systems 6.2.43
− 6.2.44
PCF8833
0 1 1 0 0 1 0 0 0 C8H temperature read back
(RDTEMP)
0 1 1 0 0 1 0 0 1 C9H − N-Line Inversion (NLI) 6.2.45
1 NLI7 NLI6 NLI5 NLI4 NLI3 NLI2 NLI1 NLI0 13H x after NLI time slots inversion 6.2.45
0 1 1 0 1 1 0 1 0 DAH x read ID1 (RDID1) 6.2.46
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2003 Feb 14
Philips Semiconductors
D/C 7 6 5 4 3 2 1 0 DEFAULT OTP DESCRIPTION SECTION
Objective specification
PCF8833
Philips Semiconductors Objective specification
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Philips Semiconductors Objective specification
6.2.2 RESET After a reset, care must be taken with respect to the reset
timing constraints (see Fig.50) when the PCF8833 is
The PCF8833 has a hardware and a software reset. After
powered-up. The power-up must be done by sending the
power-up a hardware reset (pin RES) must be applied; see
Sleep_OUT command.
Fig.50. The hardware and software resets give the same
results. After a reset, the chip has the following state: After a power-up the display RAM content is undefined.
• All LCD outputs are set to VSS (display off) Neither a hardware reset nor a software reset changes the
data that is stored in the display RAM. Sending display
• RAM data unchanged
data must stop 160 ns before issuing a hardware reset,
• Power-down mode (Sleep_IN) otherwise the last word written to the display RAM may be
• Command register set to default states; see Table 4 corrupted. The row and column outputs are tied to VSS1
with a reset because power-down (Sleep_IN) is in the
• Interface pins are set to inputs.
reset state.
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Philips Semiconductors Objective specification
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Philips Semiconductors Objective specification
6.2.4 BOOSTER VOLTAGE OFF Command Sleep_IN does not effect the setting of
BSTRON/BSTROFF or DISPON/DISPOFF, but switches
The DC-to-DC converters are turned off and pins
off the DC-to-DC converter (booster) and ties the display
VLCDOUT1 and VLCDOUT2 become 3-state.
outputs to VSS1.
In order to avoid any optical effect on the display, the
For the effect of possible combinations of commands
sequence given in Fig.2 must be used before the internal
Sleep_IN/Sleep_OUT and BSTRON/BSTROFF; see
display supply generation circuits are turned off.
Table 17 and Fig.4. Figure 7 shows the effects of the
The external LCD supply input voltages (VLCDIN1 and combination of commands BSTRON and BSTROFF with
VLCDIN2) can be applied while the display voltage DISPON and DISPOFF.
generation (BSTROFF) is off. When BSTROFF, DISPON
and Sleep_OUT are set, the external LCD supply input
voltages (VLCDIN1 and VLCDIN2) must be applied, otherwise
the display outputs will be undefined.
handbook, halfpage
start
end
MGU911
2003 Feb 14 15
Philips Semiconductors Objective specification
6.2.5 BOOSTER VOLTAGE ON The status of the LCD supply generation circuits can be
monitored with the read display status (RDDST)
The LCD supply generation circuits will be switched on
command; see Section 6.2.7.
when the Booster voltage on (BSTRON) command is sent.
The BSTRON command has a direct effect only when the Figure 3 shows two sequences for using the BSTRON
PCF8833 is not in Power-down mode (Sleep_OUT is not command, assuming BSTROFF and DISPOFF were set
active). before sending Sleep_OUT. In sequence A the command
to switch the display on (DISPON) is sent to the PCF8833
With a reset DISPON (see Section 6.2.18) and BSTRON
before the BSTRON command is sent. Therefore the
are set, the PCF8833 will start-up with Sleep_OUT (see
display will only be switched on when the LCD supply
Section 6.2.7) following the built-in start-up sequence
generation circuit generates a stable VLCD. In sequence B
which generates the requested voltages and switches on
the RDDST command is used to monitor the LCD supply
the display, unless DISPOFF and/or BSTROFF was sent.
generation circuit and, after the D31 bit of the RDDST is
When the LCD supply generation circuits are switched on,
set to logic 1, the DISPON command will be sent;
it is necessary to wait for a certain time before the power
see Section 6.2.7.
circuits become stable and the display can be switched on.
Because this time is dependent on the required VLCD For the effect of possible combinations of commands
voltage, the external components used, the applied supply Sleep_IN/Sleep_OUT and BSTRON/BSTROFF; see
voltage and some other parameters, the PCF8833 Table 17 and Fig.4. Figure 7 shows the effects of the
monitors the LCD supply generation circuit internally and combination of commands BSTRON and BSTROFF with
will only switch-on the display when the LCD supply DISPON and DISPOFF.
generation circuits are stable.
monitor D [31]
RDDST 09H D31 = 0
LCD will be switched on
when LCD supply D31 = 1
generation circuit
is stable send DISPON 29H
end end
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Philips Semiconductors Objective specification
6.2.6 READ DISPLAY IDENTIFICATION INFORMATION When less than 25 read clock cycles are sent in Serial
mode, the identification information read must be
The Read Display Identification Information (RDDIDIF)
interrupted by a hardware reset or rising edge of SCE.
command returns a 24-bit display identification
information. The identification information is valid only The definition of the display identification bits is given in
5 ms after applying a hardware reset. Therefore the Table 11.
RDDIDIF command should not be sent earlier than 5 ms
after a hardware reset.
The input and output data format is given in Table 9. After
the command byte 04H is sent, the read starts with one
dummy clock cycle followed by the 3 status bytes (see
Fig.47).
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 0 0 0 1 0 0 04H
Note
1. RDID3 will be programmed in OTP cells. This ID can be set to 03H by the module maker.
2003 Feb 14 17
Philips Semiconductors Objective specification
6.2.7 READ DISPLAY STATUS When less than 33 read clock cycles are sent in Serial
mode the status read must be interrupted by a hardware
The Read Display Status (RDDST) command returns a
reset or a rising edge of SCE.
32-bit display status information and can be accessed
when the PCF8833 is in normal Display mode (see The definition of the display status bits is given in Table 11.
Section 6.2.11), in partial Display mode (see
Section 6.2.23) or in Sleep_IN mode; see Section 6.2.8.
The input and output data format is as follows: After the
command byte 09H is sent, the read starts with one
dummy clock cycle followed by the 4 status bytes (see
Fig.48).
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 0 0 1 0 0 1 09H
1 X X X X X X X X XX
1 D31 D30 D29 D28 D27 D26 0 0 XX
1 0 D22 D21 D20 D19 D18 D17 D16 XX
1 D15 0 D13 D12 D11 D10 D9 0 XX
1 0 0 0 0 0 0 0 0 XX
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Philips Semiconductors Objective specification
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Philips Semiconductors Objective specification
6.2.8 SLEEP_IN While in Sleep_IN mode all commands and data can be
sent and will be executed as in the Sleep_OUT state,
By sending the Sleep_IN command, the PCF8833
except some OTP related commands and temperature
immediately enters the Power-down mode, also referred to
readout related commands. In the Sleep_IN mode no
as the Sleep mode. In the Sleep mode the output voltages
effect on the display can be seen.
of all LCD driver pins (rows and columns) are at VSS1
(ground, all pixels are in off state), and the LCD supply The Sleep_IN mode is exited by command Sleep_OUT;
generation circuit and the oscillator are switched off. The see Section 6.2.9.
Sleep_IN command does not change the state of the
DISPON/DISPOFF and BSTRON/BSTROFF commands,
but has the same effect as DISPOFF and BSTROFF;
see Table 17.
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 0 1 0 0 0 0 10H
Note
1. Booster is the built-in DC-to-DC converter also called voltage multiplier or charge pump.
2003 Feb 14 20
Philips Semiconductors Objective specification
Sleep_IN
D31 = 0
send Sleep_OUT
Sleep_OUT
BSTROFF
booster
BSTRON
booster on
D31 = 0
wait for D31 bit
D31 = 1
DISPOFF
display
DISPON
ready
display on display off
MGU913
Fig.4 Start-up, when leaving Power-down mode (i.e. after sending Sleep_OUT).
2003 Feb 14 21
Philips Semiconductors Objective specification
6.2.10 PARTIAL MODE ON A normal Display mode command is used to exit the Partial
mode. How the partial display area can be programmed is
Partial mode on (PTLON) turns on the partial Display
given in Section 6.2.23.
mode. Only one partial display size can be chosen. Normal
mode, Scroll mode, DALO and DAL are exited with this A sequence showing how the command PTLON can be
command. When sending DAL after PTLON, only the used is illustrated in Fig.5.
pixels of partial area are driven on.
send PTLAR
send DISPOFF
partial area def
display off
send PTLON
wait until
display supply
partial mode on
voltage is settled
send DISPON
optional
send PTLAR
display on
MGU914
(1) If the initial state is Sleep_IN, the same sequence is valid, but Sleep_OUT has to be sent to see the effect on the display (after display voltage has
settled).
When sending DAL after PTLON, only the pixels of partial area are driven on. When sending INVON, in Partial mode only the pixels of partial area are
inverted. INVON is over-ruled by DAL and DALO. Pixels outside partial area always stay off.
2003 Feb 14 22
Philips Semiconductors Objective specification
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 1 0 0 0 0 0 20H
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 1 0 0 0 0 1 21H
2003 Feb 14 23
Philips Semiconductors Objective specification
6.2.15 ALL PIXELS ON When sending DAL after PTLON, only the pixels of the
partial area are driven on. When sending INVON in Partial
The All pixels on command (DAL) can be switched off by
mode only the pixels of the partial area are inverted.
sending the normal display on command (NORON); (see
INVON is over-ruled by DAL and DALO. Pixels outside the
Section 6.2.11) or by sending the partial Display mode on
partial are always off. Figure 6 illustrates how DAL (all
command (PTLON); see Section 6.2.10. Furthermore DAL
pixels on) and DALO (all pixels off) can be used.
is left with the command DALO; see Section 6.2.14. When
DAL is active all pixels are driven, as if the display RAM All pixels will be switched on regardless of the display data
was filled with all ones (on-state). DAL does not change RAM.
the data stored in the display RAM.
MGU915
(1) If the initial state is Sleep_IN, the same sequence is valid, but Sleep_OUT has to be sent to see the effect on the display (after display voltage
has settled).
When sending DAL after PTLON, only the pixels of partial area are driven on. When sending INVON, in Partial mode only the pixels of partial area
are inverted. INVON is over-ruled by DAL and DALO. Pixels outside partial area always stay off.
2003 Feb 14 24
Philips Semiconductors Objective specification
6.2.18 DISPLAY ON
Using the Display on command (DISPON) the rows and columns are driven according to the current display data RAM
content and according to the display timing and settings.
The DISPON command is used to exit the DISPOFF state; see Section 6.2.17.
Figure 4 gives additional information on the effect of the DISPON/DISPOFF command. Figure 7 shows the effects of the
combination of commands BSTRON and BSTROFF with DISPON and DISPOFF.
2003 Feb 14 25
Philips Semiconductors Objective specification
booster on display on
Booster off
send DISPOFF
display off
D31 = 0 (2)
booster off
Booster on
send BSTRON
booster on
D31 = 0
wait for D31 bit
D31 = 1
send DISPON
display on
MGU916
(1) When an external VLCD is applied, BSTROFF needs to be sent after reset (default = booster on). The setting of Display
mode (Partial mode, Scroll mode, etc.) is not affected by sending DISPON/DISPOFF.
(2) D31 is the booster voltage status bit; see Section 6.2.7.
2003 Feb 14 26
Philips Semiconductors Objective specification
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Philips Semiconductors Objective specification
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Philips Semiconductors Objective specification
The following steps must be followed to enter the Partial When setting the addresses the following conditions must
mode: be ensured:
• Set VOP (when the MMOTP cells are used the VOP for • (AA1E + 1) − AA1S = 32 (only 1 partial display size
the Partial mode is predefined) setting is possible)
• Set bias system (when the MMOTP cells are used the • AA1 ≥ 0 and AA1E ≤ 131.
bias system for the Partial mode is predefined) Figure 8 shows how to use the Partial mode with Line
• Set start address of active area AA1S[7:0]; can be set in Address Order (LAO) set to logic 0. Figure 9 gives an
multiples of 4 example of Partial mode with LAO set to logic 1, and
• Set end address of active area AA1E[7:0] + 1; can be Fig.10 shows the position of the partial area when the start
set in multiples of 4 address of the active area is AA1S ≥ (131 + 1) − 31, i.e.
AA1S ≥ 101 (AA1S must be set in multiples of 4).
• Enter Partial mode (PTLON).
Figure 11 shows how the Partial mode can be used.
partial area 10
11
ROW 10
ROW 11
partial area
12 ROW 12
13 ROW 13
32
rows 24 ROW 24
25 ROW 25
26 ROW 26
27 ROW 27
28 ROW 28
29 ROW 29
30 ROW 30
31 ROW 31
32 ROW 32
33 ROW 33
34 ROW 34
35 ROW 35
AA1E [7:0] +1 = 36 36 ROW 36
37 ROW 37
38 ROW 38
39 ROW 39
40 ROW 40
41 ROW 41
42 ROW 42
MGU917
2003 Feb 14 29
Philips Semiconductors Objective specification
partial area 10
11
ROW 10
ROW 11
partial area
12 ROW 12
13 ROW 13
32 24 ROW 24
rows 25 ROW 25
26 ROW 26
27 ROW 27
28 ROW 28
29 ROW 29
30 ROW 30
31 ROW 31
32 ROW 32
33 ROW 33
34 ROW 34
35 ROW 35
36 ROW 36
AA1S [7:0] = 96 37 ROW 37
38 ROW 38
39 ROW 39
40 ROW 40
41 ROW 41
42 ROW 42
MGU918
2003 Feb 14 30
Philips Semiconductors Objective specification
27 ROW 27
AA1E [7:0] +1 = 28 28 ROW 28
29 ROW 29
30 ROW 30
31 ROW 31
32 ROW 32
33 ROW 33
34 ROW 34
35 ROW 35
36 ROW 36
37 ROW 37
38 ROW 38
39 ROW 39
40 ROW 40
41 ROW 41
42 ROW 42
43 ROW 43
44 ROW 44
45 ROW 45
46 ROW 46
47 ROW 47
48 ROW 48
49 ROW 49
50 ROW 50
51 ROW 51
52 ROW 52
53 ROW 53
MGU919
2003 Feb 14 31
Philips Semiconductors Objective specification
send PTLAR
send DISPOFF
partial area def
display off
send PTLON
wait until
display supply
partial mode on
voltage is settled
send DISPON
optional
send PTLAR
display on
MGU920
(1) If the initial state is Sleep_IN, the same sequence is valid, but Sleep_OUT has to be sent to see the effect on the display (after the display
voltage has settled).
When sending DAL after PTLON, only the pixels of partial area are driven on. When sending INVON, in Partial mode only the pixels of partial area
are inverted. INVON is over-ruled by DAL and DALO. Pixels outside partial area always stay off.
2003 Feb 14 32
Philips Semiconductors Objective specification
handbook, full pagewidth centre screen scroll bottom screen scroll top screen scroll whole screen scroll
MGU921
Scrolling area
2003 Feb 14 33
Philips Semiconductors Objective specification
send VSCRDEF
send SEP
scroll mode on
normal display
send VSCRDEF
send SEP
scroll mode on
MGU922
(1) If the initial state is Sleep_IN, the same sequence is valid, but Sleep_OUT has to be sent to see the effect on the display (after the
display voltage has settled).
2003 Feb 14 34
Philips Semiconductors Objective specification
6.2.24.1 Rolling Scroll mode Figure 15 gives an example for when the PCF8833 is
working in the rolling Scroll mode.
The RAM-to-display mapping for the rolling Scroll mode
when a 132 × 130 (columns × rows) display is connected When the rolling Scroll mode is used the following
to the PCF8833 is illustrated in Fig.14. In this case rows sequence can be applied:
0 and 131 must be left open. When a 132 × 132 display is • After the desired time interval increment the scroll
connected, there will be a one-to-one mapping between address to SEP + n for a n-line step
the RAM and the display, and there will be no unused
rows. • Keep incrementing the scroll address (SEP) at regular
intervals.
The rolling Scroll mode is activated when the Set Entry
Scroll Point (SEP) is set; see Table 35. The rolling Scroll mode is left when the normal Display
mode on (NORON) or the partial Display mode on
(PTLON) is selected.
SA [7:0]
SA [7:0]
121 120
2 unused 122 121
rows 123 124
124 125
125 126
126 127
127 128 BF [7:0]
BF [7:0] 128 129
129 130
130 131
131 131
MGU923
Fig.14 RAM to display mapping for the rolling Scroll mode (TF + SA + BF = 130) for LAO = 0.
2003 Feb 14 35
Philips Semiconductors Objective specification
SEP [7:0]
SA = 114
120
121
8
9
121
2 unused 122 SEP − 1
rows 123 124
124 125
125 126
126 127
127 128 BF = 8
BF = 8 128 129
129 130
130 131
131 131
MGU924
2003 Feb 14 36
Philips Semiconductors Objective specification
6.2.24.2 Non-rolling Scroll mode An example is given in Figure 17 for the case when the
PCF8833 is working in the non-rolling Scroll mode
The RAM-to-display mapping for the non-rolling Scroll
(TF + SA + BF = 131).
mode when a 132 × 130 (columns × rows) display is
connected to the PCF8833 is illustrated in Fig.16. In this When the non-rolling Scroll mode is used the following
case unused rows and columns are to be left open, for sequence can be applied:
instance row 0 and 131. If a 132 × 132 display is • Fill the background memory
connected to the PCF8833 the content of row 0 and 131
will be the same as the content which is displayed in row 1 • After the desired time interval increment the scroll
address to SEP + n for a n-line step
and 130, respectively. By doing so, the display data RAM
will have 1 row in the background, whose content can be • Keep filling the background memory and incrementing
updated when it is not displayed. scroll address (SEP) at regular intervals to obtain a
smooth scrolling.
The non-rolling Scroll mode is activated when the Set
Entry Scroll point is set; see Table Fig.36. The non-rolling Scroll mode is left when the normal Display
mode on (NORON) or the partial Display mode on
(PTLON) is selected.
SA [7:0] SA [7:0] − 1
MGU925
Fig.16 RAM to display mapping for the non-rolling Scroll mode (TF + SA + BF = 131) for LAO = 0.
2003 Feb 14 37
Philips Semiconductors Objective specification
1 buffer row
SEP [7:0]
SA − 1 = 114
121
122
8
9
MGU926
6.2.24.3 Non-rolling Scroll mode When the non-rolling Scroll mode is used the following
sequence can be applied.
The RAM-to-display mapping for the non-rolling Scroll
mode when a 132 × 130 (columns × rows) display is • Fill the background memory
connected to the PCF8833 is illustrated in Fig.18. In this • After the desired time interval increment the scroll
case unused rows and columns are to be left open, for address to SEP + n for a n-line step
instance row 0 and 131. If a 132 × 132 display is
• Keep filling the background memory and incrementing
connected to the PCF8833 the content of row 0 and 131
scroll address (SEP) at regular intervals to obtain a
will be the same as the content which is displayed in row smooth scrolling.
1 and 130, respectively. By doing so the display data RAM
will have 2 rows in the background, whose content can be The non-rolling Scroll mode is left when the normal Display
updated when they are not displayed. mode on (NORON) or the partial Display mode on
(PTLON) is selected.
The non-rolling Scroll mode is activated when the Set
Entry Scroll Point is set; see Table Fig.37.
Figure 19 shows an example for when the PCF8833 is
working in the non-rolling Scroll mode
(TF + SA + BF = 132).
2003 Feb 14 38
Philips Semiconductors Objective specification
SA [7:0] SA [7:0] − 2
121 120
2 buffer 122 121
rows 123 124
124 125
125 126
126 127
127 128 BF [7:0]
BF [7:0] 128 129
129 130
130 131
131 131
MGU927
Fig.18 RAM to display mapping for the non-rolling Scroll mode (TF + SA + BF = 132) for LAO = 0.
2003 Feb 14 39
Philips Semiconductors Objective specification
2 buffer rows
SEP [7:0]
SA − 2 = 114
122
123
8
9
121
122 SEP − 3
123 124
124 125
125 126
126 127
127 128 BF = 8
BF = 8 128 129
129 130
130 131
131 131
MGU928
2003 Feb 14 40
Philips Semiconductors Objective specification
123
8
9
SA − 2 = 114
SEP [7:0]
2 buffer rows
SEP − 1
SEP
123 124
124 125
125 126
126 127
127 128 TF = 8
TF = 8 128 129
129 130
130 131
131 131
MGU929
2003 Feb 14 41
Philips Semiconductors Objective specification
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 1 1 0 1 0 1 35H
1 X X X X X X X X 00H
Note
1. X = don’t care.
TE signal
850 µs MGU930
2003 Feb 14 42
Philips Semiconductors Objective specification
Note
1. Refer to Section 6.2.24.4 for an explanation of LAO on scroll modes and to Section 6.2.23 for an explanation of LAO
on Partial mode.
The relationship between RAM and display for the MX, MY, RGB and LAO control bits is illustrated Fig.22.
Combinations of MX, MY and V are described in more detail in Section 7.2.
D3 = 0:RGB
D3 = 1:BGR
D7 = 0 D7 = 1 D4 = 0 D4 = 1
0 131 0,0 0 131
1 1
2 2
page address
row drivers
RAM
2 2
1 1
131 0 131 0
D6 = 0 0 1 2 131
D6 = 1 131 2 1 0
2003 Feb 14 43
Philips Semiconductors Objective specification
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 1 1 1 0 0 1 39H
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 0 0 1 1 1 0 1 0 3AH
1 X X X X X P2 P1 P0 03H
Note
1. X = don’t care.
2003 Feb 14 44
Philips Semiconductors Objective specification
Table 45 Interface formats The generated VLCD can be calculated with equation (1).
Figure 24 is the graphical equivalent to equation (1).
INTERFACE
P2 P1 P0 V LCD = a + 〈 MMVOPCAL [ 5:0 ] + VCON [ 6:0 ] + (1)
FORMATS
V PR [ 8:0 ]〉 × b
0 0 0 no action
0 0 1 no action Where:
• a is a fixed constant value; see Table 47
0 1 0 8-bit/pixel(1)
• b is a fixed constant value; see Table 47
0 1 1 12-bit/pixel(2)
• VPR[8:0] is the programmed VOP value; the
1 0 0 no action
programming range for VPR[8:0] is 5 to 410 (19AH)
1 0 1 16-bit/pixel(3)
• MMVOPCAL[5:0] is the value of the offset stored in the
1 1 0 no action OTP cells in twos complement format; see Section 15.1
1 1 1 no action • VCON[6:0] is the set contrast value which can be set via
Notes the interface and is in twos complement format; see
Section 6.2.16.
1. PCF8833 is switched into 256 colour mode,
256 colours are mapped to the 4 kbyte RAM with a The VOP[8:0] value must be in the VLCD programming
LUT; see Section 6.2.22. range as shown in Fig.24. Evaluating equation (1), values
outside of the programming range indicated in Fig.24 may
2. PCF8833 is switched into 4 kbyte colour mode, which
result. Calculated values below 0 will be mapped to
is also the reset state.
VOP = 0; resulting VOP values higher than 445 will be
3. PCF8833 is switched into 64 kbyte colour mode, which mapped to VOP = 445. An overview of the complete
is achieved by means of dithering. programming range of VLCD can be found in Section 15.1.
6.2.31 SET VOP As the programming range for the internally generated
VLCD allows values above the maximum allowed VLCD
The set VOP command (SETVOP) is used to program the (20 V) the user has to ensure, while setting the VPR
optimum LCD supply voltage VLCD. register and selecting the temperature compensation, that
The reset state of VPR[8:0] is 257DEC (13.88 V). under all conditions and including all tolerances the VLCD
remains below 20 V.
The optimum LCD supply voltage can be calculated as
explained in Section 6.2.43. The VOP value is programmed
via the VPR register. Besides the VPR register the VOP
value can be calibrated by means of OTP cells or changed
with the VCON register (see Fig.23).
D/C D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
0 1 0 1 1 0 0 0 0 B0H
1 X X X X VPR8 VPR7 VPR6 VPR5 08H
1 X X X VPR4 VPR3 VPR2 VPR1 VPR0 01H
Note
1. X = don’t care.
2003 Feb 14 45
Philips Semiconductors Objective specification
b a
8 7 6 5 4 3 2 1 0 VCON [6:0] MMVOPCAL [5:0]
VOP [8:0]
VLCD
MGU932
V LCD
00 01 02 03 04 05 06 ... V OP
410DEC
2003 Feb 14 46
Philips Semiconductors Objective specification
D/C D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
0 1 0 1 1 0 1 1 TRS B6H
2003 Feb 14 47
Philips Semiconductors Objective specification
32 rows 32 rows
95 64 columns 0 31
31
32
63
64 DISPLAY
95
96
131
MGU934
31
32
63
64 DISPLAY
95
96
131
MGU935
2003 Feb 14 48
Philips Semiconductors Objective specification
64 95 columns 32 0
32 rows 32 rows
31
32
63
64 DISPLAY
95
96
131
MGU936
64 95 columns 31 0
32 rows 32 rows
31
32
63
64 DISPLAY
95
96
131
MGU937
2003 Feb 14 49
Philips Semiconductors Objective specification
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 1 0 1 1 1 0 1 DOR BAH
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Philips Semiconductors Objective specification
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 1 0 1 1 1 1 1 TCVOPE BFH
2003 Feb 14 51
Philips Semiconductors Objective specification
Note
1. X = don’t care.
Note
1. Reset state.
Note
1. X = don’t care.
2003 Feb 14 52
Philips Semiconductors Objective specification
Note
1. X = don’t care.
Note
1. For the reset state refer to Table 4. Values overwritten by OTP.
VLCD
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Philips Semiconductors Objective specification
TEMPERATURE TD 8 OFFSET 8
READOUT zero VT
offset
b a
VCON [5:0] MMVOPCAL [5:0]
VOP [8:0] 9
VPR [8:0] VLCD
MGU939
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Philips Semiconductors Objective specification
6.2.41 FRAME FREQUENCY PROGRAMMING Where fosc is the oscillator frequency which is defined in
Chapter 13.
The PCF8833 incorporates temperature segmented
Frame frequency programming (TCDF). The temperature The Divider Factor (DF) is a 7-bit number so the upper
range is split into 4 areas as shown in Fig.31. programming range is limited to 127DEC resulting in a
minimum frame frequency of 35.8 Hz. The lower
In each of the segments a Division Factor (DF) can be
programming range is limited to 20DEC resulting in a
programmed which determines the Frame Frequency
maximum frame frequency of 227 Hz. The frame
(FF). In equation (2) the frame frequency can be
frequency is derived from the built-in oscillator, and thus
calculated from a given division factor.
the tolerance of the frame frequency has the same ratio as
1
---------- × f osc that given for the oscillator frequency; see Chapter 13.
132
FF = -------------------------- (2)
DF When Partial mode is selected (see Sections 6.2.10 and
6.2.23) the same segmented frame frequencies will be
used as for the full Display mode.
Note
1. X = don’t care.
2003 Feb 14 55
Philips Semiconductors Objective specification
frame
frequency
Note
1. X = don’t care.
2003 Feb 14 56
Philips Semiconductors Objective specification
When the required bias system (a) is defined, the LCD The bias voltages needed in a MRA LCD driver depends
supply voltage for a display size N can be determined; see on the number of simultaneous selected rows (P). The
equation (4). bias voltages of the PCF8833 are given for P = 4 and
N P = 1; see Fig.32. In the PCF8833 the maximum column
V LCD = 2a × V ON × --------------------------------------
2
- (4) voltage (GMAX) is always lower or equal to the row
P ( a + N + 2a ) voltage F.
The parameter P in equation (4) is the number of
simultaneous selected rows. For the maximum number of
rows of 132, P = 4 is chosen. When partial Display mode
is selected the P value is set to 1 internally.
V1H
VC VC VC VC
V1L
V2L −Gmax V2L −Gmax
VSS −F VSS −F
P=4 P=1
MGU941
The bias voltage levels are a function of the row voltage The value of F is determined by (α + 2) × R and the value
F and a: of Gmax is determined by 2 × R.
2003 Feb 14 57
Philips Semiconductors Objective specification
Notes
1. For Partial mode internally P = 1 is set, otherwise P = 4 is selected. Limitations for Partial mode given in
Section 6.2.43.2 for respectively for full Display mode given in Section 6.2.43.1 have to be taken into account.
2. Reset state.
D/C 7 6 5 4 3 2 1 0 DEFAULT
0 1 1 0 0 0 1 1 1 C7H
1 X X X X VB3 VB2 VB1 VB0 0BH
Note
1. X = don’t care.
VLCD1: 5.5 to 11 V
6.2.43.2 Limitations on bias voltages in Partial mode
VLCD2: 10 to 20 V
VDD1: 1.5 to 3.3 V
(VLCD2 − VLCD1): 4.5 to 9 V
VLCD1: 2.9 to 12 V
V LCD2
--------------- – V LVD1 = 0 to 1 V
VLCD2: 3.8 to 12 V
2 -
( V LCD2 – V LCD1 ) max = 0.5 V
but for VLCD2: 10 to 11 V:
2003 Feb 14 58
Philips Semiconductors Objective specification
2003 Feb 14 59
Philips Semiconductors Objective specification
Note
1. X = don’t care.
Note
1. X = don’t care.
2003 Feb 14 60
Philips Semiconductors Objective specification
7 FUNCTIONAL DESCRIPTION
7.1 MPU interfaces
The PCF8833 can interface to a microcontroller with an 8-bit parallel or a serial interface to transmit both data and
commands to the PCF8833.
Note
1. X = don’t care.
MGU942
2003 Feb 14 61
Philips Semiconductors Objective specification
7.1.3 DISPLAY DATA FORMATTING There are 2 bytes used to transfer 1 pixel with the 16-bit
colour depth information; see Table 83. The most
Different display data formats are available because
significant bits are R4, G5 and B4. When the data transfer
different colour depths are supported by the PCF8833.
is stopped after the first write, the data is not transferred to
The colour depths supported are as follows:
the display data RAM. The 16-bit data coming from the
• 4 kbyte colours (12-bit/pixel), RGB 4 : 4 : 4 bits input; interface is mapped by means of dithering to 12-bit data.
see Table 82. The data coming from the interface is The dithered 12-bit data is then stored in the RAM.
directly stored in RAM.
In one byte, 1 pixel is transferred with the 8-bit colour
• 65 kbyte colours (16-bit/pixel), RGB 5 : 6 : 5 bits input;
depth information; see Table 84. The most significant bits
see Table 83. The 16-bit data coming from the interface
are R2, G2 and B1. The 8-bit data coming from the
is mapped by means of dithering to 12-bit data. The interface is mapped by means of a look-up table (see
dithered 12-bit data is then stored in the RAM.
Section 6.2.22) to 12-bit data. The mapped 12-bit data is
• 256 colours (8-bit/pixel), RGB 3 : 3 : 2 bits input; see then stored in the RAM.
Table 84. The 8-bit data coming from the interface is
mapped by means of the Look-Up Table (LUT) (see
Section 6.2.22) to 12-bit data. The mapped 12-bit data
is then stored in the RAM.
There are 3 bytes used to define 2 pixels with the 12-bit
colour depth information; see Table 82. The most
significant bits are R3, G3 and B3. Data is transferred to
the RAM only when all the information i.e. RGB data of that
particular pixel is sent.
BYTE D/C 7 6 5 4 3 2 1 0
1st write 1 R4 R3 R2 R1 R0 G5 G4 G3
2nd write 1 G2 G1 G0 B4 B3 B2 B1 B0
BYTE D/C 7 6 5 4 3 2 1 0
1st write 1 R2 R1 R0 G2 G1 G0 B1 B0
2003 Feb 14 62
Philips Semiconductors Objective specification
7.2.2 RAM ACCESS ARBITER For example, if the whole display content is written, the
window will be defined by the following values: xs = 0 (0H),
The function of the arbiter is to handle the data flow. If a
ys = 0 (0H), xe = 131 (83H) and ys = 131 (83H).
write access is done on the RAM and a read access is
requested at the same time, then the arbiter will ensure In the vertical addressing mode (V = 1), the Y address
that there are no data collisions. Writing data to the RAM increments after each pixel. After the last Y address
has priority. Therefore no handshaking is done at the (Y = ye), Y wraps around to ys and X increments to
interface side and the data can be applied to the interface address the next column. In horizontal addressing mode
without having data read/write errors on the RAM. (V = 0), the X address increments after each pixel. After
the last X address (X = xe), X wraps around to xs and
7.2.3 WR ADDRESS COUNTER Y increments to address the next row. After the very last
address (X = xe and Y = ye) the address pointers wrap
The address counter sets the addresses of the display
around to address (X = xs and Y = ys).
data RAM for writing.
For flexibility in handling a wide variety of display
Data is written pixel wise into the RAM of the PCF8833.
architectures, the command ‘Memory Data Access
The data for one pixel is collected (RGB 4 : 4 : 4 bit) before
Control (MADCTL)’ (see Section 6.2.27) defines flags
it is written into the display data RAM. The RAM locations
MX and MY, which allows mirroring of the X and
are addressed by the address pointers. The address
Y addresses. All combinations of flags are allowed.
ranges are X = 0 to X = 131 (83H) and Y = 0 to
Figures 34, 35 and 36 show the possible combinations of
Y = 131 (83H). Addresses outside of these ranges are not
writing to the display RAM. When MX, MY and V is
allowed.
changed, the data must be re-written to the display RAM.
Before writing to the RAM a window must be defined into
which data will be written. The window is programmable 7.2.4 DISPLAY ADDRESS COUNTER
via the command registers xs and ys (designating the start
The display address counter generates the addresses for
address) and xe and ye (designating the end address).
readout of the display data RAM.
xs xe MGU943 xs xe MGU944
handbook, halfpage
0 handbook, halfpage
0
ys ys
Y address
Y address
ye ye
131 131
V = 0; MX = 0 and MY = 0. V = 1; MX = 0 and MY = 0.
Fig.34 Sequence of writing data bytes into RAM showing function of V bit.
2003 Feb 14 63
Philips Semiconductors Objective specification
xs xe MGU945 xe xs MGU946
handbook, halfpage
0 handbook, halfpage
0
ys ys
Y address
Y address
ye ye
131 131
V = 0; MX = 0 and MY = 1. V = 0; MX = 1 and MY = 0.
xs xe MGU947 xe xs MGU948
handbook, halfpage
131 handbook, halfpage
131
ye ye
Y address
Y address
ys ys
0 0
V = 0; MX = 0 and MY = 0. V = 0; MX = 1 and MY = 1.
Fig.35 Sequence of writing data bytes into RAM with horizontal addressing (V = 0) showing function MX and MY.
2003 Feb 14 64
Philips Semiconductors Objective specification
xs xe MGU949 xe xs MGU950
handbook, halfpage
0 handbook, halfpage
0
ys ys
Y address
Y address
ye ye
131 131
V = 1; MX = 0 and MY = 0. V = 1; MX = 1 and MY = 0.
xs xe MGU951 xs xe MGU952
handbook, halfpage
131 handbook, halfpage
131
ye ye
Y address
Y address
ys ys
0 0
V = 1; MX = 0 and MY = 1. V = 1; MX = 1 and MY = 1.
Fig.36 Sequence of writing data bytes into RAM with vertical addressing (V = 1) showing function MX and MY.
2003 Feb 14 65
Philips Semiconductors Objective specification
7.3 Command decoder • All column and row outputs are set to VSS1 (display off)
The command decoder identifies command words arriving • RAM data undefined
at the interface and routes the following data bytes to their • Power-down mode
destination. The command set is given in Chapter 6.
• Command register set to default states; see Table 4.
7.4 Grey scale controller
7.8 LCD voltage generator and bias level generator
For a grey scale driving scheme, Frame Rate Control The LCD voltage generator and the bias level generator is
(FRC) with carefully controlled mixing of the FRC pattern
illustrated in Fig.37. The VLCD is generated by means of
on each pixel is used. The special mixing ensures that the two voltage multipliers, with voltage multiplier 1 being
pattern placed on each pixel is different from each of its programmable; see Section 6.2.39.
neighbours. In frame rate control 16 frames form together
to produce a super-frame. All 16 frames have the same Behaviour of voltage multiplier 2 depends on the mode.
duration. In the full Display mode, voltage multiplier 2 behaves as a
doubler. In the partial Display mode voltage multiplier 2
7.5 Timing generator feeds the voltage of VLCDIN1 directly to VLCDOUT2.
The timing generator produces the various signals The LCD voltage generator requires in total 9 external
required to drive the internal circuitry. Internal chip components (capacitors). The recommended values and
operation is not affected by operations on the data bus. voltage ranges for the external components are specified
in Table 85. The given values should be referred to as
7.6 Oscillator information only. It is recommended to check how patterns
with high load are displayed before finalizing the values.
The on-chip oscillator provides the clock signal for the
display system. No external components are required and The bias level generator generates the required bias levels
the OSC input must be connected to VDD1. An external according to the programmed bias systems; see
clock signal, if used, is connected to the OSC input. In this Section 6.2.43.
case the internal oscillator must be switched off by a
To save power it is recommended to apply capacitors to
software command; see Section 6.2.38.
bias level pads (V2H, V1H, VC, V1L and V2L) of
approximately 1 µF. A capacitor at VC pad is expected to
7.7 Reset
be the most effective. Depending on the application of the
The chip has a hardware and a software reset. After VC capacitor it might be advantageous or even necessary
power-up a hardware reset (pin RES) must be applied. to set the OPT bit VCBW = 1; see Table 97 and
The hardware and software reset give the same results. Section 15.8.
After a reset, the chip has the following state; see
Section 6.2.2:
2003 Feb 14 66
Philips Semiconductors Objective specification
VDD3 VDD1
CVDD2 VSS1 CVDD1 V2L
VSS1
VSS
MGU953
2003 Feb 14 67
Philips Semiconductors Objective specification
When sending commands to the PCF8833 the D/C line When using the RDDIDIF (see Section 6.2.6) or RDDST
must be pulled HIGH when the command data is (see Section 6.2.7) commands the PCF8833 sends
transferred (see Fig.38). The same is valid when RAM 24 or 32 data bits respectively back to the microcontroller.
data is sent to the PCF8833 (see Fig.39). The protocol for the RDDIDIF and RDDST commands is
illustrated in Fig.41.
The PCF8833 can send data back to the microcontroller in
2 different ways. The protocol for the RDID1, RDID2, The parallel interface timing diagram is illustrated in
RDID3 and RDTEMP commands is illustrated in Fig.40. Fig.52. For the dummy read cycle the time tACC is
Descriptions of these commands is given in Chapter 6. referenced to the rising edge of the RD signal.
When reading out RDTEMP it is recommended to read this
data several times to validate the readout number.
CS
D/C
WR
D7 to D0 command
command data command command command command
MGU954
CS
D/C
WR
D7 to D0
command RAM data RAM data RAM data RAM data RAM data
(input)
MGU955
2003 Feb 14 68
Philips Semiconductors Objective specification
CS
D/C
WR
RD
D7 to D0 read
command command command
(input)
D7 to D0
(output)
MGU956
Fig.40 Parallel bus protocol, read from register (PS[2:0] = XX1) for RDID1, RDID2, RDID3 and RDTEMP
commands.
CS
D/C
WR
RD
D7 to D0 read
command command command
(input)
D7 to D0
RDDIDIF = 24 bits, RDDST = 32 bits
(output)
MGU957
Fig.41 Parallel bus protocol, read from register (PS[2:0] = XX1) for the RDDIDIF and RDDST commands.
2003 Feb 14 69
Philips Semiconductors Objective specification
9 SERIAL INTERFACE Any instruction can be sent in any order to the PCF8833;
the MSB is transmitted first. The serial interface is
Communication with the microcontroller can also occur via
initialized when SCE is HIGH. In this state, SCLK pulses
a clock-synchronized serial peripheral interface. The
have no effect and no power is consumed by the serial
selection of this interface is achieved with pin PS0; see
interface. A falling edge on pin SCE enables the serial
Section 7.1.1.
interface and indicates the start of data transmission.
The serial interface is a 3-line bidirectional interface for
Figure 42 shows the protocol of the Write mode:
communication between the microcontroller and the LCD
driver chip. The 3 lines are chip enable (SCE), Serial • When SCE is HIGH, SCLKs are ignored. The serial
Clock (SCLK) and Serial Data (SD). The PCF8833 is interface is initialized during the HIGH time of SCE.
connected to the SD pin of the microcontroller by two pins • At the falling edge of SCE SCLK must be LOW (see
SDIN (data input) and SDOUT (data output) which are Fig.51)
connected together. • SDIN is sampled at the rising edge of SCLK
9.1 Write mode • D/C indicates, whether the byte is a command (D/C = 0)
or data (D/C = 1). It is sampled with the first rising SCLK
The Write mode of the interface means that the edge.
microcontroller writes commands and data to the
• If SCE stays LOW after the last bit of a data/command
PCF8833. Each data packet contains a control bit D/C and
byte, the serial interface will receive the D/C bit of the
a transmission byte. If bit D/C is logic 0, the following byte
next byte at the next rising edge of SCLK (see Fig.43).
is interpreted as a command byte. The command set is
given in Table 1. If bit D/C is logic 1, the following bytes are • A reset pulse at pin RES interrupts the transmission.
stored in the display data RAM or registers. After every The data being written into the RAM may be corrupted.
RAM data byte the address counter increments The registers are cleared. If SCE is LOW after the rising
automatically. Figure 42 shows the general format of the edge of RES, the serial interface is ready to receive the
Write mode and the definition of the transmission byte. D/C bit of a data/command byte; see Figs 44 and 50.
D/C D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
MGU958
2003 Feb 14 70
Philips Semiconductors Objective specification
SCE
SCLK
SDIN DC b7 b6 b5 b4 b3 b2 b1 b0 DC b7 b6 b5 b4 b3 b2 b1 b0
MGU959
Fig.43 Serial bus protocol, write to register with control bit in transmission (PS[2:0] = XX0).
SCE
RES
SCLK
SDIN DC b7 b6 b5 b4 b3 b2 DC b7 b6 b5 b4 b3 b2 b1 b0
MGU960
Fig.44 Serial bus protocol, Write mode, interrupted by reset (RES); (PS[2:0] = XX0).
SCE
RES
SCLK
SDIN DC b7 b6 b5 b4 b3 b2 DC b7 b6 b5 b4 b3 b2 b1 b0
MGU961
Fig.45 Serial bus protocol, Write mode, interrupted by chip enable (SCE); (PS[2:0] = XX0).
2003 Feb 14 71
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Philips Semiconductors
STN RGB - 132 × 132 × 3 driver
The Read mode of the serial interface means that the microcontroller reads data from the PCF8833. The PCF8833 can send data back to the
microcontroller in two different ways. The serial bus protocol for the RDID1, RDID2, RDID3 and RDTEMP commands is illustrated in Fig.46. Descriptions
of these commands are given in Section 6.2. After a command has been issued, a byte is transmitted in the opposite direction (using SDOUT). In order
to reach the timing characteristics as given in Chapter 13 data bit b7 must be handled as a don’t care. When the speed of the clock is slowed down to
at least half of maximum speed, at least for reading b7, the reading of data bit b7 is valid.
The PCF8833 samples the SDIN data at rising SCLK edges, but shifts SDOUT data at falling SCLK edges. Thus the microcontroller is supposed to
read SDOUT data at rising SCLK edges.
After the read command has been sent, the SDIN line must be set to 3-state not later than the falling SCLK edge of the last bit (see Fig.46).
When using the RDDIDIF (see Section 6.2.6) or RDDST (see Section 6.2.7) commands the PCF8833 sends 24 or 32 data bits respectively back to the
microcontroller. The serial bus protocols for the RDDIDIF and RDDST commands are illustrated in Figs. 47 and 48. After one of these commands has
been sent 3 or 4 bytes respectively are transmitted in the opposite direction (using SDOUT) after one dummy clock cycle is given.
The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge; see Figs 46, 47 and 48. The last rising SCLK edge sets
SDOUT to 3-state.
The serial interface timing diagram is illustrated in Fig.51. For the dummy read cycle the time tACC is referenced to the rising edge of the SCLK signal.
72
S TB TB TB P
SCE
SCLK
SDIN DC b7 b6 b5 b4 b3 b2 b1 b0 DC b7 b6 b5 b4 b3 b2 b1 b0
SDOUT b7 b6 b5 b4 b3 b2 b1 b0
MGU962
Objective specification
Fig.46 Serial bus protocol, Read mode (PS[2:0] = XX0) for RDID1,RDID2, RDID3 and RDTEMP commands.
PCF8833
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2003 Feb 14
Philips Semiconductors
STN RGB - 132 × 132 × 3 driver
S TB TB TB P
SCE
SCLK
SDIN DC b7 b6 b5 b4 b3 b2 b1 b0 DC b7 b6 b5 b4 b3 b2 b1 b0
MGU963
Fig.47 Serial bus protocol, Read mode (PS[2:0] = XX0) for the RDDIDIF command.
73
S TB TB TB P
SCE
SCLK
SDIN DC b7 b6 b5 b4 b3 b2 b1 b0 DC b7 b6 b5 b4 b3 b2 b1 b0
Objective specification
MGU964
PCF8833
Fig.48 Serial bus protocol, Read mode (PS[2:0] = XX0) for the RDDST command.
Philips Semiconductors Objective specification
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); note 1.
SYMBOL PARAMETER MIN. MAX. UNIT
VSS2 system ground voltage −0.5 +0.5 V
VDD1 logic supply voltage 1 −0.5 +4.0 V
VDD2 supply voltage 2 for the internal voltage generator −0.5 +6.5 V
VDD3 analog supply 3 for the internal voltage generator −0.5 +4.0 V
VLCDIN1 LCD supply voltage input 1 −0.5 +16 V
VLCDIN2 LCD supply voltage input 2 −0.5 +20 V
VLCDSENSE voltage multiplier input voltage −0.5 +20 V
VOTP(gate) supply voltage 1 for OPT programming −0.5 +10 V
VOTP(drain) supply voltage 2 for OPT programming (Vwrite) −0.5 +10 V
IDDn supply current at all VDD pins −50 +50 mA
ISSn negative supply current at all VSS pins −50 +50 mA
VI, VO input/output voltage except for row and column outputs −0.5 VDD + 0.5 V
output voltage for row and column outputs −0.5 VLCD2 + 0.5 V
II DC input current −10 +10 mA
IO DC output current −10 +10 mA
Ptot total power dissipation − 300 mW
Tstg storage temperature −55 +125 °C
Tj junction temperature − 125 °C
Note
1. Parameters are valid over the operating temperature range; all voltages are referenced to VSS1; unless otherwise
specified.
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
2003 Feb 14 74
Philips Semiconductors Objective specification
12 DC CHARACTERISTICS
VDD1 = 1.5 to 3.3 V; VDD2 = VDD3 = 2.4 to 3.5 V; VSS = 0 V; VLCD = 3.8 to 20.0 V; Tamb = −40 to +85 °C; unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDD1 logic supply voltage 1 1.5 − 3.3 V
VDD2 supply voltage 2 for the internal note 1 2.4 − 4.5 V
voltage generator
VDD3 supply voltage 3 for the internal note 1 2.4 − 3.5 V
voltage generator
VLCDIN1 LCD supply voltage input 1 LCD input voltage 1 − − 16.0 V
externally supplied (both
voltage multipliers are
disabled)
VLCDIN2 LCD supply voltage input 2 LCD input voltage 2 − − 20.0 V
externally supplied (both
voltage multipliers are
disabled)
VLCDOUT1 LCD supply voltage output 1 LCD voltage internally 3.8 − 10.0 V
generated with voltage
multiplier 1 (voltage
generator enabled); note 2
VLCDOUT2 LCD supply voltage output 2 LCD voltage internally 3.8 − 20.0 V
generated with voltage
multiplier 2 (voltage
generator enabled); note 2
VLCD(tol) tolerance of generated VLCD with calibration; note 3 −70 − +70 mV
Static current consumption
IDD1 logic supply current notes 5 and 6 − 1.5 5 µA
IDD2, IDD3 supply current for the internal notes 5 and 6 − 0.5 1 µA
voltage generator
Dynamic current consumption
IDD1 logic supply current Normal mode; note 5 − 100 − µA
IDD1 logic supply current during RAM Normal mode; notes 5 and 7; − 1000 − µA
access see Fig.49
IDD2, IDD3 supply current for the internal Normal mode; note 5 − tbf − µA
voltage generator
IDD(tot) total supply current (VDD1 + VDD2, Normal mode; note 5 − tbf − µA
VDD3)
Logic inputs and outputs
VOL LOW-level output voltage IOL = 0.5 mA VSS1 − 0.2VDD1 V
VOH HIGH-level output voltage IOH = −0.5 mA 0.8VDD1 − VDD1 V
VIL LOW-level input voltage VSS1 − 0.3VDD1 V
VIH HIGH-level input voltage 0.7VDD1 − VDD1 V
IL leakage current VI = VDD1 or VSS1 −1 − +1 µA
2003 Feb 14 75
Philips Semiconductors Objective specification
MGU965
8
handbook, halfpage
I DD1, I DD3
(mA)
6
(4)
(3)
2
(2)
(1)
0
0 2 4 6 8
fcyc (MHz)
(1) VDD1 = 1.5 V
(2) VDD1 = 1.8 V
(3) VDD1 = 2.5 V
(4) VDD1 = 3.3 V
Fig.49 Dynamic current consumption IDD1, IDD3 for different VDD1 supplies when writing data from interface to
display RAM at ambient temperature.
2003 Feb 14 76
Philips Semiconductors Objective specification
13 AC CHARACTERISTICS
VDD1 = 1.5 to 3.3 V; VDD2 = VDD3 = 2.4 to 3.5 V; VSS1 = VSS2 = 0 V; Tamb = −40 to +85 °C; note 1; unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
fframe LCD frame frequency (internal clock) VDD1 = 3.0 V − tbf − Hz
fosc oscillator frequency notes 2 and 3 − 600 − kHz
fclk(ext) external clock frequency − tbf − kHz
Reset; see Fig.50
tW(RESL) reset LOW pulse width note 4 500 − − ns
tRSS reset spike suppression − − 100 ns
tSU;RESL reset LOW pulse set-up time after power-on 0 − 1 µs
tRT initialization note 5 0 − 5 ms
tRI interface ready after reset pulse 0 − 1 µs
Serial interface; VDD1(min) = 1.65 V; note 6; see Fig.51
TSCYC serial clock SCLK period (SCLK) 150 − − ns
tSHW SCLK pulse width HIGH 60 − − ns
tSLW SCLK pulse width LOW 60 − − ns
tSDS SDIN data set-up time 60 − − ns
tSDH SDIN data hold time 60 − − ns
tACC SDOUT access time CL = 30 pF 10 − 50 ns
tOH SDOUT output disable time CL = 5 pF; 25 − 50 ns
R = 3 kΩ
tSCC SCLK to SCE time 20 − − ns
tCHW SCE pulse width HIGH 40 − − ns
tCSS SCE to SCLK set-up time 60 − − ns
tCSH SCE to SCLK hold time 65 − − ns
8-bit parallel (8080-type) interface; VDD1(min) = 1.65 V; note 6; see Fig.52
tCS CS-WR and CS-RD time note 7 10 − − ns
tAH D/C address hold time 10 − − ns
tAS address set-up time 10 − − ns
TCYC system cycle time 160 − − ns
tCCLW WR control pulse width LOW Write mode 38 − − ns
tCCLR RD control pulse width LOW Read mode 38 − − ns
tCCHW WR control pulse width HIGH Write mode 90 − − ns
tCCHR RD control pulse width HIGH Read mode 90 − − ns
tDS D0 to D7 data set-up time 10 − − ns
tDH D0 to D7 data hold time 10 − − ns
tACC read access time note 8; CL = 30 pF − − 30 ns
tOH output disable time note 8; CL = 5 pF; 30 − 160 ns
R = 3 kΩ; note 9
2003 Feb 14 77
Philips Semiconductors Objective specification
Notes
1. VDD2 and VDD3 always have to be larger than or equal to VDD1.
2. Not directly observable at any pin.
3. After calibration the following fosc can be expected at 25 °C: 600 kHz ±4%; at different temperatures an additional
variation of +0.12%/°C will not be exceeded.
4. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS1 to VDD1.
5. The initialization incorporates the start-up of the internal circuitry including the readout of the OTP cells. The start-up
time for the internal voltage generation is not included.
6. The input signal rise time and fall time (tr and tf) are specified at 15 ns or less. When the cycle time is used at high
speed, the specification is tr + tf ≤ (tCYC − tCCLW − tCCHW) or tr + tf ≤ (tCYC – tCCLR − tCCHR).
7. CS can be permanently tied LOW.
8. The output disable time and read access time is applicable after the second read cycle (see Fig.40).
9. For VDD1 = 1.8 V possible variation of tOH is between 40 and 80 ns for a temperature range of −40 to +85 °C.
t RSS
VIH
RES VIL
t SU;RESL t W(RESL) t RT
VDD1
VIH
RES
VIL
t W(RESL) t W(RESL) t RT
t RI t RI
Interface:
commands/data not accepted accepted not accepted accepted
MGU966
2003 Feb 14 78
Philips Semiconductors Objective specification
SCE
T SCYC t SCC
t SLW t SHW
SCLK
tr tr
t SDS t SDH
SDIN
t ACC t OH
high-impedance
SDOUT
MGU967
t AS t AH t CS
CS
T CYC
t CCLR, t CCLW t CCHR, t CCHW
WR, RD
t DS t DH
D0 to D7
(Write)
t ACC t OH
D0 to D7
(Read)
MGU968
2003 Feb 14 79
Philips Semiconductors Objective specification
14 APPLICATION INFORMATION
66 396 66
VLCDSENSE
PCF8833
VLCDOUT2
VLCDOUT1
VLCDIN2
VLCDIN1
VDD3
VDD2
VDD1
VSS1
VSS2
MGU969
I/O
Figure 54 shows a typical supply and capacitor connections for the PCF8833.
2003 Feb 14 80
Philips Semiconductors Objective specification
12 Ω
VOTP(drain)
600 Ω
VOTP(gate)
15 Ω
<2Ω VSS1
15 Ω
VSS2
200 Ω
<2Ω VDD3
15 Ω
VDD2
GND 30 Ω
VDD1
60 Ω
GND VLCDOUT2
5Ω 15 Ω
VLCDIN2
< 1 kΩ
GND VLDSENSE
60 Ω
C5+
C5 60 Ω PCF8833
C5−
30 Ω
5Ω VLCDOUT1
15 Ω
VLCDIN1
GND 30 Ω
C4+
C4 30 Ω
C4−
30 Ω
C3+
C3 30 Ω
C3−
30 Ω
C2+
C2 30 Ω
C2−
30 Ω
C1+
C1 30 Ω
C1−
MGU970
The indicated resistor values are the maximum recommended values. The recommended capacitor values are given in Table 85.
2003 Feb 14 81
Philips Semiconductors Objective specification
VT [7:0]
range −32 to + 31
OTP VLCD calibration, 6-bit offset
MMVOPCAL [5:0]
range − 64 to + 63
+
VOP
to high voltage
VCON register, 7-bit generator
range 0 to 445
VCON [6:0]
2003 Feb 14 82
Philips Semiconductors Objective specification
2003 Feb 14 83
Philips Semiconductors Objective specification
OR
OTP CELL
EFD
default = 0
INTERFACE 0
INTERFACE
REGISTERS
e.g. SLA [2:0]
to temperature
compensation circuit
OTP DEFAULTS 1
e.g. SLA [2:0]
MGU972
15.3 Seal bit Bit 7 of every data byte is not used. An example sequence
on how to fill the matrix is given in Table 96.
The module maker programming is performed in the
Calibration mode. This mode is entered via a special The default value of the OTP cells is shown in Table 91.
interface command (CALMM). To prevent erroneous These values may be changed by programming the OTP
programming, a seal bit has been implemented which cell. The programming of a cell will invert the default value.
prevents the device from entering Calibration mode. This This inversion may only happen once per cell, as the
seal bit, once programmed, cannot be reversed, thus programming is irreversible.
further changes in programmed values are not possible.
Table 93 shows an example on how to program the OTP
Applying the programming voltage when not in CALMM
cells to receive the values given in Table 92. Some
mode will have no effect on the programmed values.
examples are given below:
Table 89 Seal bit definition 1. The default for DFA[0] is 0; see Table 91, and it is
required to have DFA[0] = 1; see Table 92. This
SEAL BIT ACTION means that the value needs to be inverted. Therefore
0 Calibration mode enabled the OTP cell has to be programmed (a 1 in Table 93).
1 Calibration mode disabled 2. The default for DFA[4] is 1; see Table 91, and it is
required to have DFA[4] = 0; see Table 92. This
15.4 OTP architecture means that the value needs to be inverted. Therefore
the OTP cell has to be programmed (a 1 in Table 93).
An OTP cell is divided into a non-volatile programmable
3. The default for DFA[5] is 1; see Table 91, and it is
instance containing the value and a register, where the
required to have DFA[5] = 1; see Table 92. This
value is made accessible to the rest of the chip.
means that it is not necessary to change the value.
In the PCF8833 104 OTP cells are available for the Therefore it is not necessary to program the OTP cell
module maker. These cells are organised in a matrix of (a 0 in Table 93).
7 rows and 15 columns, where the last row is only partially 4. The default for DFA[6] is 0; see Table 91, and it is
used; see Table 90. All the rows of one particular column required to have DFA[6] = 0; see Table 92. This
of the matrix are filled in parallel by sending 1 byte of data means that it is not necessary to change the value.
with the OTPSHTIN command. Byte 15 is sent first Therefore it is not necessary to program the OTP cell
(containing PVB[3:0], BRS and TRS) and byte 0 last (a 0 in Table 93).
(containing MMVOP[5:0] or SEAL).
2003 Feb 14 84
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Philips Semiconductors
STN RGB - 132 × 132 × 3 driver
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 SEAL DFA0 DFB0 DFC0 DFD0 DF80 ID20 ID27 ID36 SLA0 SLC0 FVPR0 FVPR6 PVPR3 EFD TRS
1 MMVOP0 DFA1 DFB1 DFC1 DFD1 DF81 ID21 ID30 ID37 SLA1 SLC1 FVPR1 FVPR7 PVPR4 VCBW BRS
2 MMVOP1 DFA2 DFB2 DFC2 DFD2 DF82 ID22 ID31 FS0 (1) SLA2 SLC2 FVPR2 FVPR8 PVPR5 FVB0 PVB0
3 MMVOP2 DFA3 DFB3 DFC3 DFD3 DF83 ID23 ID32 FS1(1) SLB0 SLD0 FVPR3 PVPR0 PVPR6 FVB1 PVB1
4 MMVOP3 DFA4 DFB4 DFC4 DFD4 DF84 ID24 ID33 PS0(2) SLB1 SLD1 FVPR4 PVPR1 PVPR7 FVB2 PVB2
5 MMVOP4 DFA5 DFB5 DFC5 DFD5 DF85 ID25 ID34 PS1(2) SLB2 SLD2 FVPR5 PVPR2 PVPR8 FVB3 PVB3
6 MMVOP5 DFA6 DFB6 DFC6 DFD6 DF86 ID26 ID35 not used
Notes
1. FS[1:0] is the multiplication factor used in full Display mode, compare to S[1:0]; see Section 6.2.39.
2. PS[1:0] is the multiplication factor used in partial Display mode, compare to S[1:0]; see Section 6.2.39.
85
Objective specification
PCF8833
Philips Semiconductors Objective specification
2003 Feb 14 86
Philips Semiconductors Objective specification
Note
1. X = don’t care. For hexadecimal representation, don’t care bits are assumed to be 0.
2003 Feb 14 87
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Philips Semiconductors
STN RGB - 132 × 132 × 3 driver
COMMAND BYTE(1)
STEP D/C ADDR DESCRIPTION
7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 0 1 01H reset (may also be hardware reset)
2 − − − − − − − − − − wait 1 ms for refresh to take effect
3 0 1 1 1 0 1 1 1 0 EEH set SFD = 0 in order to use interface
values
4 0 0 0 1 0 1 0 0 0 28H send DISPOFF to prevent rows and
columns to toggle
5 0 1 0 1 1 0 0 0 0 B0H set VPR to desired value
1 X X X X VPR8 VPR7 VPR6 VPR5 −
1 X X X VPR4 VPR3 VPR2 VPR1 VPR0 −
6 0 1 1 0 0 0 0 1 0 C2H set multiplication stages to desired
value
1 X X X X X X S1 S0 −
7 0 1 1 1 1 0 0 0 0 F0H enter CALMM mode
1 X X 0 0 0 x 0 1 01H ORA = 000 OPE = 0 CALMM = 1
88
Notes
Objective specification
1. X = don’t care. For hexadecimal representation, don’t care bits are assumed to be logic 0.
PCF8833
2. D31 is the booster voltage status bit; see Section 6.2.7.
3. The chip stays in shift operation as long as D/C is logic 1.
Philips Semiconductors Objective specification
Notes
1. X = don’t care. For hexadecimal representation, don’t care bits are assumed to be logic 0.
2. The chip stays in shift operation as long as D/C is logic 1.
2003 Feb 14 89
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Philips Semiconductors
STN RGB - 132 × 132 × 3 driver
COMMAND BYTE(1)
STEP D/C ADDR DESCRIPTION
7 6 5 4 3 2 1 0
0 set VOTP(gate) = 0 V; VOTP(drain) = 0 V
1 0 0 0 0 0 0 0 0 1 01 reset (may also be hardware reset)
2 wait 1 ms for refresh to take effect
3 set VOTP(gate) = 8 V; VOTP(drain) = 8 V
4 0 1 1 1 1 0 0 0 0 F0 enter CALMM mode
1 X X 0 0 0 X 0 1 01 ORA = 000; OPE = 0; CALMM = 1
5 0 1 1 1 1 0 0 0 1 F1 send OTPSHTIN; note 2
shift15 1 X X PVB3 PVB2 PVB1 PVB0 BRS TRS set PVB[3:0]; BRS and TRS
shift14 1 X X FVB3 FVB2 FVB1 FVB0 VCBW EFD set FVB[3:0]; VCBW and EFD; note 3
:
shift0 1 x MMVOP5 MMVOP4 MMVOP3 MMVOP2 MMVOP1 MMVOP0 0 set MMVOP[5:0] and SEAL = 0
6 0 1 1 1 1 0 0 0 0 F0 select row 0 in OTP matrix
1 X X 0 0 0 X 0 1 01 ORA = 000; OPE = 0; CALMM = 1
90
7 0 1 1 1 1 0 0 0 0 F0 enable programming
1 X X 0 0 0 X 1 1 03 ORA = 000; OPE = 1; CALMM = 1
8 wait for 50 ms until OTP cells are
programmed
9 0 1 1 1 1 0 0 0 0 F0 disable programming
1 X X 0 0 0 X 0 1 01 ORA = 000; OPE = 0; CALMM = 1
10 0 1 1 1 1 0 0 0 0 F0 select row 1 in OTP matrix
1 X X 0 0 1 X 0 1 09 ORA = 001; OPE = 0; CALMM = 1
11 0 1 1 1 1 0 0 0 0 F0 enable programming
1 X X 0 0 1 X 1 1 0B ORA = 001; OPE = 1; CALMM = 1
Objective specification
PCF8833
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2003 Feb 14
Philips Semiconductors
COMMAND BYTE(1)
Objective specification
PCF8833
Philips Semiconductors Objective specification
Note
1. The voltage drop across the ITO track and any connector must be taken into account to guarantee a sufficiently high
voltage at the chip pins.
2003 Feb 14 92
Philips Semiconductors Objective specification
OPE
VOTP(gate)
VOTP(drain)
t WRITEPW
t OPESU t OPEHD
OPE
VOTP(gate)
VOTP(drain)
t WRITEPW
MGU973
2003 Feb 14 93
Philips Semiconductors Objective specification
VSS2
VSS1 VSS1
VSS2
VSS1
VLCDIN2 VLCDOUT2
VLCDSENSE
4 MΩ
4 MΩ
VSS1 VSS1
VLCDIN2
VSS1 VSS1
VSS1 MGU977
2003 Feb 14 94
Philips Semiconductors Objective specification
VDD1 VDD1
200 kΩ
VSS1
VSS1 VSS1
VSS1
VSS1 VSS1
MGU978
2003 Feb 14 95
Philips Semiconductors Objective specification
C191
R32 R0
C395 VSS(tieoff)
RES
TE T7
C384
C383 C1+
VSS1
C1− C144
VSS2 C143
C2+
CS/SCE C2−
VDD1
C3+
VDD3
C336 C3−
VDD2 C335
C4+
C96
D7
C4− C95
D3
D6
D5
VLCDOUT1
D2
D1
D4
D0/SDIN VLCDIN1
SDOUT
D/C/SCLK
WR C288 C5+
RD C287
PS0
PS1 C5−
PS2 C48
OSC C47
VDD(tieoff) VLCDOUT2
VLCDSENSE
VOTP(drain)
VLCDIN2
VOTP(gate)
V2L
V1L
T6 C240 VC
T5 C239
T4 V1H
T3 V2H
T2 C0
R96
T1
VSS(tieoff) R64
C192
R131 R95
pad 769 pad 1
active pads
dummy pads MGU976
alignment marks
2003 Feb 14 96
Philips Semiconductors Objective specification
2003 Feb 14 97
Philips Semiconductors Objective specification
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
C43 77 −7371.496 −1030.568 C82 116 −5502.200 −1030.568
C44 78 −7325.032 −1030.568 C83 117 −5455.736 −1030.568
C45 79 −7278.568 −1030.568 C84 118 −5409.272 −1030.568
C46 80 −7232.104 −1030.568 C85 119 −5362.808 −1030.568
C47 81 −7185.640 −1030.568 C86 120 −5316.344 −1030.568
C48 82 −7081.976 −1030.568 C87 121 −5269.880 −1030.568
C49 83 −7035.512 −1030.568 C88 122 −5223.416 −1030.568
C50 84 −6989.048 −1030.568 C89 123 −5176.952 −1030.568
C51 85 −6942.584 −1030.568 C90 124 −5130.488 −1030.568
C52 86 −6896.120 −1030.568 C91 125 −5084.024 −1030.568
C53 87 −6849.656 −1030.568 C92 126 −5037.560 −1030.568
C54 88 −6803.192 −1030.568 C93 127 −4991.096 −1030.568
C55 89 −6756.728 −1030.568 C94 128 −4944.632 −1030.568
C56 90 −6710.264 −1030.568 C95 129 −4898.168 −1030.568
C57 91 −6663.800 −1030.568 C96 130 −4794.504 −1030.568
C58 92 −6617.336 −1030.568 C97 131 −4748.040 −1030.568
C59 93 −6570.872 −1030.568 C98 132 −4701.576 −1030.568
C60 94 −6524.408 −1030.568 C99 133 −4655.112 −1030.568
C61 95 −6477.944 −1030.568 C100 134 −4608.648 −1030.568
C62 96 −6431.480 −1030.568 C101 135 −4562.184 −1030.568
C63 97 −6385.016 −1030.568 C102 136 −4515.720 −1030.568
C64 98 −6338.552 −1030.568 C103 137 −4469.256 −1030.568
C65 99 −6292.088 −1030.568 C104 138 −4422.792 −1030.568
C66 100 −6245.624 −1030.568 C105 139 −4376.328 −1030.568
C67 101 −6199.160 −1030.568 C106 140 −4329.864 −1030.568
C68 102 −6152.696 −1030.568 C107 141 −4283.400 −1030.568
C69 103 −6106.232 −1030.568 C108 142 −4236.936 −1030.568
C70 104 −6059.768 −1030.568 C109 143 −4190.472 −1030.568
C71 105 −6013.304 −1030.568 C110 144 −4144.008 −1030.568
C72 106 −5966.840 −1030.568 C111 145 −4097.544 −1030.568
C73 107 −5920.376 −1030.568 C112 146 −4051.080 −1030.568
C74 108 −5873.912 −1030.568 C113 147 −4004.616 −1030.568
C75 109 −5827.448 −1030.568 C114 148 −3958.152 −1030.568
C76 110 −5780.984 −1030.568 C115 149 −3911.688 −1030.568
C77 111 −5734.520 −1030.568 C116 150 −3865.224 −1030.568
C78 112 −5688.056 −1030.568 C117 151 −3818.760 −1030.568
C79 113 −5641.592 −1030.568 C118 152 −3772.296 −1030.568
C80 114 −5595.128 −1030.568 C119 153 −3725.832 −1030.568
C81 115 −5548.664 −1030.568 C120 154 −3679.368 −1030.568
2003 Feb 14 98
Philips Semiconductors Objective specification
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
C121 155 −3632.904 −1030.568 C160 194 −1763.608 −1030.568
C122 156 −3586.440 −1030.568 C161 195 −1717.144 −1030.568
C123 157 −3539.976 −1030.568 C162 196 −1670.680 −1030.568
C124 158 −3493.512 −1030.568 C163 197 −1624.216 −1030.568
C125 159 −3447.048 −1030.568 C164 198 −1577.752 −1030.568
C126 160 −3400.584 −1030.568 C165 199 −1531.288 −1030.568
C127 161 −3354.120 −1030.568 C166 200 −1484.824 −1030.568
C128 162 −3307.656 −1030.568 C167 201 −1438.360 −1030.568
C129 163 −3261.192 −1030.568 C168 202 −1391.896 −1030.568
C130 164 −3214.728 −1030.568 C169 203 −1345.432 −1030.568
C131 165 −3168.264 −1030.568 C170 204 −1298.968 −1030.568
C132 166 −3121.800 −1030.568 C171 205 −1252.504 −1030.568
C133 167 −3075.336 −1030.568 C172 206 −1206.040 −1030.568
C134 168 −3028.872 −1030.568 C173 207 −1159.576 −1030.568
C135 169 −2982.408 −1030.568 C174 208 −1113.112 −1030.568
C136 170 −2935.944 −1030.568 C175 209 −1066.648 −1030.568
C137 171 −2889.480 −1030.568 C176 210 −1020.184 −1030.568
C138 172 −2843.016 −1030.568 C177 211 −973.720 −1030.568
C139 173 −2796.552 −1030.568 C178 212 −927.256 −1030.568
C140 174 −2750.088 −1030.568 C179 213 −880.792 −1030.568
C141 175 −2703.624 −1030.568 C180 214 −834.328 −1030.568
C142 176 −2657.160 −1030.568 C181 215 −787.864 −1030.568
C143 177 −2610.696 −1030.568 C182 216 −741.400 −1030.568
C144 178 −2507.032 −1030.568 C183 217 −694.936 −1030.568
C145 179 −2460.568 −1030.568 C184 218 −648.472 −1030.568
C146 180 −2414.104 −1030.568 C185 219 −602.008 −1030.568
C147 181 −2367.640 −1030.568 C186 220 −555.544 −1030.568
C148 182 −2321.176 −1030.568 C187 221 −509.080 −1030.568
C149 183 −2274.712 −1030.568 C188 222 −462.616 −1030.568
C150 184 −2228.248 −1030.568 C189 223 −416.152 −1030.568
C151 185 −2181.784 −1030.568 C190 224 −369.688 −1030.568
C152 186 −2135.320 −1030.568 C191 225 −323.224 −1030.568
C153 187 −2088.856 −1030.568 C192 226 −219.560 −1030.568
C154 188 −2042.392 −1030.568 C193 227 −173.096 −1030.568
C155 189 −1995.928 −1030.568 C194 228 −126.632 −1030.568
C156 190 −1949.464 −1030.568 C195 229 −80.168 −1030.568
C157 191 −1903.000 −1030.568 C196 230 −33.704 −1030.568
C158 192 −1856.536 −1030.568 C197 231 +12.760 −1030.568
C159 193 −1810.072 −1030.568 C198 232 +59.224 −1030.568
2003 Feb 14 99
Philips Semiconductors Objective specification
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
C199 233 +105.688 −1030.568 C238 272 +1917.784 −1030.568
C200 234 +152.152 −1030.568 C239 273 +1964.248 −1030.568
C201 235 +198.616 −1030.568 C240 274 +2067.912 −1030.568
C202 236 +245.080 −1030.568 C241 275 +2114.376 −1030.568
C203 237 +291.544 −1030.568 C242 276 +2160.840 −1030.568
C204 238 +338.008 −1030.568 C243 277 +2207.304 −1030.568
C205 239 +384.472 −1030.568 C244 278 +2253.768 −1030.568
C206 240 +430.936 −1030.568 C245 279 +2300.232 −1030.568
C207 241 +477.400 −1030.568 C246 280 +2346.696 −1030.568
C208 242 +523.864 −1030.568 C247 281 +2393.160 −1030.568
C209 243 +570.328 −1030.568 C248 282 +2439.624 −1030.568
C210 244 +616.792 −1030.568 C249 283 +2486.088 −1030.568
C211 245 +663.256 −1030.568 C250 284 +2532.552 −1030.568
C212 246 +709.720 −1030.568 C251 285 +2579.016 −1030.568
C213 247 +756.184 −1030.568 C252 286 +2625.480 −1030.568
C214 248 +802.648 −1030.568 C253 287 +2671.944 −1030.568
C215 249 +849.112 −1030.568 C254 288 +2718.408 −1030.568
C216 250 +895.576 −1030.568 C255 289 +2764.872 −1030.568
C217 251 +942.040 −1030.568 C256 290 +2811.336 −1030.568
C218 252 +988.504 −1030.568 C257 291 +2857.800 −1030.568
C219 253 +1034.968 −1030.568 C258 292 +2904.264 −1030.568
C220 254 +1081.432 −1030.568 C259 293 +2950.728 −1030.568
C221 255 +1127.896 −1030.568 C260 294 +2997.192 −1030.568
C222 256 +1174.360 −1030.568 C261 295 +3043.656 −1030.568
C223 257 +1220.824 −1030.568 C262 296 +3090.120 −1030.568
C224 258 +1267.288 −1030.568 C263 297 +3136.584 −1030.568
C225 259 +1313.752 −1030.568 C264 298 +3183.048 −1030.568
C226 260 +1360.216 −1030.568 C265 299 +3229.512 −1030.568
C227 261 +1406.680 −1030.568 C266 300 +3275.976 −1030.568
C228 262 +1453.144 −1030.568 C267 301 +3322.440 −1030.568
C229 263 +1499.608 −1030.568 C268 302 +3368.904 −1030.568
C230 264 +1546.072 −1030.568 C269 303 +3415.368 −1030.568
C231 265 +1592.536 −1030.568 C270 304 +3461.832 −1030.568
C232 266 +1639.000 −1030.568 C271 305 +3508.296 −1030.568
C233 267 +1685.464 −1030.568 C272 306 +3554.760 −1030.568
C234 268 +1731.928 −1030.568 C273 307 +3601.224 −1030.568
C235 269 +1778.392 −1030.568 C274 308 +3647.688 −1030.568
C236 270 +1824.856 −1030.568 C275 309 +3694.152 −1030.568
C237 271 +1871.320 −1030.568 C276 310 +3740.616 −1030.568
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
C277 311 +3787.080 −1030.568 C316 350 +5656.376 −1030.568
C278 312 +3833.544 −1030.568 C317 351 +5702.840 −1030.568
C279 313 +3880.008 −1030.568 C318 352 +5749.304 −1030.568
C280 314 +3926.472 −1030.568 C319 353 +5795.768 −1030.568
C281 315 +3972.936 −1030.568 C320 354 +5842.232 −1030.568
C282 316 +4019.400 −1030.568 C321 355 +5888.696 −1030.568
C283 317 +4065.864 −1030.568 C322 356 +5935.160 −1030.568
C284 318 +4112.328 −1030.568 C323 357 +5981.624 −1030.568
C285 319 +4158.792 −1030.568 C324 358 +6028.088 −1030.568
C286 320 +4205.256 −1030.568 C325 359 +6074.552 −1030.568
C287 321 +4251.720 −1030.568 C326 360 +6121.016 −1030.568
C288 322 +4355.384 −1030.568 C327 361 +6167.480 −1030.568
C289 323 +4401.848 −1030.568 C328 362 +6213.944 −1030.568
C290 324 +4448.312 −1030.568 C329 363 +6260.408 −1030.568
C291 325 +4494.776 −1030.568 C330 364 +6306.872 −1030.568
C292 326 +4541.240 −1030.568 C331 365 +6353.336 −1030.568
C293 327 +4587.704 −1030.568 C332 366 +6399.800 −1030.568
C294 328 +4634.168 −1030.568 C333 367 +6446.264 −1030.568
C295 329 +4680.632 −1030.568 C334 368 +6492.728 −1030.568
C296 330 +4727.096 −1030.568 C335 369 +6539.192 −1030.568
C297 331 +4773.560 −1030.568 C336 370 +6642.856 −1030.568
C298 332 +4820.024 −1030.568 C337 371 +6689.320 −1030.568
C299 333 +4866.488 −1030.568 C338 372 +6735.784 −1030.568
C300 334 +4912.952 −1030.568 C339 373 +6782.248 −1030.568
C301 335 +4959.416 −1030.568 C340 374 +6828.712 −1030.568
C302 336 +5005.880 −1030.568 C341 375 +6875.176 −1030.568
C303 337 +5052.344 −1030.568 C342 376 +6921.640 −1030.568
C304 338 +5098.808 −1030.568 C343 377 +6968.104 −1030.568
C305 339 +5145.272 −1030.568 C344 378 +7014.568 −1030.568
C306 340 +5191.736 −1030.568 C345 379 +7061.032 −1030.568
C307 341 +5238.200 −1030.568 C346 380 +7107.496 −1030.568
C308 342 +5284.664 −1030.568 C347 381 +7153.960 −1030.568
C309 343 +5331.128 −1030.568 C348 382 +7200.424 −1030.568
C310 344 +5377.592 −1030.568 C349 383 +7246.888 −1030.568
C311 345 +5424.056 −1030.568 C350 384 +7293.352 −1030.568
C312 346 +5470.520 −1030.568 C351 385 +7339.816 −1030.568
C313 347 +5516.984 −1030.568 C352 386 +7386.280 −1030.568
C314 348 +5563.448 −1030.568 C353 387 +7432.744 −1030.568
C315 349 +5609.912 −1030.568 C354 388 +7479.208 −1030.568
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
C355 389 +7525.672 −1030.568 C394 428 +9394.968 –1030.568
C356 390 +7572.136 −1030.568 C395 429 +9441.432 –1030.568
C357 391 +7618.600 −1030.568 R0 430 +9596.664 –1035.694
C358 392 +7665.064 −1030.568 R1 431 +9649.464 –1035.694
C359 393 +7711.528 −1030.568 R2 432 +9702.264 –1035.694
C360 394 +7757.992 −1030.568 R3 433 +9755.064 –1035.694
C361 395 +7804.456 −1030.568 R4 434 +9807.864 –1035.694
C362 396 +7850.920 −1030.568 R5 435 +9860.664 –1035.694
C363 397 +7897.384 −1030.568 R6 436 +9913.464 –1035.694
C364 398 +7943.848 −1030.568 R7 437 +9966.264 –1035.694
C365 399 +7990.312 –1030.568 R8 438 +10019.064 –1035.694
C366 400 +8036.776 –1030.568 R9 439 +10071.864 −1035.694
C367 401 +8083.240 –1030.568 R10 440 +10124.664 −1035.694
C368 402 +8129.704 –1030.568 R11 441 +10177.464 −1035.694
C369 403 +8176.168 –1030.568 R12 442 +10230.264 −1035.694
C370 404 +8222.632 –1030.568 R13 443 +10283.064 −1035.694
C371 405 +8269.096 –1030.568 R14 444 +10335.864 −1035.694
C372 406 +8315.560 –1030.568 R15 445 +10388.664 −1035.694
C373 407 +8362.024 –1030.568 R16 446 +10441.464 −1035.694
C374 408 +8408.488 –1030.568 R17 447 +10494.264 −1035.694
C375 409 +8454.952 –1030.568 R18 448 +10547.064 −1035.694
C376 410 +8501.416 –1030.568 R19 449 +10599.864 −1035.694
C377 411 +8547.880 –1030.568 R20 450 +10652.664 −1035.694
C378 412 +8594.344 –1030.568 R21 451 +10705.464 −1035.694
C379 413 +8640.808 –1030.568 R22 452 +10758.264 −1035.694
C380 414 +8687.272 –1030.568 R23 453 +10811.064 −1035.694
C381 415 +8733.736 –1030.568 R24 454 +10863.864 −1035.694
C382 416 +8780.200 –1030.568 R25 455 +10916.664 −1035.694
C383 417 +8826.664 –1030.568 R26 456 +10969.464 −1035.694
C384 418 +8930.328 –1030.568 R27 457 +11022.264 −1035.694
C385 419 +8976.792 –1030.568 R28 458 +11075.064 −1035.694
C386 420 +9023.256 –1030.568 R29 459 +11127.864 −1035.694
C387 421 +9069.720 –1030.568 R30 460 +11180.664 −1035.694
C388 422 +9116.184 –1030.568 R31 461 +11233.464 −1035.694
C389 423 +9162.648 –1030.568 dummy 462 +11358.424 −1035.694
C390 424 +9209.112 –1030.568 dummy 463 +11358.424 +1035.694
C391 425 +9255.576 –1030.568 R63 464 +11233.464 +1035.694
C392 426 +9302.040 –1030.568 R62 465 +11180.664 +1035.694
C393 427 +9348.504 –1030.568 R61 466 +11127.864 +1035.694
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
R60 467 +11075.064 +1035.694 VSS1 506 +8540.664 +1035.694
R59 468 +11022.264 +1035.694 VSS1 507 +8487.864 +1035.694
R58 469 +10969.464 +1035.694 VSS2 508 +8329.464 +1035.694
R57 470 +10916.664 +1035.694 VSS2 509 +8276.664 +1035.694
R56 471 +10863.864 +1035.694 VSS2 510 +8223.864 +1035.694
R55 472 +10811.064 +1035.694 VSS2 511 +8171.064 +1035.694
R54 473 +10758.264 +1035.694 VSS2 512 +8118.264 +1035.694
R53 474 +10705.464 +1035.694 VSS2 513 +8065.464 +1035.694
R52 475 +10652.664 +1035.694 VSS2 514 +8012.664 +1035.694
R51 476 +10599.864 +1035.694 VSS2 515 +7959.864 +1035.694
R50 477 +10547.064 +1035.694 VSS2 516 +7907.064 +1035.694
R49 478 +10494.264 +1035.694 VSS2 517 +7854.264 +1035.694
R48 479 +10441.464 +1035.694 CS/SCE 518 +7643.064 +1035.694
R47 480 +10388.664 +1035.694 VDD1 519 +7431.864 +1035.694
R46 481 +10335.864 +1035.694 VDD1 520 +7379.064 +1035.694
R45 482 +10283.064 +1035.694 VDD1 521 +7326.264 +1035.694
R44 483 +10230.264 +1035.694 VDD1 522 +7273.464 +1035.694
R43 484 +10177.464 +1035.694 VDD1 523 +7220.664 +1035.694
R42 485 +10124.664 +1035.694 VDD1 524 +7167.864 +1035.694
R41 486 +10071.864 +1035.694 VDD3 525 +7009.464 +1035.694
R40 487 +10019.064 +1035.694 VDD3 526 +6956.664 +1035.694
R39 488 +9966.264 +1035.694 VDD3 527 +6903.864 +1035.694
R38 489 +9913.464 +1035.694 VDD3 528 +6851.064 +1035.694
R37 490 +9860.664 +1035.694 VDD3 529 +6798.264 +1035.694
R36 491 +9807.864 +1035.694 VDD2 530 +6639.864 +1035.694
R35 492 +9755.064 +1035.694 VDD2 531 +6587.064 +1035.694
R34 493 +9702.264 +1035.694 VDD2 532 +6534.264 +1035.694
R33 494 +9649.464 +1035.694 VDD2 533 +6481.464 +1035.694
R32 495 +9596.664 +1035.694 VDD2 534 +6428.664 +1035.694
RES 496 +9332.664 +1035.694 VDD2 535 +6375.864 +1035.694
TE 497 +9174.264 +1035.694 VDD2 536 +6323.064 +1035.694
VSS1 498 +8963.064 +1035.694 VDD2 537 +6270.264 +1035.694
VSS1 499 +8910.264 +1035.694 VDD2 538 +6217.464 +1035.694
VSS1 500 +8857.464 +1035.694 VDD2 539 +6164.664 +1035.694
VSS1 501 +8804.664 +1035.694 D7 540 +5953.464 +1035.694
VSS1 502 +8751.864 +1035.694 D3 541 +5795.064 +1035.694
VSS1 503 +8699.064 +1035.694 D6 542 +5636.664 +1035.694
VSS1 504 +8646.264 +1035.694 D2 543 +5478.264 +1035.694
VSS1 505 +8593.464 +1035.694 D5 544 +5319.864 +1035.694
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
D1 545 +5161.464 +1035.694 dummy 584 +825.880 +1035.694
D4 546 +5003.064 +1035.694 dummy 585 +773.080 +1035.694
D0/SDIN 547 +4844.664 +1035.694 dummy 586 +720.280 +1035.694
SDOUT 548 +4686.264 +1035.694 dummy 587 +667.480 +1035.694
DC/SCLK 549 +4527.864 +1035.694 dummy 588 +614.680 +1035.694
WR 550 +4369.464 +1035.694 dummy 589 +561.880 +1035.694
RD 551 +4211.064 +1035.694 dummy 590 +509.080 +1035.694
PS0 552 +4052.664 +1035.694 dummy 591 +456.280 +1035.694
PS1 553 +3894.264 +1035.694 dummy 592 +403.480 +1035.694
PS2 554 +3735.864 +1035.694 dummy 593 +350.680 +1035.694
OSC 555 +3577.464 +1035.694 dummy 594 +297.880 +1035.694
VDDTIEOFF 556 +3419.064 +1035.694 dummy 595 +245.080 +1035.694
VOTPdrain 557 +3207.864 +1035.694 dummy 596 +192.280 +1035.694
VOTPdrain 558 +3155.064 +1035.694 dummy 597 +139.480 +1035.694
VOTPdrain 559 +3102.264 +1035.694 dummy 598 +86.680 +1035.694
VOTPdrain 560 +3049.464 +1035.694 dummy 599 +33.880 +1035.694
VOTPdrain 561 +2996.664 +1035.694 dummy 600 −18.920 +1035.694
VOTPdrain 562 +2943.864 +1035.694 dummy 601 −71.720 +1035.694
VOTPdrain 563 +2891.064 +1035.694 dummy 602 −124.520 +1035.694
VOTPdrain 564 +2838.264 +1035.694 dummy 603 −177.320 +1035.694
VOTPgate 565 +2679.864 +1035.694 dummy 604 −230.120 +1035.694
VOTPgate 566 +2627.064 +1035.694 dummy 605 −282.920 +1035.694
VOTPgate 567 +2574.264 +1035.694 dummy 606 −335.720 +1035.694
VOTPgate 568 +2521.464 +1035.694 dummy 607 −388.520 +1035.694
VOTPgate 569 +2468.664 +1035.694 dummy 608 −441.320 +1035.694
VOTPgate 570 +2415.864 +1035.694 dummy 609 −494.120 +1035.694
VOTPgate 571 +2363.064 +1035.694 dummy 610 −546.920 +1035.694
VOTPgate 572 +2310.264 +1035.694 dummy 611 −599.720 +1035.694
T6 573 +2099.064 +1035.694 dummy 612 −652.520 +1035.694
T5 574 +1940.664 +1035.694 dummy 613 −705.320 +1035.694
T4 575 +1782.264 +1035.694 dummy 614 −758.120 +1035.694
T3 576 +1623.864 +1035.694 dummy 615 −810.920 +1035.694
T2 577 +1465.464 +1035.694 dummy 616 −863.720 +1035.694
T1 578 +1307.064 +1035.694 dummy 617 −916.520 +1035.694
VSSTIEOFF 579 +1148.664 +1035.694 dummy 618 −969.320 +1035.694
dummy 580 +1037.080 +1035.694 dummy 619 −1022.120 +1035.694
dummy 581 +984.280 +1035.694 dummy 620 −1074.920 +1035.694
dummy 582 +931.480 +1035.694 dummy 621 −1127.720 +1035.694
dummy 583 +878.680 +1035.694 dummy 622 −1180.520 +1035.694
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
dummy 623 −1233.320 +1035.694 C4+ 662 −4375.976 +1035.694
VSSTIEOFF 624 −1410.904 +1035.694 C4+ 663 −4428.776 +1035.694
T7 625 −1683.176 +1035.694 C4+ 664 −4481.576 +1035.694
C1+ 626 −1841.576 +1035.694 C4+ 665 −4534.376 +1035.694
C1+ 627 −1894.376 +1035.694 C4+ 666 −4587.176 +1035.694
C1+ 628 −1947.176 +1035.694 C4+ 667 −4639.976 +1035.694
C1+ 629 −1999.976 +1035.694 C4– 668 −4798.376 +1035.694
C1+ 630 −2052.776 +1035.694 C4– 669 −4851.176 +1035.694
C1+ 631 −2105.576 +1035.694 C4– 670 −4903.976 +1035.694
C1− 632 −2263.976 +1035.694 C4– 671 −4956.776 +1035.694
C1− 633 −2316.776 +1035.694 C4– 672 −5009.576 +1035.694
C1− 634 −2369.576 +1035.694 C4– 673 −5062.376 +1035.694
C1− 635 −2422.376 +1035.694 VLCDOUT1 674 −5220.776 +1035.694
C1− 636 −2475.176 +1035.694 VLCDOUT1 675 −5273.576 +1035.694
C1− 637 −2527.976 +1035.694 VLCDOUT1 676 −5326.376 +1035.694
C2+ 638 −2686.376 +1035.694 VLCDOUT1 677 −5379.176 +1035.694
C2+ 639 −2739.176 +1035.694 VLCDOUT1 678 −5431.976 +1035.694
C2+ 640 −2791.976 +1035.694 VLCDOUT1 679 −5484.776 +1035.694
C2+ 641 −2844.776 +1035.694 VLCDOUT1 680 −5537.576 +1035.694
C2+ 642 −2897.576 +1035.694 VLCDOUT1 681 −5590.376 +1035.694
C2+ 643 −2950.376 +1035.694 VLCDOUT1 682 −5643.176 +1035.694
C2− 644 −3108.776 +1035.694 VLCDOUT1 683 −5695.976 +1035.694
C2− 645 −3161.576 +1035.694 VLCDIN1 684 −5854.376 +1035.694
C2− 646 −3214.376 +1035.694 VLCDIN1 685 −5907.176 +1035.694
C2− 647 −3267.176 +1035.694 VLCDIN1 686 −5959.976 +1035.694
C2− 648 −3319.976 +1035.694 VLCDIN1 687 −6012.776 +1035.694
C2− 649 −3372.776 +1035.694 VLCDIN1 688 −6065.576 +1035.694
C3+ 650 −3531.176 +1035.694 VLCDIN1 689 −6118.376 +1035.694
C3+ 651 −3583.976 +1035.694 VLCDIN1 690 −6171.176 +1035.694
C3+ 652 −3636.776 +1035.694 C5+ 691 −6329.576 +1035.694
C3+ 653 −3689.576 +1035.694 C5+ 692 −6382.376 +1035.694
C3+ 654 −3742.376 +1035.694 C5+ 693 −6435.176 +1035.694
C3+ 655 −3795.176 +1035.694 C5+ 694 −6487.976 +1035.694
C3− 656 −3953.576 +1035.694 C5+ 695 −6540.776 +1035.694
C3− 657 −4006.376 +1035.694 C5+ 696 −6593.576 +1035.694
C3− 658 −4059.176 +1035.694 C5− 697 −6751.976 +1035.694
C3− 659 −4111.976 +1035.694 C5− 698 −6804.776 +1035.694
C3− 660 −4164.776 +1035.694 C5− 699 −6857.576 +1035.694
C3− 661 −4217.576 +1035.694 C5− 700 −6910.376 +1035.694
COORDINATES COORDINATES
SYMBOL PAD SYMBOL PAD
x y x y
C5− 701 −6963.176 +1035.694 R103 740 −9753.480 +1035.694
C5− 702 −7015.976 +1035.694 R104 741 −9806.280 +1035.694
VLCDOUT2 703 −7174.376 +1035.694 R105 742 −9859.080 +1035.694
VLCDOUT2 704 −7227.176 +1035.694 R106 743 −9911.880 +1035.694
VLCDOUT2 705 −7279.976 +1035.694 R107 744 −9964.680 +1035.694
VLCDOUT2 706 −7332.776 +1035.694 R108 745 −10017.480 +1035.694
VLCDOUT2 707 −7385.576 +1035.694 R109 746 −10070.280 +1035.694
VLCDOUT2 708 −7438.376 +1035.694 R110 747 −10123.080 +1035.694
VLCDOUT2 709 −7491.176 +1035.694 R111 748 −10175.880 +1035.694
VLCDOUT2 710 −7543.976 +1035.694 R112 749 −10228.680 +1035.694
VLCDOUT2 711 −7596.776 +1035.694 R113 750 −10281.480 +1035.694
VLCDSENSE 712 −7649.576 +1035.694 R114 751 −10334.280 +1035.694
VLCDIN2 713 −7807.976 +1035.694 R115 752 −10387.080 +1035.694
VLCDIN2 714 −7860.776 +1035.694 R116 753 −10439.880 +1035.694
VLCDIN2 715 −7913.576 +1035.694 R117 754 −10492.680 +1035.694
VLCDIN2 716 −7966.376 +1035.694 R118 755 −10545.480 +1035.694
VLCDIN2 717 −8019.176 +1035.694 R119 756 −10598.280 +1035.694
VLCDIN2 718 −8071.976 +1035.694 R120 757 −10651.080 +1035.694
VLCDIN2 719 −8124.776 +1035.694 R121 758 −10703.880 +1035.694
V2L 720 −8341.212 +1035.694 R122 759 −10756.680 +1035.694
V2L 721 −8394.012 +1035.694 R123 760 −10809.480 +1035.694
V1L 722 −8499.612 +1035.694 R124 761 −10862.280 +1035.694
V1L 723 −8552.412 +1035.694 R125 762 −10915.080 +1035.694
VC 724 −8658.012 +1035.694 R126 763 −10967.880 +1035.694
VC 725 −8710.812 +1035.694 R127 764 −11020.680 +1035.694
VC 726 −8763.612 +1035.694 R128 765 −11073.480 +1035.694
VC 727 −8816.412 +1035.694 R129 766 −11126.280 +1035.694
VC 728 −8869.212 +1035.694 R130 767 −11179.080 +1035.694
V1H 729 −8974.812 +1035.694 R131 768 −11231.880 +1035.694
V1H 730 −9027.612 +1035.694 dummy 769 −11351.208 +1035.694
V2H 731 −9133.212 +1035.694 Alignment marks (see Fig.62)
V2H 732 −9186.012 +1035.694 Alignment circle 1 −11175.032 +593.120
R96 733 −9383.880 +1035.694 Alignment circle 2 +11184.888 +593.120
R97 734 −9436.680 +1035.694 Alignment circle 3 −8717.192 +746.240
R98 735 −9489.480 +1035.694 Alignment circle 4 +9362.408 +746.240
R99 736 −9542.280 +1035.694
R100 737 −9595.080 +1035.694
R101 738 −9647.880 +1035.694
R102 739 −9700.680 +1035.694
2.34
mm PC8833-1
pitch
handbook, halfpage
y center 80
µm
x center
MGU975
18 TRAY INFORMATION
y
D
E
MGU979
20 DEFINITIONS 21 DISCLAIMERS
Short-form specification The data in a short-form Life support applications These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes in the products -
Characteristics sections of the specification is not implied. including circuits, standard cells, and/or software -
Exposure to limiting values for extended periods may described or contained herein in order to improve design
affect device reliability. and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
Application information Applications that are
communicated via a Customer Product/Process Change
described herein for any of these products are for
Notification (CPCN). Philips Semiconductors assumes no
illustrative purposes only. Philips Semiconductors make
responsibility or liability for the use of any of these
no representation or warranty that such applications will be
products, conveys no licence or title under any patent,
suitable for the specified use without further testing or
copyright, or mask work right to these products, and
modification.
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for
a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems
after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify
their application in which the die is used.
NOTES
Contact information
Printed in The Netherlands 403512/01/pp112 Date of release: 2003 Feb 14 Document order number: 9397 750 10059