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SECTION 8
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SYNCHRONOUS SERIAL INTERFACE

(SSI0 and SSI1)

MOTOROLA 8-1
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SECTION CONTENTS

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2 SSI OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.3 SSI CLOCK AND FRAME SYNC GENERATION . . . . . . . . . . . . . . . . . . . . . 8-4
8.4 SSIx DATA AND CONTROL PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.5 SSI RESET AND INITIALIZATION PROCEDURE . . . . . . . . . . . . . . . . . . . . 8-8
8.6 SSIx INTERFACE PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.7 SSI TRANSMIT SHIFT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
8.8 SSI TRANSMIT DATA REGISTER (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.9 SSI RECEIVE SHIFT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.10 SSI RECEIVE DATA REGISTER (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
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8.11 SSI CONTROL REGISTER A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.12 SSI CONTROL REGISTER B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
8.13 SSI STATUS REGISTER (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
8.14 TIME SLOT REGISTER - TSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
8.15 TRANSMIT SLOT MASK REGISTERS - TSMAx AND TSMBx . . . . . . . . . . 8-22
8.16 TRANSMIT SLOT MASK SHIFT REGISTER - TSMS . . . . . . . . . . . . . . . . . 8-23
8.17 RECEIVE SLOT MASK REGISTERS - RSMAx AND RSMBx . . . . . . . . . . . 8-23
8.18 RECEIVE SLOT MASK SHIFT REGISTER - RSMS . . . . . . . . . . . . . . . . . . 8-24
8.19 SSI OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8-2 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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INTRODUCTION

8.1 INTRODUCTION
The DSP56156 contains two identical Synchronous Serial Interfaces (SSI’s) named SSI0
and SSI1. This section describes both. In cases where the text or a figure applies equally
to both SSI’s, they will be referred to as the SSI. In cases where the information differs
between the SSI’s such as when pin numbers are mentioned, control addresses are men-
tioned or the operation affects only one of the two SSI’s like a personal reset, the SSI will
be referred to as SSIx meaning SSI0 or SSI1 – whichever applies.

The SSI is a full duplex serial port which allows the DSP to communicate with a variety of
serial devices including one or more industry standard codecs, other DSPs, or micropro-
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cessors and peripherals. A selectable logarithmic compression and expansion is available

for easier interface with PCM monocircuits and PCM highways. The SSI interface consists
of independent transmitter and receiver sections and a common SSI clock generator.

8.2 SSI OPERATING MODES

The SSI has several basic operating modes. These modes can be programmed by sev-
eral bits in the SSI Control registers. The Table 8-1 below lists the SSI operating modes:

Table 8-1 SSI Operating Modes

TX, RX Sections Serial Clock Protocol

Asynchronous Continuous Normal

Synchronous Continuous Normal

Synchronous Continuous Network

Asynchronous Continuous Network

The transmit and receive sections of this interface may be synchronous or asynchronous;
that is, the transmitter and the receiver may use common clock and synchronization sig-
nals or they may have independent frame sync signals but the same bit clock. The SYN
bit in SSI Control Register B selects synchronous or asynchronous operation. Since the
SSI is designed to operate either synchronously or asynchronously, separate receive and
transmit interrupts are provided.

Normal or network protocol may also be selected. For normal protocol the SSI functions
with one data word of I/O per frame. For network protocol, 2 to 32 data words of I/O may
be used per frame. Network mode is used in Time Division Multiplexed (TDM) networks
of codecs or DSPs. These distinctions result in the basic operating modes which allow the
SSI to communicate with a wide variety of devices.

MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8-3

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SSI CLOCK AND FRAME SYNC GENERATION

8.3 SSI CLOCK AND FRAME SYNC GENERATION

Data clock and frame sync signals can be generated internally by the DSP or may be ob-
tained from external sources. If internally generated, the SSI clock generator is used to
derive bit clock and frame sync signals from the DSP internal system clock. The SSI clock
generator consists of a selectable fixed prescaler and a programmable prescaler for bit
rate clock generation and also a programmable frame rate divider and a word length di-
vider for frame rate sync signal generation.

8.4 SSIx DATA AND CONTROL PINS

The SSIx has five dedicated I/O pins for each SSI:
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• Transmit data STDx (PC0 for SSI0 and PC5 for SSI1)
• Receive data SRDx (PC1 for SSI0 and PC6 for SSI1)
• Serial clock SCKx (PC2 for SSI0 and PC7 for SSI1)
• Serial Control Pin 1 SC1x (PC3 for SSI0 and PC8 for SSI1)
• Serial Control Pin 0 SC0x (PC4 for SSI0 and PC9 for SSI1)

Figure 8-1 through Figure 8-5 show the main configurations and the following paragraphs
describe the uses of these pins for each of the SSIx operating modes.These figures do
not represent all possible configurations, e.g., SCKx and FS don’t have to be in the same
direction. Note that the first pin name in these figures apply to SSI0 and the second
applies to SSI1 i.e., PC2/PC7 means PC2 for SSI0 and PC7 for SSI1.

8-4 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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SSIx DATA AND CONTROL PINS

PC0/PC5 STDx any

PC1/PC6 SRDx DSP
DSP56156 PC2/PC7 SCKx
or
PC3/PC8–SC1x
PC4/PC9–SC0x FS CODEC

Figure 8-1 SSIx Internal Clock, Synchronous Operation

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PC0/PC5 STDx
any
PC1/PC6 SRDx DSP
DSP56156 PC2/PC7 SCKx or
PC3/PC8–SC1x CODEC
PC4/PC9–SC0x FS

Figure 8-2 SSIx External Clock, Synchronous Operation

PC0/PC5 STDx any

PC1/PC6 SRDx
DSP56156 PC2/PC7 DSP
SCKx
PC3/PC8–SC1x or
RFS
PC4/PC9–SC0x TFS CODEC

Figure 8-3 SSIx Internal Clock, Asynchronous Operation

PC0/PC5 STDx
any
PC1/PC6 SRDx DSP
DSP56156 PC2/PC7 SCKx or
PC3/PC8–SC1x RFS CODEC
PC4/PC9–SC0x TFS

Figure 8-4 SSIx External Clock, Asynchronous Operation

MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8-5

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SSIx DATA AND CONTROL PINS

RDD
DSP56156 TDD
TDC/RDC CODEC
PC0/PC5 STDx 1
PC1/PC6 SRDx TDE/RDE
PC2/PC7 SCKx
PC3/PC8–SC1x F1
PC4/PC9–SC0x F0

RDD
TDD
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TDC/RDC CODEC
0
TDE/RDE

Figure 8-5 SSIx Internal Clock, Synchronous Operation Dual Codec Interface

Figure 8-6 shows the internal clock path connections in block diagram form. The serial bit
clock can be internal or external depending on SCKD bit in the control register.

PSR PM0-PM7

Prescale Divider
Fosc /2 /1 or /8 /1 to /256

/2

WL1, WL0 Control Reset

SCKD (1= output)
SCK Word Clock
Word
Length Divider
Internal Bit Clock

RX Shift Rx Data
Register

TX Shift Tx Data
Register

Figure 8-6 SSI Clock Generator Functional Block Diagram

8-6 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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SSIx DATA AND CONTROL PINS

Table 8-4 shows frame sync generation. When internally generated, both receive and
transmit frame sync are generated from the word clock and are defined by the frame rate
divider (DC4-DC0) bit and the word length (WL1-WL0) bits of CRA.

Figure 8-7 shows the functions of the two pins SC1x and SC0x according to the setting of
CRB flags.

8.4.1 Serial Transmit Data Pin - STDx

The Serial Transmit Data Pin (STD) is used for transmit data from the Serial Transmit Shift
Register. STD is an output when data is being transmitted and is three-stated between
data word transmissions and after the trailing edge of the bit clock after the last bit of a
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word is transmitted.

8.4.2 Serial Receive Data Pin - SRDx

The Serial Receive Data Pin (SRD) is used to input serial data into the Receive Data Shift
Register.

8.4.3 Serial Clock - SCK

The Serial Clock (SCK) pin is used as a clock input or output used by both the transmitter
and receiver in synchronous modes and in asynchronous modes.

8.4.4 Serial Control - SC1x

The function of this pin is determined by the flags SYNC, FSD0 and FSD1 of control reg-
ister B (CRB) — see Table 8-4. In Asynchronous mode (SYNC=0), this pin is the receiver
frame sync I/O. For synchronous mode (SYNC=1), with bits FSD0 and FSD1 set, pin SCIx
is used as an output flag. When SC1x is configured as an output flag (FSD0=1; FSD0=1),
this pin is controlled by bit OF1 in CRB. When SCIx is configured as an input or output
(with synchronous or asynchronous operations), this pin will update status bit IF1 of the
SSI status register as described in Section 8.13.1.

MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8-7

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SSI RESET AND INITIALIZATION PROCEDURE

SYN=0
RX
control
logic RX frame
sync in

F1 in

SC1x
DC0-DC4
word SYN&FSD0=1
clock Frame Frame FSL, FSI F1 out FSD1
rate
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Sync
divider Type FSD0 | FSD1
F0 out
SYN&FSD0=1 SC0x
TX frame
sync out

TX frame F0 in
TX sync in Where & is the logical “and” operator,
control Where | is the logical “or” operator
logic
(FSD1&SYN&FSD0) = 1

Figure 8-7 SSIx Frame Sync Generator Functional Block Diagram

8.4.5 Serial Control - SC0x

The function of this pin is determined by the SYNC, FSD0 and FSD1 flags in the CRB. In
Asynchronous mode (SYNC=0), this pin is the transmitter frame sync I/O. For synchro-
nous mode (SYNC=1), this pin is used as a frame sync I/O if bit FSD0 is cleared. If bits
FSD0 and FSD1 are set, this pin is used as an output flag. When configured as an output
flag (FSD0=1; FSD1=1), this pin is controlled by bit OF0 in the CRB and changes synchro-
nously with the first transmitted bit of the data. Control status bit IF0 of the SSI status reg-
ister will update regardless of the SYNC, FSD0 or FSD1 bits in the CRB.

8.5 SSI RESET AND INITIALIZATION PROCEDURE

The SSI is affected by three types of reset:

DSP Reset This reset is generated by either the DSP hardware reset (generated by
asserting the RESET pin) or software reset (generated by executing the
RESET instruction). The DSP reset clears the Port Control Register bits,

8-8 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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SSIx INTERFACE PROGRAMMING MODEL

which configures all I/O pins as general purpose input. The SSI will re-
main in the reset state while all SSI pins are programmed as general pur-
pose I/O (CC0-CC4/CC5-CC9 cleared) and will become active only
when at least one of the SSIx I/O pins is programmed as NOT general
purpose I/O. All status and control bits in the SSIx are affected as de-
scribed below.

SSIx Reset The SSIx personal reset is generated when CC0-CC4/CC5-CC9 bits are
cleared. This returns the SSIx pins to general purpose I/O pins. The SSIx
status bits are preset to the same state produced by the DSP reset; how-
ever, the SSIx control bits are unaffected. The SSIx personal reset is use-
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ful for selective reset of the SSIx interface without changing the present
SSIx control bits setup and without affecting the other peripherals.

STOP Reset The STOP reset is caused by executing the STOP instruction. During the
STOP state no clocks are active in the chip. The SSI status bits are preset
to the same state produced by the DSP reset. The SSI control bits are un-
affected. The SSI pins remain defined as SSIx pins. The STOP reset con-
dition is like the personal reset condition except that the SSI pins do not
revert to general purpose I/O pins.

The correct sequence to initialize the SSI interface is as follows:

1. DSP reset or SSIx reset

2. Program SSIx control registers
3. Configure SSIx pins (at least one) as not general purpose I/O
The DSP programmer should use the DSP or SSIx reset before changing the MOD, SYN,
FSI, FSL, MSB, SCKP, SCKD, FSD1, A/MU, FSD0 control bits to ensure proper operation
of the SSIx interface. That is, these control bits should not be changed during SSIx oper-
ation.

Note: The SSIx clock must go low for at least four complete periods to ensure proper SSIx
reset.

8.6 SSIx INTERFACE PROGRAMMING MODEL

The registers comprising the SSI interface are shown in Figure 8-8. Note that standard
Codec devices label the Most Significant Bit as bit 0, whereas the DSP labels the LSB as
bit 0. Therefore, when using a standard Codec (requiring LSB first), the SHFD bit in the
CRB should be cleared (MSB first).

MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8-9

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SSI TRANSMIT SHIFT REGISTER

8.7 SSI TRANSMIT SHIFT REGISTER

This is a 16-bit shift register that contains the data being transmitted. Data is shifted out
to the serial transmit data STD pin by the selected (internal/external) bit clock when the
associated frame sync I/O is asserted. The number of bits shifted out before the shift reg-
ister is considered empty and may be written to again can be 8, 12, or 16 bits as deter-
mined by the Word Length control bits in the SSI Control Register A (WL1-WL0).

The data to be transmitted occupies the most significant portion of the shift register. The
unused portion of the register is ignored. Data is shifted out of this register with the most
significant bit (MSB) first when the SHFD bit of the control register B is cleared. If the
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SHFD bit is set, the LSB is output first. The Transmit Shift Register cannot be directly ac-
cessed by the programmer.

SSIx DATA REGISTERS

15 8 7 0 SERIAL RECEIVE
SHIFT REGISTER
HIGH BYTE LOW BYTE (Cannot be accessed
directly)

15 8 7 0 READ-ONLY
SERIAL RECEIVE
HIGH BYTE LOW BYTE REGISTER
(SSI0 Address X:$FFF1
SSI1 Address X:$FFF9)
15 8 7 0 SERIAL TRANSMIT
SHIFT REGISTER
HIGH BYTE LOW BYTE (Cannot be accessed
directly)

15 8 7 0 WRITE-ONLY
SERIAL TRANSMIT
HIGH BYTE LOW BYTE REGISTER
(SSI0 Address X:$FFF1
SSI1 Address X:$FFF9)

Figure 8-8 SSIx Programming Model

8 - 10 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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SSI TRANSMIT SHIFT REGISTER

SSIx CONTROL and STATUS REGISTERS

15 14 13 12 11 10 9 8
READ-WRITE
PSR WL1 WL0 DC4 DC3 DC2 DC1 DC0 SSIx CONTROL
REGISTER A (CRA)
7 6 5 4 3 2 1 0 SSI0 ADDRESS $FFD0
SSI1 ADDRESS $FFD8
PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

15 14 13 12 11 10 9 8

READ-WRITE
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RIE TIE RE TE MOD SYN FSI FSL

SSIx CONTROL
7 6 5 4 3 2 1 0 REGISTER B (CRB)
SSI0 ADDRESS $FFD1
SHFD SCKP SCKD FSD1 A/MU FSD0 OF1 OF0 SSI1 ADDRESS $FFD9

7 6 5 4 3 2 1 0 READ-ONLY
SSIx STATUS
RDF TDE ROE TUE RFS TFS IF1 IF0 REGISTER (SR)
SSI0 ADDRESS $FFF0
SSI1 ADDRESS $FFF8
15 8 7 0 WRITE-ONLY
SSIx TIME SLOT
Dummy Register, No Content Is Actually Written REGISTER (TSR)
SSI0 ADDRESS $FFF0
SSI1 ADDRESS $FFF8
SSIx SLOT MASK REGISTERS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSMBx
SSI0: $FFF3
RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SSI1: $FFFB
READ-WRITE
SSIx RECEIVE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSMAx SLOT MASK
SSI0: $FFF2 REGISTERS
RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS RS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSI1: $FFFA

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSMBx
SSI0: $FFF5
TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS
SSI1: $FFFD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ-WRITE
SSIx TRANSMIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSMAx SLOT MASK
SSI0: $FFF4 REGISTERS
TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS TS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSI1: $FFFC

Figure 8-8 SSIx Programming Model (Continued)

MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 11

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SSI TRANSMIT DATA REGISTER (TX)

8.8 SSI TRANSMIT DATA REGISTER (TX)

The transmit data register is a 16-bit write-only register. Data to be transmitted is written
into this register and is automatically transferred to the transmit shift register when it be-
comes empty. The data written should occupy the most significant portion of the transmit
data register. The unused bits (least significant portion) of the transmit data register are
don’t care bits. The DSP is interrupted whenever the transmit data register becomes emp-
ty provided that the transmit data register empty interrupt has been enabled. Tx is memory
mapped to X:$FFF1 for SSI0 and X:$FFF9 for SSI1.

Note: 1. When FSL=1, if the data is written into TX just between the frame sync and the
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transmission of the first bit, the data will not be transmitted. TDE and TUE will
be set when the first bit is transmitted.
2. When the A/MU law is enabled, the data to be transmitted during the first en-
abled slot of a frame should be written to the TX register before the second to
last bit of the last slot of the previous frame. Otherwise a transmit underrun error
occurs.

8.9 SSI RECEIVE SHIFT REGISTER

This is a 16-bit shift register that receives the incoming data from the serial receive data
(SRD) pin. Data is shifted in by the selected (internal/external) bit clock when the associ-
ated frame sync input/output is asserted. Data is assumed to be received most significant
bit (MSB) first if the SHFD bit of CRB is cleared. If the SHFD bit is set, the data is assumed
to be received least significant bit first. Data is transferred to the SSI Receive Data Reg-
ister after 8, 12, or 16 bits have been shifted in depending on the Word Length control bits
(WL1-WL0) in SSI Control Register A. The receive shift register cannot be directly access-
ed by the programmer.

8.10 SSI RECEIVE DATA REGISTER (RX)

The SSI Receive Data Register is a 16-bit read-only register that accepts data from the
Receive Shift Register as it becomes full. The data read will occupy the most significant
portion of the receive data register. The unused bits (least significant portion) will read as
zeros. The DSP is interrupted whenever the receive data register becomes full if the as-
sociated interrupt is enabled. Rx is memory mapped to X:$FFF1 for SSI0 and X:$FFF9
for SSI1.

8.11 SSI CONTROL REGISTER A (CRA)

The SSI Control Register A is one of two 16-bit read/write control registers used to direct
the operation of the SSI. The CRA controls the SSI clock generator bit and frame sync
rates, word length, and number of words per frame for the serial data. The DSP reset

8 - 12 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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SSI CONTROL REGISTER A (CRA)

clears all CRA bits. SSIx reset and STOP reset do not affect the CRA bits. CRA is memory
mapped to X:$FFD0 for SSI0 and X:$FFD8 for SSI1. The CRA control bits are described
in the following paragraphs.

15 14 13 12 11 10 9 8

PSR WL1 WL0 DC4 DC3 DC2 DC1 DC0 READ-WRITE

SSIx CONTROL
REGISTER A (CRA);
7 6 5 4 3 2 1 0 ADDRESS $FFD0 — SSI0
ADDRESS $FFD8 — SSI1
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PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

8.11.1 CRA Prescale Modulus Select (PM0…PM7) Bits 0-7

The Prescale Modulus Select bits specify the divide ratio of the prescale divider in the SSI
clock generator. This prescaler is used only in internal clock mode to divide the internal
clock of the DSP. A divide ratio from 1 to 256 (PM=$00 to $FF) may be selected.The bit
clock output is available at SCK. The bit clock output is also used internally as the bit
clock to shift the transmit and receive shift registers. Careful choice of the crystal oscilla-
tor frequency and the prescaler modulus will allow the telecommunication industry stan-
dard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz to be
generated. For example, a 24.576 MHz clock frequency may be used to generate the
standard 2.048 MHz and 1.536 MHz rates, and a 24.704 MHz clock frequency may be
used to generate the standard 1.544 MHz rate. Table 8-2 gives examples of PM0-PM7
values that can be used in order to generate different bit clocks:

The bit clock on the SSI can be calculated from the Fosc value using the following equa-
tion:

SCK = Fosc ÷ (4 x(7PSR+1) x(PM+1))

8.11.2 CRA Frame Rate Divider Control (DC0…DC4) Bits 8-12

The Frame Rate Divider Control bits control the divide ratio for the programmable frame
rate dividers. It operates on the word clock. In network mode this ratio may be interpreted
as the number of words per frame.

In normal mode, this ratio determines the word transfer rate. The divide ratio may range
from 1 to 32 (DC = 00000 to 11111) for normal mode and 2 to 32 (DC = 00001 to 11111)
for network mode.

MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) 8 - 13

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SSI CONTROL REGISTER A (CRA)

Table 8-2 SSI Bit Clock as a Function of Fosc and PM0-PM7 (PSR=0)
Fosc Max bit PM0-PM7 Values for different SCK
Clock
(MHz) (MHz) 2.048MHz 1.544MHz 1.536MHz 128KHz 64KHz

16.384 4.096 1 - - 31($1F) 63($3F)

18.432 4.608 - - 2 35($23) 71($47)
20.480 5.12 - - - 39($27) 79($4F)
26.624 6.656 - - - 51($33) 103($67)
24.576 6.144 2 - 3 47($2F) 95($5F)
24.704 6.176 - 3 - - -
32.768 8.192 3 - - 63($3F) 127($7F)
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36.864 9.216 - - 5 71($47) 143(8F)

49.152 12.288 5 - 7 95($5F) 191($BF)
49.408 12.352 - 7 - - -
65.536 16.384 7 - - 127($7F) 255($FF)
73.728 18.432 8 - - 143($8F) -

Examples:

in 8-bit word network mode: DC0-DC4= 26, PM0-PM7=8, PSR=0, Fosc =

62.22MHz would give a bit clock of 62.22Mhz ÷ [4x9] = 1.728 kHz for a 27 slot TDM
multiplex of 8-bit words. The sampling rate for every word (FS rate) would then be
1.728 kHz ÷ [27x8] = 8kHz.

in 8-bit word normal mode: DC0-DC4= 1, PM0-PM7=9, PSR=1, Fosc =

40.96MHz would give a bit clock of 40.96Mhz ÷ [8x4x10] = 128 kHz. The 8-bit word
rate being equal to 2, the sampling rate (FS rate) would then be 128 kHz ÷ [2x8] =
8kHz.

A divide ratio of one (DC=00000) in network mode is a special case. In normal mode, a
divide ratio of one (DC=00000) provides continuous periodic data word transfer. Note that
a 1-bit sync (FSL=1) must be used in this case.

Note: The frame divider control bits have to be written before the first three serial clock
cycles of the last slot of a frame in order to become active at the beginning of the
next frame.

8.11.3 CRA Word Length Control (WL0,WL1) Bits 13, 14

The Word Length Control bits are used to select the length of the data words being trans-
ferred via the SSI. Word lengths of 8, 12, or 16 bits may be selected as shown in Table
8-3.

8 - 14 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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SSI CONTROL REGISTER B (CRB)

These bits control the Word Length Divider shown in the SSI Clock Generator. The WL
control bits also controls the frame sync pulse length when FSL=0.

When WL1-WL0= 01, the received logarithmic byte is automatically expanded to a 13 or

14 bit word in the RX register. The result is left justified in the RX register. When transmit-
ting, a 16-bit left justified word written to the TX register will be truncated to 13/14 bits be-
fore logarithmic compression. The A/MU bit 3 of CRB will select which compression law,
A or MU, is used.

Note: When the A/MU law is enabled, the data to be transmitted should be written to the
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TX register before the second to last clock of the previous slot. Otherwise a trans-
mit underrun error occurs.

Table 8-3 SSI Data Word Lengths

WL1 WL0 Number of bits/word

0 0 8
0 1 8 with log exp/comp
1 0 12
1 1 16

8.11.4 CRA Prescaler Range (PSR) Bit 15

The Prescaler Range controls a fixed divide-by-8 prescaler in series with the variable
prescaler. It is used to extend the range of the prescaler for those cases where a slower
bit clock is desired. When PSR is cleared the fixed prescaler is bypassed. When PSR is
set the fixed divide-by-8 prescaler is operational. This allows a 128kHz master clock to be
generated for Motorola codecs. The maximum internally generated bit clock frequency is
Fosc/4 and the minimum internally generated bit clock frequency is Fosc/(4*8*256).

8.12 SSI CONTROL REGISTER B (CRB)

The SSI Control Register B is one of two, 16-bit read/write control registers used to direct
the operation of the SSI. CRB controls the direction of the bit clock pin (SCK) and the func-
tion of the SC1x and SC0x pins. Interrupt enable bits for each data register interrupt are
provided in this control register. SSI operating modes are also selected in this register.
The DSP reset clears all CRB bits. SSIx reset and STOP reset do not affect the CRB bits.
The SSI Control Register B bits are described in the following paragraphs.

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SSI CONTROL REGISTER B (CRB)

15 14 13 12 11 10 9 8

RIE TIE RE TE MOD SYN FSI FSL READ-WRITE

SSIx CONTROL
REGISTER B (CRB)
7 6 5 4 3 2 1 0 SSI0 ADDRESS $FFD1
SSI1 ADDRESS $FFD9
SHFD SCKP SCKD FSD1 A/MU FSD0 OF1 OF0

Figure 8-9 SSI Control Register B

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8.12.1 CRB Serial Output Flag 0 and 1 (OF0, OF1) Bit 0, 1

When SSI is in the synchronous mode and when the FSD0 and FSD1 bits are set (indi-
cating that pins SC0x and SC1x are used as output flags) data present in OF0 and OF1
will be written to SC0x and SC1x at the beginning of the frame in normal mode or at the
beginning of the next valid time slot in network mode.

8.12.2 Transmit and Receive Frame Sync Directions - (FSD0, FSD1) Bit 2,4
The Frame Sync Direction bits (FSD1, FSD0) determine the direction of SC1x and SC0x
and whether the frame sync or the flags are used. If FSD0=0 and FSD1=0, then both pins
are inputs. If FSD0=1 and FSD1=0, then SC1x is an input and SC0x is an output. If
FSD1=1, then both pins are outputs. SC0x and SC1x are both used as frame syncs (SC0x
only if SYN=1) and SSISR flag inputs. Output pins reflect either the frame sync (FSD0=0
and FSD1=1) or the flags (FSD0=1, FSD1=1, & SYN = 1). Table 8-4 shows the functions
of the two pins SC1x and SC0x according to the definition of CRB flags SYN, FSD1 and
FSD0.

Table 8-4 Function of SC1x and SC0x Pins

CRB Flags Mode SC1x SC0x Comments
SYN FSD0 FSD1

0 0 0 Async RFS in TFS in Illegal for on-demand

0 0 1 Async RFS out TFS out
0 1 0 Async RFS in TFS out
0 1 1 - - - (Reserved)

1 0 0 Sync - FS in Illegal for on-demand

1 0 1 Sync - FS out
1 1 0 - - - (Reserved)
1 1 1 Sync F1 out F0 out Flags used for sync as
in Figure 8-5

RFS: Receive Frame Sync; TFS: Transmit Frame Sync; FS: Frame Sync

8 - 16 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA

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SSI CONTROL REGISTER B (CRB)

8.12.3 CRB A/Mu Law Selection Bit (A/MU) Bit 3

When WL1-WL0 control bit of CRA are programmed for 8-bit exchange with logarithmic
expansion/compression, the bit A/MU selects which law is used by the expanding/com-
panding hardware. This bit is a don’t care bit otherwise.

If A/Mu=0, the A law is selected and if A/MU=1, the µ law is selected. Companding/Ex-
panding hardware follows CCITT recommendation G.711.

8.12.4 Transmit and Receive Frame Sync Directions - (FSD1) Bit 4

See Paragraph 8.12.2.
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8.12.5 CRB Clock Source Direction (SCKD) Bit 5

The Clock Source Direction bit selects the source of the clock signal used to clock the
Transmit Shift Register and the Receive Shift Register. When SCKD is set, the clock
source is internal and is the bit clock output of the SSI clock generator. This clock appears
at the SCK pin (SCKD=1). When SCKD is cleared, the clock source is external; the inter-
nal clock generator is disconnected from the SCK pin and an external clock source may
drive this pin to clock the Transmit Shift Register and the Receive Shift Register in either
mode.

8.12.6 CRB Clock Polarity Bit (SCKP) Bit 6

The clock polarity bit controls on which bit clock edge data is clocked out and latched in.
If SCKP= 0, the data is clocked out on the rising edge of the bit clock and received in on
the falling edge of the clock. If SCKP = 1, the falling edge of the clock is used to clock the
data out and the rising edge of the clock is used to latch the data in.

8.12.7 CRB MSB Position Bit (SHFD) Bit 7

The SHFD bit controls whether MSB or LSB is transmitted and received first. If SHFD = 0,
the data is exchanged MSB first; if SHFD = 1, the LSB is exchanged first.

8.12.8 CRB Frame Sync Length (FSL) Bit 8

The Frame Sync Length bit selects the type of frame sync to be generated or recognized.
If FSL=1, the frame sync will be one bit-clock long during the bit period immediately pre-
ceding the first bit period of the word being transferred. If FSL=0, the frame sync will be
one data word in length.

8.12.9 CRB Frame Sync Invert (FSI) Bit 9

The Frame Sync Invert (FSI) bit selects the logic of frame sync I/O and I/O flag pins. If
FSI=1, the frame sync or flag pins are active low. If FSI=0, the frame sync or flag pins are
active high.

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SSI CONTROL REGISTER B (CRB)

8.12.10 CRB Sync/Async (SYN) Bit 10

The Sync/Async control bit controls whether receive and transmit functions of the SSI oc-
cur synchronously or asynchronously with respect to each other. When SYN is cleared,
asynchronous mode is chosen and separate frame sync signals are used for the transmit
and receive sections. When SYN is set, synchronous mode is chosen and the transmit
and receive sections use common clock and frame sync signals.

8.12.11 CRB SSI Mode Select (MOD) Bit 11

The Mode select bit selects the operational mode of the SSI. When MOD is cleared, the
normal mode is selected. When MOD is set, the network mode is selected.
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8.12.12 CRB SSI Transmit Enable (TE) Bit 12

The SSI Transmit Enable bit enables the transfer of data from the TX register to the Trans-
mit Shift Register. When TE is set and a frame sync is detected, the transmit portion of
the SSI is enabled. When TE is cleared, the transmitter will be disabled after completing
transmission of data currently in the SSI Transmit Shift Register.The serial output is then
three-stated and any data present in TX will not be transmitted; i.e., data can be written
to TX with TE cleared, TDE will get cleared but data will not be transferred to the Transmit
Shift Register.

Normal transmit enable sequence for transmit is to write data to TX or to TSR before set-
ting TE. Normal transmit disable sequence is to clear TE and TIE after TDE=1.

In the network mode, the operation of clearing TE and setting it again will disable the
transmitter after completion of transmission of a current data word until the beginning of
a new data frame period. During the disabled time period, the STD pin will remain in
three-state.

Note: TE does not inhibit TDE or transmitter interrupts. TE does not affect the generation
of frame sync.

8.12.13 CRB SSI Receive Enable (RE) Bit 13

When the SSI Receive Enable bit is set, the receive portion of the SSI is enabled. When
this bit is cleared, the receiver will be disabled by inhibiting data transfer into RX. If data
is being received while this bit is cleared, the rest of the word will be shifted in and trans-
ferred to the SSI Receive Data Register.

In network mode, the operation of clearing RE and setting it again will disable the receiver
after reception of the current data word until the beginning of the new data frame.

Note: RE does not inhibit RDF or receiver interrupts. RE does not affect the generation
of a frame sync.

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SSI STATUS REGISTER (SSISR)

8.12.14 CRB SSI Transmit Interrupt Enable (TIE) Bit 14

When the SSI Transmit Interrupt Enable bit is set, the program controller will be interrupt-
ed when the SSI Transmit Data Register Empty flag (TDE) in the SSI Status Register is
set. When TIE is cleared, this interrupt is disabled. However, the TDE bit will always indi-
cate the transmit data register empty condition even when the transmitter is disabled with
the TE bit. Writing data to the TX or TSR register will clear TDE thus clearing the interrupt.

There are two transmit data interrupts which have separate interrupt vectors:

1. Transmit data with exception status - This interrupt is generated on the follow-
ing condition:
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TIE=1 and TDE=1 and TUE=1

2. Transmit data without exceptions - This interrupt is generated on the following

condition:

TIE=1 and TDE=1 and TUE=0

8.12.15 CRB SSI Receive Interrupt Enable (RIE) Bit 15

When the SSI Receive Interrupt Enable bit is set, the program controller will be interrupted
when the SSI Receive Data Register Full flag (RDF) in the SSI Status Register is set. If
RIE is cleared, this interrupt is disabled. However, the RDF bit still indicates the receive
data register full condition. Reading the receive data register will clear RDF and thus clear
the pending interrupt.

There are two receive data interrupts which have separate interrupt vectors:

1. Receive Data with exception status - This interrupt is generated on the following
condition:

RIE=1 and RDF=1 and ROE=1

2. Receive Data without exceptions - This interrupt is generated on the following

condition:

RIE=1 and RDF=1 and ROE=0

8.13 SSI STATUS REGISTER (SSISR)

The SSI Status Register is an 8-bit read only status register used by the DSP to interro-
gate the status and serial input flags of the SSI. The status bits are described in the fol-
lowing paragraphs.

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SSI STATUS REGISTER (SSISR)

READ-ONLY
7 6 5 4 3 2 1 0 SSIx STATUS
REGISTER (SR)
RDF TDE ROE TUE RFS TFS IF1 IF0 SSI0 ADDRESS $FFF0
SSI1 ADDRESS $FFF8

Note: All the flags in the SSISR are updated one SSI clock after the beginning of a time
slot.

8.13.1 SSISR Serial Input Flag 1 and 0 (IF0, IF1) Bit 0, 1

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The SSI always latches data present on the SC1x and SC0x pins during reception of the
first received bit. IF0 and IF1 are always updated with this data when the receive shift reg-
ister is transferred into the receive data register. Hardware, software, SSI individual, and
STOP resets will clear IF0 and IF1.

8.13.2 SSISR Transmit Frame Sync (TFS) Bit 2

When set the Transmit Frame Sync flag (TFS) indicates that the first bit of the first active
word of the frame has been transmitted. Data written to the transmit data register when
TFS is set will be transmitted (in network mode) during the second active time slot in the
frame.

In network mode, TFS is set during transmission of the first active slot of the frame. It will
then be cleared when starting transmission of the next active slot of the frame. If the first
time slot of the frame is not enabled, this bit will be set on the leading edge of the first ac-
tive slot.

Note: In normal mode or in network mode with only one enabled slot, TFS will always
read as a one when transmitting data because there is only one time slot per frame.

TFS is cleared by DSP, SSIx or STOP reset and is not affected by TE.

8.13.3 SSISR Receive Frame Sync (RFS) Bit 3

When set, the Receive Frame Sync flag (RFS) indicates that reception of the word in the
Serial Receive Data Register (RX) occurred during the first active slot in the frame. When
RFS is cleared and a word is received, it indicates (only in the network mode) that the re-
ception of that word did not occur during the first active slot.

In network mode, if the first slot is disabled, this flag will be set after reception in the first
active slot and will only be cleared after receiving the next enabled time slot into the RX
register.

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SSI STATUS REGISTER (SSISR)

Note: In normal mode or network mode with one enabled slot, RFS will always be set
when reading data because data is received only in the first active time slot.

RFS is cleared by DSP, SSIx or STOP reset and is not affected by RE.

8.13.4 SSISR Transmitter Underrun Error (TUE) Bit 4

The Transmitter Underrun Error flag is set when the Serial Transmit Shift Register is emp-
ty (no data to be transmitted) and a transmit time slot occurs. When a transmit underrun
error occurs, the previous data will be re-transmitted. A transmit time slot in the normal
mode occurs when the frame sync is asserted. In the network mode, each active time slot
requires transmit data.
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TUE does not cause any interrupts; however, TUE does cause a change in the interrupt
vector used for transmit interrupts so that a different interrupt handler may be used for a
transmit underrun condition. If a transmit interrupt occurs with TUE set, the Transmit Data
With Exception Status interrupt will be generated and, if a transmit interrupt occurs with
TUE clear, the Transmit Data Without Errors interrupt will be generated.

TUE is cleared by the DSP, SSIx, or STOP reset. TUE is cleared by reading the SSISR
with TUE set followed by writing TX or TSR.

8.13.5 SSISR Receiver Overrun Error (ROE) Bit 5

The Receiver Overrun Error flag is set when the serial receive shift register is filled and
ready to transfer to the receiver data register (RX) and the RX is already full (i.e. RDF=1).
The Receiver Shift Register is not transferred to RX. ROE does not cause any interrupts;
however, ROE does cause a change in the interrupt vector used so that a different inter-
rupt handler may be used for a receive overrun condition. If a receive interrupt occurs with
ROE set, the Receive Data With Exception Status interrupt will be generated and, if a re-
ceive interrupt occurs with ROE clear, the Receive Data Without Errors interrupt will be
generated.

ROE is cleared by the DSP, SSIx, or STOP reset, and is cleared by reading the SSISR
with ROE set followed by reading the RX. Clearing RE does not affect ROE.

8.13.6 SSISR Transmit Data Register Empty (TDE) Bit 6

The SSI Transmit Data Register Empty flag is set when the contents of the Transmit Data
Register are transferred to the Transmit Shift Register.When set, TDE indicates that data
should be written to the TX or to the TSR before the transmit shift register becomes empty
(which would cause an underrun error).

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TIME SLOT REGISTER - TSR

TDE is cleared when the DSP writes to the Transmit Data Register or when the DSP
writes to the TSR to disable transmission of the next time slot. If TIE is set, a SSI Transmit
Data interrupt request will be issued when TDE is set. The interrupt vector will depend on
the state of the Transmitter Underrun TUE bit. TDE is set by the DSP, SSIx, and STOP
reset.

8.13.7 SSISR Receive Data Register Full (RDF) Bit 7

The SSI Receive Data Register Full flag is set when the contents of the Receive Shift Reg-
ister are transferred to the Receive Data Register. When set, RDF indicates that data
should be read from RX so that the next word can be received without an overrun error.
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RDF is cleared when the DSP reads the Receive Data Register. If RIE is set, a DSP re-
ceive data interrupt request will be issued when RDF is set. The interrupt vector request
will depend on the state of the Receiver Overrun ROE bit. RDF is cleared by the DSP,
SSIx, and STOP reset.

8.14 TIME SLOT REGISTER - TSR

The Time Slot Register is used when the data is not to be transmitted (i.e., a blank time
slot) in the available transmit time slot. For the purposes of timing, the time slot register is
a write-only register that behaves like an alternative transmit data register except that
rather than transmitting data, the transmit data pin, STD, is three-stated for that time slot.

8.15 TRANSMIT SLOT MASK REGISTERS - TSMAx AND TSMBx

The Transmit Slot Mask Registers are two 16-bit read/write registers. They are used by
the transmitter in network mode to determine for each slot whether to transmit a data word
and generate a transmitter empty condition (TDE=1), or to three-state the transmit data
pin, STD. TSMAx and TSMBx should be seen as only one 32-bit register, TSMx. Bit num-
ber N in TSMx is an enable/disable control bit for transmission in slot number N.

When bit number N in TSMx is cleared, the transmit data pin STD is three-stated during
transmit time slot number N. The data is still transferred from the Transmit Data Register
to the transmit shift register and the Transmitter Data Empty flag (TDE) is set. Also the
Transmitter Underrun Error flag is not set. This means that during a disabled slot, no
Transmitter Empty interrupt is generated (TDE=0). The DSP is interrupted by activity in
enabled slots only. Data that is written to the Transmit Data Register when servicing this
request is transmitted in the next enabled transmit time slot.

When bit number N in TSMx is set, the transmit sequence is as usual: data is transferred
from TX to the shift register, it is transmitted during transmit time slot number N, and the
TDE flag is set.

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TRANSMIT SLOT MASK SHIFT REGISTER - TSMS

The 32-bit data written into TSMx is transferred to the Transmit Slot Mask Shift Register
(TSMS) during the last slot of the last frame. Writing to TSMx will not affect the state of
the active (enabled) transmit slots during the current transmit frame but only that of the
next frame.

Using the slot mask in TSMx does not conflict with using TSR. Even if a slot is enabled in
TSMx, the user may choose to write to TSR instead of writing to the transmit data register
TX. This will cause the transmit data pin to be three-stated during the next slot.

After DSP reset, the Transmit Slot Mask Register is preset to $FFFFFFFF, which means
that all 32 possible slots are enabled for data transmission.
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Note: The Transmit Slot Mask Registers have to be written before the last three serial
clock cycles of a frame in order to become active at the beginning of the next frame.

8.16 TRANSMIT SLOT MASK SHIFT REGISTER - TSMS

The Transmit Slot Mask Shift Register is a 32-bit shift register. At the end of each frame,
it is loaded with the 32-bit mask from TSM. Then, it is shifted one bit to the right near the
end of each transmitted word. The LSB of TSMS is used as an enable/disable for trans-
mitting data to the transmit data pin (STD) and setting the TDE flag after transmitting data.
This register is not accessible to the programmer.

8.17 RECEIVE SLOT MASK REGISTERS - RSMAx AND RSMBx

The Receive Slot Mask Registers are two 16-bit read/write registers. They are used by
the receiver in network mode to determine for each slot whether to receive a data word
and generate a receiver full condition (RDF=1), or to ignore the received data. RSMAx
and RSMBx should be seen as only one 32-bit register RSMx. Bit number N in RSMx is
an enable/disable control bit for receiving data in slot number N.

When bit number N in RSMx is cleared, the data from the receive data pin is shifted into
the Receive Shift Register during slot number N. Data is not transferred from the Receive
Shift Register to the Receive Data Register and the Receiver Full flag (RDF) is not set.
Also the Receiver Overrun Error flag is not set. This means that during a disabled slot, no
Receiver Full interrupt is generated. The DSP is interrupted (RDF=0). The DSP is inter-
rupted by activity in enabled slots only.

When bit number N in RSMx is set, the receive sequence is as usual: data which is shifted
into the receive shift register is transferred to the Receive Data register and the RDF flag
is set.

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RECEIVE SLOT MASK SHIFT REGISTER - RSMS

The 32-bit mask which is written into RSMx, is transferred to the Receive Slot Mask Shift
Register (RSMS) during the last slot of the last frame. Writing to RSMx will not affect the
state of the active (enabled) receive slots during the current receive frame, but only that
of the next frame.

After DSP reset, the Receive Slot Mask Register is preset to $FFFFFFFF, which means
that all 32 possible slots are enabled for data reception.

Note: The Receive Slot Mask Registers have to be written before the last three serial
clock cycles of a frame in order to become active at the beginning of the next frame.
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8.18 RECEIVE SLOT MASK SHIFT REGISTER - RSMS

The Receive Slot Mask Shift Register (RSMS) is a 32-bit shift register. At the beginning
of each receive frame, it is loaded with the 32-bit mask from RSM. Then, it is shifted one
bit to the right near the end of each received word. The LSB of RSMSR is used as an en-
able/disable for receiving a word and setting the RDF flag. This register is not accessible
to the programmer.

8.19 SSI OPERATING MODES

The SSI on-chip peripheral can operate in three operating modes – Normal, Network, and
On-Demand. In the Normal and Network modes, data is transferred and interrupts are
generated (if enabled) periodically. The On-Demand mode is a special mode which per-
mits data to be transferred serially when necessary in a non-periodic fashion.

Table 8-5 SSI modes

Mode SYN SC1x SC0x

Normal Async RFS In TFS In

RFS Out TFS Out
RFS In TFS Out
Sync — FS In
— FS Out

Network Async RFS In TFS In

RFS Out TFS Out
RFS In TFS Out
Sync — FS In
— FS Out

On-Demand Async RFS Out TFS Out

RFS In TFS Out
Sync — FS Out

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SSI OPERATING MODES

8.19.1 Normal Operating Mode

In the normal mode, the frame rate divider determines the word transfer rate - one word
is transferred per frame sync, during the frame sync time slot.

8.19.1.1 Normal Mode Transmit

The conditions for data transmission from the SSI are:

1. Transmitter Enabled (TE=1)

2. Frame sync becomes active

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When the above conditions occur in normal mode, the next data word will be transferred
from TX to the Transmit shift register, the TDE flag will be set (transmitter empty), and the
transmit interrupt will occur if TIE=1 (Transmit interrupt is enabled). The new data word
will be transmitted immediately.

The transmit data output (STD) is three-stated except during the data transmission period.
The optional frame sync output and clock outputs are not three-stated even if both receiv-
er and transmitter are disabled.

The program must write another word to TX before the next frame sync is received or TUE
will be set and a Transmitter Underrun Error will be generated.

8.19.1.2 Normal Mode Receive

If the receiver is enabled, then each time the frame sync signal is generated (or detected)
a data word will be clocked in. After receiving the data word it will be transferred from the
SSI Receive Shift Register to the Receive Data Register (RX), the RDF flag will be set
(Receiver full), and the Receive Interrupt will occur if it is enabled (RIE=1).

The DSP program has to read the data from RX before a new data word is transferred
from the Receive Shift Register, otherwise the Receiver Overrun error will be set (ROE).

8.19.2 Network Mode

In this mode the SSI can be used in TDM networks and is the typical mode in which the
DSP would interface to a TDM codec network or a network of DSPs. The DSP may be a
master device that controls its own private network or a slave device that is connected to
an existing TDM network and occupies one or more time slots. The distinction of the net-
work mode is that active time slots (data word time) are identified by the transmit and re-
ceive slot mask registers (TSMA0, TSMB0, RSMA0, and RSMB0). For the transmitter,
this allows the option of ignoring a time slot or transmitting data during that time slot. The
receiver is treated in the same manner except that data is always being shifted into the

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SSI OPERATING MODES

Receive Shift Register and transferred to the RX when the corresponding time slot is en-
abled. The DSP will read the receive data register and either use or discard the data ac-
cording to the time slot register and mask.

The frame sync signal indicates the beginning of a new data frame. Each data frame is
divided into time slots and transmission or reception can occur in each time slot (rather
than in just the frame sync time slot as in the normal mode). The frame rate dividers, con-
trolled by DC4, DC3, DC2, DC1, and DC0 control the number of time slots per frame from
2 to 32.

8.19.2.1 Network Mode Transmit

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The transmit portion of the SSI is enabled when TE=1. However, when TE is sets the
transmitter will be enabled only after detection of a new data frame sync. This allows the
SSI to synchronize to the network timing.

Normal start up sequence for transmission in the first time slot is to write the data to be
transmitted to the Transmit Register (TX), this clears the TDE flag. Then set TE and TIE
to enable the transmitter on the next frame sync and to enable transmit interrupts.

Alternatively, the DSP programmer may decide not to transmit in the first time slot by writ-
ing (any data) to the Time Slot Register (TSR). This will clear the TDE flag just as if data
were going to be transmitted, but the STD pin will remain in three-state for the first time
slot. The programmer then sets TE and TIE as above.

When the frame sync is detected (or generated), the first enabled data word will be trans-
ferred from TX to the Transmit Shift Register and will be shifted out (transmitted). TX now
being empty will cause TDE to be set which, if TIE is set, will cause a transmitter interrupt.
Software can (1) poll TDE, or (2) use interrupts to reload the TX register with new data for
the next time slot, or (3) write to the TSR to prevent transmitting in the next active time
slot. The transmit and receive slot mask registers control which time slots will be used.
Failing to reload TX (or writing to TSR) before the next active time slot will cause a trans-
mitter underrun and the TUE error bit will be set.

Clearing TE and setting it again will disable the transmitter after completion of transmis-
sion of the current data word until the beginning of the next frame sync period. During that
time the STD pin will be three-stated. TE should be cleared after TDE gets set to ensure
that all pending data is transmitted.

To summarize, the network mode transmitter generates interrupts every enabled time
slot (TE=1, TIE=1) and requires the DSP program to respond to each enabled time slot.
These responses may be:

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1. Write TX data register with data for transmission in the next time slot

2. Write the time slot register to disable transmission in the next time slot

3. Do nothing - transmit underrun will occur at the beginning of the next active time
slot and the previous data will be transmitted

8.19.2.2 Network Mode Receive

The receiver portion of SSI is enabled when RE is set; however, the receive enable will
take place only after detection of a new data frame. After detection of the new data frame,
the first data word will be shifted into the Receive Shift Register during the first active slot.
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When the word is completely received, it is transferred to the RX which sets the RDF flag
(Receive Data register full). Setting RDF will cause a receive interrupt to occur if the re-
ceiver interrupt is enabled (RIE=1).

During the second active time slot, the second data word begins shifting in. The DSP pro-
gram must read the data from RX (which clears RDF) before the second data word is com-
pletely received (ready to transfer to RX) or a receive overrun error will occur (ROE gets
set).

If the RE bit is cleared and set again by the DSP programmer, the receiver, after receiving
the current time slot in progress, will be disabled until the next frame sync (first time slot).
This mechanism allows the DSP programmer to ignore data in the last portion of a data
frame.

Note: The optional frame sync output and clock output signals are not affected even if the
transmitter and/or receiver are disabled. TE and RE do not disable bit clock and
frame sync generation.

To summarize, in the Network mode, an interrupt can occur after the reception of each
enabled data word or the programmer can poll the RDF flag. The DSP program response
can be:

1. Read RX and use the data

2. Read RX and ignore the data

3. Do nothing - the receiver overrun exception will occur at the end of the next ac-
tive time slot

8.19.2.3 On-Demand Mode

A divide ratio of one (DC=00000) in the network mode is a special case. This is the only
data driven mode of the SSI and is defined as the on-demand mode. This special case

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will not generate a periodic frame sync. A frame sync pulse will be generated only when
there is data available to transmit. The On-demand mode requires that the transmit frame
sync be internal (output) — i.e., the on-demand mode is disallowed whenever the transmit
frame sync is configured as an input. Data transmission is data driven and is enabled by
writing data into the TX register. Receive and transmit interrupts function with the TDE and
RDF flags as normally; however, transmit underruns (TUE) are impossible for on-demand
transmission.
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