462 IEEE WESCANEX ’95 PROCEEDINGS

Synthesizing Testability Features into a Design with the

Synopsys Test Compiler
Zaifu Zhang, Richard Wieler, GUYJonatschick, and Hart Poskar
Department of Electrical and Computer Engineering
University Of Manitoba, Winnipeg, Manitoba, Canada R3T 5V6

Abstract 0 Register transfer

I n t h i s paper, w e present a methodology f o r s y n t h e -
0 Gate level functional with unit delay
sizing testability f e a t u r e s in a design described u s i n g
Hardware Description Langvage ( H D L ) a n d t h e S y n - 0 Gate level with detailed timing
opsys T e s t C o m p z l e r tool. Because a n H D L described
design of a n IC device c a n be automatically trans- Also, an HDL specified design of a system can be au-
f o r m e d i n t o a gate-level i m p l e m e n t a t i o n for a given tomatically transformed into a gate-level implemen-
technology w i t h S y n o p s y s S y n t h e s i s Tools, adding in- tation for a given technology by Synopsys Synthesis
t e r n a l s c a n t e s t circuitry or boundary scan t e s t cir- Tools.
c u i t r y can be easily achieved w i t h t h e S y n o p s y s Tesi Synopsys Synthesis Tools include HDL Compiler.
C o m p i l e r . W e will discuss scan styles, iest methodolo- Design Compiler, and Test Compiler families. Syn-
g7fs. i e s f p a i i e r n generation, as well as t h e application
opsys Synthesis Tools have functional verification, be-
& f o r m a i of test patierns. havior simulation, and testability insertion features.
HDL[7] (e.g. VHDL and Verilog) which describes
1 Introduction the architecture and behavior of a micro-elect,ronic
IVith the growing complexity of modern VLSI cir- system provides technology-independent documenta-
cuitry, the abi1it.y to perform both time and cost effec- tion of a design and its funct.ionality. The HDL Com-
tive design and t,est of integrated circuit _(IC) devices piler performs two functions: translating HDLs to an
has become increasingly difficult. Since each IC de- internal format which Synopsys Synthesis Tools can
vice is of very high densit.y and the ratio of pins t o accept and recognize, and optimizing the block level
gates in each IC device is quite low, there is limited representation through various optimization methods.
accessibility to the internal nodes of an IC circuit. In Design Compiler[G] reads the design in the internal for-
order to reduce the cost of testing and to improve the mat generated by the HDL Compiler, then optimizes
quality of test. inherent testability is a desirable fea- and maps the design’s logical struct,ure for a specific
ture of modern IC logic design. Design for test and ASIC technology library.
built-in test strategies give better test coverage in less
2 Synopsys Test Compiler
time and eliminate the need for expensive specialized
test equipment to diagnose faults[l][2][3][4]. Synthe- The Synopsys Test Compiler and Test Compiler
Plus[8] support various implementation styles for in-
sizing testability features into an IC device is impera-
tive in modern IC logic design. Also, designing an IC ternal full-scan and boundary scan. Test Compiler
Plus supports constraint-driven partial scan imple-
device with behavior-based design automation (DA)
tools will ease the bottleneck difficulty of designing an mentation styles. Both t,ools provide a programmable
test protocol and support scanned and transparent
IC device at, gate level[5].
Synopsys Synthesis Tools[6][7][8] are top-down latches.
behavior-based design tools. By starting at the level The Synopsys Test Compiler family performs the
following tasks:
of architecture and behavior of an IC micro-electronic
system with Synopsys Synthesis Tools, the gate-level 0 Automatically checks the user’s design against
design bottleneck is eliminated. An HDL specified de- the design rules of his chosen internal scan-t,est
sign of a system can be written at various levels of implementation style
abstraction which include:
- The user can choose a scan implementation
0 Algorithmic style based on the design requirements of the

IEEE CAT. NO. 95CH3581-6/0-7803-2741-1/95/$3.000 1995 IEEE

ZHANG, Z. etal.: SYNTHESIZING TESTABILITY FEATURES INTO A DESIGN WITH THE SYNOPSYS TEST COMPILER 463

clocking schemes, number of additional 1/0 0 Allows the user to view results and examine re-
pins, performance impact, area impact, and ports through the Design Analyzer’s graphical
latches or (and) flip-flops. interface to trace design rule violations back to
- The user can include boundary scan cir-
schematics
cuitry in the design. - The user can display test-related informa-
- The user can define a test mode. tion about the design
- The user can create a scan-test protocol.
3 Design Flow Using the Syiiopsys
- The user can test latches in transparent
mode.
Test Compiler
To synthesize a fully-optimized design with
Adds test circuitry to a design internal-scan and (or) boundary-scan circuitry, the fol-
lowing commands in d c s h e l l script[6] are required as
- When synthesizing internal scan circuitry, follows:
the Synopsys Test Compiler replaces the se-
quential logic elements (flip-flops) in a design 1 Read an HDL (VHDL or Verilog format) circuit
with logically equivalent elements that also description of a design.
perform a serial shift function for scanning.
dcshell>read -format vhdl destgn-name.vhdl
- The Synopsys Test Compiler supports both
full scan and partial scan design. 2 Select the target technology library and the design
- The Synopsys Test Compiler Plus can also constraints:
add boundary-scan test circuitry to a design. dcshell>targetlibrary = aszc-vendor.db
- The user can configure the scan cells in the dcshell>maxarea 1000
design into single or multiple scan chains. dcshell>niaxdelay 10.O
- The user can determining the scan chain or- dcshell>create-clock c l o c k p a r t -period ?O \
der. -waveform { l O , l S }

0 Accepts designs with existing scan 3 Synthesize a design to meet the constraints set,
and map the circuit description to cells from the
0 Handles internal three-state Busses target technology library:
- The Synopsys Test Compiler prevents bus dcshelbcompile
contention and bus float problems during The command compile not only perforins synthe-
scan shift by adding disabling logic. sis and optimization on the design with respect to area
and speed, but also removes redundant logic
Generates test patterns
4 Declare the methodology (full scan or partial
- The user can control the ATPG (automatic
scan), select the scan implementation style (mul-
test pattern generation) process.
tiplexed flip-flops, clocked scan cells, LSSD scan
- The user can determine which faults are con- cells) and set minimum fault coverage constraint.
sidered.
dcshelbset-test methodology full-scan
- The user can interrupt and restart the pat-
dcshell>setscanstyle multiplexed-flip-flop
tern generation process.
dcshell>setfaultxoverage 95
- The user can specify how much effort is used
in the test pattern compaction process. 5 Check the design rules based on the above cho-
sen scan implementation style. and describe any
0 Formats Test Patterns potential problems:
- The user can write out test patterns in a va- dcshelbcheck-test
riety of formats including Synopsys generzc,
TSSI, Verzlog and VHDL formats. 6 Add scan circuitry to the design.
- The user can control the key test vector dcshell>insert -test
timing parameters including period, strobe,
clock waveforms, input delay and bidirec- 7 Minimize the performance and area impact of
tional delay added scan circuitry.
464 IEEE WESCANEX '95 PROCEEDINGS

.:.-
. I.
.combinational
..- ..
:
).

.. ., ..
:.' sequential

(C) (d)

Figure 1: (a) shows a D flip-flop without and with scan feature, (b) shows a circuit in which sequential and
combinational logic are included without adding scan circuitry. (c) shows full scan style test circuitry is inserted
in the circuit, and (d) shows partial scan style test circuit,ry is inserted in the circuit

dcshell>compile -incremental (e.g. multiplexed flip-flops shown in figure l ( a ) ,

clocked scan cells, or LSSD scan cells) to replace
8 Synthesis default JTAG circuitry to prepare for
non-scannable storage elements, and test methodolo-
board level testing:
gies ( f u l l scan or partial scan) with the Synopsys
dcshell>insert jtag Test Compiler to achieve internal t,estability of the
9 Generate a compacted set of test vectors for the circuit. The Synopsys Test, Compiler also can au-
complete design with medium ( m e d ) CPU re- tomatically assign I/O pins for test ports: scan-in,
sources (This applies only to a full-scan design): scan-ont, a test-clock <master>, b test-clock <slave>,
scan-enable, iest-scan-clock, and test-clock to the de-
dcshell>create-test-patterns \ sign. The user can use the command setsignal-type
-compaction_effort me$
t,o specify which available ports are to be used as test
10 LVrite out the complete design in Synopsys ports in order to prevent the creation of additional
database ( d b ) format to save the link between the ports for test purposes.
design and the generated vectors:
Figure 1 shows a block diagram of a circuit wit.h
d c s h e l l > w r i t e -format db -out desrgn.db scan-loadable sequential logic (represented by rectan-
11 Write out the test vectors and timing parameters gles) and combinational logic (ovals). The clock di-
in an ASCII format (The default Synopsys generic agram also shows the scan path through the circuit.
format is used here): In full scan design shown in figure l(c), all sequen-
tial cells are modified. In partial scan design shown in
dcshell>write_test-out test-vectors figure l(d), only part of sequential cells are modified.
The above testability feature insertion procedure The Synopsys Test Compiler can set the constrainQs
can also be done from design-analyzer through the for a design to be based on area (number of gates),
command window. performance (tolerant delay (ns)), fault coverage (per-
centage of detected faults), number of scan chains, and
4 Synthesizing Testability into a De- order of cells in scan chains etc.. The Synopsj-s Test
sign with t h e Synopsys Test Com- Compiler checks design rules by simulating the scan
piler test protocol symbolically and verifying that, user's de-
For a design of an IC device described by an sign complies with scan design rules, and issues eit.lier
HDL, we may use different styles of scannable cells warnings or error messages.
ZHANG, Z. et al.: SYNTHESIZING TESTABILITY FEATURES INTO A DESIGN WITH THE SYNOPSYS TEST COMPILER 465

l h I- I
i IDI Qh
' I
B

A
-I1 pQNpq

Figure 2: A circuit design with tri-state busses Figure 3: The circuit design with multiplexed flip-flop
style scan circuitry and three-state disabling logic

As an example, a circuit design D-EXAMPLE us- with the option -scan-chams and the maximum num-
ing tri-state gates without test circuitry is shown in ber of scan cells that can be connected 111 any one
figure 2. After we perform the following commands in scan chain with the option -max-scan_chazn-leiigfh
the dcshell script: Therefore, when the user inserts a testability feature
dcshelbcurrentdesign = D-EXA MPLE into the design with the Synopsys Test Compiler. the
dcshell >set s c a nstyle mult iplcxed-flip-flop user can configure the preferred routing order of the
dcshell >insert -test scan cells and the appropriate number of the scan
the multiplexed flip-flop style scan circuitry and tri- chains to enhance scan-based skewed-load delay fault
state disabling logic which is used to prevent tri-state test [ 111[ 121[ 131.
buss cont,ention have been added by t,he Synopsys Test
Compiler. Also, the signals test-se, test-si, and test-so
5 Adding Boundary Scan Test Cir-
are added and globally connected to the scan chain. cuitry
The scan cells are routed in the default alphabetical The Synopsys Test Compiler automatically s\ n-
routing order in a single scan chain. New additional thesizes JTAG boundary scan components for a de-
ports have been created for the test signals and are sign These components comply with the JTAG IEEE
connected to the scan cells. Figure 3 illustrates the 1149.1 standard. By default, the Synopsys Test Com-
design with multiplexed flip-flop style scan circuitry piler generates a 5-pin TAP which includes TAW,
and tri-state disabling logic after insertion of test cir- TCK, TDI, TDO and the optional asynchronous re-
cuitry. set, T R S T ports. All boundary scan register (BSR)
The user can specify rout.ing order of the scan chain cells except clocks have both control and observe ca-
when adding a scan circuitry into the design. For ex- pabilities. Also, the default instruction set contains
ample, if the following commands in dcshell script: the three mandatory JTAG instructions. BYPASS.
are issued E X T E S T , and SAMPLE/PRELOAD.
Figure 5 shows a default JTAG architecture. The
dcshell>setfestroutingDrder { FF2/QN, \ Synopsys Test Compiler can identify existing JTAG
FFS/QN, F F l / Q N ) test ports, define JTAG instructions, and configure
dcshelbinsert-test -noinsert the BSR boundary scan cells. The user also can con-
the scan chain is routed through the pin QN of scan figure a preferred BIST scheme[9] for the internal core
flip-flop FF2, then the pin QN of scan flip-flop FF3. logic with the less correlated Cellular Automata as a
and finally the QN of scan flip-flop FF1 shown in figure pattern generator and signature analyzer[lO] with the
4. Synopsys Test Compiler.
The command insert -test can specify the number The Synopsys Test Compiler supports a pro-
of scan chains the user wants to construct in a design grammable JTAG synthesis capability The user caii
466 IEEE WESCANEX '9.5 PROCEEDINGS

4, Bypass Register

a ........................................................
_.. ............................................. .........,

t?St_Sl
: Ins-zdction Cecode Logic control

: InsUutlm~le

2-511 Lxtruction Register ( I R I

hi?St_S3

Figure 4: The circuit design aft.er insert-test with

preferred routing order
R?Sei*
%S ;
ClockIR
TS?'":
U?dace:F.
use the command insert-jtag with its options to syn- ICk ~

Select
t,hesize the TRST port, include a device identification "3Xe 7
register, indicate and specify the size of the instruc-
tion regist,er, and synthesize 1/0 pads in the JTAG Test Access Port (TAP) j
.....................................................................,
design. The user can specify a JTAG boundary scan
instruction that is recognized, decoded and acted upon Figure 5: Default JTAG Architecture
by the synthesized JTAG test circuitry with the com-
mand set-jtaginstruction. Also, the user can set
the routing order of BSR cells, JTAG port modes bariety of options to determine maximum total ATPG
and types, and choose BSR cell implement,ations with CPI: time, maximum CPU time spent per fault dur-
the commands which include set-jtag_port-order, ing the deterministic generation phase, backtracking
set -j t ag -por t -iode, set -jt ag -por t -t ype , and limit for the deterministic generation phase maximum
set -jt ag implementation. number of random patterns generated during the ran-
dom generation phase, and when the random genera-
6 Generating Test P a t t e r n s tion phase terminates based on the number of patterns
The test pat.terns can be generated and compacbed that fail to increase fault coverage The user can input
to form a minimal t,est set for a design after test. cir- the command set-testfault to eliminate considera-
cuitry has been inserted with the Synopsys Test. Com- tion of some faults by the Synopsys Test Compiler
piler. The Synopsys Test Compiler can a.nalyze each The Synopsys Test Compiler supports test pattern
node in the design and automatically generates test generation for one or multiple scan chains In gen-
patterns to target all the detectable stuck-at faults. eral, the procedure of full scan-test sequence is given
The Synopsys Test Compiler can estimate testability in following
of the design to incrementally improve testability of a
design by updating test circuitry for the design, espe- 1 Serially shift in the test patterns through the
cially for partial-scan design. scan-in port
For a full-scan design, the Synopsys Test Compiler's
ATPG process has three phases which include random 2. Apply stimuli to the primary inputs
generation of patterns to cover easy-to-detect faults ef- 3 Measure the output response
ficiently, det.erministic generation of patterns to cover
specific stuck-at faults that are hard to detect, and 4 Pulse the system clock once to latch all the inter-
compaction of t.he original set of patterns into a sub- nal states
set that achieves the same fault coverage. The user
can use the command create-test-patterns with a 5. Shift out the response at the scan-out port.
WANG, Z. et ai.. SYNTHESIZING TESTABILITY FEATURES INTO A DESIGN WITH THE SYNOPSYS TEST COMPILER 467

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[4]V.D. Agrawal, C.R. Kinie, and K . K . Saluja.
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I
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[5] C.H. Gebotys and M.I. Elmasry, “Optimal VLSI
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1992.
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Compiler allows the users to write his a protocol to de-
[7] “Synopsys: I’HDL Compiler Reference
fine t,he testing process for a design, the user can easily
Manual”, Version 3.Ub, Synopsys Inc., June
formulate scan-based skewed-load delay fault testing
1993.
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a delay fault test procedure to be similar to that given [8] “Synopsys: Test CompilerTJir and Test
in [ 141. Compiler P l u ~ ~Reference
” ~ Manual” l e r s i o n
The Synopsys Test Compiler can generate test pat- 3.Uj Synopsys Inc., December 1992.
terns in a tester-independent format. It then for- [9] C. Gloster. Jr. and F. Brglez, “Boundary Scan
mats the test patterns into manufacturing test vec- with Cellular-based Built-In Self-Test“ , IEEE
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sys generic, (TSSI) TDS ASCII, Verilog, VHDL, and
Based Pseudo-random “umber Generators for
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command writefest to format. the test vectors.
pp ,842-859 , 1989.
7 Summary [113 G.L. Smith, “Model for Delay Faults”, IEEE
In this article, we have surveyed the synthesizing Int ’I Test Conference, pp.342-349, 1985.
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piler. The user can refine or modify a design to more [13] Z . Zhang, R.D. McLeod, and W. Pedrycz.
easily integrate testing. Synopsys Synthesizing Tools “Augmenting Scan Path SRLs with an XOR
are user friendly design tools. The period of designing Net.work to Enhance Delay Fault Testing”,
an IC device, verifying it, synthesizing testability fea- IEEE Int’l Workshop on Defect a n d Fauli
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reduced with the help of Synopsys Synthesizing Tools.
Also, we can extend the Synopsys Test Compiler’s syn- [14] Y. Aizenbud, M . Leibowitz, P. Chang, D. Smith,
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fault testing. “AC Test. Quality: Beyond Transition Fault
Coverage”, IEEE In2 ’I Test Conference. pp.568-
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