Third-order PLL

There is still one residual problem that we have overlooked. The phase detector produces
pulses of variable width that activate the switches to either charge or discharge the
capacitor CP in the case of the charge pump PFD-CP combination. Now that we have
added the resistor RP, which is absolutely necessary for stability, we find that the control
voltage coming out of the charge pump will jump up or down before settling to its steady
state value. This occurs because you cannot change the voltage across a capacitor
instantaneously, so the initial voltage drop occurs across RP, which then charges CP
exponentially. This jumpy control voltage frequency modulates the VCO at the reference
frequency, creating reference spurs. This is not such a big problem if N = 1 because the
jump will be at the same frequency as the VCO. But, at larger N values, it creates low
frequency jitter producing FM sidebands.

φin(t) φout(t)
Phase Loop
detector Filter F(s) VCO

1/N

ωout
Frequency spectrum of output.
Reference spur sidebands are spaced at intervals of ωin.

So, we need to fix this by adding a second capacitor, C2, whose function is to filter out
the jumpy response of the series RC network. The magnitude of the reference spur
sidebands is reduced. Unfortunately, however, C2 adds a third pole of finite frequency
that will reduce the stability of the PLL. Now, the handy tools we have been using for
predicting performance of the second-order PLL no longer are accurate.
A look at the Bode plot verifies this.

IP

fREF
φIN QA UP

PFD VCO
DOWN
QB
RP C2 φOUT
IP
fOUT

CP

1/N

1 C P + C2
ωz = ω p3 =
RP CP RPCPC2

20 log |T(jω)|

Crossover freq.
0 dB ωC2

ωz

0
∠T(jω)
-90

PM
-180

5/22/08 Prof. S. Long/ UCSB 2

The pole frequency is given by RP in parallel with the series combination of CP and C2.
Thus, the pole is always higher in frequency than the zero. We can see that the added
pole reduces the phase margin. In fact, now when the loop gain is increased, phase
margin is reduced.

Since the second order model using ωn and ζ are no longer valid for predicting settling
behavior, a different way is needed to relate crossover frequency and phase margin to
settling time. The figure below, from Vaucher1 provides this link. A frequency step
response is plotted. In this figure, the frequency error, Δf, is normalized to a frequency
step, fstep, and is plotted against a normalized time axis, fCt. Here, fC is the crossover
frequency. φm is the phase margin.

According to the plot, a PM of 50 degrees produces more overshoot, but settles faster
than 65 degrees. If the higher overshoot can be tolerated, this would be a better choice.
If less overshoot is required, then the 65 degree PM is best. A higher fC will be required,
however, to meet the same settling time spec. The 30 degree case seems to have no
benefits.

1
C. S. Vaucher, “An adaptive PLL tuning system architecture combining high spectral purity and fast
settling time, IEEE J. Solid State Cir., Vol. 35, #4, pp. 490 – 502, April 2000.

5/22/08 Prof. S. Long/ UCSB 3

The next plot shows the settling transient for different PM values expanded on a log scale
[1]. The vertical axis plots ln(| Δf ( f ct ) | / f step . This gives the remaining frequency
error Δf in response to a step in frequency f step plotted against a normalized time axis
fC t .

Fig. 3(b). The red and green lines trace the envelope for the 30 and 50 degree cases. For
example, at tlock = 2fCt and φm = 50 degrees, the frequency has settled to within e-9 = 1.23
x 10-4 of its final value. (ref. C. Vaucher, op. cit.)

This plot can be used to determine the crossover frequency required for a particular
settling time, tlock.

Ex. Suppose we want to achieve settling to within 0.1 % in 2 ms.

ln(0.001) = -6.9.

If we choose the 50 degree PM, fC tlock = 1.7

So, fC = 1.7/0.002 = 850 Hz.

5/22/08 Prof. S. Long/ UCSB 4

Because some applications require a smaller residual settling error, Vaucher [1] also
provides a plot showing settling time to e-10 (4.5 x 10-5) vs. phase margin.

(ref. C. Vaucher, op. cit.)

The settling time reaches a sharp minimum at about 51 degree PM. This is the phase
margin just below the point at which the closed loop poles are coincident at – fC. [1]
Thus, the design of critically damped loops, a PM of about 70 degrees, does not lead to
the fastest settling time for third order CP PLLs.

5/22/08 Prof. S. Long/ UCSB 5

Alternatively:
Recall that the rate at which a second-order low pass system responds to a step in phase
−ω ζ t
or frequency is given by e n , the envelope of the damped ringing. Vaucher
hypothesizes that an effective damping factor, ζ e (φm ) , can be defined from the envelope
of the responses in fig. 3(b). Then,

−Δ( env(ln( Δf ( f c t ) / f step )))

ζ e ( φm ) =
Δ( f c t )

ln ( f step / f error )
1
fC =
tlock ζ e ( φm )

fstep is the amplitude of the frequency jump

ferror is the maximum frequency error at tlock

Figure 6 is extracted from Fig. 4. It shows the effective damping factor vs phase margin
for ln(fstep/ferror) = -10.

5/22/08 Prof. S. Long/ UCSB 6

Design of charge pump PLL. The equation for loop gain T(s) can be used with the
Bode plot to set the crossover frequency and determine k to obtain a particular phase
margin. fC and φm can be determined from the above plots to match a particular settling
time specification.

The phase frequency detector (PFD) with single capacitor CP has

Vout ( s ) IP
=
Δφ 2π CP s

To find the frequency response of the input current, we note that,

I(s) = Vout(s)/Z(s) = Vout(s)/(1/sCP)

where Z(s) is the complex impedance. So, the current source can be modeled as:

I( s ) I P
= .
Δφ 2π

Now, let’s use this to modify the PFD-CP combination for the third-order loop filter.
Multiply the current by the new Z(s):

1 ⎛ 1 ⎞ 1 (1 + s / ω z )
Z ( s) = || ⎜ RP + ⎟=
sC2 ⎝ sCP ⎠ CP + C2 s(1 + s / ω p 3 )

So, the loop gain, T(s),

I P KO (1 + s / ω z )
T (s) =
2π N (CP + C2 ) s (1 + s / ω p 3 )
2

Where ω z = 1/ RPCP and ω p 3 = (CP + C2 ) /( RPCPC2 ) .

The next step is to determine the zero and third pole frequencies needed to obtain the
desired phase margin. One strategy is to choose these frequencies centered around the
crossover frequency. The Bode plot can be used to estimate this. We want to choose k
such that

5/22/08 Prof. S. Long/ UCSB 7

 ωz = ωc / k
ω p 3 = ωc ⋅ k

|Τ(jω)| dB

ωz ωC ωp3

∠ Τ(jω)

1 10 100 103 104

Rad/sec

Here we see a solution sketched out for k = 4. The factor k can be estimated by2

1/ 2
⎡1 + sin(φm ) ⎤
k=⎢ ⎥
⎣1 − sin(φm ) ⎦

2
D. Shaeffer, Design Criteria for Frequency Synthesis in Wireless Systems, Session F1, Girafe Design
Forum, ISSCC 2005.

5/22/08 Prof. S. Long/ UCSB 8

Design process:
1. fC and φm are determined by settling time using the plots from [1].
2. k is derived from φm. So, ωz and ωp3 are known.
3..At this stage, you can estimate the loop filter components. Here are three ways that
give reasonably accurate results. You can later use ADS to optimize from these initial
results if they are not sufficiently accurate for your design.

a. First method does not make any assumptions. Start from loop gain.

I P KO (1 + s / ω z )
T (s) =
2π N (CP + C2 ) s 2 (1 + s / ω p 3 )

Evaluate the magnitude at the crossover frequency. We see that the frequency ratios at
crossover are just defined by k. And, at crossover, | T ( jωC ) | = 1

I P KO 1 + (ωc / ω z ) 2 I P KO 1 + (k )2
| T ( jωc ) | = = =1
2π N (C2 + CP )ωc2 1 + (ωc / ω p 3 ) 2 2π N (C2 + CP )ωc 1 + (1/ k ) 2
2

Thus, CT = C2 + CP can be determined. Then,

ω p3 C + CP C + CP
= k2 = 2 i RPCP = 2
ωz RPCPC2 C2
so,
C2 + C P
C2 =
k2
and
CP = CT − C2
and
1
RP =
ω z CP

b. Another method makes the assumptions that ωz << ωC, ωC << ωp3 and
C P + C2 ≈ C P

Start with the magnitude of T(jω).

5/22/08 Prof. S. Long/ UCSB 9

 I P KO 1 + (ω RPCP ) 2
| T ( jω ) | =
2π N (CP + C2 )ω 2 1 + (ω / ω p 3 ) 2

Then at crossover, | T ( jωC ) | = 1 , so solve for RP.

I K (ωC RPCP ) 2 I P KO RP
| T ( jωC ) | ≈ P O ≈ =1
2π NCP ωC2 2π N ωC

Once RP is known, then CP and C2 follow from ωz and ωp3.

C P + C2
ω p3 =
RPCPC2

1
ωz =
RPCP
CP C
C2 = = 2P
(ω P 3 / ω z − 1) k − 1
OR:

c. Calculate the loop gain at a low enough frequency that both zero and third pole
contribution to the magnitude can be ignored. Suppose you set ω = 1 rad/s. The loop
gain can be determined by a Bode plot method, either on the graph or using:

⎛ω ⎞
dB of | T ( j1) | = 20log ⎜ C ⎟ + 40log (ω z ) . (dB)
⎝ ωz ⎠

Then, convert from dB to a ratio:

I P KO
| T ( j1) | =
2π N (CP + C2 )

so, CP + C2 can be determined. Let’s call this CT. Then, using, ωz and ωP3, then using
the equations in part a., RP and CP can be found from ωz and C2:

5/22/08 Prof. S. Long/ UCSB 10

 1
RP =
ω z (CT − C2 )
1
CP =
ω z RP

Implicit in all of this is that you have a specific divide ratio N that you are designing for.
In all cases, however, N will vary over some range so that the synthesizer frequency can
be tuned. And, over this frequency range, KO is not constant either. Both of these
variations will affect the phase margin and settling time since the loop gain depends on
both of these factors.

Your job, then, is to figure out ahead of time which extreme represents the worst case in
terms of whatever parameter you are trying to specify: overshoot, spur rejection or
settling time. Design for the worst case, and the other extreme will most likely exceed
specs.

In the case of the second order loop, the end with the lowest KV and highest N generally
produces the lowest phase margin. Phase margin increases as the crossover frequency
increases. ωn increases, but ζ also increases. Thus, the settling time must be estimated at
both ends and depends on the specific design details. Spur rejection gets worse for higher
crossover.

You can estimate the settling time from the exponential behavior of the transient
response:

Δf
e −ωnζ ts = = fractional freqerror
f final
− ln(Δf / f final )
ts =
ωnζ

For the third-order PLL, the opposite is true. Phase margin, overshoot and spur rejection
get worse as the crossover frequency increases. Analysis is more difficult, but a Bode
plot can be used to estimate the crossover frequency and phase margin. Settling response
can be estimated from the normalized curves. ADS or MATLAB simulation should be
used to verify the results.

5/22/08 Prof. S. Long/ UCSB 11

Reference spur rejection. Refer to the magnitude Bode plot below.

The slope approaching and leaving the crossover region is – 40 dB/decade because:
1. Type 2 loop gain function has a factor of 1/s2. However,
2. The zero reduces slope to – 20 dB/decade in the crossover region, but because the
reference frequency must be at least 10 times fC, the slope again approaches -40
dB when the third pole kicks in.

So, depending on the relationship between the reference and crossover frequencies, we
can predict the spur rejection based upon either a – 20 or -40 dB/decade extrapolation.
From the Bode plot, you can see that the closed loop gain is the same as open loop gain
after crossover. The gain at crossover is 0 dB, so anything beyond that frequency will be
attenuated as shown.

Example: suppose the reference frequency is 100 KHz. Crossover is about 2 kHz in this
example. We can see that the graph predicts – 60 dB of attenuation for 100 kHz signals.

Or, estimate from the equation below:

⎛ f ⎞ ⎛ f ⎞
SR ≅ 20 log ⎜ P 3 ⎟ + 40 log ⎜ ref ⎟
⎝ fC ⎠ ⎝ f P3 ⎠

5/22/08 Prof. S. Long/ UCSB 12

OpAmp Loop Filter Version
The charge pump solution, although quite popular, is not the only possibility. You can
also produce the Type 2, third-order loop gain function using the opamp style loop filter
shown below. Capacitor C1 gives the third pole in this case.

R2

R1 R1 C2
_
1
ωZ = PD inputs
C1
+
R2C2
R1 R1
2
ω p3 = C1 R2
R1C1
C2

Because the phase-frequency detector has limited current output capability, you need to
make sure that R1 is sufficiently large so that this current is not exceeded, otherwise the
filter will not work correctly. In deriving the transfer function, F(s), you should note that
only one input at a time is being driven. The PFD output gives either UP or DOWN
pulses (neglecting the very narrow pulses produced at both outputs when the loop is
locked) if the phase is lagging or leading respectively.

(1 + s / ω z )
F ( s) =
2sC2 R1 (1 + s / ωP 3 )

The block diagram of the PLL with opamp filter is shown below. From the diagram, T(s)
can be seen to be:

K D KO (1 + s / ω z )
T (s) =
2 NC2 R1s (1 + s / ωP 3 )
2

Then the design can proceed in a similar manner as with the charge pump if phase margin
and settling time are known.

5/22/08 Prof. S. Long/ UCSB 13

 R2

D R1 R1 VCO
C2
_
C1 KO/s
PFD
fREF +
R1 R1
U
KD
C1 R2

C2

1/N

I P KO 1 + (ωc / ω z ) 2 I P KO 1 + (k )2
| T ( jωc ) | = = =1
2 NC2 R1ωc2 1 + (ω p 3 / ωc )2 2 NC2 R1ωc 1 + (1/ k ) 2
2

R1 is known from the phase frequency detector maximum current limitation.

So, solve for C2. Then,

1
R2 =
ω z C2

2
C1 =
ω p 3 R1

5/22/08 Prof. S. Long/ UCSB 14

Simulation tool: You can verify your design using the ADS PLL design guide.

1. The first step is to select the PLL design guide from the DesignGuide menu. Then
select the application, in this example, Frequency Synthesizer.

2. Next, specify which type of simulation you wish to perform.

5/22/08 Prof. S. Long/ UCSB 15

3. The type of phase detector being used must be selected.

4. Finally, select the filter type. The RPCPC2 combination is a passive 3 pole, of course.

The frequency response simulation mode uses the AC analysis method. It plots a Bode
plot of the open and closed loop gain. Component values can be optimized.

5/22/08 Prof. S. Long/ UCSB 16

You will need to specify your reference frequency, charge pump current, the divide ratio,
and your VCO tuning coefficient. Enter the corresponding filter component values. To
evaluate your calculated component values, you should disable the optimization
controller. Then, the Bode plot that is produced will reflect your choice of components.
You can refine the solution later by using the optimization feature.

With optimization disabled, the lowpass filter component values are not displayed, but
crossover frequency, phase margin and spur attenuation are calculated.

When you optimize, then specify the desired crossover frequency and phase margin. But,
start from the component values you have already selected to obtain a solution that is
closer to optimum. The optimizer does not generate a unique solution, and the closer the
initial values are to your goal, the more useful the result.

5/22/08 Prof. S. Long/ UCSB 17

A transient simulation can also be used to verify settling time.

Note the components on the far right, R4 and C3. These model the input to your VCO.
If C3 is large, it will produce a 4th pole that could badly affect your step response. Be
sure that the VCO does not have any large filtering capacitors at the tuning port.

5/22/08 Prof. S. Long/ UCSB 18