11/16/2017 UNATE : Timing Arc |VLSI Concepts

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Monday, December 26, 2016

"Fresher" become
UNATE : Timing Arc 3Ps (Passion, Pati

The Journey from Fres

easy as everyone think
Previous Article is all about "What is Timing Arc?" and "How can you categorize them (Net Arc and Gate Arc; Delay Arc and Constraint Arc)?" suggest to students/ca
But still we need to understand how timing arc help us to answer our questions related to any Standard Cell or any Flip-flop or any system (like
Macros, IPs)...
Vlsi ex
1. For a Particular Input (Rising or falling), What type of Output (output is rising or falling or no change) you get ?
Like
2. How much time (may be in the form of Delay) it will take to respond for a particular Input ?
3. Is there any constraint on any pin and if yes, then what are those and on what pin ?
Be the first of your f

First Question can be Answer if we know: How Input pin is logically connected with Output pin.

What is the meaning of Logically connection? It Means, what is going to happen “For Rising Input"...whether Output
Fall or
Rise or
No Change

Timing Arc help us to identify this with a property known as Unate.

UNATE
VLSI EXPERT (v
Unate are of three types:
google.com/+Vlsi-e

Bridging Gap Betw

Positive Unate: Acdamia and Indu

Rising Input – Rising Output OR No change in Output.

Follow
If we apply rising signal to the input of a Timing Arc, corresponding output signal is either Rising or there is "No
change". 307 followers

Falling Input – Falling Output OR No change in Output

If we apply Faling signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No
Total Pageviews
change".
E.g: 5,399,548
BUFFER
AND gate (will explain this in detail later below)
OR gate (will explain this in detail later below)
Negative Unate:
Rising Input – Falling Output OR No change in Output. Subscribe To VLSI EXP

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11/16/2017 UNATE : Timing Arc |VLSI Concepts
If we apply rising signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No Posts
Content VLSI change".
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Falling Input
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Rising Output OR No change
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If we apply Falling signal to the input of a Timing Arc, corresponding output signal is either Rising or there is
"No change".
E.g:
Inverter (NOT gate)
NAND gate (will explain this in detail later below)
NOR gate (will explain this in detail later below)
Non_Unate:
The non-unate represents a function where change in output value cannot be determined from the direction of the change Edusaksham
in the input value. Output pin value is not dependent on single Input Pin. It also depends on 2nd Input pin. Since Timing arc VLSI - Self...
will be between the Single Input and Single Output pin, so it’s difficult to identify this relationship directly. INR 5,750.00
E.g:
Shop now
XOR gate (will explain this in detail later below)
XNOR gate (will explain this in detail later below)

Buffer:

Edusaksham
VLSI - Static...
INR 2,300.00

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In the Buffer there is one input pin and one output pin. Behavior of Buffer we all know.
Rising Input results Rising Output.
Popular Posts
Falling Input results Falling Output.
"Timing Paths" : Sta
Timing Analysis (ST
So, Timing Arc between Input and Output pin of Buffer are Positive Unate. basic (Part 1)

Remember, there are 2 Timing arcs in Buffer: One for Rising Edge and other for Falling edge. Basic of Timing
Analysis in Physical
Design
Inverter:
"Setup and Hold Tim
: Static Timing Analy
(STA) basic (Part 3a

"Setup and Hold Tim

Violation" : Static
Timing Analysis (ST
basic (Part 3b)

Delay - "Wire Load

Model" : Static Timin
In the NOT Gate (Inverter) there is one input pin and one output pin. Behavior of Inverter also we know very well. Analysis (STA) basic
(Part 4c)
Rising Input results Falling Output.
Falling Input results Rising Output. "Examples Of Setup
and Hold time" : Sta
Timing Analysis (ST
So, Timing Arc between Input and Output pin of Inverter are Negative Unate. basic (Part 3c)

Delay - "Interconnec
Remember, there are 2 Timing arcs in Inverter: One for Rising Edge and other for Falling edge. Delay Models" : Sta
Timing Analysis (ST
basic (Part 4b)
AND Gate:
"Time Borrowing" :
Static Timing Analys
(STA) basic (Part 2)

5 Steps to Crack VL
Interview

10 Ways to fix SETU

and HOLD violation
Static Timing Analys
(STA) Basic (Part-8)

Above is the "Truth Table" of AND gate (for Input Pin A and B, Output Pin Y).
Recent Visitors

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 0)

A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 0)

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B = 1 , A (0-> 1) ; Y - Changes from 0-> 1 Live Traffic Feed
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In the same way we can also summarize the falling edge: "Blockage: Placem
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So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.
View, California ar
from google.com a
Capturing again:
viewed "VLSI Con
There are 4 Timing arcs in AND gate:
STA
A visitor
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1. Input Pin A to Output Pin Y for Rising Edge Republic of arrived
2. Input Pin A to Output Pin Y for Falling Edge
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"How To Read SDF
3. Input Pin B to Output Pin Y for Rising Edge
(Standard Delay Fo
4. Input Pin B to Output Pin Y for Falling Edge P 2view |VLSI C
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OR Gate:
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Above is the "Truth Table" of OR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1

A = 1 , B (0-> 1) ; Y - No change (constant at 1)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1

B = 1 , A (0-> 1) ; Y - No change (constant at 1)

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In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0

A = 1 , B (1-> 0) ; Y - No change (constant at 1)
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - No change (constant at 1)

So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in OR gate:

1. Input Pin A to Output Pin Y for Rising Edge

2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

NAND Gate:

Above is the "Truth Table" of NAND gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 1)

A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 1)

B = 1 , A (0-> 1) ; Y - Changes from 1-> 0

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In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - No change (constant at 1)

A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - No change (constant at 1)
B = 1 , A (1-> 0) ; Y - Change from 0-> 1

So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NAND gate:

1. Input Pin A to Output Pin Y for Rising Edge

2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

NOR Gate:

Above is the "Truth Table" of NOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0

A = 1 , B (0-> 1) ; Y - No change (constant at 0)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 1-> 0

B = 1 , A (0-> 1) ; Y - No change (constant at 0)

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In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1

A = 1 , B (1-> 0) ; Y - No change (constant at 0)
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - No change (constant at 0)

So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NOR gate:

1. Input Pin A to Output Pin Y for Rising Edge

2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

XOR Gate:

Above is the "Truth Table" of XOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1

A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1

B = 1 , A (0-> 1) ; Y - Changes from 1-> 0

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In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0

A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - Change from 0-> 1

This one is little bit different from other gates (which we have reviewed till now).
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change
from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with
respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XOR gate:

1. Input Pin A to Output Pin Y for Rising Edge

2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

XNOR Gate:

Above is the "Truth Table" of XNOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0

A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

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11/16/2017 UNATE : Timing Arc |VLSI Concepts
B = 0 , A (0-> 1) ; Y - Changes from 1-> 0
Content VLSI
B = 1 , A (0-> 1) ; BASIC
Y - ChangesSTA
from&0->
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In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1

A = 1 , B (1-> 0) ; Y - Change from 1-> 0
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - Change from 1-> 0

Explanation is same as in case of XOR gate. (copy paste the same paragraph here :) )
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change
from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with
respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XNOR gate:

1. Input Pin A to Output Pin Y for Rising Edge

2. Input Pin A to Output Pin Y for Falling Edge
3. Input Pin B to Output Pin Y for Rising Edge
4. Input Pin B to Output Pin Y for Falling Edge

I am sure, by now, you have developed or revise the concept of Unate in Timing Arc. With the help of Truth table, you can easily figure out the
Unateness of any Timing arc. Even If you are going to design any circuit or system (which is not in the list of Standard gates), then you can
yourself figure out the Unateness property of different Timing arcs in that system.

We will discuss about that in more detail in next few article. Like how these (Timing Arc , Unateness ) represent in Timing Library, how different
values are captured in Timing Library and a lot about the Timing Arcs. :)

Interview Questions

I have tried to capture few Interview questions here which can help you big time during your preparation.

1. What are the different types of Timing Arc ?

2. What is Unateness of a Timing Arc ?
3. What do you mean by Positive_unate of a Timing Arc?
4. What do you mean by Negative_unate of a Timing Arc?
5. What is the difference between Non-unate Timing arc and Positive Timing Arc ?

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11/16/2017 UNATE : Timing Arc |VLSI Concepts
6. How many Timing Arcs are present in case of Buffer?
Content VLSI BASIC STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Job Posting
7. How many Timing Arcs are present in a 2 input NAND gate?
Video 8. How to represent
Lectures VLSITiming Arcs Insight
Industry: in the TimingRecommended
Library ? Book About Us Assessment
9. A timing arc is positive Unate, if we apply rising edge at the input of the Timing arc, corresponding output will change or not ?
10. How many Timing arc is present for a 3 input XOR gate?
11. What's the Unateness of different Timing Arc for a 3 input XNOR gate ?

The newly launched product "VLSI Self Mentorship Program" by Edusaksham, can help you in preparing for Interview and
written test. This Course is designed by Industry people. To know more click here.

Posted by VLSI EXPERT at 10:05 PM

Reactions: Excellent (6) Good (0) Interesting (0) Need More (0)

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Content VLSI BASIC STA & SI Extraction & DFM Low Power Physical Design Vlsi Interview Questions Job Posting

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