5 4 3 2 1

RIYA Discrete Schematics Document

D D

AMD Giffin CPU S1G2

VGA ATI M92S2-LP
TABLE OF CONTENTS

01_Cover Page
02_Block Diagram
41_VREG : +VCC_GFX_CORE
42_LCD&Inverter CONN
RS780M + SB700
03_Power Block Diagram 43_(LAN&CRT CONN)
04_SMBUS BLOCK DIAGRAM 44_MiniCard&Card Reader CONN
05_THERMAL/AUDIO BLOCK DIAGRAM 45_HDD&ODD&FAN CONN
C C
06_Table of Content 46_KeyBoard&TouchPad&BT CONN
07_Clock Generator ICS9LPRS480 47_USB CONN
08_CPU_HT_LINK I/F_(1/4)
09_CPU_DDR_(2/4)
10_CPU_Control&Debug_(3/4)
48_EEPROM&LED&Camera&RTC CONN
49_Audio Jack
50_IO BOARD CONN
2009-08-25
11_CPU_Power_(4/4)
12_DDR_DIMM1
13_DDR_DIMM2
51_Express Card Board CONN
52_Power Button&Hall Sensor&MDC
53_Miscellaneous Components
REV : A00
14_ATi-RS780M_HT LINK&PCIe(1/4) 54_VGA-PCIE/LVDS(1/4)
15_ATi-RS780M_LVDS&CRT_(2/4) 55_VGA-TV/CRT/DP PORT(2/4)
16_ATi-RS780M_SidePort_(3/4) 56_VGA-POWER/GND(3/4)
17_ATi-RS780M_PWR&GD_(4/4) 57_VGA-MEMORY/STRAPS(4/4)
18_ATi-SB700_PCIE&PCI_(1/5) 58_VRAM DY : Nopop Component
19_ATi-SB700_USB&GPIO_(2/5) 59_VRAM
B 20_ATi-SB700_SATA-IDE_(3/5) 60_CLOCK BLOCK DIAGRAM B

61_RESET BLOCK DIAGRAM

21_ATi-SB700_POWER&GND_(4/5)
62_POWER SEQUENCE
22_ATi-SB700_STRAPPING_(5/5)
63_Change List-EE
23_AUDIO CODEC IDT-92HD81
64_Change List-Power
24_(AUDIO AMP)
25_Card Reader Realtek RTS5159
26_LAN Realtek RTL8103EL
27_KBC WPCE773L
28_(Super I/O)
29_THERMAL EMC2102
30_Power On Logic

31_Power Plane Enable

32_DC IN/BATT CONN
33_Charger MAX8731A
A A
34_VREG : +3.3V_ALW&+5V_ALW Main Source

35_VREG : +VCC_CORE&+VDDNB
36_(Reserve for Power) Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
37_VREG : +1.1V_RUN
Title
38_VREG : +1.2V_RUN
Cover Page
39_VREG : +1.8V_SUS&+0.9V_VTT Size Document Number Rev
Custom
40_VREG : +1.5V_RUN&+2.5V_RUN Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 1 of 65
5 4 3 2 1
 5 4 3 2 1

DATE VERSON ITEM PAGE Modify List Issue Description OWNER

2009/08/22 A00
28 48 Change U4801 from 72.25X16.A01 to 72.25Q16.001 0909

29 48 Del PWR_LED_B AFTE Pad,ADD AFTP5 test point to GND,move EC4802,EC4803

D D

C C

0903

0903

0903
B B

0903

0903
0903
0908

0908

0908
0908

A Main Source A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Title
Change List - Power
<Title>
Size Document Number Rev
Size
Custom Document Number Rev
Custom<Doc> Riya Discrete A00
<RevCode
Date: Wednesday, September 09, 2009 Sheet 65 of 65
Date: Wednesday, September 09, 2009 Sheet 1 of 1
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 5 4 3 2 1

CHARGER
28
MAX8731AETI-GP 33
RIYA Discrete Block Diagram INPUTS OUTPUTS
Project code : 91.4CX01.001 +DC_IN_SS
+CHAGER_SRC
+PWR_SRC

PCB P/N : 08267 DDRII DIMM1

AMD Giffin CPU DDR II 667 SYSTEM DC/DC
667/800 12
TPS51125RGER-GP
D
Revision : -1 S1G2 (35W) INPUTS OUTPUTS
34
D

DDR II 667 DDRII DIMM2

8,9,10,11
667/800 13
+5V_AUX
+PWR_SRC +3.3V_RTC_LDO
+5V_ALW
HyperTransport

OUT
Clock Generator +3.3V_ALW

IN
VRAM 16X16 AMD SB700 S5 POWER
ICS9LPRS480BKLFT
7 64Mx16bx4 (512M)4 RT9013-12PB-GP 34
58
INPUTS OUTPUTS
+3.3V_ALW +1.2V_ALW
GDDR2 North Bridge
400MHz CPU CORE
AMD RS780M ISL6265AHRTZ-T-GP 35
Power SW
CRT CPU I/F LVDS, CRT I/F INPUTS OUTPUTS
RGB CRT G577DSR91U 51
(on I/Oboard) 48 INTEGRATED GRAHPICS +VCC_CORE0
PCIE
ATI M92S2-LP PCIe x 16 +PWR_SRC +VCC_CORE1
LVDS(Dual Channel) 14,15,16,17 +VDDNB
C LCD C
42 54,55,56,57
PCIE x 1 & USB 2.0 x 1 Express Card51 AMD RS780M CORE
RT8209BGQW-GP 37
INPUTS OUTPUTS
A-LINK PCIE x 1 10/100 NIC RJ45
+1.1V_RUN

I/O Board
Connector
+PWR_SRC
4X4 Realtek RTL8103EL 26 CONN
AMD SB700 CORE
RT8209BGQW-GP 38

USB 2.0 x 2
Left Side: INPUTS OUTPUTS
CardReader South Bridge 50 USB x 2
+PWR_SRC +1.2V_RUN
AMD SB700 DDR II SUS&VTT
SD/SDIO/MMC
Realtek USB2.0
PCIE x 1& USB 2.0 x 1 Mini-Card RT8209BGQW-GP 39
MS/MS Pro/xD
44
USB 2.0/1.1 ports 44
RTS5159 802.11a/b/g INPUTS OUTPUTS
ETHERNET (10/100/1000Mb)
25 +PWR_SRC +1.8V_SUS
High Definition Audio
ATA 66/100 USB 2.0 USB 2.0 x 1 CAMERA DDR II SUS&VTT
48
(Option) TPS51100DGQR-GP 39
B B
INPUTS OUTPUTS
ACPI 1.1
Digital Mic Array AZALIA +1.8V_SUS +0.9V_VTT
Azalia LPC I/F USB 2.0 x 1 Bluetooth 46
DDR II SUS&VTT
Internal Analog MIC
CODEC PCI/PCI BRIDGE TPS51100DGQR-GP 41
LPC Bus
INPUTS OUTPUTS
MIC IN & 18,19,20,21,22
USB 2.0 x 1 Right Side:
USB x 1 47 +PWR_SRC +VCC_GFX_CORE
OP AMP PCB LAYER
HP OUT
IDT 92HD8123 L1: Top
KBC L2: GND
SATA

SATA

SPI WINBOND L3: Signal

27
2CH SPEAKER WPCE773L L4: Signal
L5: VCC
L6: Signal
L7: GND
A Main Source L8: Bottom A
Flash ROM Touch Int. Thermal
HDD ODD
45 45 2MB PAD KB EMC2102 Wistron Corporation
48 46 46 25 29 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Fan Size Document Number Rev
45
A3 Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 2 of 65
5 4 3 2 1
 A B C D E

Power Shape
Regulator LDO Switch
Power Block Diagram
4 4

+PWR_SRC
Adapter

ISL6265AHRTZ RT8209BGQW RT8209BGQW TPS51117RGYR RT8209BGQW

AO4407A
Charger
MAX8731A +VCC_CORE0 +VCC_CORE1 +VDDNB +1.1V_RUN +1.2V_RUN +VCC_GFX_CORE +1.8V_SUS

Battery +PBATT

TPS51100 APL5930 FDS8880 FDS8880

TPS51125RGER
3 3

+0.9V_VTT +1.5V_RUN +1.8V_RUN +1.8V_GFX_RUN

+3.3V_RTC_LDO +5V_ALW +5V_AUX +3.3V_ALW

G577BR91U

G546B2P1UF AO4468 RT9711BPF RT9013-12PB AO4468 G577BR91U AO3403

+1.5V_CARD

+5V_USB1 +5V_RUN +5V_USB2 +1.2V_ALW +3.3V_RUN +3.3V_CARDAUX +3.3V_LAN

2 2
RESISTER RESISTER GAP GAP G5281RC1U G577BR91U RTS5159 RT9013-25PB RTL8103EL

+PVDD +AVDD +5V_HDD +5V_MOD +LCDVDD +3.3V_CARD +3.3V_RUN_CARD +2.5V_RUN +1.2V_LAN_DVDD

1 1
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Power Block Diagram
Size Document Number Rev
Custom
Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 3 of 65
A B C D E
 5 4 3 2 1

KBC SMBus Block Diagram

+5V_RUN

D D

SB700 SMBus Block Diagram SRN10KJ-5-GP

PSDAT1 TPDATA TPDATA

TouchPad Conn.
TPDATA

PSCLK1 TPCLK TPCLK TPCLK

+3.3V_RTC_LDO

+3.3V_RUN SRN4K7J-8-GP

SCL1 BAT_SCL
SRN100J-3-GP
PBAT_SMBCLK1
Battery Conn. SMBus address:16
CLK_SMB
SDA1 BAT_SDA PBAT_SMBDAT1 DAT_SMB
SRN4K7J-8-GP

SB700 SCL0 SMB_CLK_0

SMB_CLK_0
DIMM 1
C
SDA0 SMB_DATA_0
SMB_DATA_0
SCL
MAX8731A C

SCL1 SMB_CLK
+3.3V_ALW
SDA

SMBus Address:A0
KBC SCL

SDA
SMBus address:12
SDA1 SMB_DATA

SCL3_LV/IMC_GPIO13 CPU_SIC
WPC773L
SDA3_LV/IMC_GPIO14 CPU_SID
SMB_CLK_0
DIMM 2 +3.3V_RUN

SCL
SRN4K7J-8-GP SMB_DATA_0 SDA
+3.3V_RTC_LDO
+3.3V_RUN
SMBus Address:A4
SRN4K7J-8-GP

EXP CARD CLOCK GEN Thermal

THERM_SCL SCL SMBus address:7A
SRN4K7J-8-GP
THERM_SDA SDA
SMB_CLK SMB_CLK_0
SMB_CLK SCLK
SMB_DATA SMB_DATA SMB_DATA_0 SDATA GPIO61/SCL2 KBC_SCL1
2N7002SPT
GPIO62/SDA2 KBC_SDA1
SMBus address:D2

MINI CARD
SMB_CLK_0 SMB_CLK
B SMB_DATA_0 SMB_DATA
B

+3.3V_DELAY
+1.8V_SUS

2K2R2J CPU S1G2 2K2R2J-2-GP

CPU_SIC SIC DDC1CLK LCD_DDCLK

CPU_SID SID DDC1DATA LCD_DDCDAT LCD Conn.
SMBus address:98

+5V_CRT_RUN

ATI +3.3V_DELAY
+3.3V_DELAY

I/O Board CONN.

SRN4K7J-8-GP

M92LP-S2
DDC_CLK_CON

A
SRN4K7J-8-GP
DDC_DATA_CON CRT CONN A

DDC2CLK M92CRT_DDCCLK
2N7002SPT
DDC2DATA M92CRT_DDCDATA
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
SMBUS BLOCK DIAGRAM
Size Document Number Rev
A2
Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 4 of 65
5 4 3 2 1
 5 4 3 2 1

D
Thermal Block Diagram Audio Block Diagram D

0R3-0-U-GP
SPKR_PORT_D_L+

SPKR_PORT_D_L-
AUD_SPK_L+

AUD_SPK_L-
AUD_SPK_R_L+

AUD_SPK_R_L-
SPEAKER
SPKR_PORT_D_R- AUD_SPK_R- AUD_SPK_R_R-
SPKR_PORT_D_R+ AUD_SPK_R+ AUD_SPK_R_R+

0R3-0-U-V-GP 44

CPU
HP1_PORT_B_L
HP1_PORT_B_R
AUD_HP1_JACK_L
AUD_HP1_JACK_R
HP
DP1 H_THERMDA THERMDA

SC470P50V3JN-2GP
OUT
C
DN1 H_THERMDC THERMDC
Codec 50
C

Thermal 92HD81
EMC2102 VREFOUT_A_OR_F AUD_VREFOUT_B

4K7R2J-2-GP

4K7R2J-2-GP
DP2 VGA_THERMDA
GPU
DPLUS
MIC
SC470P50V3JN-2GP HP0_PORT_A_L AUD_EXT_MIC_L IN
DN2 VGA_THERMDC DMINUS HP0_PORT_A_R AUD_EXT_MIC_R
50

B
DMIC_CLK/GPIO1 AUD_DMIC_CLK 33R2J-2-GP AUD_DMIC_CLK_G_R Digital B

DMIC0/GPIO2
AUD_DMIC_IN0
33R2J-2-GP
AUD_DMIC_IN0_R MIC
Array 47
DP3 EMC2102_DP3
MMBT3904-3-GP
SC470P50V3JN-2GP
SC1U10V3KX-3GP
DN3 EMC2102_DN3

AUD_INT_MIC_R_L INT_MIC_L_R
System sensor, put PORT_C_L Internal
between CPU and NB.
PORT_C_R AUD_INT_MIC_R_L MIC
VREFOUT_C
AUD_VREFOUT_C

23 4K7R2J-2-GP 44

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
THERMAL/AUDIO BLOCK DIAGRAM
Size Document Number Rev
Custom
Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 5 of 65
5 4 3 2 1
 5 4 3 2 1

SB700 MULTIFUNCTION and GPIO Definitions WPCE773L MULTIFUNCTION and GPIO Definitions
SB700 45215_sb710_ds_nda Rev.1.05 SB700 45215_sb710_ds_nda Rev.1.05 WPCE773L Preliminary Datasheet - Revision 0.8
MULTIFUNCTION PINS FUNCTION I/O POWER DOMAIN MULTIFUNCTION PINS FUNCTION I/O POWER DOMAIN MULTIFUNCTION PINS FUNCTION I/O POWER DOMAIN
REQ3#/GPIO70 - I/O 3.3V-5V_S0/15K PU IMC_GPIO22 - I/O 3.3V_S5 GPIO01/TB2 PM_SLP_S3# I/O 3.3V-5V_AUX
REQ4#/GPIO71 TP I/O 3.3V-5V_S0/15K PU IMC_GPIO23 - I/O 3.3V_S5 GPIO03 KBC_PWRBTN# I/O 3.3V_AUX
GNT3#/GPIO72 - I/O 3.3V-5V_S0 IMC_GPIO24 - I/O 3.3V_S5 GPIO04 SYS_THERMTRIP# I/O 3.3V_AUX
GNT4#/GPIO73 TP I/O 3.3V-5V_S0 IMC_GPIO25 - I/O 3.3V_S5 GPIO05 LCD_EC_DET I/O 3.3V_AUX
GPIO06 AC_IN# I/O 3.3V-5V_AUX
INTE#/GPIO33 - I/O 3.3V-5V_S0/8.2K PU IMC_GPIO26 - I/O
D GPIO07 LID_CLOSE# I/O 3.3V_AUX D
INTF#/GPIO34 - I/O 3.3V-5V_S0/8.2K PU IMC_GPIO27 - I/O 3.3V_S5
GPIO10/LPCPD# ADAPT_TRIP_SEL I/O 3.3V-5V_AUX
INTG#/GPIO35 - I/O 3.3V-5V_S0/8.2K PU IMC_GPIO28 - I/O 3.3V_S5
GPIO11/CLKRUN# PM_CLKRUN# I/O 3.3V-5V_AUX
INTH#/GPIO36 - I/O 3.3V-5V_S0/8.2K PU IMC_GPIO29 - I/O 3.3V_S5
GPIO12/PSDAT3 KB_DET# I/O 3.3V-5V_AUX
LDRQ1#/GNT5#/GPIO68 TP I/O 3.3V-5V_S0/15K PU IMC_GPIO30 - I/O 3.3V_S5
GPIO13/C_PWM BRIGHTNESS I/O 3.3V-5V_AUX
BMREQ#/REQ5#/GPIO65 SB700_GPIO65 I/O 3.3V-5V_S0 IMC_GPIO31 - I/O 3.3V_S5
GPIO14/TB1 PSID_EC I/O 3.3V-5V_AUX
PCI_PME#/GEVENT4# TP I/O 3.3V_S5/10K PU IMC_GPIO32 - I/O 3.3V_S5
GPIO15/A_PWM KBC_BEEP I/O 3.3V-5V_AUX
RI#/EXTEVNT0# KBC_ECSWI# I/O 3.3V_S5/10K PU IMC_GPIO33 - I/O 3.3V_S5
GPIO16 PM_LAN_ENABLE I/O 3.3V-5V_AUX
SLP_S2/GPM9# TP I/O 3.3V_S5/10K PD IMC_GPIO34 - I/O 3.3V_S5
GPIO17/SCL1 BAT_SCL I/O 3.3V-5V_AUX
GA20IN/GEVENT0# A20GATE I/O 3.3V-5V_S0/8.2K PU IMC_GPIO35 - I/O 3.3V_S5
GPIO20/TA2 PM_PWRBTN# I/O 3.3V-5V_AUX
KBRST#/GEVENT1# KBRCIN# I/O 3.3V-5V_S0/8.2K PU IMC_GPIO36 - I/O 3.3V_S5
GPIO21/B_PWM BATLOW_LED I/O 3.3V-5V_AUX
LPC_PME#/GEVENT3# KBC_ECSCI# I/O 3.3V_S5/10K PU IMC_GPIO37 - I/O 3.3V_S5
GPIO22/SDA1 BAT_SDA I/O 3.3V-5V_AUX
LPC_SMI#/EXTEVNT1# TP I/O 3.3V-5V_S0/8.2K PU IMC_GPIO38 - I/O 3.3V_S5
GPIO23 1.8V_GFX_RUN_PWRGD# I/O 3.3V-5V_AUX
S3_STATE/GEVENT5# - I/O 3.3V_S5/10K PU IMC_GPIO39 - I/O 3.3V_S5
GPIO25/PSCLK3 LCD_CBL_DET# I/O 3.3V-5V_AUX
SYS_RESET#/GPM7# TP I/O 3.3V_S5/10K PU IMC_GPIO40 - I/O 3.3V_S5
GPIO26/PSCLK2 LCD_TST I/O 3.3V-5V_AUX
WAKE#/GEVENT8# PCIE_WAKE# I/O 3.3V_S5/10K PU IMC_GPIO41 - I/O 3.3V_S5
GPIO30 EC_SPI_WP#_R I/O 3.3V-5V_AUX
BLINK/GPM6# KBC_ECSMI# I/O 3.3V_S5/10K PU SATA_ACT#/GPIO67 TP I/O
GPIO31 RUNPWROK I/O 3.3V-5V_AUX
SMBALERT#/THRMTRIP#/GEVENT2# SB_THERMTRIP# I/O 3.3V_S5/10K PU IDE_D0/GPIO15 - I/O
GPIO32/D_PWM PWRLED I/O 3.3V-5V_AUX
SATA_IS0#/GPIO10 TP I/O 3.3V-5V_S0 IDE_D1/GPIO16 - I/O
GPIO33/H_PWM HP_MUTE I/O 3.3V-5V_AUX
CLK_REQ3#/SATA_IS1#/GPIO6 TP I/O 3.3V-5V_S0 IDE_D2/GPIO17 - I/O
GPIO35/PSDAT1 TPDATA I/O 3.3V-5V_AUX
SMARTVOLT/SATA_IS2#/GPIO4 TP I/O 3.3V-5V_S0 IDE_D3/GPIO18 - I/O
GPIO36 S5_ENABLE I/O 3.3V-5V_AUX
C
CLK_REQ0#/SATA_IS3#/GPIO0 TP I/O 3.3V-5V_S0/10K PD IDE_D4/GPIO19 - I/O C
GPIO37/PSCLK1 TPCLK I/O 3.3V-5V_AUX
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 TP I/O 3.3V-5V_S0/10K PD IDE_D5/GPIO20 - I/O
GPIO40/F_PWM 3.3V_DELAY_EN I/O 3.3V-5V_AUX
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 TP I/O 3.3V-5V_S0/10K PD IDE_D6/GPIO21 - I/O
GPIO41 BAT_IN# I/O 3.3V-5V_AUX
SPKR/GPIO2 SB_SPKR I/O 3.3V-5V_S0 IDE_D7/GPIO22 - I/O
GPIO42/TCK AD_OFF I/O 3.3V-5V_AUX
SCL0/GPOC0# TP I/O 3.3V-5V_S0 IDE_D8/GPIO23 - I/O
GPIO43/TMS KBC_RSMRST# I/O 3.3V-5V_AUX
SDA0/GPOC1# TP I/O 3.3V-5V_S0 IDE_D9/GPIO24 - I/O
GPIO44/TDI PM_SLP_S5# I/O 3.3V-5V_AUX
SCL1/GPOC2# SMB_CLK I/O 3.3V_S5 IDE_D10/GPIO25 - I/O
GPIO45/E_PWM KBC_PLTRST_DELAY# I/O 3.3V-5V_AUX
SDA1/GPOC3# SMB_DATA I/O 3.3V_S5 IDE_D11/GPIO26 - I/O
GPIO46/TRST# 3V_5V_POK I/O 3.3V-5V_AUX
DDC1_SCL/GPIO9 TP I/O 3.3V-5V_S0 IDE_D12/GPIO27 - I/O
GPIO50/TDO PSID_DISABLE# I/O 3.3V-5V_AUX
DDC1_SDA/GPIO8 TP I/O 3.3V-5V_S0 IDE_D13/GPIO28 - I/O
GPIO52/RDY# BLON_OUT I/O 3.3V-5V_AUX
LLB#/GPIO66 TP I/O 3.3V_S5/10K PU IDE_D14/GPIO29 - I/O
ECSCI#/GPIO54 KBC_D_ECSCI# I/O 3.3V-5V_AUX
SHUTDOWN#/GPIO5 TP I/O 3.3V-5V_S0 IDE_D15/GPIO30 - I/O
GPIO55/CLKOUT AMP_MUTE# I/O 3.3V_AUX
DDR3_RST#/GEVENT7# - I/O 3.3V_S5/10K PU SPI_DI/GPIO12 TP I/O 3.3V_S5/10K PD
GPIO56/TA1 LCD_TST_EN I/O 3.3V-5V_AUX
USB_OC6#/IR_TX1/GEVENT6# TP I/O 3.3V_S5/10K PU SPI_DO/GPIO11 TP I/O 3.3V_S5/10K PD
GPIO65/SMI# PANEL_BKEN I/O 3.3V-5V_AUX
USB_OC5#/IR_TX0/GPM5# TP I/O/OD 3.3V_S5 SPI_CLK/GPIO47 TP I/O 3.3V_S5/10K PD
GPIO66/G_PWM 1.8V_GFX_RUN_EN I/O 3.3V-5V_AUX
USB_OC4#/IR_RX0/GPM4# CPPE# I/O 3.3V_S5/10K PU SPI_HOLD#/GPIO31 TP I/O 3.3V_S5/10K PU
GPIO67/PWUREQ# KBC_D_ECSWI# I/O 3.3V-5V_AUX
USB_OC3#/IR_RX1/GPM3# TP I/O 3.3V_S5/10K PU SPI_CS#/GPIO32 TP I/O 3.3V_S5/10K PU
GPIO70 KBC_D_ECSMI# I/O 3.3V-5V_AUX
USB_OC2#/GPM2# TP I/O 3.3V_S5/10K PU LAN_RST#/GPIO13 TP I/O 3.3V-5V_S0
GPIO71 GFX_CORE_EN I/O 3.3V-5V_AUX
USB_OC1#/GPM1# USB_OC_2_# I/O 3.3V_S5/10K PU ROM_RST#/GPIO14 TP I/O 3.3V-5V_S0
GPIO73/SCL2 KBC_SCL1 I/O 3.3V-5V_AUX
USB_OC0#/GPM0# USB_OC_01_# I/O 3.3V_S5/10K PU FANOUT0/GPIO3 TP I/O 3.3V-5V_S0/8.2K PU
GPIO74/SDA2 KBC_SDA1 I/O 3.3V-5V_AUX
B
SCL0/GPOC0# TP I/O 3.3V-5V_S0 FANOUT1/GPIO48 SB_GPIO48 I/O 3.3V-5V_S0/8.2K PU B
GPIO75 WIFI_RF_EN I/O 3.3V-5V_AUX
SDA0/GPOC1# TP I/O 3.3V-5V_S0 FANOUT2/GPIO49 TP I/O 3.3V-5V_S0/8.2K PU
GPIO76/SHBM KBC_SHBM O 3.3V-5V_AUX
SCL1/GPOC2# SMB_CLK I/O 3.3V_S5 FANIN0/GPIO50 - I/O 3.3V-5V_S0
GPIO77 BLUETOOTH_EN I/O 3.3V-5V_AUX
SDA1/GPOC3# SMB_DATA I/O 3.3V_S5 FANIN1/GPIO51 TP I/O 3.3V-5V_S0
GPIO81 1.1V_GFX_RUN_EN I/O 3.3V-5V_AUX
AZ_SDIN0/GPIO42 SB_AZ_CODEC_SDIN0 I/O 3.3V_S5/50K PD FANIN2/GPIO52 TP I/O 3.3V-5V_S0
GPO82/TRIS# USB_PWR_EN# O 3.3V-5V_AUX
AZ_SDIN1/GPIO43 - I/O 3.3V_S5/50K PD TEMPIN0/GPIO61 TP I/O 3.3V_S5
GPO83/SOUT_CR/BADDR1 E51_TxD O 3.3V-5V_AUX
AZ_SDIN2/GPIO44 - I/O 3.3V_S5/50K PD TEMPIN1/GPIO62 - I/O 3.3V_S5
GPIO87/SIN_CR E51_RxD I/O 3.3V-5V_AUX
AZ_SDIN3/GPIO46 - I/O 3.3V_S5/50K PD TEMPIN2/GPIO63 - I/O 3.3V_S5
GPI90/AD0 AD_IA I 3.3V_AUX
AZ_DOCK_RST#/GPM8# - 10K PU TEMPIN3/TALERT#/GPIO64 TALERT# I/O 3.3V_S5
GPI92/AD2 THERMTRIP_VGA# I 3.3V_AUX
SPI_CS2#/IMC_GPIO2 TP I/O 3.3V_S5/10K PU VIN0/GPIO53 - I/O 3.3V_S5
GPI93/AD3 ADAPT_OC I 3.3V_AUX
IDE_RST#/F_RST#/IMC_GPO3 IDE_RST# OD 3.3V-5V_S5 VIN1/GPIO54 - I/O 3.3V_S5
GPI94 PCB_VER0 I 3.3V_AUX
IMC_GPIO4 TP I/O 3.3V-5V_S5 VIN2/GPIO55 - I/O 3.3V_S5
GPI95 PCB_VER1 I 3.3V_AUX
IMC_GPIO5 TP I/O 3.3V-5V_S5 VIN3/GPIO56 - I/O 3.3V_S5
GPI96 PCB_VER2 I 3.3V_AUX
IMC_GPIO6 TP I/O 3.3V-5V_S5 VIN4/GPIO57 - I/O 3.3V_S5
GPI97 CAMERA_DET# I 3.3V_AUX
IMC_GPIO7 TP I/O 3.3V-5V_S5 VIN5/GPIO58 - I/O 3.3V_S5
IMC_GPIO8 - I/O 3.3V_S5 VIN6/GPIO59 - I/O 3.3V_S5 USB Table
-
PCIE Routing
IMC_GPIO9 - I/O 3.3V_S5 VIN7/GPIO60 - I/O 3.3V_S5 Pair Controllers Device Pair Device
IMC_PWM0/IMC_GPIO10 - I/O 3.3V_S5 0 I/O BOARD Left Side PE_GPP1 LAN

EHCI Dev.18 EHCI Dev.19

OHCI 0
SCL2/IMC_GPIO11 - OD 3.3V-5V_S5 1 I/O BOARD Left Side PE_GPP2 MINI Card
SDA2/IMC_GPIO12 - OD 3.3V-5V_S5 2 Camera PE_GPP3 EXP Card
SCL3_LV/IMC_GPIO13 CPU_SIC OD 3.3V_S5 3 RESERVED
CIRCUIT NOTE
OHCI 1
A A
SDA3_LV/IMC_GPIO14 CPU_SID OD 3.3V_S5 4 Express Card
IMC_PWM1/IMC_GPIO15 - I/O 3.3V_S5 5 RESERVED
IMC_PWM2/IMC_GPO16 SB_GPO16 I/O 3.3V-5V_S5 6 BLUETOOTH
IMC_PWM3/IMC_GPO17 SB_GPO17 I/O 3.3V-5V_S5 7
OHCI 0
RESERVED For Circuit Main Source

IMC_GPIO18 - I/O 3.3V_S5 8 RESERVED Wistron Corporation

IMC_GPIO19 - I/O 3.3V_S5 9 Card Reader For Layout 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
OHCI 1

IMC_GPIO20 - I/O 3.3V_S5 10 MINI CARD Title

IMC_GPIO21 - I/O 3.3V_S5 11 USB Port Right Side Table of Content
12 RESERVED For EMI Size Document Number Rev
OHCI Dev.20 A2
13 RESERVED Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 6 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = CLOCK

1'nd 68.00084.A31(MURATA)
2'nd
+3.3V_RUN +3.3V_CLK_VDD
D R701 +3.3V_CLK_VDD (40 mils) A00 D

1 2
Do Not Stuff 8/24

SC22U6D3V5MX-2GP

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
Change R701,R702,R704 from 0 ohm to short pad

1
C701

C702

C703

C704

C705

C706

C707

C708

C709
2

2
+3.3V_RUN +3.3V_CLK_VDDIO
R702
1 2
Do Not Stuff
XTAL
SC22U6D3V5MX-2GP

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
1'nd 82.30005.901
1

1
C711

C712

C713

C714

C715

C716

C717

C710
2'nd 82.30005.A51 CLKREQ# MAP
2

2
C718
1 2
CLKREQ0# No use

X-14D31818M-37GP
CLKREQ1# CLKSRC1 MINI1

Do Not Stuff
SC12P50V2JN-3GP

1
+3.3V_CLK_VDD CLKREQ2# CLKSRC2 EXPCARD

R703

X701
C X01 U701
C
+3.3V_RUN +3.3V_CLK_VDDREF 04/15 Add +3.3V_CLK_VDDIO DY CLKREQ3# No use

2
R704 1.Add EC703 For EMI CLKGEN_X1 C720
26 61 CLKREQ4# No use

2
+3.3V_CLK_VDDREF VDD_ATIG XTAL_IN CLKGEN_X2
1 2 25 VDD_ATIG_IO XTAL_OUT 62 1 2
Do Not Stuff
SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

48 SC12P50V2JN-3GP
VDD_CPU
47 VDD_CPU_IO SCL 2 SMB_CLK_0 12,13,19,44 X01
1

+3.3V_RUN
C719

C721

SDA 3 SMB_DATA_0 12,13,19,44

16 04/08 modify
VDD_SRC
10KR2J-3-GP

1.Change Clk gen,Mini Card SMBus from Ch1 to Ch0

17
2

VDD_SRC_IO
1

11 VDD_SRC_IO ATIGCLK_0 30 VGA_PCIE_CLK 54

R705

35
ATIGCLK_0# 29
28
VGA_PCIE_CLK# 54 VGA(100MHz)
VDD_SB_SRC ATIGCLK_1 NB_GFX_CLK 15
34 VDD_SB_SRC_IO ATIGCLK_1# 27 NB_GFX_CLK# 15
EC703 +3.3V_RUN
2

R706 SC10P50V2JN-4GP 40 VDD_SATA TP_CLKREQ0# R707

19,30 SB_PWRGD 1
DY 2 4 VDD_DOT CLKREQ_0# 23
1

55 45 MINI1_CLK_REQ# MINI1_CLK_REQ# 1 2
VDD_HTT CLKREQ_1# MINI1_CLK_REQ# 44
Do Not Stuff 56 44 EXPCARD_CLK_REQ#
VDD_REF CLKREQ_2# EXPCARD_CLK_REQ# 51
63 39 TP_CLKREQ3# 10KR2J-3-GP
2

VDD_48 CLKREQ_3# TP_CLKREQ4# R708

CLKREQ_4# 38
EXPCARD_CLK_REQ# 1 2
NBGPP(100MHz) 15 NB_GPP_CLK 2 3 RN701 CLKGEN_PD# 51 PD#
4 Do Not Stuff CPU_CLK(200MHz) 10KR2J-3-GP
15 NB_GPP_CLK# 1
DY CPU_K8_0 50
49
CPU_CLK 10
CPU_K8_0# CPU_CLK# 10
R_NB_GPP_CLK
WLAN(100MHz) 44 MINI1_PCIE_CLK R_NB_GPP_CLK#
22 SRC_0 48M_CLK R709 1 22R2J-2-GP
44 MINI1_PCIE_CLK# 21
20
SRC_0# 48MHZ_0 64
R710 1
2
2 22R2J-2-GP
CARD_48M_CLK 25 CardReader(48MHz)
SRC_1 USB_48M_CLK 19

Do Not Stuff

Do Not Stuff
B
EXP(100MHz) 51 EXP_PCIE_CLK 19
15
SRC_1#
59 FS0
SB700_USB(48MHz) B
51 EXP_PCIE_CLK# SRC_2 REF_0/SEL_HTT66

1
EC702

EC701
14 58 FS1 +3.3V_RUN
SRC_2# REF_1/SEL_SATA FS2
LAN(100MHz) 26 LAN_PCIE_CLK 13 SRC_3 REF_2/SEL_27 57
DY DY
12 For EMI

2
26 LAN_PCIE_CLK# TP_CLK_SRC4 SRC_3#
9 SRC_4

1
8K2R2J-3-GP

8K2R2J-3-GP
TP_CLK_SRC4# 8 SRC_4#

R711

R712
TP_CLK_SRC6 42 43
TP_CLK_SRC6# SRC_6/SATA VSS_SATA
41 SRC_6#/SATA# VSS_ATIG 24
R713 1 2 33R2J-2-GP R_VGA_27M_SS_CLK 6 7
55 VGA_27M_SS_CLK R714 1 SRC_7/27M_SS VSS_DOT
VGA(27MHz) 2 33R2J-2-GP R_VGA_27M_NSS_CLK 5 52 NB OSCIN(14MHz)

2
55 VGA_27M_NSS_CLK SRC_7#/27M VSS_HTT R715 1 Do Not Stuff
VSS_REF 60
DY 2 R716 1 Do Not Stuff
NB_14M_CLK 15
37
VSS_CPU 46
1
DY 2 SB_14M_CLK 18 SB OSCIN(14MHz)
15 NB_GPPSB_CLK SB_SRC_0 VSS_48M
15 NB_GPPSB_CLK# 36 SB_SRC_0#
32 SB_SRC_1 VSS_SRC 10 OSC_14M_NB

1
8K2R2J-3-GP

Do Not Stuff

Do Not Stuff
18 SB_PCIE_CLK 31 SB_SRC_1# VSS_SRC 18

R719

R717

R718
18 SB_PCIE_CLK# RS780M 1.1V 158R/90.9R
54
VSS_SB_SRC 33
DY DY
15 CLK_NBHT_CLK HTT_0/66M_0
53 65

2
15 CLK_NBHT_CLK# HTT_0#/66M_1 GND
SB TYPE R716
SLG8SP628-GP
X01 *SB700 EMPTY
03/31 modify
SB710 STUFF
71.08628.003 1.Change R709/R710 from 33 ohm to 22 ohm
*DEFAULT

TP701 1 TP_CLK_SRC6
A00
A TP702 TP_CLK_SRC6# 08/22 modify A
1 Main Source
TP703 TP_CLKREQ0#
TP704
1
1 TP_CLKREQ3#
change U702 to 71.08628.003. NB ALINK SEL_HTT66 1 66 MHz 3.3V single ended HTT clock
2nd source is 71.09480.A03
TP705
TP706
1 TP_CLKREQ4#
TP_CLK_SRC4
(100MHz) FS0
0* 100 MHz differential HTT clock Wistron Corporation
1
TP707 TP_CLK_SRC4# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 SB PCIE SEL_SATA 1* 100 MHz non-spreading differential SRC clock Taipei Hsien 221, Taiwan, R.O.C.
(100MHz) FS1
0 100 MHz spreading differential SRC clock Title
VGA M92 SEL_27MHz 1*
27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6
Clock Generator ICS9LPRS480
Size Document Number Rev
(27MHz) FS2
Custom
* default
0 100MHz differential spreading SRC clock Riya Discrete A00
Date: Tuesday, August 25, 2009 Sheet 7 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

CPU TYPE C801~C803

*Griffin 4.7uF
Tigris
*DEFAULT
10uF
CPU HT3.0
+1.2V_RUN
Place close to socket 1.2V(1.5A) for VLDT

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SC180P50V2JN-1GP

SC180P50V2JN-1GP
1

1
C801

C802

C803

C804

C805

C806

C807
U1A

2
D1 VLDT_A0 HT LINK VLDT_B0 AE2
D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5

C 14 HT_NB_CPU_CAD_H0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CPU_NB_CAD_H0 14 C

14 HT_NB_CPU_CAD_L0 E2 L0_CADIN_L0 L0_CADOUT_L0 AC1 HT_CPU_NB_CAD_L0 14
14 HT_NB_CPU_CAD_H1 E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 HT_CPU_NB_CAD_H1 14
14 HT_NB_CPU_CAD_L1 F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 HT_CPU_NB_CAD_L1 14
14 HT_NB_CPU_CAD_H2 G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 HT_CPU_NB_CAD_H2 14
14 HT_NB_CPU_CAD_L2 G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 HT_CPU_NB_CAD_L2 14
14 HT_NB_CPU_CAD_H3 G1 L0_CADIN_H3 L0_CADOUT_H3 AA2 HT_CPU_NB_CAD_H3 14
14 HT_NB_CPU_CAD_L3 H1 L0_CADIN_L3 L0_CADOUT_L3 AA3 HT_CPU_NB_CAD_L3 14
14 HT_NB_CPU_CAD_H4 J1 L0_CADIN_H4 L0_CADOUT_H4 W2 HT_CPU_NB_CAD_H4 14
14 HT_NB_CPU_CAD_L4 K1 L0_CADIN_L4 L0_CADOUT_L4 W3 HT_CPU_NB_CAD_L4 14
14 HT_NB_CPU_CAD_H5 L3 L0_CADIN_H5 L0_CADOUT_H5 V1 HT_CPU_NB_CAD_H5 14
14 HT_NB_CPU_CAD_L5 L2 L0_CADIN_L5 L0_CADOUT_L5 U1 HT_CPU_NB_CAD_L5 14
14 HT_NB_CPU_CAD_H6 L1 L0_CADIN_H6 L0_CADOUT_H6 U2 HT_CPU_NB_CAD_H6 14
14 HT_NB_CPU_CAD_L6 M1 L0_CADIN_L6 L0_CADOUT_L6 U3 HT_CPU_NB_CAD_L6 14
14 HT_NB_CPU_CAD_H7 N3 L0_CADIN_H7 L0_CADOUT_H7 T1 HT_CPU_NB_CAD_H7 14
14 HT_NB_CPU_CAD_L7 N2 L0_CADIN_L7 L0_CADOUT_L7 R1 HT_CPU_NB_CAD_L7 14
14 HT_NB_CPU_CAD_H8 E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 HT_CPU_NB_CAD_H8 14
14 HT_NB_CPU_CAD_L8 F5 L0_CADIN_L8 L0_CADOUT_L8 AD3 HT_CPU_NB_CAD_L8 14
14 HT_NB_CPU_CAD_H9 F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 HT_CPU_NB_CAD_H9 14
14 HT_NB_CPU_CAD_L9 F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 HT_CPU_NB_CAD_L9 14
14 HT_NB_CPU_CAD_H10 G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 HT_CPU_NB_CAD_H10 14
14 HT_NB_CPU_CAD_L10 H5 L0_CADIN_L10 L0_CADOUT_L10 AB3 HT_CPU_NB_CAD_L10 14
14 HT_NB_CPU_CAD_H11 H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 HT_CPU_NB_CAD_H11 14
14 HT_NB_CPU_CAD_L11 H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 HT_CPU_NB_CAD_L11 14
14 HT_NB_CPU_CAD_H12 K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 HT_CPU_NB_CAD_H12 14
14 HT_NB_CPU_CAD_L12 K4 L0_CADIN_L12 L0_CADOUT_L12 W5 HT_CPU_NB_CAD_L12 14
14 HT_NB_CPU_CAD_H13 L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CPU_NB_CAD_H13 14
14 HT_NB_CPU_CAD_L13 M5 L0_CADIN_L13 L0_CADOUT_L13 V3 HT_CPU_NB_CAD_L13 14
14 HT_NB_CPU_CAD_H14 M3 L0_CADIN_H14 L0_CADOUT_H14 V5 HT_CPU_NB_CAD_H14 14
14 HT_NB_CPU_CAD_L14 M4 L0_CADIN_L14 L0_CADOUT_L14 U5 HT_CPU_NB_CAD_L14 14
B
14 HT_NB_CPU_CAD_H15 N5 L0_CADIN_H15 L0_CADOUT_H15 T4 HT_CPU_NB_CAD_H15 14 B
14 HT_NB_CPU_CAD_L15 P5 L0_CADIN_L15 L0_CADOUT_L15 T3 HT_CPU_NB_CAD_L15 14

14 HT_NB_CPU_CLK_H0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 HT_CPU_NB_CLK_H0 14

14 HT_NB_CPU_CLK_L0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 HT_CPU_NB_CLK_L0 14
14 HT_NB_CPU_CLK_H1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HT_CPU_NB_CLK_H1 14
14 HT_NB_CPU_CLK_L1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CPU_NB_CLK_L1 14

14 HT_NB_CPU_CTL_H0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CPU_NB_CTL_H0 14

14 HT_NB_CPU_CTL_L0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CPU_NB_CTL_L0 14
14 HT_NB_CPU_CTL_H1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 HT_CPU_NB_CTL_H1 14
14 HT_NB_CPU_CTL_L1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 HT_CPU_NB_CTL_L1 14

SKT-CPU638P-GP-U2
62.10055.111

SKT-BGA638H176
1'nd 62.10055.111
2'nd 62.10055.171
A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_HT_LINK I/F_(1/4)
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 8 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = CPU U1C

MEM:DATA
13 MEM_MA_DATA0 G12 MA_DATA0 MB_DATA0 C11 MEM_MB_DATA0 12
13 MEM_MA_DATA1 F12 MA_DATA1 MB_DATA1 A11 MEM_MB_DATA1 12
13 MEM_MA_DATA2 H14 MA_DATA2 MB_DATA2 A14 MEM_MB_DATA2 12
13 MEM_MA_DATA3 G14 MA_DATA3 MB_DATA3 B14 MEM_MB_DATA3 12
13 MEM_MA_DATA4 H11 MA_DATA4 MB_DATA4 G11 MEM_MB_DATA4 12
13 MEM_MA_DATA5 H12 MA_DATA5 MB_DATA5 E11 MEM_MB_DATA5 12
13 MEM_MA_DATA6 C13 MA_DATA6 MB_DATA6 D12 MEM_MB_DATA6 12
13 MEM_MA_DATA7 E13 MA_DATA7 MB_DATA7 A13 MEM_MB_DATA7 12
D +0.9V_VTT D
Place near to CPU 13 MEM_MA_DATA8 H15
E15
MA_DATA8 MB_DATA8 A15
A16
MEM_MB_DATA8 12
13 MEM_MA_DATA9 MA_DATA9 MB_DATA9 MEM_MB_DATA9 12
13 MEM_MA_DATA10 E17 MA_DATA10 MB_DATA10 A19 MEM_MB_DATA10 12
SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

SC180P50V2JN-1GP

SC180P50V2JN-1GP

SC180P50V2JN-1GP

SC180P50V2JN-1GP
13 MEM_MA_DATA11 H17 MA_DATA11 MB_DATA11 A20 MEM_MB_DATA11 12
13 MEM_MA_DATA12 E14 MA_DATA12 MB_DATA12 C14 MEM_MB_DATA12 12
1

1
C901

C916

C902

C903

C904

C905

C906

C907

C908

C909

C910

C911

C912

C913

C914

C915
13 MEM_MA_DATA13 F14 MA_DATA13 MB_DATA13 D14 MEM_MB_DATA13 12
13 MEM_MA_DATA14 C17 MA_DATA14 MB_DATA14 C18 MEM_MB_DATA14 12
13 MEM_MA_DATA15 G17 D18 MEM_MB_DATA15 12
2

2
MA_DATA15 MB_DATA15
13 MEM_MA_DATA16 G18 MA_DATA16 MB_DATA16 D20 MEM_MB_DATA16 12
13 MEM_MA_DATA17 C19 MA_DATA17 MB_DATA17 A21 MEM_MB_DATA17 12
13 MEM_MA_DATA18 D22 MA_DATA18 MB_DATA18 D24 MEM_MB_DATA18 12
13 MEM_MA_DATA19 E20 MA_DATA19 MB_DATA19 C25 MEM_MB_DATA19 12
13 MEM_MA_DATA20 E18 MA_DATA20 MB_DATA20 B20 MEM_MB_DATA20 12
13 MEM_MA_DATA21 F18 MA_DATA21 MB_DATA21 C20 MEM_MB_DATA21 12
13 MEM_MA_DATA22 B22 MA_DATA22 MB_DATA22 B24 MEM_MB_DATA22 12
13 MEM_MA_DATA23 C23 MA_DATA23 MB_DATA23 C24 MEM_MB_DATA23 12
13 MEM_MA_DATA24 F20 MA_DATA24 MB_DATA24 E23 MEM_MB_DATA24 12
13 MEM_MA_DATA25 F22 MA_DATA25 MB_DATA25 E24 MEM_MB_DATA25 12
13 MEM_MA_DATA26 H24 MA_DATA26 MB_DATA26 G25 MEM_MB_DATA26 12
13 MEM_MA_DATA27 J19 MA_DATA27 MB_DATA27 G26 MEM_MB_DATA27 12
13 MEM_MA_DATA28 E21 MA_DATA28 MB_DATA28 C26 MEM_MB_DATA28 12
+0.9V_VTT E22 D26
13 MEM_MA_DATA29 MA_DATA29 MB_DATA29 MEM_MB_DATA29 12
0.9V(750mA) for VTT 13 MEM_MA_DATA30 H20
H22
MA_DATA30 MB_DATA30 G23
G24
MEM_MB_DATA30 12
13 MEM_MA_DATA31 MA_DATA31 MB_DATA31 MEM_MB_DATA31 12
+1.8V_SUS 13 MEM_MA_DATA32 Y24 MA_DATA32 MB_DATA32 AA24 MEM_MB_DATA32 12
U1B
13 MEM_MA_DATA33 AB24 MA_DATA33 MB_DATA33 AA23 MEM_MB_DATA33 12
13 MEM_MA_DATA34 AB22 MA_DATA34 MB_DATA34 AD24 MEM_MB_DATA34 12

SCD1U10V2KX-4GP SCD1U10V2KX-4GP
D10 VTT1 W10 13 MEM_MA_DATA35 AA21 AE24 MEM_MB_DATA35 12
C10 MEM:CMD/CTRL/CLK VTT5 AC10 W22
MA_DATA35 MB_DATA35
AA26
VTT2 VTT6 13 MEM_MA_DATA36 MA_DATA36 MB_DATA36 MEM_MB_DATA36 12

1
1KR3F-GP
C B10 VTT3 VTT7 AB10 13 MEM_MA_DATA37 W21 MA_DATA37 MB_DATA37 AA25 MEM_MB_DATA37 12 C

1
C917

R902
AD10 VTT4 VTT8 AA10 13 MEM_MA_DATA38 Y22 MA_DATA38 MB_DATA38 AD26 MEM_MB_DATA38 12
+1.8V_SUS A10 AA22 AE25
VTT9 +0.9V_SUS_CPU_M_VREF +V_DDR_VREF_M 13 MEM_MA_DATA39 MA_DATA39 MB_DATA39 MEM_MB_DATA39 12
R901 1 2 39D2R2F-L-GP MEMZP AF10 Y20 AC22
13 MEM_MA_DATA40 MEM_MB_DATA40 12

2
R903 1 MEMZP MA_DATA40 MB_DATA40
2 39D2R2F-L-GP MEMZN AE10 Y10 TP_CPU_VTT_SUS_FB
13 MEM_MA_DATA41 AA20 AD22 MEM_MB_DATA41 12

2
MEMZN VTT_SENSE R904 MA_DATA41 MB_DATA41
13 MEM_MA_DATA42 AA18 MA_DATA42 MB_DATA42 AE20 MEM_MB_DATA42 12
TP_MEM_RSVD_M1 H16 W17 1 2 AB18 AF20
RSVD_M1 MEMVREF DY 13 MEM_MA_DATA43 MA_DATA43 MB_DATA43 MEM_MB_DATA43 12

SC1000P50V3JN-GP-U
13 MEM_MA_DATA44 AB21 MA_DATA44 MB_DATA44 AF24 MEM_MB_DATA44 12

1
1KR3F-GP
T19 B18 TP_MEM_RSVD_M2 Do Not Stuff AD21 AF23
13 MEM_MA0_ODT0 MA0_ODT0 RSVD_M2 13 MEM_MA_DATA45 MA_DATA45 MB_DATA45 MEM_MB_DATA45 12

1
C918

C919

R905
13 MEM_MA0_ODT1 V22 MA0_ODT1 13 MEM_MA_DATA46 AD19 MA_DATA46 MB_DATA46 AC20 MEM_MB_DATA46 12
U21 MA1_ODT0 MB0_ODT0 W26 MEM_MB0_ODT0 12 13 MEM_MA_DATA47 Y18 MA_DATA47 MB_DATA47 AD20 MEM_MB_DATA47 12
V19 W23 MEM_MB0_ODT1 12 13 MEM_MA_DATA48 AD17 AD18 MEM_MB_DATA48 12

2
MA1_ODT1 MB0_ODT1 MA_DATA48 MB_DATA48
Y26 13 MEM_MA_DATA49 W16 AE18 MEM_MB_DATA49 12

2
MB1_ODT0 MA_DATA49 MB_DATA49
13 MEM_MA0_CS#0 T20 MA0_CS_L0 13 MEM_MA_DATA50 W14 MA_DATA50 MB_DATA50 AC14 MEM_MB_DATA50 12
13 MEM_MA0_CS#1 U19 MA0_CS_L1 MB0_CS_L0 V26 MEM_MB0_CS#0 12 13 MEM_MA_DATA51 Y14 MA_DATA51 MB_DATA51 AD14 MEM_MB_DATA51 12
U20 MA1_CS_L0 MB0_CS_L1 W25 MEM_MB0_CS#1 12 13 MEM_MA_DATA52 Y17 MA_DATA52 MB_DATA52 AF19 MEM_MB_DATA52 12
V20 MA1_CS_L1 MB1_CS_L0 U22 CLOSE TO CPU 13 MEM_MA_DATA53 AB17
AB15
MA_DATA53 MB_DATA53 AC18
AF16
MEM_MB_DATA53 12
13 MEM_MA_DATA54 MA_DATA54 MB_DATA54 MEM_MB_DATA54 12
13 MEM_MA_CKE0 J22 MA_CKE0 MB_CKE0 J25 MEM_MB_CKE0 12 13 MEM_MA_DATA55 AD15 MA_DATA55 MB_DATA55 AF15 MEM_MB_DATA55 12
13 MEM_MA_CKE1 J20 MA_CKE1 MB_CKE1 H26 MEM_MB_CKE1 12 13 MEM_MA_DATA56 AB13 MA_DATA56 MB_DATA56 AF13 MEM_MB_DATA56 12
13 MEM_MA_DATA57 AD13 MA_DATA57 MB_DATA57 AC12 MEM_MB_DATA57 12
N19 MA_CLK_H5 MB_CLK_H5 P22 13 MEM_MA_DATA58 Y12 MA_DATA58 MB_DATA58 AB11 MEM_MB_DATA58 12
N20 MA_CLK_L5 MB_CLK_L5 R22 13 MEM_MA_DATA59 W11 MA_DATA59 MB_DATA59 Y11 MEM_MB_DATA59 12
13 MEM_MA_CLK0_P E16 MA_CLK_H1 MB_CLK_H1 A17 MEM_MB_CLK0_P 12 13 MEM_MA_DATA60 AB14 MA_DATA60 MB_DATA60 AE14 MEM_MB_DATA60 12
13 MEM_MA_CLK0_N F16 MA_CLK_L1 MB_CLK_L1 A18 MEM_MB_CLK0_N 12 13 MEM_MA_DATA61 AA14 MA_DATA61 MB_DATA61 AF14 MEM_MB_DATA61 12
13 MEM_MA_CLK1_P Y16 MA_CLK_H7 MB_CLK_H7 AF18 MEM_MB_CLK1_P 12 13 MEM_MA_DATA62 AB12 MA_DATA62 MB_DATA62 AF11 MEM_MB_DATA62 12
13 MEM_MA_CLK1_N AA16 MA_CLK_L7 MB_CLK_L7 AF17 MEM_MB_CLK1_N 12 13 MEM_MA_DATA63 AA12 MA_DATA63 MB_DATA63 AD11 MEM_MB_DATA63 12
P19 MA_CLK_H4 MB_CLK_H4 R26
P20 MA_CLK_L4 MB_CLK_L4 R25 13 MEM_MA_DM0 E12 MA_DM0 MB_DM0 A12 MEM_MB_DM0 12
13 MEM_MA_DM1 C15 MA_DM1 MB_DM1 B16 MEM_MB_DM1 12
B
13 MEM_MA_ADD0 N21 MA_ADD0 MB_ADD0 P24 MEM_MB_ADD0 12 13 MEM_MA_DM2 E19 MA_DM2 MB_DM2 A22 MEM_MB_DM2 12 B
13 MEM_MA_ADD1 M20 MA_ADD1 MB_ADD1 N24 MEM_MB_ADD1 12 13 MEM_MA_DM3 F24 MA_DM3 MB_DM3 E25 MEM_MB_DM3 12
13 MEM_MA_ADD2 N22 MA_ADD2 MB_ADD2 P26 MEM_MB_ADD2 12 13 MEM_MA_DM4 AC24 MA_DM4 MB_DM4 AB26 MEM_MB_DM4 12
13 MEM_MA_ADD3 M19 MA_ADD3 MB_ADD3 N23 MEM_MB_ADD3 12 13 MEM_MA_DM5 Y19 MA_DM5 MB_DM5 AE22 MEM_MB_DM5 12
13 MEM_MA_ADD4 M22 MA_ADD4 MB_ADD4 N26 MEM_MB_ADD4 12 13 MEM_MA_DM6 AB16 MA_DM6 MB_DM6 AC16 MEM_MB_DM6 12
13 MEM_MA_ADD5 L20 MA_ADD5 MB_ADD5 L23 MEM_MB_ADD5 12 13 MEM_MA_DM7 Y13 MA_DM7 MB_DM7 AD12 MEM_MB_DM7 12
13 MEM_MA_ADD6 M24 MA_ADD6 MB_ADD6 N25 MEM_MB_ADD6 12
13 MEM_MA_ADD7 L21 MA_ADD7 MB_ADD7 L24 MEM_MB_ADD7 12 13 MEM_MA_DQS0_P G13 MA_DQS_H0 MB_DQS_H0 C12 MEM_MB_DQS0_P 12
13 MEM_MA_ADD8 L19 MA_ADD8 MB_ADD8 M26 MEM_MB_ADD8 12 13 MEM_MA_DQS0_N H13 MA_DQS_L0 MB_DQS_L0 B12 MEM_MB_DQS0_N 12
13 MEM_MA_ADD9 K22 MA_ADD9 MB_ADD9 K26 MEM_MB_ADD9 12 13 MEM_MA_DQS1_P G16 MA_DQS_H1 MB_DQS_H1 D16 MEM_MB_DQS1_P 12
13 MEM_MA_ADD10 R21 MA_ADD10 MB_ADD10 T26 MEM_MB_ADD10 12 13 MEM_MA_DQS1_N G15 MA_DQS_L1 MB_DQS_L1 C16 MEM_MB_DQS1_N 12
13 MEM_MA_ADD11 L22 MA_ADD11 MB_ADD11 L26 MEM_MB_ADD11 12 13 MEM_MA_DQS2_P C22 MA_DQS_H2 MB_DQS_H2 A24 MEM_MB_DQS2_P 12
13 MEM_MA_ADD12 K20 MA_ADD12 MB_ADD12 L25 MEM_MB_ADD12 12 13 MEM_MA_DQS2_N C21 MA_DQS_L2 MB_DQS_L2 A23 MEM_MB_DQS2_N 12
13 MEM_MA_ADD13 V24 MA_ADD13 MB_ADD13 W24 MEM_MB_ADD13 12 13 MEM_MA_DQS3_P G22 MA_DQS_H3 MB_DQS_H3 F26 MEM_MB_DQS3_P 12
13 MEM_MA_ADD14 K24 MA_ADD14 MB_ADD14 J23 MEM_MB_ADD14 12 13 MEM_MA_DQS3_N G21 MA_DQS_L3 MB_DQS_L3 E26 MEM_MB_DQS3_N 12
13 MEM_MA_ADD15 K19 MA_ADD15 MB_ADD15 J24 MEM_MB_ADD15 12 13 MEM_MA_DQS4_P AD23 MA_DQS_H4 MB_DQS_H4 AC25 MEM_MB_DQS4_P 12
13 MEM_MA_DQS4_N AC23 MA_DQS_L4 MB_DQS_L4 AC26 MEM_MB_DQS4_N 12
13 MEM_MA_BANK0 R20 MA_BANK0 MB_BANK0 R24 MEM_MB_BANK0 12 13 MEM_MA_DQS5_P AB19 MA_DQS_H5 MB_DQS_H5 AF21 MEM_MB_DQS5_P 12
13 MEM_MA_BANK1 R23 MA_BANK1 MB_BANK1 U26 MEM_MB_BANK1 12 13 MEM_MA_DQS5_N AB20 MA_DQS_L5 MB_DQS_L5 AF22 MEM_MB_DQS5_N 12
13 MEM_MA_BANK2 J21 MA_BANK2 MB_BANK2 J26 MEM_MB_BANK2 12 13 MEM_MA_DQS6_P Y15 MA_DQS_H6 MB_DQS_H6 AE16 MEM_MB_DQS6_P 12
13 MEM_MA_DQS6_N W15 MA_DQS_L6 MB_DQS_L6 AD16 MEM_MB_DQS6_N 12
13 MEM_MA_RAS# R19 MA_RAS_L MB_RAS_L U25 MEM_MB_RAS# 12 13 MEM_MA_DQS7_P W12 MA_DQS_H7 MB_DQS_H7 AF12 MEM_MB_DQS7_P 12
13 MEM_MA_CAS# T22 MA_CAS_L MB_CAS_L U24 MEM_MB_CAS# 12 13 MEM_MA_DQS7_N W13 MA_DQS_L7 MB_DQS_L7 AE12 MEM_MB_DQS7_N 12
13 MEM_MA_WE# T24 MA_WE_L MB_WE_L U23 MEM_MB_WE# 12
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2 62.10055.111
62.10055.111
A TP901 TP_MEM_RSVD_M1 A
1 Main Source
TP902 1 TP_CPU_VTT_SUS_FB
TP903 1 TP_MEM_RSVD_M2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_DDR_(2/4)
Size Document Number Rev
Custom Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 9 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = CPU
LYAOUT:ROUTE VDDA TRACE APPROX.
50mils WIDE(USE 2X25 mil TRACES TO
+1.8V_RUN
EXIT BALL FIELD) AND 500 mils LONG.
X01
04/14 Del
1.Del R1001 ,reserve closed-gap.
Del R1002 ,reserve closed-gap.

8
7
6
5
Del R1003 ,reserve closed-gap. +2.5V_RUN +2.5V_RUN_VDDA
D D
RN1001 L1001
SRN300J-1-GP 1 2
2.5V(250mA) for VDDA

SC180P50V2JN-1GP

SC4D7U6D3V5KX-3GP

SCD22U6D3V2KX-1GP

SC3300P50V2KX-1GP
BLM18PG330SN1D-GP
1
2
3
4

1
+1.8V_RUN

C1008

C1001

C1002

C1003
1 2 CPU_R_LDT_RST# +1.8V_SUS
18 CPU_LDT_RST#
R1001 Do Not Stuff
1 2 CPU_R_LDT_PWRGD The Processor has
18 CPU_LDT_PWRGD

2
R1002 Do Not Stuff reached a preset

1
1KR2J-1-GP

1KR2J-1-GP
18 CPU_LDT_STOP# 1 2 CPU_R_LDT_STOP# 15 U1D maximum operating

1
R1007

R1005

300R2J-4-GP

300R2J-4-GP

Do Not Stuff
R1003 Do Not Stuff

R1008

R1009

R1010
1 2 CPU_LDT_REQ#
15,18 ALLOW_LDTSTOP R1004 0R2J-2-GP temperature. 100℃
Cloce To CPU
F8
F9
VDDA1 KEY1 M11
W18
DY I=Active HTC

2
R1011 1 VDDA2 KEY2
2169R2F-GP

2
7 CPU_CLK
C1004 1 2SC3900P50V2KX-2GP CPUCLK_IN A9 CLKIN_H SVC A6 CPU_SVC 35 O=FAN
C1005 1 2SC3900P50V2KX-2GP CPUCLK_IN#
CPU_CLK(200MHz) 7 CPU_CLK# A8 CLKIN_L SVD A4 CPU_SVD 35
CPU_R_LDT_RST# B7
CPU_R_LDT_PWRGD RESET_L
A7 PWROK

Do Not Stuff
CPU TYPE R1004 R1006 CPU_R_LDT_STOP# F10 AF6 CPU_THERMTRIP#
LDTSTOP_L THERMTRIP_L

1
C1006
HDT_RST# 1 DY 2 CPU_LDT_REQ# C6 AC7 CPU_PROCHOT#
LDTREQ_L PROCHOT_L CPU_PROCHOT# 18
CPU_MEMHOT#
*Griffin STUFF
Do Not Stuff
DY CPU_SIC MEMHOT_L AA8
For HDT DBG AF4

2
CPU_SID SIC
Tigris EMPTY AF5 SID
CPU_ALERT# AE6 W7
+1.2V_RUN ALERT_L THERMDC H_THERMDC 29
*DEFAULT THERMDA W8 H_THERMDA 29
R1012 2 44D2R2F-GP CPU_HTREF0
Close CPU R1013
1
1 2 44D2R2F-GP CPU_HTREF1
R6
P6
HT_REF0 1 DY2
C1007
HT_REF1 Do Not Stuff
C C
F6 W9 TP_CPU_VDDIO_SUS_FB_H
35 CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H
E6 Y9 TP_CPU_VDDIO_SUS_FB_L
35 CPU_VDD0_RUN_FB_L VDD0_FB_L VDDIO_FB_L

35 CPU_VDD1_RUN_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_RUN_FB_H 35

35 CPU_VDD1_RUN_FB_L AB6 VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_RUN_FB_L 35
CPU_DBRDY G10 R1014
CPU_TMS DBRDY CPU_DBREQ# 1
AA9 TMS DBREQ_L E10 2 +1.8V_RUN
CPU_TCK AC9
CPU_TRST# TCK CPU_TDO 300R2J-4-GP
AD9 TRST_L TDO AE9
+1.8V_SUS CPU_TDI AF9 TDI
CPU_TEST23 AD7 J7 TP_CPU_TEST28_H
TEST23 TEST28_H TP_CPU_TEST28_L
CPU_TEST18 H10
TEST28_L H8 LAYOUT: Route FBCLKOUT_H/L
CPU_TEST19 TEST18 TP_CPU_TEST17
G9 TEST19 TEST17 D7
E7 TP_CPU_TEST16 differentially impedance 80
R1015 CPU_TEST25_H TEST16 TP_CPU_TEST15
E9 TEST25_H TEST15 F7
1 2 CPU_TEST25_L E8 C7 TP_CPU_TEST14
TEST25_L TEST14 +1.2V_RUN
300R2J-4-GP CPU_TEST21 AB8 C3 R1032
CPU_TEST20 TEST21 TEST7 CPU_TEST10
AF7 K8 1
DY 2
HDT Connectors
CPU_TEST24 TEST20 TEST10
AE7 TEST24
CPU_TEST22 AE8 C4 Do Not Stuff
TP_CPU_TEST12 TEST22 TEST8
AC8 TEST12
1

1
300R2J-4-GP

Do Not Stuff

Do Not Stuff

300R2J-4-GP

300R2J-4-GP

300R2J-4-GP

300R2J-4-GP

Do Not Stuff

CPU TYPE R1015 R1017 TP_CPU_TEST27 AF8 TEST27

R1016

R1033

R1034

R1017

R1018

R1019

R1020

R1035

R1021 C9 TP_CPU_TEST29H
CPU_TEST9 TEST29_H TP_CPU_TEST29L
*Griffin 300 ohm DY DY DY 1 2 C2
AA6
TEST9 TEST29_L C8

0R2J-2-GP TEST6
B Tigris 510 ohm B
2

A3 RSVD1 RSVD10 H18

*DEFAULT A5 RSVD2 RSVD9 H19
B3 RSVD3 RSVD8 AA7
B5 RSVD4 RSVD7 D5
C1 RSVD5 RSVD6 C5

SKT-CPU638P-GP-U2 HDT1
62.10055.111 1 2
X01 3
DY
4
04/09 Modify 5 6
1.Change CPU SID/SIC from SB_SMBus_Ch1 to SCL3_LV/SDA3_LV. CPU_DBREQ# 7 8
2.Del Q1001,R1027,Q1003,R1028. +3.3V_RTC_LDO CPU_DBRDY 9 10
CPU_R_LDT_PWRGD CPU_TCK 11 12
CPU_TMS
X01 13 14

1
Do Not Stuff

2K2R2J-2-GP
CPU_TDI 15 16

R1022

R1023
04/14 BOM CPU_TRST# 17 18
1.Dummy R1022. CPU_TDO
+1.8V_SUS DY 19
21
20
22
+1.8V_SUS 23 24

1 2
26
Q1002
1

1
2K2R2J-2-GP

2K2R2J-2-GP

2K2R2J-2-GP

1KR2J-1-GP

Do Not Stuff
R1024

R1025

R1026

R1029

3 2 CPU_THERMTRIP#
19,27,29 SYS_THERMTRIP#
HDT_RST#
MMBT3904-7-F-GP
2

TP1004 1 TP_CPU_TEST12 +3.3V_RUN +1.8V_SUS

A TP1005 TP_CPU_TEST27 A
1 Main Source
TP1006 1 TP_CPU_VDDIO_SUS_FB_H
1

1
10KR2J-3-GP

TP1007 TP_CPU_VDDIO_SUS_FB_L CPU_SIC 2K2R2J-2-GP

1 19 CPU_SIC
R1031

R1030
TP1008 TP_CPU_TEST28_H
TP1009
1
1 TP_CPU_TEST28_L Wistron Corporation
TP1010 1 TP_CPU_TEST17 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
TP1011 1 TP_CPU_TEST16 CPU_SID Taipei Hsien 221, Taiwan, R.O.C.
19 CPU_SID
2

1 2

TP1012 1 TP_CPU_TEST15
1

TP1013 1 TP_CPU_TEST14 Q1005 Q1004 Title

TP1014
TP1015
1 TP_CPU_TEST29H
TP_CPU_TEST29L CPU_ALERT# CPU_R_LDT_PWRGD
CPU_Control&Debug_(3/4)
1 20,29 TALERT# 3 2 35 CPU_PWRGD_SVID_REG 3 2
Size Document Number Rev
Custom
MMBT3904-7-F-GP MMBT3904-7-F-GP Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 10 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = CPU

D D

U1F
AA4
AA11
VSS1 VSS66 J6
J8 +VCC_CORE0 (36A) for VDD0&VDD1 U1E +VCC_CORE1
VSS2 VSS67
AA13
AA15
VSS3 VSS68 J10
J12
Bottom Side Decoupling G4 P8
Bottom Side Decoupling
VSS4 VSS69 VDD0_1 VDD1_1

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SCD22U6D3V2KX-1GP

SCD01U50V2KX-1GP

SC180P50V2JN-1GP

SC180P50V2JN-1GP

SCD01U50V2KX-1GP

SCD22U6D3V2KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
AA17 VSS5 VSS70 J14 H2 VDD0_2 VDD1_2 P10
AA19 VSS6 VSS71 J16 J9 VDD0_3 VDD1_3 R4
AB2 VSS7 VSS72 J18 J11 VDD0_4 VDD1_4 R7

1
C1101

C1102

C1103

C1104

C1105

C1106

C1107

C1108

C1109

C1110

C1111

C1112

C1113

C1114
AB7 VSS8 VSS73 K2 J13 VDD0_5 VDD1_5 R9
AB9 VSS9 VSS74 K7 J15 VDD0_6 VDD1_6 R11
AB23 VSS10 VSS75 K9 K6 T2

2
VDD0_7 VDD1_7

2
AB25 VSS11 VSS76 K11 K10 VDD0_8 VDD1_8 T6
AC11 VSS12 VSS77 K13 K12 VDD0_9 VDD1_9 T8
AC13 VSS13 VSS78 K15 K14 VDD0_10 VDD1_10 T10
AC15 VSS14 VSS79 K17 L4 VDD0_11 VDD1_11 T12
AC17 VSS15 VSS80 L6 L7 VDD0_12 VDD1_12 T14
AC19 VSS16 VSS81 L8 L9 VDD0_13 VDD1_13 U7
AC21 VSS17 VSS82 L10 L11 VDD0_14 VDD1_14 U9
AD6 VSS18 VSS83 L12 L13 VDD0_15 VDD1_15 U11
C AD8 L14 L15 U13 C
VSS19 VSS84 VDD0_16 VDD1_16
AD25 VSS20 VSS85 L16 M2 VDD0_17 VDD1_17 U15
AE11 VSS21 VSS86 L18 M6 VDD0_18 VDD1_18 V6
AE13 VSS22 VSS87 M7 M8 VDD0_19 VDD1_19 V8
AE15 VSS23 VSS88 M9 M10 VDD0_20 VDD1_20 V10
AE17 VSS24 VSS89 AC6 N7 VDD0_21 VDD1_21 V12
AE19 VSS25 VSS90 M17 N9 VDD0_22 VDD1_22 V14
+VDDNB
AE21
AE23
VSS26 VSS91 N4
N8
0.8~1.1V(4A) for VDDNB N11 VDD0_23 VDD1_23 W4
Y2
VSS27 VSS92 VDD1_24
B4 VSS28 VSS93 N10 K16 VDDNB_1 VDD1_25 AC4
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
B6 N16 M16 AD2 +1.8V_SUS
VSS29 VSS94 VDDNB_2 VDD1_26
B8
B9
VSS30 VSS95 N18
P2
P16
T16
VDDNB_3
Y25
Place near to CPU
VSS31 VSS96 VDDNB_4 VDDIO27
1

1
C1115

C1116

C1117

SC180P50V2JN-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
B11 VSS32 VSS97 P7 V16 VDDNB_5 VDDIO26 V25
B13 VSS33 VSS98 P9 VDDIO25 V23
B15 VSS34 VSS99 P11 H25 V21
2

2
VDDIO1 VDDIO24

1
C1118

C1119

C1120

C1121

C1122

C1123

C1124

C1125

C1126

C1127

C1128
B17 VSS35 VSS100 P17 J17 VDDIO2 VDDIO23 V18
B19 VSS36 VSS101 R8 K18 VDDIO3 VDDIO22 U17
B21 VSS37 VSS102 R10 K21 VDDIO4 VDDIO21 T25

2
B23 VSS38 VSS103 R16 K23 VDDIO5 VDDIO20 T23
B25 VSS39 VSS104 R18 K25 VDDIO6 VDDIO19 T21
D6 VSS40 VSS105 T7 L17 VDDIO7 VDDIO18 T18
D8 VSS41 VSS106 T9 M18 VDDIO8 VDDIO17 R17
D9
D11
VSS42 VSS107 T11
T13 +1.8V_SUS 1.8V(2A) for VDDIO M21
M23
VDDIO9 VDDIO16 P25
P23
VSS43 VSS108 VDDIO10 VDDIO15
D13 VSS44 VSS109 T15 Bottom Side Decoupling M25 VDDIO11 VDDIO14 P21
D15 VSS45 VSS110 T17 N17 VDDIO12 VDDIO13 P18
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

SCD22U6D3V2KX-1GP

SCD22U6D3V2KX-1GP

SC180P50V2JN-1GP

D17 VSS46 VSS111 U4 SC180P50V2JN-1GP

D19 VSS47 VSS112 U6
B SKT-CPU638P-GP-U2 B
D21 VSS48 VSS113 U8
1

1
C1129

C1130

C1131

C1132

C1133

D23 VSS49 VSS114 U10 C1134 62.10055.111

D25 VSS50 VSS115 U12
E4 VSS51 VSS116 U14
2

F2 VSS52 VSS117 U16

F11 VSS53 VSS118 U18
F13 VSS54 VSS119 V2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
F23 VSS59 VSS124 V15
F25 VSS60 VSS125 V17
H7 VSS61 VSS126 W6
H9 VSS62 VSS127 Y21
H21 VSS63 VSS128 Y23
H23 VSS64 VSS129 N6
J4 VSS65
SKT-CPU638P-GP-U2
62.10055.111

A Main Source A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU_Power_(4/4)
Size Document Number Rev
A3
Riya Discrete A00
Date: Tuesday, September 08, 2009 Sheet 11 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY

DIMM1

D 9 MEM_MB_ADD0 102 A0 RAS# 108 MEM_MB_RAS# 9 D

9 MEM_MB_ADD1 101 A1 WE# 109 MEM_MB_WE# 9
9 MEM_MB_ADD2 100 A2 CAS# 113 MEM_MB_CAS# 9
9 MEM_MB_ADD3 99 A3
98 110
9 MEM_MB_ADD4
9 MEM_MB_ADD5
9 MEM_MB_ADD6
97
94
A4
A5
A6
CS0#
CS1# 115
MEM_MB0_CS#0 9
MEM_MB0_CS#1 9 PARALLEL TERMINATION
9 MEM_MB_ADD7 92 A7 CKE0 79 MEM_MB_CKE0 9
93 80 +0.9V_VTT
9 MEM_MB_ADD8 A8 CKE1 MEM_MB_CKE1 9
9 MEM_MB_ADD9 91 A9 Put decap near power(0.9V) and pull-up resistor
9 MEM_MB_ADD10 105 30 MEM_MB_CLK0_P 9 RN1201
A10/AP CK0
9 MEM_MB_ADD11 90 A11 CK0# 32 MEM_MB_CLK0_N 9 1 4 MEM_MB_CKE0 9
9 MEM_MB_ADD12 89 A12 2 3 MEM_MB_CKE1 9
9 MEM_MB_ADD13 116 A13 CK1 164 MEM_MB_CLK1_P 9
86 166 SRN47J-7-GP
9 MEM_MB_ADD14 A14 CK1# MEM_MB_CLK1_N 9
9 MEM_MB_ADD15 84 RN1208
A15
85 A16/BA2 DM0 10 MEM_MB_DM0 9 1 4 MEM_MB_ADD14 9
9 MEM_MB_BANK2 DM1 26 MEM_MB_DM1 9 Do not share the Term resistor between 2 3 MEM_MB_ADD15 9
9 MEM_MB_BANK0 107 52 MEM_MB_DM2 9
106
BA0 DM2
67
the DDR addess and Control Signals. SRN47J-7-GP
9 MEM_MB_BANK1 BA1 DM3 MEM_MB_DM3 9
130 MEM_MB_DM4 9 RN1202
DM4
DM5 147 MEM_MB_DM5 9 1 8 MEM_MB_ADD10 9
9 MEM_MB_DATA0 5
7
DQ0 DM6 170
185
MEM_MB_DM6 9 X01 2
3
7
6
MEM_MB_BANK0 9
9 MEM_MB_DATA1 DQ1 DM7 MEM_MB_DM7 9 03/31 modify MEM_MB_ADD3 9
9 MEM_MB_DATA2 17 DQ2 4 5 MEM_MB_ADD1 9
1.Change DIMM SPD SMBus from Ch1 to Ch0
9 MEM_MB_DATA3 19 DQ3
9 MEM_MB_DATA4 4 195 SMB_DATA_0 7,13,19,44 SRN47J-4-GP
DQ4 SDA
9 MEM_MB_DATA5 6 197 SMB_CLK_0 7,13,19,44 RN1203
DQ5 SCL
9 MEM_MB_DATA6 14 DQ6 1 8 MEM_MB_ADD4 9
9 MEM_MB_DATA7 16 DQ7 VDDSPD 199 +3.3V_RUN 2 7 MEM_MB_ADD2 9

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP
9 MEM_MB_DATA8 23 DQ8 3 6 MEM_MB_ADD0 9

C1201

C1202
25 198 DIMM2_SA0 R1201 1 210KR2J-3-GP 4 5
9 MEM_MB_DATA9 DQ9 SA0 MEM_MB_BANK1 9

1
35 200 DIMM2_SA1 R1202 1 210KR2J-3-GP
9 MEM_MB_DATA10 DQ10 SA1 +3.3V_RUN
9 MEM_MB_DATA11 37 SRN47J-4-GP
DQ11
20 50 RN1204
9 MEM_MB_DATA12
(A4)

2
DQ12 NC#50
9 MEM_MB_DATA13 22 DQ13 NC#69 69 1 8 MEM_MB_ADD8 9
9 MEM_MB_DATA14 36 DQ14 NC#83 83 2 7 MEM_MB_ADD9 9
9 MEM_MB_DATA15 38 DQ15 NC#120 120 3 6 MEM_MB_ADD12 9
9 MEM_MB_DATA16 43 DQ16 NC#163/TEST 163 4 5 MEM_MB_BANK2 9
45 +1.8V_SUS
9 MEM_MB_DATA17 DQ17
55 SRN47J-4-GP
9 MEM_MB_DATA18 DQ18
C
9 MEM_MB_DATA19 57 81 RN1205 C
DQ19 VDD
9 MEM_MB_DATA20 44 DQ20 VDD 82 1 8 MEM_MB_ADD11 9
46 87 2 7
9 MEM_MB_DATA21
9 MEM_MB_DATA22
9 MEM_MB_DATA23
56
58
61
DQ21
DQ22
DQ23
REVERSE TYPE VDD
VDD
VDD
88
95
96
3
4
6
5
MEM_MB_ADD7 9
MEM_MB_ADD5 9
MEM_MB_ADD6 9
9 MEM_MB_DATA24 DQ24 VDD
9 MEM_MB_DATA25 63 103 PLACE CLOSE TO PROCESSOR SRN47J-4-GP
DQ25 VDD
9 MEM_MB_DATA26 73 104 WITHIN 1.5 INCH RN1206
DQ26 VDD
9 MEM_MB_DATA27 75 DQ27 VDD 111 1 4 MEM_MB_RAS# 9
62 112 MEM_MB_CLK0_P 2 3
9 MEM_MB_DATA28 DQ28 VDD MEM_MB0_CS#0 9

SC1D5P50V2CN-1GP
9 MEM_MB_DATA29 64 DQ29 VDD 117
74 118 SRN47J-7-GP
9 MEM_MB_DATA30 DQ30 VDD

C1203
9 MEM_MB_DATA31 76 RN1209
DQ31

1
9 MEM_MB_DATA32 123 DQ32 VSS 3 1 4 MEM_MB0_ODT0 9
9 MEM_MB_DATA33 125 DQ33 VSS 8 2 3 MEM_MB_ADD13 9
9 MEM_MB_DATA34 135 9

2
DQ34 VSS SRN47J-7-GP
9 MEM_MB_DATA35 137 DQ35 VSS 12
9 MEM_MB_DATA36 124 15 RN1207
DQ36 VSS MEM_MB_CLK0_N
9 MEM_MB_DATA37 126 DQ37 VSS 18 1 8 MEM_MB0_ODT1 9
9 MEM_MB_DATA38 134 DQ38 VSS 21 2 7 MEM_MB0_CS#1 9
136 24 MEM_MB_CLK1_P 3 6
9 MEM_MB_DATA39 DQ39 VSS MEM_MB_WE# 9

SC1D5P50V2CN-1GP
9 MEM_MB_DATA40 141 DQ40 VSS 27 4 5 MEM_MB_CAS# 9
9 MEM_MB_DATA41 143 DQ41 VSS 28

C1204
9 MEM_MB_DATA42 151 33 SRN47J-4-GP
DQ42 VSS

1
9 MEM_MB_DATA43 153 DQ43 VSS 34
9 MEM_MB_DATA44 140 DQ44 VSS 39
9 MEM_MB_DATA45 142 40

2
DQ45 VSS
9 MEM_MB_DATA46 152 DQ46 VSS 41
9 MEM_MB_DATA47 154 DQ47 VSS 42
157 47 MEM_MB_CLK1_N
9 MEM_MB_DATA48 DQ48 VSS
9 MEM_MB_DATA49 159 DQ49 VSS 48
9 MEM_MB_DATA50 173 DQ50 VSS 53
9 MEM_MB_DATA51 175 DQ51 VSS 54
9 MEM_MB_DATA52 158 DQ52 VSS 59
9 MEM_MB_DATA53 160 DQ53 VSS 60
9 MEM_MB_DATA54 174 DQ54 VSS 65
176 66
9 MEM_MB_DATA55
9 MEM_MB_DATA56
9 MEM_MB_DATA57
179
181
DQ55
DQ56
DQ57
VSS
VSS
VSS
71
72
Decoupling Capacitor +0.9V_VTT
C1205
+1.8V_SUS
C1206
9 MEM_MB_DATA58 189 DQ58 VSS 77 1 2 1 2
191 78
B
9 MEM_MB_DATA59
9 MEM_MB_DATA60
9 MEM_MB_DATA61
180
182
DQ59
DQ60
DQ61
VSS
VSS
VSS
121
122 +1.8V_SUS Place these Caps near DM2 SCD1U10V2KX-4GP
C1235
SCD1U10V2KX-4GP
C1207
B

9 MEM_MB_DATA62 192 DQ62 VSS 127 1 2 1 2

9 MEM_MB_DATA63 194 DQ63 VSS 128
SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SCD01U50V2KX-1GP

SC180P50V2JN-1GP

SCD01U50V2KX-1GP

SC180P50V2JN-1GP
132 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
VSS C1236 C1217
9 MEM_MB_DQS0_N 11 DQS0# VSS 133
9 MEM_MB_DQS1_N 29 DQS1# VSS 138 1 2 1 2
1

1
C1208

C1209

C1210

C1211

C1212

C1213

C1214

C1215

C1216
9 MEM_MB_DQS2_N 49 DQS2# VSS 139
68 144 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
9 MEM_MB_DQS3_N DQS3# VSS
129 145 C1237 C1218
9 MEM_MB_DQS4_N
2

2
DQS4# VSS
9 MEM_MB_DQS5_N 146 DQS5# VSS 149 1 2 1 2
9 MEM_MB_DQS6_N 167 DQS6# VSS 150
186 155 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
9 MEM_MB_DQS7_N DQS7# VSS
156 C1238
VSS
9 MEM_MB_DQS0_P 13 DQS0 VSS 161 1 2
9 MEM_MB_DQS1_P 31 DQS1 VSS 162
51 165 SCD1U10V2KX-4GP
9 MEM_MB_DQS2_P DQS2 VSS
70 168 C1239
9 MEM_MB_DQS3_P DQS3 VSS
9 MEM_MB_DQS4_P 131 DQS4 VSS 171 1 2
9 MEM_MB_DQS5_P 148 DQS5 VSS 172
169 177 SCD1U10V2KX-4GP
9 MEM_MB_DQS6_P DQS6 VSS
188 178 Layout Note: C1240
9 MEM_MB_DQS7_P DQS7 VSS
183 1 2
114
VSS
184 Place one cap close to every 2 pullup
9 MEM_MB0_ODT0 OTD0 VSS +0.9V_VTT
119 187 resistors terminated to +0.9V_VTT SCD1U10V2KX-4GP
9 MEM_MB0_ODT1 OTD1 VSS
190 C1241
VSS
+VREF_DDR_MEM 1 VREF VSS 193 1 2
SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
2 VSS VSS 196
SCD1U10V2KX-4GP
1

1
C1219

C1220

202 201 C1242

GND GND
1

1
C1221

C1222

C1223

C1224

C1225

C1226

C1227

C1228

C1229

C1230

C1231

C1232

C1233

C1234
1 2
MH1 MH2
2

MH1 MH2 SCD1U10V2KX-4GP

2

2
DDR2-200P-20-GP-U1

Place C2.2uF and 0.1uF < 1'nd:62.10017.A41

500mils from DDR connector
2'nd 62.10017.B01
A
LOW 5.2 mm A

Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR_DIMM1
Size Document Number Rev
A2
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 12 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = MEMORY

DIMM1 (A0)
A
DIMM2 (A4) +0.9V_VTT
D D
RN1301
DIMM2
1 8 MEM_MA0_ODT1 9
2 7
9 MEM_MA_ADD0 102 A0 RAS# 108 MEM_MA_RAS# 9
A B 3 6
MEM_MA0_CS#1 9
MEM_MA_CAS# 9
9 MEM_MA_ADD1 101 A1 WE# 109 MEM_MA_WE# 9 4 5 MEM_MA_ADD0 9

A1
100 113

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24
9 MEM_MA_ADD2 A2 CAS# MEM_MA_CAS# 9

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25
99 SRN47J-4-GP

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26
9 MEM_MA_ADD3 A3

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26
98 110 RN1302

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26
9 MEM_MA_ADD4 A4 CS0# MEM_MA0_CS#0 9

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26
97 115 1 8

G10

G11

G12

G13

G14

G15

G16

G17

G18

G21

G22

G23

G24

G25

G26
G1

G2

G3

G4

G5

G6

G9
9 MEM_MA_ADD5 A5 CS1# MEM_MA0_CS#1 9 MEM_MA_ADD1 9

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26
94 2 7

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26
BGA638_50_26SQ_S1G2_OEM
9 MEM_MA_ADD6 A6 MEM_MA_ADD5 9

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26
92 79 3 6

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26
9 MEM_MA_ADD7 A7 CKE0 MEM_MA_CKE0 9 MEM_MA_ADD3 9

M10

M11

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26
M1

M2

M3

M4

M5

M6

M7

M8

M9
93 80 4 5

N1

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26
9 MEM_MA_ADD8 A8 CKE1 MEM_MA_CKE1 9 MEM_MA_ADD8 9
B

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26
91

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26
9 MEM_MA_ADD9 A9

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26
105 30 SRN47J-4-GP

U1

U2

U3

U4

U5

U6

U7

U8

U9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26
9 MEM_MA_ADD10 A10/AP CK0 MEM_MA_CLK0_P 9

V1

V2

V3

V4

V5

V6

V7

V8

V9

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26
90 32 RN1303

W10

W11

W12

W13

W14

W15

W16

W17

W18

W21

W22

W23

W24

W25

W26
W1

W2

W3

W4

W5

W6

W7

W8

W9
9 MEM_MA_ADD11 A11 CK0# MEM_MA_CLK0_N 9

Y1

Y2

Y3

Y4

Y5

Y6

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26
89 1 8

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26
AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9
9 MEM_MA_ADD12 A12 MEM_MA_BANK1 9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26
AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9
116 164 2 7

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26
AC1

AC2

AC3

AC4

AC5

AC6

AC7

AC8

AC9
9 MEM_MA_ADD13 A13 CK1 MEM_MA_CLK1_P 9 MEM_MA_BANK0 9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26
AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9
86 166 3 6

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25
AE2

AE3

AE4

AE5

AE6

AE7

AE8

AE9
9 MEM_MA_ADD14 A14 CK1# MEM_MA_CLK1_N 9 MEM_MA_ADD10 9

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24
AF4

AF5

AF6

AF7

AF8

AF9
9 MEM_MA_ADD15 84 A15 4 5 MEM_MA_WE# 9
85 A16/BA2 DM0 10 MEM_MA_DM0 9
9 MEM_MA_BANK2 26 MEM_MA_DM1 9 SRN47J-4-GP
DM1
9 MEM_MA_BANK0 107 52 MEM_MA_DM2 9 RN1304
BA0 DM2
9 MEM_MA_BANK1 106 BA1 DM3 67 MEM_MA_DM3 9 1 4 MEM_MA_ADD9 9
DM4 130 MEM_MA_DM4 9 2 3 MEM_MA_ADD12 9
DM5 147 MEM_MA_DM5 9
SRN47J-7-GP
9 MEM_MA_DATA0 5
7
DQ0 DM6 170
185
MEM_MA_DM6 9 X01 RN1308
9 MEM_MA_DATA1 DQ1 DM7 MEM_MA_DM7 9 03/31 modify
9 MEM_MA_DATA2 17 DQ2 1 4 MEM_MA_CKE0 9
1.Change DIMM SPD SMBus from Ch1 to Ch0
9 MEM_MA_DATA3 19 DQ3 2 3 MEM_MA_BANK2 9
9 MEM_MA_DATA4 4 DQ4 SDA 195 SMB_DATA_0 7,12,19,44
6 197 SRN47J-7-GP
9 MEM_MA_DATA5 DQ5 SCL SMB_CLK_0 7,12,19,44
9 MEM_MA_DATA6 14 RN1305
DQ6
9 MEM_MA_DATA7 16 DQ7 VDDSPD 199 +3.3V_RUN 1 8 MEM_MA_ADD7 9

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP
9 MEM_MA_DATA8 23 DQ8 2 7 MEM_MA_ADD6 9

C1301

C1302
25 198 DIMM1_SA0 R1301 1 2 10KR2J-3-GP 3 6
9 MEM_MA_DATA9 DQ9 SA0 MEM_MA_ADD4 9

1
35 200 DIMM1_SA1 R1302 1 2 10KR2J-3-GP 4 5
9 MEM_MA_DATA10 DQ10 SA1 MEM_MA_ADD2 9
37
9
9
MEM_MA_DATA11
MEM_MA_DATA12 20
DQ11
50
(A0) PARALLEL TERMINATION SRN47J-4-GP

2
DQ12 NC#50
9 MEM_MA_DATA13 22 69 RN1306
DQ13 NC#69
9 MEM_MA_DATA14 36 DQ14 NC#83 83 1 4 MEM_MA_ADD15 9
C
9 MEM_MA_DATA15 38 DQ15 NC#120 120 2 3 MEM_MA_CKE1 9 C
9 MEM_MA_DATA16 43 DQ16 NC#163/TEST 163 Put decap near power(0.9V) and pull-up resistor
45 +1.8V_SUS SRN47J-7-GP
REVERSE TYPE
9 MEM_MA_DATA17 DQ17
9 MEM_MA_DATA18 55 RN1309
DQ18
9 MEM_MA_DATA19 57 DQ19 VDD 81 1 4 MEM_MA_ADD14 9
9 MEM_MA_DATA20 44 DQ20 VDD 82 2 3 MEM_MA_ADD11 9
9 MEM_MA_DATA21 46 DQ21 VDD 87
56 88 SRN47J-7-GP
9 MEM_MA_DATA22 DQ22 VDD
9 MEM_MA_DATA23 58 95 PLACE CLOSE TO PROCESSOR RN1307
DQ23 VDD
9 MEM_MA_DATA24 61 DQ24 VDD 96 WITHIN 1.5 INCH Do not share the Term resistor between 1 8 MEM_MA_RAS# 9
9 MEM_MA_DATA25 63 103 2 7 MEM_MA0_CS#0 9
73
DQ25 VDD
104 MEM_MA_CLK0_P the DDR addess and Control Signals. 3 6
9 MEM_MA_DATA26 DQ26 VDD MEM_MA0_ODT0 9

SC1D5P50V2CN-1GP
9 MEM_MA_DATA27 75 DQ27 VDD 111 4 5 MEM_MA_ADD13 9
9 MEM_MA_DATA28 62 DQ28 VDD 112

C1303
9 MEM_MA_DATA29 64 117 SRN47J-4-GP
DQ29 VDD

1
9 MEM_MA_DATA30 74 DQ30 VDD 118
9 MEM_MA_DATA31 76 DQ31
9 MEM_MA_DATA32 123 3

2
DQ32 VSS
9 MEM_MA_DATA33 125 DQ33 VSS 8
9 MEM_MA_DATA34 135 DQ34 VSS 9
137 12 MEM_MA_CLK0_N
9 MEM_MA_DATA35 DQ35 VSS
9 MEM_MA_DATA36 124 DQ36 VSS 15
126 18 MEM_MA_CLK1_P
9 MEM_MA_DATA37 DQ37 VSS
Decoupling Capacitor
SC1D5P50V2CN-1GP

9 MEM_MA_DATA38 134 DQ38 VSS 21

9 MEM_MA_DATA39 136 DQ39 VSS 24
C1304

9 MEM_MA_DATA40 141 DQ40 VSS 27

1

143 28
9
9
9
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
151
153
DQ41
DQ42
VSS
VSS 33
34
Place these Caps near DM1
2

DQ43 VSS +1.8V_SUS

9 MEM_MA_DATA44 140 DQ44 VSS 39
9 MEM_MA_DATA45 142 DQ45 VSS 40
152 41 MEM_MA_CLK1_N
9 MEM_MA_DATA46 DQ46 VSS

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SCD01U50V2KX-1GP

SC180P50V2JN-1GP

SCD01U50V2KX-1GP

SC180P50V2JN-1GP
9 MEM_MA_DATA47 154 DQ47 VSS 42
9 MEM_MA_DATA48 157 DQ48 VSS 47

C1305

C1306

C1307

C1308

C1309

C1310

C1311

C1312

C1313
9 MEM_MA_DATA49 159 DQ49 VSS 48

1
9 MEM_MA_DATA50 173 DQ50 VSS 53
175 54 +0.9V_VTT +1.8V_SUS
9 MEM_MA_DATA51 DQ51 VSS
158 59 C1314 C1315

DDR_VREF
9 MEM_MA_DATA52

2
DQ52 VSS
9 MEM_MA_DATA53 160 DQ53 VSS 60 1 2 1 2
9 MEM_MA_DATA54 174 DQ54 VSS 65
176 66 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
9 MEM_MA_DATA55 DQ55 VSS
B 179 71 C1338 C1316 B
9 MEM_MA_DATA56 DQ56 VSS
9 MEM_MA_DATA57 181 DQ57 VSS 72 1 2 1 2
+1.8V_SUS +VREF_DDR_MEM +V_DDR_VREF_M
9 MEM_MA_DATA58 189 DQ58 VSS 77
191 78 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
9 MEM_MA_DATA59 DQ59 VSS
180 121 C1339 C1317
9 MEM_MA_DATA60 DQ60 VSS
SCD1U10V2KX-4GP

9 MEM_MA_DATA61 182 DQ61 VSS 122 1 2 1 2

1
1KR2F-3-GP

9 MEM_MA_DATA62 192 DQ62 VSS 127

R1303

C1318

194 128 SCD1U10V2KX-4GP SCD1U10V2KX-4GP

1

9 MEM_MA_DATA63 DQ63 VSS

132 C1340 C1319
VSS
9 MEM_MA_DQS0_N 11 DQS0# VSS 133 Layout Note: 1 2 1 2
29 138
2

9 MEM_MA_DQS1_N Place one cap close to every 2 pullup

2

DQS1# VSS R1304 SCD1U10V2KX-4GP SCD1U10V2KX-4GP

9 MEM_MA_DQS2_N 49 DQS2# VSS 139
+0.9V_VTT C1341
9 MEM_MA_DQS3_N 68 DQS3# VSS 144 1 DY 2 resistors terminated to +0.9V_VTT
SCD1U10V2KX-4GP

SC1KP50V2KX-1GP

9 MEM_MA_DQS4_N 129 DQS4# VSS 145 1 2

1
1KR2F-3-GP

C1320

C1321

146 149 Do Not Stuff

9 MEM_MA_DQS5_N DQS5# VSS
1

1
R1305

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
167 150 SCD1U10V2KX-4GP
9 MEM_MA_DQS6_N DQS6# VSS
186 155 C1342
9 MEM_MA_DQS7_N DQS7# VSS

C1322

C1323

C1324

C1325

C1326

C1327

C1328

C1329

C1330

C1331

C1332

C1333

C1334

C1335
156 1 2
2

VSS

1
9 MEM_MA_DQS0_P 13 161
2

DQS0 VSS SCD1U10V2KX-4GP

9 MEM_MA_DQS1_P 31 DQS1 VSS 162
51 165 C1343
9 MEM_MA_DQS2_P

2
DQS2 VSS
70 168 1 2
9
9
MEM_MA_DQS3_P
MEM_MA_DQS4_P 131
DQS3
DQS4
VSS
VSS 171 LAYOUT: Locate close to DIMM
148 172 SCD1U10V2KX-4GP
9 MEM_MA_DQS5_P DQS5 VSS
169 177 C1344
9 MEM_MA_DQS6_P DQS6 VSS
9 MEM_MA_DQS7_P 188 DQS7 VSS 178 1 2
VSS 183
114 184 SCD1U10V2KX-4GP
9 MEM_MA0_ODT0 OTD0 VSS
119 187 C1345
9 MEM_MA0_ODT1 OTD1 VSS
VSS 190 1 2
+VREF_DDR_MEM 1 VREF VSS 193
SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

2 196 SCD1U10V2KX-4GP
VSS VSS
C1336

C1337
1

202 GND GND 201

MH1 MH2
2

MH1 MH2

DDR2-200P-21-GP-U1

A
Place C2.2uF and 0.1uF < HI 9.2mm A
500mils from DDR connector
1'nd:62.10017.A51
2'nd 62.10017.A61
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR_DIMM2
Size Document Number Rev
A2 A00
Riya Discrete
Date: Wednesday, August 26, 2009 Sheet 13 of 65
5 4 3 2 1
 5 4 3 2 1

U2A
8 HT_CPU_NB_CAD_H0 Y25 HT_RXCAD0P HT_TXCAD0P D24 HT_NB_CPU_CAD_H0 8
Y24 PART 1 OF 6 D25
SSID = N.B 8
8
8
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
V22
V23
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
E24
E25
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
8
8
8
8 HT_CPU_NB_CAD_H2 V25 HT_RXCAD2P HT_TXCAD2P F24 HT_NB_CPU_CAD_H2 8
8 HT_CPU_NB_CAD_L2 V24 HT_RXCAD2N HT_TXCAD2N F25 HT_NB_CPU_CAD_L2 8
RS780M A13 : 71.RS780.M11 8
8
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
U24
U25
HT_RXCAD3P
HT_RXCAD3N
HT_TXCAD3P
HT_TXCAD3N
F23
F22
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
8
8
8 HT_CPU_NB_CAD_H4 T25 HT_RXCAD4P HT_TXCAD4P H23 HT_NB_CPU_CAD_H4 8
8 HT_CPU_NB_CAD_L4 T24 HT_RXCAD4N HT_TXCAD4N H22 HT_NB_CPU_CAD_L4 8

HYPER TRANSPORT CPU I/F

8 HT_CPU_NB_CAD_H5 P22 HT_RXCAD5P HT_TXCAD5P J25 HT_NB_CPU_CAD_H5 8
8 HT_CPU_NB_CAD_L5 P23 HT_RXCAD5N HT_TXCAD5N J24 HT_NB_CPU_CAD_L5 8
8 HT_CPU_NB_CAD_H6 P25 HT_RXCAD6P HT_TXCAD6P K24 HT_NB_CPU_CAD_H6 8
D D
8 HT_CPU_NB_CAD_L6 P24 HT_RXCAD6N HT_TXCAD6N K25 HT_NB_CPU_CAD_L6 8
8 HT_CPU_NB_CAD_H7 N24 HT_RXCAD7P HT_TXCAD7P K23 HT_NB_CPU_CAD_H7 8
8 HT_CPU_NB_CAD_L7 N25 HT_RXCAD7N HT_TXCAD7N K22 HT_NB_CPU_CAD_L7 8

8 HT_CPU_NB_CAD_H8 AC24 HT_RXCAD8P HT_TXCAD8P F21 HT_NB_CPU_CAD_H8 8

8 HT_CPU_NB_CAD_L8 AC25 HT_RXCAD8N HT_TXCAD8N G21 HT_NB_CPU_CAD_L8 8
8 HT_CPU_NB_CAD_H9 AB25 HT_RXCAD9P HT_TXCAD9P G20 HT_NB_CPU_CAD_H9 8
8 HT_CPU_NB_CAD_L9 AB24 HT_RXCAD9N HT_TXCAD9N H21 HT_NB_CPU_CAD_L9 8
8 HT_CPU_NB_CAD_H10 AA24 HT_RXCAD10P HT_TXCAD10P J20 HT_NB_CPU_CAD_H10 8
8 HT_CPU_NB_CAD_L10 AA25 HT_RXCAD10N HT_TXCAD10N J21 HT_NB_CPU_CAD_L10 8
8 HT_CPU_NB_CAD_H11 Y22 HT_RXCAD11P HT_TXCAD11P J18 HT_NB_CPU_CAD_H11 8
8 HT_CPU_NB_CAD_L11 Y23 HT_RXCAD11N HT_TXCAD11N K17 HT_NB_CPU_CAD_L11 8
8 HT_CPU_NB_CAD_H12 W21 HT_RXCAD12P HT_TXCAD12P L19 HT_NB_CPU_CAD_H12 8
8 HT_CPU_NB_CAD_L12 W20 HT_RXCAD12N HT_TXCAD12N J19 HT_NB_CPU_CAD_L12 8
8 HT_CPU_NB_CAD_H13 V21 HT_RXCAD13P HT_TXCAD13P M19 HT_NB_CPU_CAD_H13 8
8 HT_CPU_NB_CAD_L13 V20 HT_RXCAD13N HT_TXCAD13N L18 HT_NB_CPU_CAD_L13 8
8 HT_CPU_NB_CAD_H14 U20 HT_RXCAD14P HT_TXCAD14P M21 HT_NB_CPU_CAD_H14 8
8 HT_CPU_NB_CAD_L14 U21 HT_RXCAD14N HT_TXCAD14N P21 HT_NB_CPU_CAD_L14 8
8 HT_CPU_NB_CAD_H15 U19 HT_RXCAD15P HT_TXCAD15P P18 HT_NB_CPU_CAD_H15 8
8 HT_CPU_NB_CAD_L15 U18 HT_RXCAD15N HT_TXCAD15N M18 HT_NB_CPU_CAD_L15 8

8 HT_CPU_NB_CLK_H0 T22 HT_RXCLK0P HT_TXCLK0P H24 HT_NB_CPU_CLK_H0 8

8 HT_CPU_NB_CLK_L0 T23 HT_RXCLK0N HT_TXCLK0N H25 HT_NB_CPU_CLK_L0 8
8 HT_CPU_NB_CLK_H1 AB23 HT_RXCLK1P HT_TXCLK1P L21 HT_NB_CPU_CLK_H1 8
8 HT_CPU_NB_CLK_L1 AA22 HT_RXCLK1N HT_TXCLK1N L20 HT_NB_CPU_CLK_L1 8

8 HT_CPU_NB_CTL_H0 M22 HT_RXCTL0P HT_TXCTL0P M24 HT_NB_CPU_CTL_H0 8

8 HT_CPU_NB_CTL_L0 M23 HT_RXCTL0N HT_TXCTL0N M25 HT_NB_CPU_CTL_L0 8
8 HT_CPU_NB_CTL_H1 R21 HT_RXCTL1P HT_TXCTL1P P19 HT_NB_CPU_CTL_H1 8
C 8 HT_CPU_NB_CTL_L1 R20 HT_RXCTL1N HT_TXCTL1N R18 HT_NB_CPU_CTL_L1 8 C

R1401 1 2 301R2F-GP HT_RXCALP C23 B24 HT_TXCALP R1402 1 2 301R2F-GP

HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
A24 HT_RXCALN HT_TXCALN B25
Place < 100mils from pin C23 and A24 Place < 100mils from pin B25 and B24
RS780M-GP-U2
N131K

U2B
PCIE_NRX_GTX_P0 D4 A5 PCIE_NTX_GRX_C_P0 C1401 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P0
PCIE_NRX_GTX_N0 GFX_RX0P GFX_TX0P PCIE_NTX_GRX_C_N0 C1402 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N0 PCIE_NTX_GRX_P[0..15]
PCIE_NRX_GTX_P1
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
PCIE_NTX_GRX_C_P1 C1403 1
2
SCD1U16V2KX-3GP PCIE_NTX_GRX_P1 PCIE_NTX_GRX_N[0..15] PCIE_NTX_GRX_P[0..15] 54
A3 GFX_RX1P GFX_TX1P A4 2 PCIE_NTX_GRX_N[0..15] 54
PCIE_NRX_GTX_N1 B3 B4 PCIE_NTX_GRX_C_N1 C1404 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_N1
PCIE_NRX_GTX_P2 GFX_RX1N GFX_TX1N PCIE_NTX_GRX_C_P2 C1405 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_P2 PCIE_NRX_GTX_P[0..15]
C2 GFX_RX2P GFX_TX2P C3 2 PCIE_NRX_GTX_P[0..15] 54
PCIE_NRX_GTX_N2 C1 B2 PCIE_NTX_GRX_C_N2 C1406 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_N2 PCIE_NRX_GTX_N[0..15]
GFX_RX2N GFX_TX2N PCIE_NRX_GTX_N[0..15] 54
PCIE_NRX_GTX_P3 E5 D1 PCIE_NTX_GRX_C_P3 C1407 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P3
PCIE_NRX_GTX_N3 GFX_RX3P GFX_TX3P PCIE_NTX_GRX_C_N3 C1408 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N3
F5 GFX_RX3N GFX_TX3N D2 2
PCIE_NRX_GTX_P4 G5 E2 PCIE_NTX_GRX_C_P4 C1409 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P4
PCIE_NRX_GTX_N4 GFX_RX4P GFX_TX4P PCIE_NTX_GRX_C_N4 C1410 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N4
G6 GFX_RX4N GFX_TX4N E1 2
PCIE_NRX_GTX_P5 H5 F4 PCIE_NTX_GRX_C_P5 C1411 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P5
PCIE_NRX_GTX_N5 GFX_RX5P GFX_TX5P PCIE_NTX_GRX_C_N5 C1412 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N5
H6 GFX_RX5N GFX_TX5N F3 2
PCIE_NRX_GTX_P6 J6 F1 PCIE_NTX_GRX_C_P6 C1413 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P6
PCIE_NRX_GTX_N6 GFX_RX6P GFX_TX6P PCIE_NTX_GRX_C_N6 C1414 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N6
J5 GFX_RX6N GFX_TX6N F2 2
PCIE_NRX_GTX_P7 J7 H4 PCIE_NTX_GRX_C_P7 C1415 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P7
PCIE_NRX_GTX_N7 GFX_RX7P GFX_TX7P PCIE_NTX_GRX_C_N7 C1416 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N7
J8 GFX_RX7N GFX_TX7N H3 2
PCIE_NRX_GTX_P8 L5 H1 PCIE_NTX_GRX_C_P8 C1417 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P8
PCIE_NRX_GTX_N8 GFX_RX8P GFX_TX8P PCIE_NTX_GRX_C_N8 C1418 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N8
L6 GFX_RX8N GFX_TX8N H2 2
PCIE_NRX_GTX_P9 M8 J2 PCIE_NTX_GRX_C_P9 C1419 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P9
PCIE_NRX_GTX_N9 GFX_RX9P GFX_TX9P PCIE_NTX_GRX_C_N9 C1420 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N9
L8 GFX_RX9N GFX_TX9N J1 2
PCIE I/F GFX

PCIE_NRX_GTX_P10 P7 K4 PCIE_NTX_GRX_C_P10 C1421 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P10

PCIE_NRX_GTX_N10 GFX_RX10P GFX_TX10P PCIE_NTX_GRX_C_N10 C1422 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N10
B M7 GFX_RX10N GFX_TX10N K3 2 B
PCIE_NRX_GTX_P11 P5 K1 PCIE_NTX_GRX_C_P11 C1423 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P11
PCIE_NRX_GTX_N11 GFX_RX11P GFX_TX11P PCIE_NTX_GRX_C_N11 C1424 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N11
M5 GFX_RX11N GFX_TX11N K2 2
PCIE_NRX_GTX_P12 R8 M4 PCIE_NTX_GRX_C_P12 C1425 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P12
PCIE_NRX_GTX_N12 GFX_RX12P GFX_TX12P PCIE_NTX_GRX_C_N12 C1426 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N12
P8 GFX_RX12N GFX_TX12N M3 2
PCIE_NRX_GTX_P13 R6 M1 PCIE_NTX_GRX_C_P13 C1427 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P13
PCIE_NRX_GTX_N13 GFX_RX13P GFX_TX13P PCIE_NTX_GRX_C_N13 C1428 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N13
R5 GFX_RX13N GFX_TX13N M2 2
PCIE_NRX_GTX_P14 P4 N2 PCIE_NTX_GRX_C_P14 C1429 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P14
PCIE_NRX_GTX_N14 GFX_RX14P GFX_TX14P PCIE_NTX_GRX_C_N14 C1430 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N14
P3 GFX_RX14N GFX_TX14N N1 2
PCIE_NRX_GTX_P15 T4 P1 PCIE_NTX_GRX_C_P15 C1431 1 2 SCD1U16V2KX-3GP PCIE_NTX_GRX_P15
PCIE_NRX_GTX_N15 GFX_RX15P GFX_TX15P PCIE_NTX_GRX_C_N15 C1432 1 SCD1U16V2KX-3GP PCIE_NTX_GRX_N15
T3 GFX_RX15N GFX_TX15N P2 2

AE3 GPP_RX0P GPP_TX0P AC1

AD4 GPP_RX0N GPP_TX0N AC2
26 PCIE_NRX_LANTX_P1 AE2 AB4 PCIE_NTX_LANRX_C_P1 C1433 1 2 SCD1U16V2KX-3GP
GPP_RX1P GPP_TX1P PCIE_NTX_LANRX_P1 26
PCIE_NTX_LANRX_C_N1 C1434 1 SCD1U16V2KX-3GP
LAN 26 PCIE_NRX_LANTX_N1 AD3
AD1
GPP_RX1N GPP_TX1N AB3
AA2 PCIE_NTX_MINRX_C_P2 C1435 1
2
2 SCD1U16V2KX-3GP
PCIE_NTX_LANRX_N1 26 LAN
44 PCIE_NRX_MINTX_P2 GPP_RX2P GPP_TX2P PCIE_NTX_MINRX_P2 44
PCIE_NTX_MINRX_C_N2 C1436 1 SCD1U16V2KX-3GP
WLAN 44 PCIE_NRX_MINTX_N2 AD2
V5
GPP_RX2N PCIE I/F GPP GPP_TX2N AA1
Y1 PCIE_NTX_EXPRX_C_P3 C1437 1
2
2 SCD1U16V2KX-3GP
PCIE_NTX_MINRX_N2 44 WLAN
51 PCIE_NRX_EXPTX_P3 GPP_RX3P GPP_TX3P PCIE_NTX_EXPRX_P3 51
PCIE_NTX_EXPRX_C_N3 C1438 1 SCD1U16V2KX-3GP
EXP 51 PCIE_NRX_EXPTX_N3 W6
U5
GPP_RX3N GPP_TX3N Y2
Y4
2 PCIE_NTX_EXPRX_N3 51 EXP
GPP_RX4P GPP_TX4P
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2

18 ALINK_NBRX_SBTX_P0 AA8 AD7 ALINK_NBTX_SBRX_C_P0 C1439 1 2 SCD1U16V2KX-3GP

SB_RX0P SB_TX0P ALINK_NBTX_SBRX_P0 18
18 ALINK_NBRX_SBTX_N0 Y8 AE7 ALINK_NBTX_SBRX_C_N0 C1440 1 2 SCD1U16V2KX-3GP
SB_RX0N SB_TX0N ALINK_NBTX_SBRX_N0 18
18 ALINK_NBRX_SBTX_P1 AA7 AE6 ALINK_NBTX_SBRX_C_P1 C1441 1 2 SCD1U16V2KX-3GP
SB_RX1P SB_TX1P ALINK_NBTX_SBRX_P1 18
ALINK_NBTX_SBRX_C_N1 C1442 1 SCD1U16V2KX-3GP
A-LINK 18
18
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
Y7
AA5
SB_RX1N
SB_RX2P PCIE I/F SB
SB_TX1N
SB_TX2P
AD6
AB6 ALINK_NBTX_SBRX_C_P2 C1443 1
2
2 SCD1U16V2KX-3GP
ALINK_NBTX_SBRX_N1
ALINK_NBTX_SBRX_P2
18
18
A-LINK
A ALINK_NBTX_SBRX_C_N2 C1444 1 SCD1U16V2KX-3GP A
18 ALINK_NBRX_SBTX_N2 AA6 SB_RX2N SB_TX2N AC6 2 ALINK_NBTX_SBRX_N2 18 Main Source
18 ALINK_NBRX_SBTX_P3 W5 AD5 ALINK_NBTX_SBRX_C_P3 C1445 1 2 SCD1U16V2KX-3GP
SB_RX3P SB_TX3P ALINK_NBTX_SBRX_P3 18
18 ALINK_NBRX_SBTX_N3 Y5 AE5 ALINK_NBTX_SBRX_C_N3 C1446 1 2 SCD1U16V2KX-3GP
SB_RX3N SB_TX3N ALINK_NBTX_SBRX_N3 18

PCE_CALRP AC8 PCE_PCAL R1403 1 2 1K27R2F-L-GP

Wistron Corporation
AB8 PCE_NCAL R1404 1 2 2KR2F-3-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
PCE_CALRN +1.1V_RUN Taipei Hsien 221, Taiwan, R.O.C.
RS780M-GP-U2
N131K Place < 100mils from pin AC8 and AB8 Title
ATi-RS780M_HT LINK&PCIe(1/4)
Size Document Number Rev
Custom
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 14 of 65
5 4 3 2 1
 5 4 3 2 1

+3.3V_RUN STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS780M use DAC_VSYNC)

Enables debug bus access through memory I/O pads and GPIOs.
SSID = N.B 0 : Enable * 1 : Disable

1
3KR2J-2-GP

3KR2J-2-GP
R1502

R1503
SIDE_PORT_EN# ( RS780M use DAC_HSYNC)
0 : Available * 1 : Not available
+1.8V_RUN 15 mil

2
L1503 NB_VGA_VSYNC LOAD_EEPROM_STRAPS#(RS780M use SUS_STAT#)
1 2 +1.8V_VDDA18HTPLL NB_VGA_HSYNC Selects Loading of STRAPS From EEPROM

SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP
*1 : Bypass the loading of EEPROM straps and use Hardware Default Values

1
Do Not Stuff

Do Not Stuff
BLM15AG221SS1D-GP

1
0 : I2C Master can load strap values from EEPROM if connected,

C1504

C1505

R1504

R1505
D 220 ohm 300mA D

DY DY or use default values if not connected

2

2
*DEFAULT

2
+1.8V_RUN
15 mil
L1504 U2C
1 2 +1.8V_VDDA18PCIEPLL F12 A22
AVDD1 TXOUT_L0P
SC2D2U6D3V3KX-GP

SCD1U10V2KX-4GP

E12 AVDD2 PART 3 OF 6 TXOUT_L0N B22

BLM15AG221SS1D-GP F14 A21
AVDDDI TXOUT_L1P
1

1
C1506

C1507

220 ohm 300mA G15 AVSSDI TXOUT_L1N B21

H15 AVDDQ TXOUT_L2P B20
H14 A20
2

AVSSQ TXOUT_L2N
TXOUT_L3P A19
E17 C_Pr TXOUT_L3N B19
F17 Y
F15 COMP_Pb TXOUT_U0P B18

CRT/TVOUT
TXOUT_U0N A18
Layout Note G18 RED TXOUT_U1P A17
G17 REDb TXOUT_U1N B17
E18 GREEN TXOUT_U2P D20
F18 GREENb TXOUT_U2N D21
E19 BLUE TXOUT_U3P D18
F19 BLUEb TXOUT_U3N D19

NB_VGA_HSYNC A11 B16

NB_VGA_VSYNC DAC_HSYNC TXCLK_LP
B11 DAC_VSYNC TXCLK_LN A16
C A00 F8 DAC_SCL TXCLK_UP D16 C
E8 DAC_SDA TXCLK_UN D17
8/22 R1501
Change R1509 from 0 ohm to short pad
X01 1 2DAC_RSET G14 DAC_RSET
715R2F-GP A13
04/17 Del VDDLTP18
A12 PLLVDD VSSLTP18 B13
+3.3V_RUN 1.Del R1508, No reserve
D14 PLLVDD18
B12 PLLVSS VDDLT18_1 A15
VDDLT18_2 B15
+1.8V_VDDA18HTPLL H17 A14

LVTM
VDDA18HTPLL VDDLT33_1
1

1
Do Not Stuff

Do Not Stuff

B14

PLL PWR
VDDLT33_2
R1506

R1507

+1.8V_VDDA18PCIEPLL D7 VDDA18PCIEPLL1
DY DY E7 VDDA18PCIEPLL2 VSSLT1 C14
D15
SYSREST# VSSLT2
18 PLT_RST# 1R1509 2 D8 C16
2

Do Not Stuff SYSRESET# VSSLT3

30 1D8_NB_PWRGD A10 POWERGOOD VSSLT4 C18
R1510 1 2 Do Not Stuff NB_LDT_STOP# C10 C20
10 CPU_R_LDT_STOP# LDTSTOP# VSSLT5
R1511 1 2 Do Not Stuff NB_ALLOW_LDTSTOP C12 E20
10,18 ALLOW_LDTSTOP ALLOW_LDTSTOP VSSLT6
VSSLT7 C22
C25

CLOCKs PM
7 CLK_NBHT_CLK HT_REFCLKP
7 CLK_NBHT_CLK# C24 HT_REFCLKN
+1.1V_RUN
R1512 E11
7 NB_14M_CLK REFCLK_P/OSCIN
NB_REFCLK_N
1
DY 2 R1513
F11 REFCLK_N LVDS_DIGON E9
X01 Do Not Stuff LVDS_BLON F7
04/14 Del
1
DY 2 7 NB_GFX_CLK T2
T1
GFX_REFCLKP LVDS_ENA_BL G12
1.Del R1510 ,reserve closed-gap. 7 NB_GFX_CLK# GFX_REFCLKN
Do Not Stuff
Del R1511 ,reserve closed-gap.
7 NB_GPP_CLK U1 GPP_REFCLKP
B B
7 NB_GPP_CLK# U2 GPP_REFCLKN

7 NB_GPPSB_CLK V4 GPPSB_REFCLKP
7 NB_GPPSB_CLK# V3 GPPSB_REFCLKN
B9 I2C_CLK +3.3V_RUN
TP_NB_DDC_DATA0
A9
B8
I2C_DATA MIS. TMDS_HPD D9
D10
TP_NB_DDC_CLK0 DDC_DATA0/AUX0N HPD R1514
A8 DDC_CLK0/AUX0P
+3.3V_RUN TP_NB_DDC_CLK1 B7 D12 NB_SUS_STAT# 1 2
TP_NB_DDC_DATA1 DDC_CLK1/AUX1P SUS_STAT#
A7 DDC_DATA1/AUX1N
GPIO MODE R1515 AE8 3KR2J-2-GP
STRP_DATA THERMALDIODE_P
STRP_DATA VCC_NB
1
DY 2 B10 STRP_DATA THERMALDIODE_N AD8

Do Not Stuff TP_NB_RESERVED G11 D13 TESTMODE_NB

R1516 RESERVED TESTMODE
* 1 1.0V

1
1K8R2F-GP
1 2 RS780_AUX_CAL C8
AUX_CAL

R1517
0 1.1V
150R2F-1-GP RS780M-GP-U2
*DEFAULT N131K

2
A Main Source A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
TP1501 1 TP_NB_DDC_DATA0
TP1502 1 TP_NB_DDC_CLK0 Title
TP1503
TP1504
1
1
TP_NB_DDC_CLK1
TP_NB_DDC_DATA1
ATi-RS780M_LVDS&CRT_(2/4)
TP1505 1 TP_NB_RESERVED Size Document Number Rev
A3
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 15 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = N.B

D D

U2D
PAR 4 OF 6
AB12 MEM_A0 MEM_DQ0/DVO_VSYNC AA18
AE16 MEM_A1 MEM_DQ1/DVO_HSYNC AA20
V11 MEM_A2 MEM_DQ2/DVO_DE AA19
AE15 MEM_A3 MEM_DQ3/DVO_D0 Y19
AA12 MEM_A4 MEM_DQ4 V17
AB16 MEM_A5 MEM_DQ5/DVO_D1 AA17
AB14 MEM_A6 MEM_DQ6/DVO_D2 AA15
AD14 MEM_A7 MEM_DQ7/DVO_D4 Y15
AD13 MEM_A8 MEM_DQ8/DVO_D3 AC20
AD15 MEM_A9 MEM_DQ9/DVO_D5 AD19

SBD_MEM/DVO_I/F
AC16 MEM_A10 MEM_DQ10/DVO_D6 AE22
AE13 MEM_A11 MEM_DQ11/DVO_D7 AC18
AC14 MEM_A12 MEM_DQ12 AB20
Y14 MEM_A13 MEM_DQ13/DVO_D9 AD22
MEM_DQ14/DVO_D10 AC22
AD16 MEM_BA0 MEM_DQ15/DVO_D11 AD21
AE17 MEM_BA1
AD17 MEM_BA2 MEM_DQS0P/DVO_IDCKP Y17
MEM_DQS0N/DVO_IDCKN W18
W12 MEM_RAS# MEM_DQS1P AD20
Y12 MEM_CAS# MEM_DQS1N AE21
C AD18 C
MEM_WE#
AB13 MEM_CS# MEM_DM0 W17
+1.8V_RUN +1.1V_RUN
AB18 MEM_CKE MEM_DM1/DVO_D8 AE19
V14 MEM_ODT
IOPLLVDD18 AE23
V15 MEM_CKP IOPLLVDD AE24
W14 MEM_CKN
IOPLLVSS AD23
AE12 MEM_COMPP
AD12 MEM_COMPN MEM_VREF AE18

RS780M-GP-U2
N131K

B B

A Main Source A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ATi-RS780M_SidePort_(3/4)
Size Document Number Rev
A3
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 16 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = N.B

D D

+1.1V_RUN
L1701 1.1V(0.593A) for VDDHT
1 2
40 mils +1.1V_RUN_VDDHT U2F
SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
A25 VSSAHT1 VSSAPCIE1 A2
BLM21PG221SN-1GP +1.1V_RUN D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
1

1
C1701

C1705

C1702

C1706
220 ohm @ 100MHz,2A U2E 1.1V(1.99A) for VDDPCIE L1702 E22 VSSAHT3 VSSAPCIE3 D3

J17 A6 +1.1V_RUN_VDDPCIE
130 mils 1 2
G22
G24
VSSAHT4 VSSAPCIE4 D5
E4
2

2
VDDHT_1 VDDPCIE_1 VSSAHT5 VSSAPCIE5

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC4D7U6D3V3KX-GP
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6
HCB2012KF-600T30-GP
G25 VSSAHT6 VSSAPCIE6 G1
L16 VDDHT_3 VDDPCIE_3 C6 H19 VSSAHT7 VSSAPCIE7 G2

1
C1707

C1704

C1708

C1709

C1710
M16 VDDHT_4 VDDPCIE_4 D6 J22 VSSAHT8 VSSAPCIE8 G4

+1.1V_RUN
P16 VDDHT_5 VDDPCIE_5 E6 60 ohm @ 100MHz, 3A L17 VSSAHT9 VSSAPCIE9 H7
R16 VDDHT_6 VDDPCIE_6 F6 L22 J4

2
VSSAHT10 VSSAPCIE10
L1703 1.1V(0.645A) for VDDHTRX T16 VDDHT_7 VDDPCIE_7 G7 L24 VSSAHT11 VSSAPCIE11 R7

1 2
40 mils +1.1V_RUN_VDDHTRX H18
VDDPCIE_8 H8
J9
L25
M20
VSSAHT12 VSSAPCIE12 L1
L2
VDDHTRX_1 VDDPCIE_9 VSSAHT13 VSSAPCIE13
SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

G19 VDDHTRX_2 VDDPCIE_10 K9 N22 VSSAHT14 VSSAPCIE14 L4

BLM21PG221SN-1GP F20 M9 P20 L7
VDDHTRX_3 VDDPCIE_11 VSSAHT15 VSSAPCIE15
1

1
C1711

C1703

C1712

C1713

220 ohm @ 100MHz,2A E21 VDDHTRX_4 VDDPCIE_12 L9 R19 VSSAHT16 VSSAPCIE16 M6

D22 VDDHTRX_5 VDDPCIE_13 P9 R22 VSSAHT17 VSSAPCIE17 N4
B23 R9 R24 P6
2

C VDDHTRX_6 VDDPCIE_14 VSSAHT18 VSSAPCIE18 C

A23 VDDHTRX_7 VDDPCIE_15 T9
V9
+NB_VCORE R25
H20
VSSAHT19 VSSAPCIE19 R1
R2
VDDPCIE_16 +1.1V_RUN VSSAHT20 VSSAPCIE20
AE25 VDDHTTX_1 VDDPCIE_17 U9
1.1V(9.33A) for VDDC U22 VSSAHT21 VSSAPCIE21 R4

+1.2V_RUN
AD24 VDDHTTX_2 380 mils V19 VSSAHT22 VSSAPCIE22 V7

GROUND
1.2V(0.391A) for VDDHTTX AC23 VDDHTTX_3 VDDC_1 K12 W22 VSSAHT23 VSSAPCIE23 U4

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
L1704
1 2
20 mils +1.2V_RUN_VDDHTTX
AB22
AA21
VDDHTTX_4 VDDC_2 J14
U16
W24
W25
VSSAHT24 VSSAPCIE24 V8
V6
VDDHTTX_5 VDDC_3 VSSAHT25 VSSAPCIE25

1
SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C1719

C1720

C1721

C1722

C1723

C1724

C1725

C1726

C1727
Y20 VDDHTTX_6 VDDC_4 J11 Y21 VSSAHT26 VSSAPCIE26 W1
BLM21PG221SN-1GP W19 K15 AD25 W2
VDDHTTX_7 VDDC_5 VSSAHT27 VSSAPCIE27
1

1
C1714

C1715

C1716

C1717

C1718

220 ohm @ 100MHz,2A V18 VDDHTTX_8 VDDC_6 M12 W4

2
VSSAPCIE28
U17 L14 L12 W7

POWER
VDDHTTX_9 VDDC_7 VSS11 VSSAPCIE29
T17 L11 M14 W8
2

VDDHTTX_10 VDDC_8 VSS12 VSSAPCIE30

R17 VDDHTTX_11 VDDC_9 M13 N13 VSS13 VSSAPCIE31 Y6
P17 VDDHTTX_12 VDDC_10 M15 P12 VSS14 VSSAPCIE32 AA4
M17 VDDHTTX_13 VDDC_11 N12 P15 VSS15 VSSAPCIE33 AB5
+1.8V_RUN N14 R11 AB1
VDDC_12 VSS16 VSSAPCIE34
L1705 1.8V(0.441A) for VDDA18PCIE J10 VDDA18PCIE_1 VDDC_13 P11 R14 VSS17 VSSAPCIE35 AB7

1 2
25 mils +1.8V_RUN_VDDA18PCIE
P10
K10
VDDA18PCIE_2 VDDC_14 P13
P14
T12
U14
VSS18 VSSAPCIE36 AC3
AC4
VDDA18PCIE_3 VDDC_15 VSS19 VSSAPCIE37
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

M10 VDDA18PCIE_4 VDDC_16 R12 U11 VSS20 VSSAPCIE38 AE1

BLM21PG221SN-1GP L10 R15 U15 AE4
VDDA18PCIE_5 VDDC_17 VSS21 VSSAPCIE39
1

1
C1728

C1729

C1730

C1731

C1732

C1733

220 ohm @ 100MHz,2A W9 VDDA18PCIE_6 VDDC_18 T11 V12 VSS22 VSSAPCIE40 AB2
H9 VDDA18PCIE_7 VDDC_19 T15 W11 VSS23
T10 U12 W15
2

VDDA18PCIE_8 VDDC_20 VSS24

R10 VDDA18PCIE_9 VDDC_21 T14 AC12 VSS25 VSS1 AE14
Y9 VDDA18PCIE_10 VDDC_22 J16 AA14 VSS26 VSS2 D11
AA9 VDDA18PCIE_11 Y18 VSS27 VSS3 G8
AB9 VDDA18PCIE_12 VDD_MEM1 AE10 AB11 VSS28 VSS4 E14
AD9 VDDA18PCIE_13 VDD_MEM2 AA11 AB15 VSS29 VSS5 E15
B B
AE9 VDDA18PCIE_14 VDD_MEM3 Y11 AB17 VSS30 VSS6 J15
+1.8V_RUN
1.8V(0.07mA) for VDD18 U10 VDDA18PCIE_15 VDD_MEM4 AD10 AB19 VSS31 VSS7 J12
15 mils F9
VDD_MEM5 AB10
AC10 +3.3V_RUN
AE20
AB21
VSS32 VSS8 K14
M11
VDD18_1 VDD_MEM6 VSS33 VSS9
SC1U6D3V2KX-GP

G9 VDD18_2 3.3V(5.84mA) for VDD33 K11 VSS34 VSS10 L15

AE11 VDD18_MEM1 VDD33_1 H11 15 mils
1
C1740

AD11 H12 RS780M-GP-U2

VDD18_MEM2 VDD33_2

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP
71.RS780.M02
RS780M-GP-U2
2

1
C1741

C1742
N131K Layout Note

2
Layout Note

A Main Source A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ATi-RS780M_PWR&GD_(4/4)
Size Document Number Rev
A3
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 17 of 65
5 4 3 2 1
 5 4 3 2 1

U3A
SSID = S.B 15 PLT_RST# R1801 1 233R2J-2-GP SB_A_RST# N2 A_RST#
SB700
PCICLK0 P4 KBC_PCI_R_CLK R1804 1 2 33R2J-2-GP KBC_PCI_CLK 27
Part 1 of 5 FWH_PCI_R_CLK R1805 1 Do Not Stuff
SB700 A12 : 71.SB700.M05 PCICLK1 P3
DY 2 FWH_PCI_CLK 44

PCI CLKS
C1801 1 2 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_P0 V23 P1
14 ALINK_NBRX_SBTX_P0 PCIE_TX0P PCICLK2 PCI_CLK2 22
C1802 1 2 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_N0 V22 P2
14 ALINK_NBRX_SBTX_N0 PCIE_TX0N PCICLK3 PCI_CLK3 22
C1803 1 2 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_P1 V24 T4 TP_PCI_CLK4
14 ALINK_NBRX_SBTX_P1 PCIE_TX1P PCICLK4
C1804 1 2 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_N1 V25 T3 TP_PCI_CLK5
14 ALINK_NBRX_SBTX_N1 PCIE_TX1N PCICLK5/GPIO41
C1805 1 2 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_P2 U25
14 ALINK_NBRX_SBTX_P2 PCIE_TX2P

Do Not Stuff

EC1802
Do Not Stuff

EC1801
C1806 1 2 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_N2 U24
14 ALINK_NBRX_SBTX_N2 PCIE_TX2N

1
C1807 1 2 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_P3 T23
14 ALINK_NBRX_SBTX_P3 PCIE_TX3P
C1808 1 SCD1U10V2KX-4GP ALINK_NBRX_SBTX_C_N3 TP_PCIRST#
D 14 ALINK_NBRX_SBTX_N3 2 T22 PCIE_TX3N PCIRST# N1
DY DY D

2
PCI EXPRESS INTERFACE
14 ALINK_NBTX_SBRX_P0 U22 PCIE_RX0P
14 ALINK_NBTX_SBRX_N0 U21 PCIE_RX0N AD0 U2
14 ALINK_NBTX_SBRX_P1 U19 PCIE_RX1P AD1 P7
14 ALINK_NBTX_SBRX_N1 V19 PCIE_RX1N AD2 V4
14 ALINK_NBTX_SBRX_P2 R20 PCIE_RX2P AD3 T1
14 ALINK_NBTX_SBRX_N2 R21 V3
14 ALINK_NBTX_SBRX_P3 R18
PCIE_RX2N
PCIE_RX3P
AD4
AD5 U1 PCI CLK EMI
14 ALINK_NBTX_SBRX_N3 R17 PCIE_RX3N AD6 V1
+1.2V_PCIE_VDDR V2
+1.2V_RUN +1.2V_RUN_PCIE_PVDD R1802 1 SB_PCIE_CALRP AD7
2 562R2F-GP T25 PCIE_CALRP AD8 T2
R1803 1 2 2K05R2F-GP SB_PCIE_CALRN T24 PCIE_CALRN AD9 W1
L1801 20mil Width T9
AD10
1 2 P24 PCIE_PVDD AD11 R6
SC2D2U6D3V3KX-GP

AD12 R7
BLM15AG221SS1D-GP P25 R5
PCIE_PVSS AD13
1
C1809

220 ohm 300mA AD14 U8

Place R <100mils form pins T25,T24 AD15 U5
Y7
2

AD16
AD17 W8
AD18 V9
AD19 Y8
AD20 AA8
AD21 Y4
AD22 Y3
Y2 TP_PCI_AD23
AD23
AD24 AA2 PCI_AD24 22
AD25 AB4 PCI_AD25 22
C N25 AA1 C
7 SB_PCIE_CLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 22
7 SB_PCIE_CLK# N24 PCIE_RCLKN/NB_LNK_CLKN AD27 AB3 PCI_AD27 22
AD28 AB2 PCI_AD28 22
K23 AC1 TP_PCI_AD29
NB_DISP_CLKP AD29 TP_PCI_AD30
K22 NB_DISP_CLKN AD30 AC2

PCI INTERFACE
AD31 AD1
M24 NB_HT_CLKP CBE0# W2
M25 NB_HT_CLKN CBE1# U7
CBE2# AA7 SB TYPE RN1801
P17 CPU_HT_CLKP CBE3# Y1
M18 CPU_HT_CLKN FRAME# AA6
W5
*SB700 STUFF
DEVSEL#
M23 SLT_GFX_CLKP IRDY# AA5 SB710 EMPTY
M22 SLT_GFX_CLKN TRDY# Y5
PAR U6 *DEFAULT
J19 GPP_CLK0P STOP# W6
J18 W4 +3.3V_RUN
GPP_CLK0N PERR#
X01 L20
SERR# V7
AC3 RN1801
04/14 modify GPP_CLK1P REQ0# LPC_LAD0
L19 GPP_CLK1N REQ1# AD4 1 8
1.Change C1810/C1812 from 18P to 15P LPC_LAD1
REQ2# AB7 2 7
M19 AE6 LPC_LAD3 3 6
GPP_CLK2P REQ3#/GPIO70 TP_PCI_REQ4# LPC_LAD2
M20 AB6 4 5

CLOCK GENERATOR
7 SB_14M_CLK GPP_CLK2N REQ4#/GPIO71
GNT0# AD2
N22 AE4 SRN10KJ-6-GP
GPP_CLK3P GNT1#
1
Do Not Stuff

P22 GPP_CLK3N GNT2# AD5

R1807

R1806 1 DY 2 Do Not Stuff AC6

GNT3#/GPIO72 TP_PCI_GNT4#
L18 25M_48M_66M_OSC GNT4#/GPIO73 AE5
C1810
B
1 2 32K_X1 DY TP_25M_X1 CLKRUN# AD6
V5
PM_CLKRUN# 27 B
2

LOCK#

1
Do Not Stuff
J21 25M_X1

R1808
SC15P50V2JN-2-GP R2_SB_14M_CLK AD3
INTE#/GPIO33
Do Not Stuff

C1811

INTF#/GPIO34 AC4 DY
1

INTG#/GPIO35 AE2
3

CPU TYPE R1813 TP_25M_X2

DY J20 25M_X2 INTH#/GPIO36 AE3

2
R1809
2

20MR3-GP
*Griffin 300 ohm
G22
LPC Bus Routing first connects to
LPCCLK0 LPCCLK0 22 MINICARD then connects to KBC
Tigris 1K ohm E22 LPCCLK1 22
2

LPCCLK1 LPC_LAD0
A3 H24 LPC_LAD0 27,44
2

X1801 X1 LAD0 LPC_LAD1

*DEFAULT LAD1 H23 LPC_LAD1 27,44
X-32D768KHZ-38GPU LPC_LAD2
RTC XTAL

LAD2 J25 LPC_LAD2 27,44

C1812 R1812 J24 LPC_LAD3
LAD3 LPC_LAD3 27,44
LPC

1 2 32K_X2 1 2 32K_X2_R B3 H25

TP1811 TP_25M_X1 Do Not Stuff X2 LFRAME# TP_LPC_LDRQ0# +3.3V_RUN LPC_LFRAME# 27,44
1 LDRQ0# H22
TP1812 1 TP_25M_X2 SC15P50V2JN-2-GP +1.8V_RUN AB8 TP_LPC_LDRQ1#
R1813 LDRQ1#/GNT5#/GPIO68 SB700_GPIO65 R1814 1 2 Do Not Stuff
TP1801 1 TP_PCIRST# A00 1 2
BMREQ#/REQ5#/GPIO65 AD7
V15
DY
SERIRQ INT_SERIRQ 27 +RTC_CELL
TP1802 1 TP_PCI_CLK5
TP1803 1 TP_LPC_LDRQ0# 8/24
10,15 ALLOW_LDTSTOP 300R2J-4-GP F23
TP1804 TP_LPC_LDRQ1# Change R1812 from 0 ohm to short pad ALLOW_LDTSTP
1 10 CPU_PROCHOT# F24 PROCHOT# RTCCLK C3 RTCCLK 29
TP1805 TP_PCI_CLK4 9/8 INTRUDER_ALERT# R1815 1 Do Not Stuff
TP1806
1
TP_PCI_AD23 Add TP_25M_X1,TP_25M_X2 10 CPU_LDT_PWRGD F22 LDT_PG INTRUDER_ALERT# C2
DY 2
CPU

1 10 CPU_LDT_STOP# G25 LDT_STP# VBAT B2 SC1U6D3V2KX-GP

SCD1U10V2KX-4GP
TP1807 1 TP_PCI_AD29 10 CPU_LDT_RST# G24
RTC

TP1808 TP_PCI_AD30 LDT_RST#

1 1

1
C1813

C1814
TP1809 1 TP_PCI_REQ4#
TP1810 1 TP_PCI_GNT4# R1816 1 2 33R2J-2-GP SB700-1-GP-U1
GPU_PLT_RST# 27 Y708D
A Main Source A
2

2
+3.3V_ALW
1'nd 73.01G08.DHG
2'nd 73.01G08.L04
SCD1U10V2KX-4GP

R1818 1 2 33R2J-2-GP LAN_PLT_RST# 26 X01 Wistron Corporation

U1801 R1819 1 2 33R2J-2-GP 04/08 Del 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
KBC_PLT_RST# 27
1
C1815

SNLVC1G08DCKRG4-GP 1.Del R1817 ( Card reader System reset depend on 3.3V_Run power rails, Taipei Hsien 221, Taiwan, R.O.C.
R1820 1 Not reserve for A_RST. )
1 A VCC 5 2 33R2J-2-GP 80PORT_PLT_RST# 44 Title
2

15 PLT_RST# 2 B
R1821 1 2 33R2J-2-GP MINI_PLT_RST# 44 ATi-SB700_PCIE&PCI_(1/5)
3 4 B_PLT_RST# R1822 1 2 33R2J-2-GP Size Document Number Rev
GND Y EXP_PLT_RST# 51 A3
Cloce To U38 Riya Discrete A00
Date: Tuesday, September 08, 2009 Sheet 18 of 65
5 4 3 2 1
 5 4 3 2 1

U3D

SB700 Part 4 of 5
SSID = S.B 27 KBC_ECSWI#
TP_PCI_PME#
KBC_ECSWI#
E1
E2
PCI_PME#/GEVENT4#
RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 USB_48M_CLK 7
TP_SLPS2 H7 R1903
SLP_S2/GPM9# USB_PCOMP R1904 C1902
27,30,31,39,40,41,51 PM_SLP_S3# F5 SLP_S3# USB_RCOMP G8 1 2
USB_48M_R2_CLK1 DY2

USB MISC
+3.3V_RUN 27,39,51 PM_SLP_S5# G1 SLP_S5# 1 DY 2

ACPI / WAKE UP EVENTS

10K7R2F-1-GP
27 PM_PWRBTN# H2
H1
PWR_BTN# 1% Do Not Stuff Do Not Stuff
7,30 SB_PWRGD PWR_GOOD
TP_SB_SUS_STAT# K3 Place R near pin14. Route it with 10mils Place these close SB700
R1901 3D3_NB_PWRGD_R SB_TEST2 SUS_STAT#
1
DY 2 Do Not Stuff SB_TEST1
H5
H4
TEST2 USB_FSD13P E6
E7
Trace width and 25mils spacing to any
+3.3V_ALW SB_TEST0 TEST1 USB_FSD13N signals in X, Y, Z directions.
D X01 H3
Y15
TEST0
F7 TP_USB12_P D

USB 1.1
27 A20GATE GA20IN/GEVENT0# USB_FSD12P
RN1901 04/14 Del TP_USB12_N
4 1 SMB_DATA 1.Del R1902 ,reserve closed-gap. 27 KBRCIN# W15
K4
KBRST#/GEVENT1# USB_FSD12N E8 ----->RESERVED
27 KBC_ECSCI# LPC_PME#/GEVENT3#
3 2 SMB_CLK TP_LPC_SMI# K24 H11
LPC_SMI#/EXTEVNT1# USB_HSD11P USB11_P 47
SRN4K7J-8-GP TP_SYS_RESET#
F1
J2
S3_STATE/GEVENT5# USB_HSD11N J10 USB11_N 47 ----->USB Port Right Side USB_OC_2_#
SYS_RESET#/GPM7#
26,51 PCIE_WAKE# H6 WAKE#/GEVENT8# USB_HSD10P E11 USB10_P 44
2 R1908 SB_TEST2
----->MINI CARD A00
1
DY Do Not Stuff
27 KBC_ECSMI#
R1906 1 DY 2 Do Not Stuff SB_THERMTRIP#
F2
J6
BLINK/GPM6# USB_HSD10N F11 USB10_N 44
10,27,29 SYS_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
R1902 1 2 Do Not Stuff 3D3_NB_PWRGD_R W14 A11 8/22
30 3D3_NB_PWRGD NB_PWRGD USB_HSD9P USB9_P 25 Change R1903 from 11.8k to 10.7k
R1909 SB_TEST1
1
DY 2 Do Not Stuff 1 R1907 2 KBC_R_RSMRST# D3
USB_HSD9N B11 USB9_N 25 ----->Card Reader
27 KBC_RSMRST# RSMRST#

Do Not Stuff
Do Not Stuff C10 TP_USB8_P 9/3
R1910 SB_TEST0 USB_HSD8P TP_USB8_N Change R1903 from 10K7R2D to 10k7R2F
1
DY 2 USB_HSD8N D10 ----->RESERVED

1
C1901
Do Not Stuff
DY TP_SB_GPIO10 AE18 G11 TP_USB7_P
R1911 PCIE_WAKE# TP_SB_GPIO6 SATA_IS0#/GPIO10 USB_HSD7P TP_USB7_N
1
DY 2 Close SB AD18 H12 ----->RESERVED

2
Do Not Stuff TP_SB_GPIO4 CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N
AA19 SMARTVOLT/SATA_IS2#/GPIO4
TP_SB_GPIO0 W17 E12
CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB6_P 46
R1912 KBC_RSMRST# TP_SB_GPIO39
1
DY 2 Do Not Stuff TP_SB_GPIO40
V17 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N E14 USB6_N 46 ----->BLUETOOTH
W20
W21
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
C12 TP_USB5_P
X01
23 SB_SPKR SPKR/GPIO2 USB_HSD5P

USB 2.0
1 2 R1905 KBC_ECSWI# 7,12,13,44 SMB_CLK_0 R1920 1 Do Not Stuff
2 SCL0 AA18 SCL0/GPOC0# USB_HSD5N D12 TP_USB5_N
----->RESERVED 03/31 modify
10KR2J-3-GP R1921 1 Do Not Stuff SDA0 1.Change Bluetooth from USB Port-12 to Port-6
7,12,13,44 SMB_DATA_0 2 W18 SDA0/GPOC1#
51 SMB_CLK SMB_CLK K1 B12
SCL1/GPOC2# USB_HSD4P USB4_P 51
R1918 KBC_ECSCI# SMB_DATA
1
DY 2 51 SMB_DATA K2 SDA1/GPOC3# USB_HSD4N A12 USB4_N 51 ----->Express Card

GPIO
Do Not Stuff TP_DDC1_SCL AA20
TP_DDC1_SDA DDC1_SCL/GPIO9 TP_USB3_P
R1919 KBC_ECSMI#
X01 TP_SATA_DET#
Y18 DDC1_SDA/GPIO8 USB_HSD3P G12
TP_USB3_N
1
DY 2 Do Not Stuff 03/31 modify TP_SB_GPIO5
C1
Y19
LLB#/GPIO66 USB_HSD3N G14 ----->RESERVED
C SHUTDOWN#/GPIO5 C
1.Change DIMM SPD SMBus from Ch1 to Ch0
G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USB2_P 48
04/08 modify
+3.3V_RUN 1.Change Clk gen,Mini Card SMBus from Ch1 to Ch0 USB_HSD2N H15 USB2_N 48 ----->Camera
USB_HSD1P A13 USB1_P 50
RN1903 A00
4 1 SDA0 USB_HSD1N B13 USB1_N 50 ----->I/O BOARD Left Side USB_OC_01_#
3 2 SCL0 8/22 B14
Change R1907, R1920,R1921 from 0 ohm to short pad USB_HSD0P USB0_P 50
TP_USB_OC6#
SRN4K7J-8-GP TP_USB_OC5#
B9
B8
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N A14 USB0_N 50 ----->I/O BOARD Left Side USB_OC_01_#
USB_OC5#/IR_TX0/GPM5#
X01 51 CPPE# A8 USB_OC4#/IR_RX0/GPM4# IMC_GPIO8 A18

USB OC
TP_USB_OC3# A9 B18
04/06 Change TP_USB_OC2# USB_OC3#/IR_RX1/GPM3# IMC_GPIO9
1.Change R1914 from 33 ohm to 47 ohm
E5
F8
USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21
D21
X01
47 USB_OC_2_# USB_OC1#/GPM1# SCL2/IMC_GPIO11 04/09 Modify
50 USB_OC_01_# E4 USB_OC0#/GPM0# SDA2/IMC_GPIO12 F19
1.Change CPU SID/SIC from SB_SMBus_Ch1
SCL3_LV/IMC_GPIO13 E20 CPU_SIC 10
R1913 to SCL3_LV/SDA3_LV.
23 SB_AZ_CODEC_BITCLK 1 2 33R2J-2-GP SB_AZ_BITCLK M1 AZ_BITCLK SDA3_LV/IMC_GPIO14 E21 CPU_SID 10
R1914 1 2 47R2J-2-GP SB_AZ_SDOUT M2 E19
23 SB_AZ_CODEC_SDOUT AZ_SDOUT IMC_PWM1/IMC_GPIO15
23 SB_AZ_CODEC_SDIN0 SB_AZ_CODEC_SDIN0 J7 D19 SB_GPO16 22
AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16
J8 AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 SB_GPO17 22

HD AUDIO
L8 AZ_SDIN2/GPIO44
M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
R1915 2 33R2J-2-GP SB_AZ_SYNC
23 SB_AZ_CODEC_SYNC
R1916
1
1 2 33R2J-2-GP SB_AZ_RST#
L6
M4
AZ_SYNC IMC_GPIO19 G21
D25
Strap Pin / define to use LPC or SPI ROM
23 SB_AZ_CODEC_RST# AZ_RST# IMC_GPIO20
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

TP_SB_GPM8# L5 D24

INTEGRATED uC
AZ_DOCK_RST#/GPM8# IMC_GPIO21
IMC_GPIO22 C25
1

1
C1903

C1904

C1905

C1906

IMC_GPIO23 C24
DY DY DY DY SB_AZ_RST# 22 IMC_GPIO24 B25
Close to SB700 C23
2

IMC_GPIO25
TO STRAPS
B
IMC_GPIO26 B24 B

IMC_GPIO27 B23
IMC_GPIO28 A23
+1.8V_RUN C22
IMC_GPIO29
IMC_GPIO30 A22
IMC_GPIO31 B22
1
Do Not Stuff

IMC_GPIO32 B21
R1917

IMC_GPIO33 A21
TP_SB_IMC_GPIO0 H19
DY TP_SB_IMC_GPIO1 H20 IMC_GPIO0 IMC_GPIO34 D20
C20

INTEGRATED uC
TP_SB_SPI_CS1# H21 IMC_GPIO1 IMC_GPIO35
A20
2

IDE_RST# SPI_CS2#/IMC_GPIO2 IMC_GPIO36

F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20
IMC_GPIO38 B19
TP_SB_IMC_GPIO4 D22 A19
TP_SB_IMC_GPIO5 E24 IMC_GPIO4 IMC_GPIO39
IMC_GPIO5 IMC_GPIO40 D18
TP_SB_IMC_GPIO6 E25 C18
TP_SB_IMC_GPIO7 D23 IMC_GPIO6 IMC_GPIO41
IMC_GPIO7

TP1901 1 TP_PCI_PME# TP1902 1 TP_USB_OC2# SB700-1-GP-U1

TP1903 1 TP_USB_OC6# TP1904 1 TP_SB_GPM8# Y708D
TP1905 1 TP_SLPS2 TP1906 1 TP_SB_IMC_GPIO0
TP1907 1 TP_SYS_RESET# TP1908 1 TP_SB_IMC_GPIO1
TP1909 1 TP_SB_GPIO10 TP1910 1 TP_SB_SPI_CS1#
TP1911 1 TP_SB_GPIO6 TP1912 1 TP_SB_IMC_GPIO4
TP1913 1 TP_SB_GPIO4 TP1914 1 TP_SB_IMC_GPIO5
TP1915 1 TP_SB_GPIO0 TP1916 1 TP_SB_IMC_GPIO6
TP1917 1 TP_SB_GPIO39 TP1918 1 TP_SB_IMC_GPIO7
TP1919 1 TP_SB_GPIO40 TP1920 1 TP_USB8_P
A TP1922 TP_USB8_N A
1 Main Source
TP1924 1 TP_USB7_P
TP1925 1 TP_DDC1_SCL TP1926 1 TP_USB7_N
TP1927 TP_DDC1_SDA TP1928 TP_USB5_P
TP1929
1
1 TP_SATA_DET# TP1930
1
1 TP_USB5_N Wistron Corporation
TP1931 1 TP_SB_GPIO5 TP1932 1 TP_USB3_P 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
TP1935 1 TP_USB_OC5# TP1934 1 TP_USB3_N Taipei Hsien 221, Taiwan, R.O.C.
TP1937 1 TP_USB_OC3# TP1936 1 TP_SB_SUS_STAT#
TP1938 1 TP_LPC_SMI# Title
TP1939
TP1940
1
1
TP_USB12_P
TP_USB12_N
ATi-SB700_USB&GPIO_(2/5)
Size Document Number Rev
Custom
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 19 of 65
5 4 3 2 1
 SSID = S.B X01
04/06 modify
1.Change SATA HD from Port-3 to Port-0

U3B

45 SATA_TX0P C2005 1 2SCD01U50V2KX-1GP SATA_C_TX0P AD9

SB700 AA24
C2006 1 SATA_TX0P IDE_IORDY
45 SATA_TX0N 2SCD01U50V2KX-1GP SATA_C_TX0N AE9 SATA_TX0N Part 2 of 5 IDE_IRQ AA25
SATA HDD 45 SATA_RX0N C2007 1 2SCD01U50V2KX-1GP SATA_C_RX0N AB10
IDE_A0 Y22
AB23
C2008 1 SATA_RX0N IDE_A1
45 SATA_RX0P 2SCD01U50V2KX-1GP SATA_C_RX0P AC10 SATA_RX0P IDE_A2 Y23
IDE_DACK# AB24
45 SATA_TX1P C2001 1 2SCD01U50V2KX-1GP SATA_C_TX1P AE10 AD25
C2002 1 SATA_TX1P IDE_DRQ
45 SATA_TX1N 2SCD01U50V2KX-1GP SATA_C_TX1N AD10 SATA_TX1N IDE_IOR# AC25
SATA ODD 45 SATA_RX1N C2003 1 2SCD01U50V2KX-1GP SATA_C_RX1N AD11
IDE_IOW# AC24
Y25
C2004 1 SATA_RX1N IDE_CS1#
45 SATA_RX1P 2SCD01U50V2KX-1GP SATA_C_RX1P AE11 SATA_RX1P IDE_CS3# Y24

AB12 SATA_TX2P IDE_D0/GPIO15 AD24

AC12 SATA_TX2N IDE_D1/GPIO16 AD23
PLACE SATA AC DECOUPLING AE22

ATA 66/100/133
IDE_D2/GPIO17
AE12 AC22
CAPS CLOSE TO SB700 AD12
SATA_RX2N IDE_D3/GPIO18
AD21
SATA_RX2P IDE_D4/GPIO19
IDE_D5/GPIO20 AE20
AD13 SATA_TX3P IDE_D6/GPIO21 AB20

SERIAL ATA
AE13 SATA_TX3N IDE_D7/GPIO22 AD19
IDE_D8/GPIO23 AE19
AB14 SATA_RX3N IDE_D9/GPIO24 AC20
AC14 SATA_RX3P IDE_D10/GPIO25 AD20
X01 AE14
IDE_D11/GPIO26 AE21
AB22
04/06 modify SATA_TX4P IDE_D12/GPIO27
AD14 SATA_TX4N IDE_D13/GPIO28 AD22
1.Change C2009/C2010 from 10P to 12P
IDE_D14/GPIO29 AE23
XTAL AD15
AE15
SATA_RX4N IDE_D15/GPIO30 AC23
SATA_RX4P
1'nd 82.30020.851
AB16 SATA_TX5P
2'nd 82.30020.791 Very Close AC16 SATA_TX5N
C2009 G6 TP_SPI_DI
SPI_DI/GPIO12
XTAL-25MHZ-102-GP

1 2 to SB700 AE16 SATA_RX5N SPI_DO/GPIO11 D2 TP_SPI_DO

TP_SPI_CLK
AD16 SATA_RX5P SPI_CLK/GPIO47 D1
1

1
10MR2J-L-GP

SC12P50V2JN-3GP R2006 F4 TP_SPI_HOLD#

SPI_HOLD#/GPIO31

SPI ROM
X2001

R2005

1 2 SATA_CAL V12 F3 TP_SPI_CS#

1KR2F-3-GP SATA_CAL SPI_CS#/GPIO32
SATA_X1 Y12 U15 TP_SB_GPIO13
2

C2010 SATA_X1 LAN_RST#/GPIO13 TP_ROM_RST#

J1
2

SATA_X2 ROM_RST#/GPIO14
1 2 AA12 SATA_X2 TP_SB_GPIO3
SC12P50V2JN-3GP TP_SB_SATA_ACT# W11 FANOUT0/GPIO3 M8
M5
X01
+1.2V_RUN +1.2V_PLLVDD_SATA SATA_ACT#/GPIO67 FANOUT1/GPIO48 TP_SB_GPIO49 04/02 modify
FANOUT2/GPIO49 M7
L2001 1.Add SB GPIO48 To detect LCD Size +3.3V_ALW
1 2 AA11 P5 06/09 modify

SATA PWR
PLLVDD_SATA FANIN0/GPIO50
SC2D2U6D3V3KX-GP

TP_SB_GPIO50 1.Del R2009 R2010 TALERT# R2008 1

FANIN1/GPIO51 P8 2 10KR2J-3-GP
BLM15AG221SS1D-GP W12 R8 TP_SB_GPIO52
XTLVDD_SATA FANIN2/GPIO52
1
C2011

20mil Width
220 ohm 300mA Very Close TEMP_COMM C6
TP_SB_GPIO61
B6
2

TEMPIN0/GPIO61
to SB700 TEMPIN1/GPIO62 A6
A5

HW MONITOR
TEMPIN2/GPIO63 TALERT#
TEMPIN3/TALERT#/GPIO64 B5 TALERT# 10,29
+3.3V_RUN +3.3V_XTLVDD_SATA A4
L2002 VIN0/GPIO53
VIN1/GPIO54 B4
1 2 VIN2/GPIO55 C4
SC1U6D3V2KX-GP

VIN3/GPIO56 D4
BLM15AG221SS1D-GP D5
VIN4/GPIO57
1
C2012

20mil Width VIN5/GPIO58 D6

220 ohm 300mA Very Close VIN6/GPIO59 A7
B7
2

VIN7/GPIO60
to SB700 +3.3V_AVDD_HWM +3.3V_ALW
L2003 A00
AVDD F6 1 2

Do Not Stuff

Do Not Stuff
Do Not Stuff 8/24
Change L2003 from 0 ohm to short pad
AVSS G7

1
C2013

C2014
SB700-1-GP-U1 DY DY

2
Y708D

Layout Notice connect

to cap then Gnd

TP2001 1 TP_ROM_RST#
TP2002 1 TP_SPI_DI
TP2003 1 TP_SPI_DO Main Source
TP2004 1 TP_SPI_CLK
TP2005 1 TP_SPI_HOLD#
TP2006 TP_SPI_CS#
TP2007
1
1 TP_SB_SATA_ACT# Wistron Corporation
TP2008 1 TP_SB_GPIO13 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
TP2009 1 TP_SB_GPIO3 Taipei Hsien 221, Taiwan, R.O.C.

TP2011 1 TP_SB_GPIO49 Title

TP2012
TP2013
1 TP_SB_GPIO50
TP_SB_GPIO52
ATi-SB700_SATA-IDE_(3/5)
1
TP2014 1 TP_SB_GPIO61 Size Document Number Rev
Custom
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 20 of 65
 5 4 3 2 1

SSID = S.B

+3.3V_RUN U3C +1.2V_RUN

3.3V(0.131A) for VDDQ 1.2V(0.510A) for VDD 100mil Width
U3E
L9
SB700 L15
SC22U6D3V5MX-2GP VDDQ_1 VDD_1

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U10V5KX-2GP
D
M9 VDDQ_2 Part 3 of 5 VDD_2 M12 SB700 Part 5 of 5 D

TC2101

C2101

C2108

C2103

C2105

C2102

C2106

C2107

C2109
1 T15 VDDQ_3 VDD_3 M14 VSS_1 A2

1
U9 VDDQ_4 VDD_4 N13 VSS_2 A25

CORE S0
U16 VDDQ_5 VDD_5 P12 VSS_3 B1

PCI/GPIO I/O
U17 P14 D7
2

2
VDDQ_6 VDD_6 VSS_4
V8 VDDQ_7 VDD_7 R11 T10 AVSS_SATA_1 VSS_5 F20
W7 VDDQ_8 VDD_8 R15 U10 AVSS_SATA_2 VSS_6 G19
Y6 VDDQ_9 VDD_9 T16 U11 AVSS_SATA_3 VSS_7 H8
AA4 VDDQ_10 U12 AVSS_SATA_4 VSS_8 K9
AB5 VDDQ_11 V11 AVSS_SATA_5 VSS_9 K11
AB21 VDDQ_12 V14 AVSS_SATA_6 VSS_10 K16
W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
+3.3V_RUN +1.2V_RUN
3.3V(0.71A) for VDD33_18 20mil Width
Y11
Y14
AVSS_SATA_9 VSS_13 L10
L11
AVSS_SATA_10 VSS_14
Y20 VDD33_18_1 CKVDD_1.2V_1 L21 Y17 AVSS_SATA_11 VSS_15 L12
Use Flash I/O:+1.8V / IDE:+3.3V AA21 VDD33_18_2 CKVDD_1.2V_2 L22 AA9 AVSS_SATA_12 VSS_16 L14

IDE/FLSH I/O

CLKGEN I/O
AA22 VDD33_18_3 CKVDD_1.2V_3 L24 AB9 AVSS_SATA_13 VSS_17 L16
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB11 AVSS_SATA_14 VSS_18 M6
AB13 AVSS_SATA_15 VSS_19 M10
AB15 AVSS_SATA_16 VSS_20 M11
+3.3V_ALW
3.3V(0.32A) for S5_3.3V 20mil Width
AB17
AC8
AVSS_SATA_17 VSS_21 M13
M15
AVSS_SATA_18 VSS_22
AD8 AVSS_SATA_19 VSS_23 N4

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP
AE8 AVSS_SATA_20 VSS_24 N12

C2116

C2117
1.2V(0.600A) for PCIE_VDDR POWER VSS_25 N14

1
VSS_26 P6
+1.2V_RUN +1.2V_PCIE_VDDR P9
L2101 VSS_27
100mil Width P10

2
VSS_28
1 2 P18 PCIE_VDDR_1 A15 AVSS_USB_1 VSS_29 P11
SC4D7U6D3V3KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C P19 PCIE_VDDR_2 B15 AVSS_USB_2 VSS_30 P13 C

C2118

C2119

C2120

C2121

BLM21PG221SN-1GP P20 C14 P15

A-LINK I/O
PCIE_VDDR_3 AVSS_USB_3 VSS_31
1

220 ohm 2A P21 PCIE_VDDR_4 S5_3.3V_1 A17

+1.2V_ALW
D8 AVSS_USB_4 VSS_32 R1
R22
R24
PCIE_VDDR_5 S5_3.3V_2 A24
B17
1.2V(0.113A) for S5_1.2V 15mil Width
D9
D11
AVSS_USB_5 VSS_33 R2
R4
2

PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_6 VSS_34

R25 J4 D13 R9

3.3V_S5 I/O
PCIE_VDDR_7 S5_3.3V_4 AVSS_USB_7 VSS_35

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

GROUND
S5_3.3V_5 J5 D14 AVSS_USB_8 VSS_36 R10

C2122

C2123
S5_3.3V_6 L1 D15 AVSS_USB_9 VSS_37 R12

1
+1.2V_RUN 1.2V(0.567A) for AVDD_SATA S5_3.3V_7 L2 E15
F12
AVSS_USB_10 VSS_38 R14
T11
L2105 AVSS_USB_11 VSS_39
50mil Width F14 T12

2
+1.2V_AVDD_SATA AVSS_USB_12 VSS_40
1 2 AA14 AVDD_SATA_1 G9 AVSS_USB_13 VSS_41 T14
SC22U6D3V5MX-2GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

AB18 AVDD_SATA_4 H9 AVSS_USB_14 VSS_42 U4

C2125

C2126

C2127

C2128

C2129

BLM21PG221SN-1GP AA15 H17 U14

AVDD_SATA_2 AVSS_USB_15 VSS_43
SATA I/O
1

220 ohm 2A AA17 AVDD_SATA_3 S5_1.2V_1 G2 J9 AVSS_USB_16 VSS_44 V6

CORE S5
+1.2V_ALW
AC18
AD17
AVDD_SATA_5 S5_1.2V_2 G4
1.2V(0.197A) for USB_PHY_1.2V15mil Width J11
J12
AVSS_USB_17 VSS_45 Y21
AB1
2

AVDD_SATA_6 AVSS_USB_18 VSS_46

AE17 AVDD_SATA_7 J14 AVSS_USB_19 VSS_47 AB19

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U10V5KX-2GP
J15 AVSS_USB_20 VSS_48 AB25

C2130

C2131

C2132
USB_PHY_1.2V_1 A10 K10 AVSS_USB_21 VSS_49 AE1

1
USB_PHY_1.2V_2 B10 K12 AVSS_USB_22 VSS_50 AE24
K14 AVSS_USB_23
K15

2
AVSS_USB_24
Use Plane Shape for +3.3V_AVDD_USB PCIE_CK_VSS_9 P23
+3.3V_ALW 3.3V(0.658A) for AVDDTX/RX +5V_RUN PCIE_CK_VSS_10 R16

L2106 50mil Width

5V(0.001A) for V5_VREF R2101 PCIE_CK_VSS_11 R19
T17
+3.3V_AVDD_USB +5V_VREF1 PCIE_CK_VSS_12
1 2 A16 AVDDTX_0 V5_VREF AE7 1 2 PCIE_CK_VSS_13 U18
SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP

SC1U10V3KX-3GP
B16 AVDDTX_1 H18 PCIE_CK_VSS_1 PCIE_CK_VSS_14 U20
C2133

C2134

C2135

C2136

C2137
BLM21PG221SN-1GP C16 J16 +3.3V_AVDDCK 1KR2J-1-GP J17 V18
AVDDTX_2 AVDDCK_3.3V PCIE_CK_VSS_2 PCIE_CK_VSS_15
1

1
+3.3V_RUN
B 220 ohm 2A D16 AVDDTX_3 +1.2V_AVDDCK D2101
J22 PCIE_CK_VSS_3 PCIE_CK_VSS_16 V20 B
D17 AVDDTX_4 AVDDCK_1.2V K17 K25 PCIE_CK_VSS_4 PCIE_CK_VSS_17 V21
PLL

E17 K A M16 W19

2

2
AVDDTX_5 +3.3V_ALW_AVDDC PCIE_CK_VSS_5 PCIE_CK_VSS_18
USB I/O

F15 AVDDRX_0 AVDDC E9 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22

F17 SDMK0340L-7-F-GP M21 W24
AVDDRX_1 PCIE_CK_VSS_7 PCIE_CK_VSS_20
F18 AVDDRX_2 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
G15 AVDDRX_3 Layout Note
G17 AVDDRX_4 F9 AVSSC AVSSCK L17
Layout Note G18 AVDDRX_5
SB700-1-GP-U1
SB700-1-GP-U1 71.SB700.M02
Y708D

3.3V(0.017A) for AVDDC 1.2V(0.062A) for AVDDCK_1.2V 3.3V(0.047A) for AVDDCK_3.3V

15mil Width +3.3V_ALW 15mil Width +1.2V_RUN 15mil Width +3.3V_RUN
A L2107 L2109 L2108 A
Main Source
+3.3V_ALW_AVDDC 1 2 +1.2V_AVDDCK 1 2 +3.3V_AVDDCK 1 2
SCD1U10V2KX-4GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP
C2138

C2139

C2141

C2140
BLM15AG221SS1D-GP BLM15AG221SS1D-GP BLM15AG221SS1D-GP
Wistron Corporation
1

1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
220 ohm 300mA 220 ohm 300mA 220 ohm 300mA Taipei Hsien 221, Taiwan, R.O.C.
2

2
Title
ATi-SB700_POWER&GND_(4/5)
Size Document Number Rev
Custom
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 21 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = S.B

D D

REQUIRED STRAPS
+3.3V_ALW +3.3V_RUN DEBUG STRAPS
1 R2205

1 R2203

1 R2204

1 R2206

1 R2207

1 R2209

1 R2210
DY DY DY DY DY DY
X01
2

2K2R2J-2-GP 2

2
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

PCI_CLK2 18
PCI_CLK3 18
C C
LPCCLK0 18
LPCCLK1 18
PCI_AD24 18
SB_AZ_RST# 19 PCI_AD25 18
SB_GPO16 19 PCI_AD26 18
SB_GPO17 19 PCI_AD27 18
PCI_AD28 18
1 R2212

1 R2213

1 R2214

1 R2216

1 R2217

1 R2219

1 R2220

1 R2223

1 R2224

1 R2225

1 R2226

1 R2227
DY
DYDYDYDYDY
2K2R2J-2-GP 2

10KR2J-3-GP 2

10KR2J-3-GP 2

10KR2J-3-GP 2

10KR2J-3-GP 2

10KR2J-3-GP 2

2
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
B REQUIRED SYSTEM STRAPS B

SB_GPO17 , SB_GPO16
PCI_CLK2 PCI_CLK3 LPCCLK0 LPCCLK1 SB_AZ_RST# PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24
ROM TYPE:
USE USE PCI USE ACPI USE IDE USE DEFAULT
WatchDOG USE IMC CLKGEN ENABLE PCI PULL LONG PLL BCLK PLL PCIE STRAPS
PULL (NB_PWRGD) DEBUG ENABLED ENABLED ROM BOOT H, H = Reserved HIGH RESET
HIGH ENABLED STRAPS H, L = SPI ROM (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT) (DEFAULT)
(Use Internal)
WatchDog IGNORE IMC CLKGEN DISABLE PCI USE BYPASS BYPASS BYPASS IDE USE EEPROM
PULL (NB_PWRGD) DEBUG DISABLED DISABLED ROM BOOT DEFAULT L, H = LPC ROM PULL SHORT PCI PLL ACPI PLL PCIE STRAPS
LOW DISABLED STRAPS (Use External) L, L = FWH ROM LOW RESET BCLK
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

Note: SB700 has 15K internal PU FOR PCI_AD[30:23]

A Main Source A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ATi-SB700_STRAPPING_(5/5)
Size Document Number Rev
A3
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 22 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO X01

06/16 modify
1.Change U2301 to new version
+AVDD +5V_RUN
A00
+3.3V_RUN +3.3V_RUN
Close to codec Close to codec 9/8 1 R2302 2

SCD1U10V2KX-4GP

SC1U10V3KX-3GP
Change U2301 to new version
AUD_DVDDCORE from 71.92H81.E03 to 71.92H81.E03 Do Not Stuff
+PVDD +5V_RUN

SCD1U10V2KX-4GP

SC1U6D3V2KX-GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

C2305

C2306
1

1
C2301

C2302

C2303

C2304
1

1
D D
1 R2303 2

SCD1U10V2KX-4GP

SC1U10V3KX-3GP

SC10U6D3V5MX-3GP
2

2
U2301 Do Not Stuff

C2307

C2308

C2309
1

1
1 DVDD_CORE AVDD 27
AVDD 38 1 R2304 2
9

2
SB_AZ_CODEC_BITCLK DVDD Do Not Stuff
PVDD 39
Do Not Stuff

3 DVDD_IO PVDD 45
C2310

13 AUD_SENSE_A
SENSE_A
1

SB_AZ_CODEC_BITCLK 6 14 AUD_SENSE_B
19 SB_AZ_CODEC_BITCLK HDA_BITCLK SENSE_B
DY A00
R2301 1 2 33R2J-2-GP SB_AZ_CODEC_SDIN0_R 8
19 SB_AZ_CODEC_SDIN0
2

HDA_SDI AUD_EXT_MIC_L 8/24

HP0_PORT_A_L 28 AUD_EXT_MIC_L 49
SB_AZ_CODEC_SDOUT AUD_EXT_MIC_R Change R2302,R2303,R2304 from 0 ohm to short pad
19 SB_AZ_CODEC_SDOUT 5 HDA_SDO HP0_PORT_A_R 29 AUD_EXT_MIC_R 49
23 AUD_VREFOUT_B AUD_VREFOUT_B 49
SB_AZ_CODEC_SYNC VREFOUT_A_OR_F
19 SB_AZ_CODEC_SYNC 10 HDA_SYNC
31 AUD_HP1_JACK_L AUD_HP1_JACK_L 49
SB_AZ_CODEC_RST# HP1_PORT_B_L AUD_HP1_JACK_R
19 SB_AZ_CODEC_RST# 11 HDA_RST# HP1_PORT_B_R 32 AUD_HP1_JACK_R 49
+3.3V_RUN
19 AUD_INT_MIC_R_L C2311 1 2 SC1U10V3KX-3GP
PORT_C_L INT_MIC_L_R 49
PORT_C_R 20
24 AUD_VREFOUT_C R2305 1 2 4K7R2J-2-GP
VREFOUT_C
1
10KR2J-3-GP

AUD_DMIC_CLK 2 DMIC_CLK/GPIO1
R2306

AUD_DMIC_IN0 4 40 AUD_SPK_L+ AUD_SPK_L+ 49

48 AUD_DMIC_IN0 DMIC0/GPIO2 SPKR_PORT_D_L+
41 AUD_SPK_L- AUD_SPK_L- 49
SPKR_PORT_D_L-
46 DMIC1/GPIO0/SPDIF_OUT_1
43 AUD_SPK_R- AUD_SPK_R- 49
2

SPKR_PORT_D_R- AUD_SPK_R+
C 48 SPDIF_OUT_0 SPKR_PORT_D_R+ 44 AUD_SPK_R+ 49 C
AMP_MUTE#
AMP_MUTE# 47 15
27 AMP_MUTE# EAPD PORT_E_L
PORT_E_R 16
R2307 C2312

SC4D7U25V5KX-GP
PUMP_CAPN 17 AUD_PC_BEEP 1 2 SB_SPKR_C 1 2
PORT_F_L SB_SPKR 19
35 CAP- PORT_F_R 18

C2313
AUD_PC_BEEP 499KR2F-1-GP SCD1U10V2KX-4GP From SB
12 R2308 C2314
36
PC_BEEP Trace width>15 mils 1 2 KBC_BEEP_C 1 2 KBC_BEEP 27
2

PUMP_CAPP CAP+
MONO_OUT 25

1
499KR2F-1-GP SCD1U10V2KX-4GP From EC

Do Not Stuff

R2309
7 DVSS
+3.3V_RUN 33 22 AUD_CAP2
U2302 AVSS CAP2
30 AVSS
5 1 26 21 AUD_VREFFLT

2
VCC OE# AVSS VREFFILT
AUD_DMIC_CLK_Y 4
DY A 2
3 42 34 AUD_V_B
Y GND PVSS V-
Do Not Stuff 49 37 AUD_VREG
GND VREG
1
Do Not Stuff

SC4D7U6D3V3KX-GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP
R2310

SC1U6D3V2KX-GP
C2315

C2316

C2317

C2318
92HD81B1A5NLGXUAX8-GP
DY

1
71.92H81.G03
2

R2311

2
1 2 AUD_DMIC_CLK
48 AUD_DMIC_CLK_G
Do Not Stuff

C2321

33R2J-2-GP
1

B B

DY
2

Close to codec

Azalia I/F EMI

SB_AZ_CODEC_SDOUT
1
Do Not Stuff

R2315

DY +AVDD +AVDD
R2316
2

1 2 AUD_HP1_JD# 49
1

1
2K49R2F-GP SC1000P50V3JN-GP-U

2K49R2F-GP
SB_AZ_CODEC_SDOUT1

R2317

R2318

20KR2F-L-GP
2

A AUD_SENSE_A AUD_SENSE_B A
Main Source
1
C2319

20KR2F-L-GP
1

R2319

Wistron Corporation
Do Not Stuff

R2320 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

Taipei Hsien 221, Taiwan, R.O.C.

C2320

1 2 EXT_MIC_JD# 49
2
1

39K2R2F-L-GP Title
DY AUDIO CODEC IDT-92HD81
2

Close to Pin13 Size Document Number Rev

Close to Pin14 Custom
Riya Discrete A00
Date: Tuesday, September 08, 2009 Sheet 23 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = SDIO

Please close to pin8.

+3.3V_PHY
+3.3V_PHY +3.3V_RUN
R2501
D D

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
VREG 1 2

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

Do Not Stuff

SCD1U16V2KX-3GP

SC4D7U6D3V3KX-GP
Do Not Stuff

1
C2501

C2502

C2505

C2506

C2507
1

1
C2503

C2504
DY

2
+3.3V_PHY

200KR2J-L1-GP
1
R2502
Please close to pin11 and pin33. MODE_SEL

SD_CMD
SD_CMD 44

2
+3.3V_RUN_CARD CARD_RREF 1 R2503 2
6K2R2F-GP L2501
CARD_R_L_PLT_RST# 1 2 CARD_R_PLT_RST#

SCD1U16V2KX-3GP
X01

SCD1U10V2KX-4GP
0R3J-0-U-GP

1
C2508

499KR2F-1-GP

C2509
04/08 Del

1
R2505
1.Del R2504,C2510,R1817

10

33
11

45
36
14

44
9

2
U2501

CARD_3V3

AV_PLL

VREG

3V3_IN

D3V3
D3V3

MODE_SEL
SD_CMD
GPIO0
RREF
RST#

2
A00

2
XD_CD# 19 5 R_USB9_P 8/24
44 XD_CD# SP1 DP Change R2501,R2508,R2511,R2512 from 0 ohm to short pad
SD_WP 20 4 R_USB9_N
44 SD_WP SP2 DM +3.3V_PHY
SD_CD# 21
44 SD_CD# SP3
XD_D4/SD_DAT1 23 R2506 8/26
44 XD_D4/SD_DAT1 SP4 Del L2502
XD_D5/MS_BS 25 13 XTAL_CTR 1 2
C 44 XD_D5/MS_BS SP5 XTAL_CTR C
XD_D3/MS_D1 26
44 XD_D3/MS_D1 SP6
SD_DAT0/XD_D6/MS_D0 27 10KR2J-3-GP
44 SD_DAT0/XD_D6/MS_D0 SP7
XD_D2/MS_D2 28 47
44 XD_D2/MS_D2 SP8 XTLO
MS_INS# 29 48
44 MS_INS# SP9 XTLI CARD_48M_CLK 7
XD_D7/MS_D3 31
44 XD_D7/MS_D3 SP10
SD_CLK/XD_D1/MS_CLK 34 R2507 C2511
44
44
SD_CLK/XD_D1/MS_CLK
XD_D0
XD_D0 35
SP11
SP12
RTS5159-GR-GP 1
DY 2 R2_CARD_48M_CLK 1
DY2
XD_WP# 37
44 XD_WP# SP13
XD_RDY 38 17 Do Not Stuff Do Not Stuff
44 XD_RDY SP14 EESK
SD_DAT3/XD_WE# 39 16 Place these close RTS5159
44 SD_DAT3/XD_WE# SP15 EECS
SD_DAT2/XD_RE# 40
44 SD_DAT2/XD_RE# SP16
XD_ALE 41
44 XD_ALE SP17
XD_CE# 42 15
44 XD_CE# SP18 EEDO
XD_CLE 43 18
44 XD_CLE SP19 EEDI

MS_D5
MS_D4

NC#30
NC#7
NC#3

GND
GND
GND
GND
24
22

30
7
3

6
12
32
46
USB9_P 19

R2508
1 2
Do Not Stuff

R2509 R_USB9_P
MS_CLK 1 2 R_USB9_N
44 MS_CLK
B Do Not Stuff B
R2511
SD_CLK/XD_D1/MS_CLK 1 2
Do Not Stuff
R2510
SD_CLK 1 2
44 SD_CLK
Do Not Stuff
USB9_N 19
Do Not Stuff

Do Not Stuff

A00
1

1
C2512

C2513

8/22
Change R2509,R2510 from 0 ohm to short pad
DY DY
2

Power mode select

No staff R and C for power saving mode.

MODE_SEL
A A
Main Source
Do Not Stuff
1

1
Do Not Stuff
R2512

C2514

DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2

Taipei Hsien 221, Taiwan, R.O.C.

2

Title
Card Reader Realtek RTS5159
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 25 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = LOM

+1.2V_LAN_DVDD

SCD1U10V2KX-4GP

C2601
D D

1
+1.2V_LAN_DVDD

2
C2602 1 2 SCD1U10V2KX-4GP

TP_LAN_TX/RX#
C2603 1 2 SCD1U10V2KX-4GP
R2601

+3.3V_LAN
1 2 RSET C2604 1 2 SCD1U10V2KX-4GP

LANX2
LANX1
SCD1U10V2KX-4GP
2K49R2F-GP C2605 1 2 SCD1U10V2KX-4GP
CTRL12A

C2606
1
Place close to

48
47
46
45
44
43
42
41
40
39
38
37
2
U2601 PIN 10, 13, 30, 36

VCTRL12A
GND
RSET
VCTRL12D
NC#44
NC#43
CKXTAL2
CKXTAL1
NC#40
NC#39
LED0
VDD33
Lay out close to Pin48.
+3.3V_LAN 1 36 +1.2V_LAN_DVDD +3.3V_LAN
MDI0+ AVDD33 DVDD12 TP_LED1/EESK
50 MDI0+ 2 MDIP0 LED1/EESK 35
50 MDI0- MDI0- 3 34 LED2/EEDI R2602 1 2 3KK6R2J-GP +3.3V_LAN C2607 1 2 SCD1U10V2KX-4GP
MDIN0 LED2/EEDI/AUX TP_LED3/EEDO
4 NC#4 LED3/EEDO 33
50 MDI1+ MDI1+ 5 32 EECS R2603 1 2 1KR2J-1-GP C2608 1 2 SCD1U10V2KX-4GP
MDI1- MDIP1 EECS
50 MDI1- 6 MDIN1 GND 31
7 30 +1.2V_LAN_DVDD C2609 1 2 SCD1U10V2KX-4GP
GND DVDD12 +3.3V_LAN
8 NC#8 VDD33 29
9 28 LAN_ISOLATE# R2604 1 2 1KR2J-1-GP +3.3V_RUN
C NC#9 ISOLATE# C
+1.2V_LAN_DVDD 10 DVDD12 PERST# 27
11 26 R2605 1 2 15KR2J-1-GP
NC#11 LANWAKE#
12 25 X01

REFCLK_M
NC#12 CLKREQ#

REFCLK_P
DVDD12
04/06 modify

GNDTX
VDDTX
LAN_PLT_RST# 18

NC#23
NC#24
HSON
HSOP
1.Change C2611/C2613 from 18P to 15P
HSIN
HSIP
GND

PCIE_WAKE# 19,51
C2610 LANX1
LANX2 R2606 2Do Not Stuff
RTL8103EL-GR-GP
1
DY 2 1
DY
13
14
15
16
17
18
19
20
21
22
23
24
Do Not Stuff

+1.2V_LAN_DVDD

SC15P50V2JN-2-GP

SC15P50V2JN-2-GP
X2601
LANX2 1 2 LANX1

C2613

C2611
1

1
XTAL-25MHZ-102-GP

2
PCIE_NRX_LANTX_C_N1 C2612 1 2 SCD1U16V2KX-3GP PCIE_NRX_LANTX_N1 14
PCIE_NRX_LANTX_C_P1 C2614 1 2 SCD1U16V2KX-3GP PCIE_NRX_LANTX_P1 14

C2615 1 2SC1U6D3V2KX-GP
XTAL
C2616 1
Lay out close to Pin19. 1'nd 82.30020.851
2SC1U6D3V2KX-GP
2'nd 82.30020.791
LAN_PCIE_CLK# 7
B LAN_PCIE_CLK 7 B

PCIE_NTX_LANRX_N1 14
PCIE_NTX_LANRX_P1 14
+3.3V_LAN

R2607 1 2 Do Not Stuff

DY
+3.3V_ALW
Q2601

S
Max current: 333mA
SCD1U10V2KX-4GP

D
1
C2617

10KR2J-3-GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC4D7U6D3V5KX-3GP

SC4D7U6D3V5KX-3GP

SC10U6D3V5MX-3GP
30 mils
1

G
R2608

C2618

C2619

C2620

C2621

C2622
1

1
AO3403-GP
G

2.2A
2

R2609
Rds= 260m ohm
2

2
1 2
SC1U10V3KX-3GP

C2623

1KR2J-1-GP
1
D

Q2602
27 PM_LAN_ENABLE G
2N7002A-7-GP

A Main Source A
S

A00
8/22
Change Q2602 from 84.27002.N31 to 84.2N702.E31 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

TP2601 TP_LED3/EEDO Title

TP2602
1
1 TP_LED1/EESK
X01 LAN Realtek RTL8103EL
TP2603 1 TP_LAN_TX/RX# 06/09 modify
1.stuff C2623 Size Document Number Rev
2.add R2609 A3
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 26 of 65
5 4 3 2 1
 5 4 3 2 1
+3.3V_RUN
+3.3V_RTC_LDO +3.3V_RUN
220 ohm 300mA KBC_SHBM SHBM
L2701 1(EMPTY R2713) Disables
SSID = KBC
VBAT R2702 1
1 2
DY 2Do Not Stuff

SCD1U10V2KX-4GP

Do Not Stuff
*0(STUFF R2713) Enable

C2702

C2703
BLM15AG221SS1D-GP

1
*DEFAULT U2702
SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP

Do Not Stuff

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP
DY
C2701

C2709
4 3 KBC_SDA1
29 THERM_SDA

2
1

1
C2704

C2705

C2706

C2707

C2708

C2710
DY 5 2
2

115

102
KBC_SCL1

88
76
46
19

80
6 1 THERM_SCL 29

4
U2701A 1 OF 2
D BAT_IN# 32 D
DMN66D0LDW-7-GP A00

GPIO41
VCC
VCC
VCC
VCC
VCC

AVCC

VDD
CAP close to VCC-GND pin pair 8/22
+3.3V_RTC_LDO R2703 1 Change U2702 from 84.27002.B3F to 84.DMN66.03F
R2701 R2735 1 Do Not Stuff DY 2Do Not Stuff
1 2
104 VREF GPIO10/LPCPD# 124
7 KBC_LRESET#
ADAPT_TRIP_SEL 33 DY 2
10KR2J-3-GP LRESET# D2704 +3.3V_RUN
33 AD_IA 97
98
GPI90/AD0 A/D LCLK 2
3 KBC_LPC_LFRAME#
KBC_PCI_CLK 18
A K
GPI91/AD1 LFRAME# LPC_LFRAME# 18,44
55 THERMTRIP_VGA# 99 126 LPC_LAD0
GPI92/AD2 LAD0 LPC_LAD1 SDMK0340L-7-F-GP KBC_LPC_LFRAME# R2734 1
33 ADAPT_OC 100 GPI93/AD3 LAD1 127 LPC_LAD[0..3] 18,44 2 300R2J-4-GP
50 LCD_EC_DET 108 128 LPC_LAD2
GPIO05 LAD2 LPC_LAD3 E51_RxD R2704 1 Do Not Stuff
X01 10,19,29 SYS_THERMTRIP# 96 GPIO04 LPC LAD3 1
125
DY 2
SERIRQ INT_SERIRQ 18
06/09 modify 8 RN2701
1.Connect net LCD_EC_DET to I/O connector GPIO11/CLKRUN# PM_CLKRUN# 18
122 KBRCIN# 19 SB TYPE D2704 R2734 R2735 A20GATE 4 1
PCB_VER0 KBRST# A20GATE KBRCIN#
PCB_VER1
101 GPI94 GA20 121
KBC_D_ECSCI#
A20GATE 19 3
DY 2

PCB_VER2
105 GPI95 ECSCI#/GPIO54 29
PANEL_BKEN
*SB700 STUFF STUFF EMPTY
Do Not Stuff
106
107
GPI96 D/A GPIO65/SMI# 9
123 KBC_D_ECSWI#
PANEL_BKEN 55
SB710 EMPTY EMPTY STUFF +3.3V_RTC_LDO
48 CAMERA_DET# GPI97 GPIO67/PWUREQ# RN2702
*DEFAULT KBC_SCL1 4 1
KBC_SDA1 3 2

Do Not Stuff
19,30,31,39,40,41,51 PM_SLP_S3# 64 68 KBC_SDA1
GPIO01/TB2 GPIO74/SDA2

EC2701
KBC_SCL1 SRN4K7J-8-GP
52 KBC_PWRBTN# 95 GPIO03 SMB GPIO73/SCL2 67

1
33 AC_IN# 93 69 D2701 RN2703
GPIO06 GPIO22/SDA1 BAT_SDA 32,33
BAT_SDA
51 LID_CLOSE#
30 1.8V_GFX_RUN_PWRGD#
94
119
GPIO07 GPIO17/SCL1 70 BAT_SCL 32,33 19 KBC_ECSWI# 1
BAT_SCL
4
3
1
2
DY

2
GPIO23 KBC_D_ECSWI#
6 GPIO24 3
109 BAS16-1-GP SRN4K7J-8-GP
48 EC_SPI_WP#_R GPIO30
C 29,30,38,40,41 RUNPWROK 1 R2705 2 R_RUNPWROK 120 GPIO31 SP GPIO66/G_PWM 81 1.8V_GFX_RUN_EN 31 2 KBC_PWRBTN# R2706 1 2 100KR2J-1-GP C
Do Not Stuff 65
48 PWRLED GPIO32/D_PWM LID_CLOSE# R2707 1 2 Do Not Stuff
49 HP_MUTE# 66
16
GPIO33/H_PWM D2702 DY
41 3.3V_DELAY_EN GPIO40/F_PWM
17 84 BLUETOOTH_EN 46 1 LCD_CBL_DET# R2708 1 2 100KR2J-1-GP
50 AD_OFF GPIO42/TCK GPIO77 19 KBC_ECSCI#
KBC_SHBM
19 KBC_RSMRST# 20 GPIO43/TMS SPI GPIO76/SHBM 83
KBC_D_ECSCI# KB_DET# R2709 1 2 Do Not Stuff
19,39,51 PM_SLP_S5# 21
KBC_PLTRST_DELAY# 22 GPIO44/TDI GPIO GPIO75 82
91
WIFI_RF_EN 44
BAS16-1-GP
3
DY
GPIO45/E_PWM GPIO81 1.1V_GFX_RUN_EN 37
30,34 3V_5V_POK 23 2 CAMERA_DET# R2710 1 2 100KR2J-1-GP
GPIO46/TRST#
24 GPIO47
25 PANEL_BKEN R2733 1 2 10KR2J-3-GP
50 PSID_DISABLE# GPIO50/TDO
26 111 E51_TxD E51_TxD 44 D2703
BLON_OUT GPIO51 GPO83/SOUT_CR/BADDR1 E51_RxD S5_ENABLE R2711 1
42 BLON_OUT 27 GPIO52/RDY# GPIO87/SIN_CR 113 E51_RxD 44 19 KBC_ECSMI# 1 2 10KR2J-3-GP
28 GPIO53 GPO84/BADDR0 112
KBC_D_ECSMI# BAS16-1-GP KBC_D_ECSMI# KCOL0 R2712 1 2 Do Not Stuff
73
74
GPIO70
114 PM_LAN_ENABLE 26
3
DY
41 GFX_CORE_EN GPIO71 GPIO16 KBC_SHBM R2713 1 2 10KR2J-3-GP
X01 75
110
GPIO72 GPIO34 14
15
2
47,50 USB_PWR_EN# GPO82/TRIS# GPIO36 S5_ENABLE 30
04/14 Change BLON_OUT R2714 1 2 10KR2J-3-GP
1.Change netname from HP_MUTE to HP_MUTE# SER/IR
04/14 Del
1.Del R2705 ,reserve closed-gap.
44 KBC_VCORF
VCORF

SC1U10V3KX-3GP
U2701B 2 OF 2

C2711
KCOL[0..16] 46

1
AGND

+3.3V_RUN
GND
GND
GND
GND
GND
GND

A00 KBC_XI 77 53 KCOL0

32KX1/32KCLKIN KBSOUT0/JENK# KCOL1
52

2
WPCE773LA0DG-GP KBSOUT1/TCK KCOL2
51
116
89
78
45
18
5

103

KBSOUT2/TMS KCOL3
KBSOUT3/TDI 50
1

1
10KR2J-3-GP

10KR2J-3-GP

Do Not Stuff

KBC_XO 79 49 KCOL4
32KX2 KBSOUT4/JEN0# KCOL5
B 30 48 B
MB VERSION ID 23 AMP_MUTE# GPIO55/CLKOUT KBSOUT5/TDO
1
R2715

R2718

R2716

0R2J-2-GP

KCOL6
DY KBSOUT6/RDY# 47
R2717

50 PSID_EC 63 43 KCOL7
GPIO14/TB1 KBSOUT7 KCOL8
VER2 VER1 VER0 19 PM_PWRBTN# 117 KBC 42
2

GPIO20/TA2 KBSOUT8 KCOL9

42 LCD_TST_EN 31 GPIO56/TA1 KBSOUT9 41
PCB_VER0 32 40 KCOL10
X00 0 0 0 23 KBC_BEEP
2

PCB_VER1 GPIO15/A_PWM KBSOUT10 KCOL11

48 BATLOW_LED 118 GPIO21/B_PWM KBSOUT11 39
PCB_VER2 62 38 KCOL12
X01 0 0 1 42 BRIGHTNESS GPIO13/C_PWM KBSOUT12/GPIO64
KBSOUT13/GPIO63 37 KCOL13
1

1
Do Not Stuff

Do Not Stuff

10KR2J-3-GP

36 KCOL14
X02 0 1 0 R2722 1
DY 2 Do Not Stuff KBC_PLTRST_DELAY# KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT 35 KCOL15
R2719

R2720

R2721

DY KCOL16
DY * -1 0 1 1 54 PLTRST_DELAY# 1 R2723 2 Do Not Stuff GPU_PLT_RST# 18
46 KB_DET#
42 LCD_CBL_DET#
13
12
GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO60/KBSOUT16
GPIO57/KBSOUT17
34
33 KCOL17 1 TP2701
*DEFAULT 11 KROW[0..7] 46
2

KBC_LRESET# GPIO27/PSDAT2
1 R2724 2 Do Not Stuff KBC_PLT_RST# 18 42 LCD_TST 10 GPIO26/PSCLK2
Do Not Stuff

71 54 KROW0
46 TPDATA GPIO35/PSDAT1 KBSIN0 KROW1
46 TPCLK 72 GPIO37/PSCLK1 PS/2 KBSIN1 55
1
C2712

A00 56 KROW2
KBSIN2 KROW3
DY 8/22 KBSIN3 57
KROW4
X01 58
2

Change R2723,R2724 from 0 ohm to short pad KBSIN4 KROW5

86 59
KBC CLK 04/06 modify 48
48
EC_SPI_DI
EC_SPI_DO 87
F_SDI
F_SDO
KBSIN5
KBSIN6 60 KROW6
1.Add EC LCD_EC_DET To detect LCD Size KROW7
+3.3V_RUN EMI KBC_PCI_CLK 06/09 modify 48 EC_SPI_CS#
1 R2725 2
90
EC_SPI_CLK_C 92 F_CS0# FIU KBSIN7 61
1.Del R2736 R2737 48 EC_SPI_CLK F_SCK
0R2J-2-GP
1
Do Not Stuff

C2713 85 ECRST#
VCC_POR#
1
Do Not Stuff

R2727

KBC_XI
1 2 X01
R2726

DY SC15P50V2JN-2-GP 04/14 Del

DY 1.Del R2731 ,reserve closed-gap. +3.3V_RTC_LDO WPCE773LA0DG-GP
2

X-32D768KHZ-38GPU

A 10KR2J-3-GP A
KBC_RC_PCI_CLK

Main Source
2

E51_TxD R2730 1 2ECRST#

2

1
20MR3-GP

X2701
1
4K7R2J-2-GP

R2729

Wistron Corporation
R2728

SC1U10V3KX-3GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Do Not Stuff

C2715
Q2701

1
CH3906PT-GP Taipei Hsien 221, Taiwan, R.O.C.
2

E
2

4
1

Title
C2714

29,30 PURE_HW_SHUTDOWN# 1 R2731 2 ECRST#_C

B
KBC WPCE773L

2
Do Not Stuff
DY C2716 R2732
2

C
1 2 X3_1 1 2 KBC_XO Size Document Number Rev
Custom
SC15P50V2JN-2-GP 33KR3-GP
Riya Discrete A00
Date: Wednesday, September 09, 2009 Sheet 27 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = Thermal
+5V_RUN +3.3V_RUN
X01 +5V_RUN
06/22 modify
1.Empty D2901, Stuff R2902
25 mils

1
SC4D7U6D3V5KX-3GP

SCD1U16V2KX-3GP

10KR2J-3-GP

Do Not Stuff
A00

C2901

C2902

R2901

R2903
1 R2902 2

1
Do Not Stuff 8/24
DY Change R2902 from 0 ohm to short pad

2
D D
D2901
EMC2102_FAN_TACH EMC2102_FAN_TACH_1
A
DY K EMC2102_FAN_TACH_1 45
Do Not Stuff
EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 45

RN2901
3 2 +3.3V_RUN
4 1

SRN4K7J-8-GP
THERM_SCL 27
THERM_SDA 27
+3.3V_RUN
R2904
1 2EMC2102_VDD_3D3 X01

29

28

27

26

25

24

23

22
SCD1U16V2KX-3GP
U2901
49D9R2F-GP 04/14 Del

GND

TACH

VDD_5Va

FANa

FANb

VDD_5Vb

SMCLK

SMDATA
1.Del R2905 ,reserve closed-gap.

1
C2903
1.For CPU Sensor
10 H_THERMDC
SC470P50V3JN-2GP

2
1
C2904

Layout notice : 1 21
Both H_THERMDA and THERMDC routing VDD_3V NC#21
10 mil trace width and 10 mil spacing. 2 20
2

DN1 GND
C C
3 19 TALERT_R# 1 R2905 2 TALERT# 10,20
10 H_THERMDA DP1 ALERT# Do Not Stuff
4 EMC2102 18 32K_CLK +3.3V_RUN
GND = Internal Oscillator Selected
DN2 CLK_IN
2.For GPU Sensor 5 17 EMC2102_CLK_SEL R2906 1 2 10KR2J-3-GP +3.3V = External 32.768kHz Clock Selected
DP2 CLK_SEL
55 VGA_THERMDC
SC470P50V3JN-2GP

EMC2102_DN3 6 16 RUNPWROK 27,30,38,40,41

DN3 RESET#
1

+3.3V_RUN
C2905

Layout notice : EMC2102_DP3 7 15

Both VGA_THERMDA and VGA_THERMDC routing DP3 NC#15

THERMTRIP#

POWER_OK#
10 mil trace width and 10 mil spacing.

SYS_SHDN#
FAN_MODE
2

SHDN_SEL

TRIP_SET

1
10KR2J-3-GP

10KR2J-3-GP
55 VGA_THERMDA

R2907

R2908
NC#8
X01
04/14 BOM
GND = Channel 1 1.Stuff R2917
3.HW T8 sensor EMC2102-DZK-GP
OPEN = Channel 3

10

11

12

13

14

2
Do Not Stuff

SC470P50V3JN-2GP

+3.3V = Disabled
E

C2907 must be near EMC2102 R2917

1

CH3904PT-GP
C2906

C2907

R2909
Q2901
B
DY C2906 must be near Q2901
1 2 EMC2102_SHDN
1 2 SYS_THERMTRIP# 10,19,27
Layout notice : DY +3.3V_RUN +3.3V_RTC_LDO 0R2J-2-GP
C

Both DN3 and DP3 routing 10 mil Do Not Stuff

trace width and 10 mil spacing.

1
+3.3V_RUN

10KR2J-3-GP

10KR2J-3-GP
+3.3V_RUN

R2911

R2912
R2910
1 2 EMC2102_FAN_mode
DY

SCD1U16V2KX-3GP
B Do Not Stuff B

1
C2908

10KR2F-2-GP
Q2902

R2914
R2913
1 2 2N7002A-7-GP

2
TP2901 1 EMC2102_FAN_TACH_1 10KR2J-3-GP S D PURE_HW_SHUTDOWN# 27,30

2
TP2902 1 EMC2102_FAN_DRIVE GND = Fan is OFF
OPEN = Fan is at 60% full-scale TRIP_SET Pin Voltage
V_DEGREE
V_DEGREE=(((Degree-75)/21)
SCD1U16V2KX-3GP

+3.3V = Fan is at 75% full-scale

1
C2909

2K37R2F-GP
A00
1

R2915
8/22
Change Q2902 from 84.27002.N31 to 84.2N702.E31
2

2
32K suspend clock output

Q2903
2N7002A-7-GP
R2916
A D S R_32K_CLK 32K_CLK A
18 RTCCLK 1 2 Main Source
Do Not Stuff

10R2J-2-GP
1
C2910

DY
Wistron Corporation
G

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

Taipei Hsien 221, Taiwan, R.O.C.

A00 RUN_POWER_ON Title
8/22
Change Q2903 from 84.27002.N31 to 84.2N702.E31
THERMAL EMC2102
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 29 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = Reset.Suspend

D D
A00
08/22 modify
change C3001 for sloving +2.5V_RUN +3.3V_RUN +3.3V_ALW
CORE_RUN_EN signal shake.

100KR2J-1-GP
1

1
100KR2J-1-GP

100KR2J-1-GP
R3001

R3002

R3003
A00 +3.3V_ALW
2
D3002
BAS16-1-GP 3
C3001 PURE_HW_SHUTDOWN# 27,29
D3001 U3001

2
1 2+2.5V_RUN_PWRGD 2 41 VCC_GFX_CORE_PWRGD 1 A VCC 5 34 3V_5V_EN 1

BAW56-2-GP 3 2 R3005
SCD1U25V2KX-GP B

1
Do Not Stuff
1 2 S5_ENABLE 27

R3004
19,27,31,39,40,41,51 PM_SLP_S3# 1 3 GND Y 4 VCORE_RUN_EN 31,35,37,38
1KR2J-1-GP
DY
R3006 SNLVC1G08DCKRG4-GP

2
27,34 3V_5V_POK 1 DY 2

Do Not Stuff

R3007
39 1.8V_SUS_PWRGD 1 DY 2
+1.8V_GFX_RUN 1.8V_GFX_RUN_PWRGD# 27
Do Not Stuff

3
C R3008 C
1.8V_GFX_RUN_PWRGD1 MMBT3904-7-F-GP
1 2
Q3001

Do Not Stuff

C3002
10KR2J-3-GP

2
1
DY

2
+3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN
+1.8V_RUN
1

1
B B
10KR2J-3-GP

10KR2J-3-GP

10KR2J-3-GP

Do Not Stuff

1
R3009

R3010

R3011

R3012

300R2J-4-GP
+1.8V_RUN

R3013
DY U3002
D3003
2

2
1 NC#1 VCC 5

2
+3.3V_ALW K SB_PWRGD_D
DY A 2 A
U3003 Do Not Stuff
3 GND DY Y 4 1D8_NB_PWRGD 15

19,27,31,39,40,41,51 PM_SLP_S3# 1 A VCC 5

Do Not Stuff
2 B
2 D3004 3 4 SB_PWRGD 7,19
37 1.1V_RUN_PWRGD GND Y R3014
3 19 3D3_NB_PWRGD 1 2
SNLVC1G08DCKRG4-GP Do Not Stuff
27,29,38,40,41 RUNPWROK 1

BAW56-2-GP A00
R3015 8/24
Change R3014 from 0 ohm to short pad
35 CPU_VCORE_PWRGD 1 DY 2 1.1V_RUN_PWRGD 37
Do Not Stuff

A Main Source A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Power On Logic
Size Document Number Rev
A3
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 30 of 65
5 4 3 2 1
 5 4 3 2 1

Run Power
D D

+15V_ALW

1
+5V_ALW

10KR2J-3-GP
+5V_RUN

R3102
U3101
1 S D 8
+5V_AUX RUN_POWER_ON 2 S D 7
R3103 3 S D 6

2
1 2 5V_RUN_POWER_ON 4 G D 5

1
100KR2J-1-GP

SCD1U25V3KX-GP
R3101

C3101
0R2J-2-GP AO4468-GP

1
D
Q3102

2
G
2N7002A-7-GP

S
Q3101 +3.3V_RUN +3.3V_ALW
U3102
G 1 S D 8
19,27,30,39,40,41,51 PM_SLP_S3#
2N7002A-7-GP 2 S D 7
R3104 3 S D 6
1 2 3D3V_RUN_POWER_ON 4 G D 5

SCD1U25V3KX-GP

C3102
C
10KR2J-3-GP AO4468-GP C

1
2
+1.8V_RUN +1.8V_GFX_RUN
1

1
Do Not Stuff

10R3J-3-GP

+1.8V_RUN +1.8V_SUS
R3105

R3106

SC10U6D3V5KX-1GP
U3103
DY 1 S D 8
2 S D 7
2

1
C3103
3 S D 6
4 G D 5

2
FDS8880-NL-GP
R3107
1 2 1D8V_RUN_POWER_ON Id: 11.6A
D

+3.3V_RTC_LDO

SCD1U25V3KX-GP
Rds: 0.01ohm

C3104
Q3103 20KR2J-L2-GP

1
R3108
1 2 1.8V_GFX_RUN_EN# G
2N7002A-7-GP

2
100KR2J-1-GP
S

+15V_ALW
A00
+1.8V_GFX_RUN +1.8V_SUS

SC10U6D3V5KX-1GP
6

U3104
B Q3104 1 S D 8 B
1
10KR2J-3-GP

C3105
DMN66D0LDW-7-GP 2 S D 7

1
R3112

3 S D 6
4 G D 5
1

2
FDS8880-NL-GP
2

R3115 SCD1U25V3KX-GP
A00
C3106
27 1.8V_GFX_RUN_EN 1 2 1
Do Not Stuff 8/22
Change Q3101,Q3102,Q3103
R3117 Do Not Stuff from 84.27002.N31 to 84.2N702.E31
30,35,37,38 VCORE_RUN_EN 1
DY 2
2
Do Not Stuff

C3107

8/22
1

Change Q3104 from 84.27002.B3F to 84.DMN66.03F

DY 8/24
2

Change R3115 from 0 ohm to short pad

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Power Plane Enable
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 31 of 65
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

B
Batt Connecter AFTP188
1
1
PBAT_PRES1#
PBAT_SMBDAT1 B
AFTP189 1 PBAT_SMBCLK1
BATT1 AFTP191 1 +PBATT
AFTP190 +3.3V_RTC_LDO
11 D3201
GND +3.3V_RTC_LDO
GND 10 2
9 1 AFTP192 R3202
GND2 BAT_SCL
GND1 8 2 1 3
7 PBAT_ALARM# 1 AFTP193
BAT_ALERT 470KR2J-2-GP
SYS_PRES# 6 1
5 PBAT_PRES1# R3201
1 2 100R2J-2-GP BAT_IN# 27
BATT_PRS# PBAT_SMBDAT1 BAV99-4-GP
DAT_SMB 4 2 3 BAT_SDA 27,33
3 PBAT_SMBCLK1 RN3201 1 4 SRN100J-3-GP
CLK_SMB BAT_SCL 27,33
BATT2+ 2
1 +PBATT D3202
BATT1+
SCD1U25V3KX-GP

SC2200P50V2KX-2GP

2
1 2 BATT_SENSE BATT_SENSE 33
1

1
C3201

C3202

TYCO-CON9-1-GP BAT_SDA 3
20.80959.009 R3203
Do Not Stuff 1
2

BAV99-4-GP

D3203
X01 2
04/14 Del BAT_IN# 3
1.Del R3203 ,,reserve closed-gap.
1
A A
Main Source
BAV99-4-GP

D3204 Wistron Corporation

2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
PBAT_ALARM# 3
DY Title
1 DC IN/BATT CONN
Do Not Stuff Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 32 of 65
5 4 3 2 1
 5 4 3 2 1

+PBATT

SSID = Charger

SCD1U25V3KX-GP

SCD1U25V3KX-GP

SCD1U25V3KX-GP

SCD1U25V3KX-GP
Id=-12A
+3.3V_RTC_LDO
Adaptor In Soft-Start Circuit

EC3301

EC3302

EC3303

EC3304
Qg=-39nC

1
100KR2J-1-GP
Rdson=38mohm

2
PR3301
+DC_IN_SS
Layout Trace 250mil
Layout Trace 300mil

2
PU3302 Layout Trace 300mil
D 27 AC_IN# +SDC_IN +PWR_SRC +PBATT D
SC1U10V3KX-3GP

8 D S 1
7 D S 2 PR3302 PU3303

D
1
PC3301

6 D S 3 1 2 1 S D 8
5 D G 4 2 S D 7
D01R2512F-4-GP 3 S D 6
2

1
10KR2J-3-GP
G ACAV_IN AO4407A-GP +DC_IN_SS 4 G D 5

PR3303

Do Not Stuff

Do Not Stuff
AO4407A-GP
PQ3301
S

1
470KR2J-2-GP
2N7002A-7-GP

2
MAX8731_LDO

PG3301

PG3302

PR3304
DC_IN_D Id=-12A
PR3305 PR3306
DCIN_GATE1 1 2 DCIN_GATE2 1 2 Qg=-39nC

2
1
10KR2F-2-GP

Rdson=38mohm

2
PR3307

PQ3302 49K9R2F-L-GP 100KR2J-1-GP

D
X01 G

SCD1U25V3KX-GP

SCD1U25V3KX-GP
2N7002A-7-GP
2

PC3303

PC3302
ACAV_IN 04/14 Del

1
1.Del PR3309 ,reserve closed-gap. ACAV_IN
S G
1
15K4R2F-GP

PR3308

A00

2
MAX8731_CSSN
MAX8731_CSSP
+DC_IN_SS PQ3303

S
2N7002A-7-GP
1 PR3309 2
2

SC1U25V5KX-1GP

Do Not Stuff CHG_AGND CHG_AGND CHG_AGND

1
365KR3F-GP

PC3304

SC1U10V3KX-3GP
1
PR3310

SCD1U25V3KX-GP
A00 Id=9A

1
33R2J-2-GP

PC3305

Do Not Stuff
PU3301
Qg=-13nC

PR3311

SC10U25V6KX-1GP

PC3306

PC3307

PC3308
8/22

ASNS
C C
2

1
Change PQ3301,PQ3302,PQ3303 MAX8731_DCIN 22 28 Rdson=30mohm
2

2
DCIN CSSP

5
6
7
8
from 84.27002.N31 to 84.2N702.E31
DY
SCD1U25V3KX-GP

MAX8731_ACIN 2

D
D
D
D
2

2
ACIN
SCD01U50V2KX-1GP

CSSN 27
1
49K9R2F-L-GP

+3.3V_RTC_LDO 11 26 MAX8731_VCC CHG_AGND PU3304

VDD VCC
1
PR3312

PC3309

SI4800BDY-T1-GP
1
PC3310

PR3313 PD3301 PC3311 A00

25 MAX8731_BST 1 2MAX8731_BST1 K A 1 2 DELTA
2

BST

G
S
S
S
21 MAX8731_LDO 0R3J-0-U-GP 9/8
I=7A ∆L<50%
2

4
3
2
1
ACAV_IN LDO BAS516-1-GP SC1U10V3KX-3GP Change PC3306,PC3307,PC3314,PC3315
13 ACOK
CHG_AGND from 78.10622.53L to 78.10622.52L
Rdson=24mohm
24 MAX8731_DHI
CHG_AGND PG3303 BAT_SCL DHI PR3314 CHG_PWR +PBATT
27,32 BAT_SCL 1 2 10 SCL PL3301
1R3F-GP PC3312
1 2 SCD1U25V3KX-GP PR3315 Layout Trace 300mil
Do Not Stuff 23 MAX8731_LX 1 2 MAX8731_LX1 1 2 1 2
LX PC33131 2 SC220P50V2KX-3GP

Do Not Stuff

Do Not Stuff
PG3304
1 2 BAT_SDA 9 IND-5D8UH-GP D01R2512F-4-GP
27,32 BAT_SDA

K
SDA

SC10U25V6KX-1GP

PC3314

SC10U25V6KX-1GP

PC3315

PC3316
20 MAX8731_DLO
DLO

5
6
7
8

PD3302
Do Not Stuff
A00 DY DY

D
D
D
D

Do Not Stuff

Do Not Stuff
14 19

2
8/24 BATSEL PGND PU3305

A
1

1
Change PR3316 from 0 ohm to short pad MAX8731_CSIP SI4800BDY-T1-GP
CSIP 18

PG3305

PG3306
CHG_AGND Id=9A
PR3316 17 MAX8731_CSIN
Qg=-13nC

G
S
S
S
MAX8731_INP CSIN
1 2 8

4
3
2
1

2
27 AD_IA Do Not Stuff INP
Rdson=30mohm

B B
PR3317
1 2 10KR2F-2-GP MAX8731_CCV 6 CCV
1MAX8731_CCV1

MAX8731_CCI 5 16
MAX8731_CCS CCI FBSB
4 CCS
MAX8731_REF 3
MAX8731_DAC 7 REF PR3318
DAC BAT_SENSE
12 15 1 2
GND

GND FBSA
SCD1U16V2KX-3GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SC1U10V3KX-3GP

SCD1U16V2KX-3GP

SCD01U50V2KX-1GP
1
10KR2F-2-GP

PC3323

100R2F-L1-GP-U BATT_SENSE
BATT_SENSE 32
1

1
PR3319

PC3317

PC3318

PC3319

PC3320

PC3321

PC3322

MAX8731AETI-GP
29

+3.3V_ALW
2

PG3307 PR3320
2

1
Do Not Stuff
MAX8731_REF1 ADAPT_OC1
1
DY 2

PR3321
1 2
Do Not Stuff +5V_ALW
DY

Do Not Stuff

Do Not Stuff
Do Not Stuff CHG_AGND

2
PC3324

PC3325

Do Not Stuff
ADAPT_OC ADAPT_OC 27

1
PR3322
DY DY

1
10KR2J-3-GP
DY

PR3323
DY

2
MAX8731_INP PR3324 1 MAX8731_IINP1 A00
2
Do Not Stuff DY G

2
MAX8731_REF PR3325 1 8/22
2
DY +5V_ALW
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff PQ3304 Change PQ3304 from 84.27002.N31 to 84.2N702.E31

S
5
6
7
8
PC3326

PC3327

Do Not Stuff

PC3328

PC3329
Do Not Stuff

Do Not Stuff
1

A CHG_AGND A
Main Source

2IN+
2IN-
2OUT
VCC
PR3326

PR3327

DY DY DY DY PU3306
DY DY
2

Do Not Stuff
DY CHG_AGND Wistron Corporation
2

MAX8731_REF2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

CHG_AGNDCHG_AGND Taipei Hsien 221, Taiwan, R.O.C.
1
Do Not Stuff

1OUT
CHG_AGND ADAPT_TRIP_SEL
GND
1IN+
ADAPT_TRIP_SEL 27 1IN- Title
PR3328

DY ADAPT_TRIP_SEL=1 Adapter is 90w CHG_AGND Charger MAX8731A

4
3
2
1

Size Document Number Rev

ADAPT_TRIP_SEL=0 Adapter is 65w
2

Custom
CHG_AGND
Riya Discrete A00
Date: Tuesday, September 08, 2009 Sheet 33 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_3p3v5v

+3.3V_ALW +3.3V_ALWP +PWR_SRC +3.3V_5V_PWR_SRC

TPS51125RGER for +3.3V_ALW&+5V_ALW
PG3401 PG3402 +3.3V_RTC_LDO
2 1 1 2
+5V_ALWP +5V_ALW

1
100KR2J-1-GP
Do Not Stuff Do Not Stuff PG3405

PR3401
PG3403 PG3404 1 2
2 1 1 2
Do Not Stuff
D Do Not Stuff Do Not Stuff PG3408 D

2
PG3406 PG3407 1 2
2 1 1 2 51125_ENTRIP
Do Not Stuff
Do Not Stuff Do Not Stuff PG3411

G
PG3409 PG3410 1 2
2 1 1 2
A00 Do Not Stuff
Do Not Stuff Do Not Stuff 51125_ENTIP1 D S PG3414

Do Not Stuff
PG3412 PG3413 1 2

1
PC3402

137KR2F-1-GP
2 1 1 2

PR3402
Do Not Stuff
Do Not Stuff Do Not Stuff PQ3402 PG3416
DY 2N7002A-7-GP
PG3415 1 2

G
2
2 1 30 3V_5V_EN G

2
Do Not Stuff
Do Not Stuff A00 PG3417
PQ3401 D S 1 2

S
2N7002A-7-GP 51125_ENTIP2

Do Not Stuff
Do Not Stuff

1
PC3403
102KR2F-GP
PG3418
PQ3403

PR3421
1 2
2N7002A-7-GP
DY
A00 Do Not Stuff

2
PG3419

2
+PWR_SRC 8/22 1 2
Change PQ3401,PQ3402,PQ3403
+3.3V_5V_PWR_SRC from 84.27002.N31 to 84.2N702.E31 Do Not Stuff
+3.3V_5V_PWR_SRC

SC1U25V3KX-1-GP

PC3409
1
Do Not Stuff

SC10U25V6KX-1GP
PC3401

PC3404

SC10U25V6KX-1GP

SC10U25V6KX-1GP

Do Not Stuff
1

PC3410

PC3405

PC3406
DY D D
8
7
6
5

5
6
7
8

1
2

D
D
D
D
SIS412DN-T1-GE3-GP
D
D
D
D
PU3402

FDS8880-NL-GP

PU3403
DY

16

2
PU3401
Design Current = 4.784A Design Current = 7.117A

VIN
PeakCurrent = 6.835A Peak Current = 10.167A

G
S
S
S
S
S
S
G

C 7.519A <OCP<9.569A PC3407 PR3403 PR3404 PC3408 11.18A<OCP< 14.224A C

1
2
3
4

4
3
2
1
51125_VBST2 51125_VBST1
1 2 1 2 9 VBST2 VBST1 22 1 2 1 2 G S
+3.3V_ALWP S GSCD1U25V3KX-GP 0R3J-0-U-GP 51125_DRVH2 10 21 51125_DRVH1 0R3J-0-U-GP SCD1U25V3KX-GP +5V_ALWP
PL3401 DRVH2 DRVH1 PL3402
1 2 51125_LL2 11 20 51125_LL1 1 2
LL2 LL1
Do Not Stuff

ST220U6D3VDM-15GP

Do Not Stuff

Do Not Stuff

ST220U6D3VDM-15GP

Do Not Stuff
1
PTC3401

2D2R5F-2-GP SC330P50V3KX-GP

PTC3402

PTC3403
IND-3D3UH-57GP 51125_DRVL2 51125_DRVL1 IND-2D2UH-46-GP-U
D 12 DRVL2 DRVL1 19

1
PC3411

Do Not Stuff

PR3405

2D2R5F-2-GP SC330P50V3KX-GP

PC3412
D
1

8
7
6
5

5
6
7
8

1
PR3406

PG3421
D
D
D
D
SIS406DN-T1-GE3-GP
D
D
D
D
PU3404

FDS6690AS-GP

PU3405
51125_VO2 51125_VO1
DY 7 VO2 VO1 24 DY DY
1
PG3420
2

2
51125_FB2 5 2 51125_FB1

2
VFB2 VFB1
PC3413

PC3414
PR3407
2

1
51125_EN 13 3V_5V_POK

G
S
S
S
1 DY 2 23
S
S
S
G

EN0 PGOOD
1
2
3
4

4
3
2
1
Do Not Stuff 51125_ENTIP2 6 51125_ENTIP1
1 G S
2

2
51125_VREF ENTRIP2 ENTRIP1
S G 3 15
VREF GND
SCD22U6D3V2KX-1GP

PC3415

51125_TONSEL
X01 4 TONSEL GND 25 X01
1

1
Do Not Stuff
04/06 Stuff 04/09 Stuff
1
Do Not Stuff Do Not Stuff

PR3409 PC3417
1.Stuff PR3405,PC3413 51125_VCLK 1.Stuff PR3406,PC3414
14 18
2

SKIPSEL VCLK

1
PR3408 PC3416

30K9R2F-GP
51125_SKIPSEL DY
1
6K65R2F-GP

PR3411
VREG3

VREG5
PR3410

DY

1 2
TPS51125RGER-GP 51125_FB1_R
1 2

Do Not Stuff
51125_FB2_R 74.51125.073

2
+3.3V_RTC_LDO
DY
2

17

DY

2
+3.3V_RTC_LDO +5V_AUX
2

1
100KR2J-1-GP
PG3422 PG3423

1
PR3412

20KR2F-L-GP
3D3V_AUX_51125

1 2 1 2

PR3414
5V_AUX_51125
1
10KR2F-2-GP

PR3413 1 Do Not Stuff Do Not Stuff

51125_VREF DY 2
PR3415

Do Not Stuff Close to VFB Pin (pin2)

2
+3.3V_RTC_LDO 1 PR3416 2 3V_5V_POK 27,30
SC10U10V5KX-2GP

SC10U10V5KX-2GP

Do Not Stuff
2

B B
PC3418

PC3419

51125_VREF 1 PR3417 2
1

Do Not Stuff
Close to VFB Pin (pin5) I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
PR3418 1
+3.3V_RTC_LDO DY 2 Inductor: 2.2uH PCMC063T-2R2MN 18mohm Isat =14Arms CYNTEC/68.2R210.20B
2

2
Do Not Stuff
SC1KP50V2KX-1GP
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L

SCD1U25V3KX-GP

SCD1U25V3KX-GP
PD3402

PC3430

PC3420

PC3421
PR3419 1
DY 2 1 BAT54-7-F-GP O/P cap: 150U 6.3V PSLB20J157M(45) 45mOhm 1.374rms NEC_TOKIN/77.C1571.09L

1
Do Not Stuff
H/S: FDS8880-NL SO-8/9.6mohm/[email protected]/ 84.08880.037
L/S: FDS6690AS SO-8/ 12mohm/[email protected]/ 84.06690.E37
2

3
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L X01
Inductor: 3.3UH PCMC063T3R3MN CYNTEC DCR 28~30mohm Isat =13.5Arms 68.3R310.20A 04/14 Del
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L 1.Del PR3416,PR3417 ,reserve closed-gap.
3

3
H/S:VISHAY SIS412DN-T1-GE3/ 24mohm/[email protected]/ 84.00412.037 PD3401 PD3403
L/S:VISHAY SIS406DN-T1-GE3/ 11.5mohm/[email protected]/ 84.00406.037 BAT54S-7F-GP BAT54S-7F-GP
2

1
TONSEL CH1 CH2 SKIPSEL VREG3 or VREG5 VREF(2V) GND
GND 200kHz 265kHz Operating OOA Auto Skip Auto Skip
VREF 245kHz 305kHz
Mode PWM only +15V_ALW

PG3424
+15V_ALW_P +15V_ALW_P +5V_ALWP
RT9013 for +1.2V_ALW
BZT52C15S-GP

SC1U25V3KX-1-GP

SCD1U25V3KX-GP

SCD1U25V3KX-GP
VREG3 300kHz 375kHz 1 2
K

PC3422

PC3423

PC3424
1

1
PD3404

VREG5 365kHz 460kHz EN0 Open 820kΩ to GND GND Do Not Stuff +3.3V_ALW PU3406 +1.2V_ALW

Operating 1 5
2

VIN VOUT

SC1U10V3KX-3GP

Do Not Stuff

Do Not Stuff

Do Not Stuff
enable both enable both LDOs, disable all PR3420 2
Mode
A

1.2VALW_EN3 GND

PC3425

PC3426

PC3428

PC3429
LDOs, VCLK on VCLK off and circuit 1 2 EN NC#4 4

1
Do Not Stuff
and ready to DY

1
ready to turn on
turn on switcher channels RT9013-12PB-GP
DY DY
DY

2
switcher

2
channels

A PC3427 A

A00 Do Not Stuff

8/22
Change PR3420 from 0 ohm to short pad

Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VREG : +3.3V_ALW&+5V_ALW
Size Document Number Rev
A2
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 34 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = CPU.Regulator ISL6265HRTZ-T for +VCC_CORE&+VDDNB +PWR_SRC +VDDNB_PWR_SRC

PC3502
1 2 I/P cap: 10U 25V K1206 X5R/ 78.10622.52L PG3502
+5V_RUN 1 2
PR3501 SC33P50V2JN-3GP Inductor:4.7uH PCMC063T-4R7MN 35mohm Isat =10Arms CYNTEC/68.4R710.20D
1 2 O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01 Do Not Stuff

SC1U16V3KX-2GP
PR3502 PC3503 H/S:VISHAY SIS412DN-T1-GE3/ 24mohm/[email protected]/ 84.00412.037

PC3501
2R3J-GP 1 2 6265_FB_NB_R 1 2
L/S:VISHAY SIS406DN-T1-GE3/ 11.5mohm/[email protected]/ 84.00406.037

1
44K2R2F-1-GP SC1200P50V2KX-1GP

SC10U25V6KX-1GP

SC4D7U25V5MX-1GP
2

PC3505

PC3506
X01

1
PC3504

5
6
7
8
1 2 04/07 Change

D
D
D
D
SIS412DN-T1-GE3-GP

PU3502
GNDA_VCORE 1.Change PC3505 Footprint from 1210 to 1206.
D D

2
+PWR_SRC SC1KP50V2KX-1GP
PR3503 PR3504 +VDDNB +VDDNB
1 2 1 2 GNDA_VCORE
Design Current: 2.1A

SCD1U50V3KX-GP

1
Peak current: 3A

PC3507

10R2J-2-GP
2R3J-GP 22KR2F-GP

G
S
S
S
X01

PR3505
OCP_min:5A

4
3
2
1
04/14 Del
1.Del PR3509 ,reserve closed-gap.

2
PR3506 UGATE_NB

2
1 2 +VDDNB
CPU_VDDNB_RUN_FB_H 10
+3.3V_RUN +5V_RUN +3.3V_RUN Do Not Stuff PR3508 PC3508 PL3501

CPU_VDDNB_RUN_FB_H_R
GNDA_VCORE 1 PR3507 2 PHASE_NB BOOT_NB 1 2BOOT_NB_R PHASE_NB
X01 1 2 1 2

SC1U10V2KX-1GP

SC4D7U6D3V5KX-3GP

SE330U2VDM-L-GP

PTC3501
3K32R2F-GP

PC3509

PC3510
2 04/06 Change 0R3J-0-U-GP SCD22U25V3KX-GP IND-4D7UH-88-GP

1
PHASE_NB_R
LGATE_NB 1.Change PR3507 from 4.53k to 3.32k.

1
Do Not Stuff

PR3510

Do Not Stuff
PR3509

5
6
7
8
6265_COMP_NB

PR3511
PHASE_NB

6265_FSET_NB
Do Not Stuff DY

2
D
D
D
D
SIS406DN-T1-GE3-GP

PU3503
DY

6265_FB_NB
UGATE_NB

6265_VCC
1

6265_VIN
PR3514

PHASE_NB_RC2
1

1
10KR2J-3-GP

Do Not Stuff

CPU_VDDNB_RUN_FB_L_R 1 2 CPU_VDDNB_RUN_FB_L 10
PR3512

PR3513

Do Not Stuff

S
S
S
G
DY
1

1
Do Not Stuff

10R2F-L-GP

4
3
2
1
+PWR_SRC +VCC_CORE0_PWR_SRC

6265_OFS/VFIXEN
PR3515

PR3516
2

GNDA_VCORE PG3503
DY

49
48
47
46
45
44
43
42
41
40
39
38
37
LGATE_NB 1 2

Do Not Stuff

PC3511

Do Not Stuff
X01

GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
2

PTC3502
Do Not Stuff
04/14 Del PG3504
DY

1
1.Del PR3517,PR3518 reserve closed-gap.
1 2

2
GNDA_VCORE
1 36 BOOT_NB DY Do Not Stuff

2
OFS/VFIXEN BOOT_NB BOOT0 PG3505
30 CPU_VCORE_PWRGD 2
3
PGOOD BOOT0 35
34 UGATE0
X01 1 2
10 CPU_PWRGD_SVID_REG PWROK UGATE0
1 PR3517 2 Do Not Stuff CPU_SVD_R 4 33 PHASE0 06/11 modify
10 CPU_SVD SVD PHASE0 1.Change PU3501 Ver. from ISL6265HRTZ to ISL6265AHRTZ
PR3519 1 PR3518 2 Do Not Stuff CPU_SVC_R 5 32 +5V_RUN Do Not Stuff
10 CPU_SVC SVC PGND0
1 2 VCC_CORE_EN 6 31 LGATE0
30,31,37,38 VCORE_RUN_EN ENABLE LGATE0
Do Not Stuff 1 PR3520 293K1R2F-L-GP 6265_RBIAS 7 30
RBIAS
PU3501 PVCC

SC2D2U10V3KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC4D7U25V5MX-1GP

SCD1U25V2ZY-1GP
1PR3521 224KR2F-GP 6265_OCSET 8 29 LGATE1
OCSET LGATE1

PC3512

PC3513

PC3514
C 6265_VDIFF0 9 28 D C
VDIFF0 PGND1

PC3515

PC3516

PC3517
6265_FB0 10 ISL6265AHRTZ-T-GP 27 PHASE1
FB0 PHASE1

5
6
7
8

1
6265_COMP0 11 26 UGATE1 +VCC_CORE0
COMP0 UGATE1

D
D
D
D
SIR462DP-T1-GE3-GP

PU3504
GNDA_VCORE 6265_VW0 12 25 BOOT1
Design Current: 12.6A

2
VW0 BOOT1
Do Not Stuff

2
Peak current: 18A
PC3518

COMP1
VDIFF1
VSEN0

VSEN1
1

PG3501
RTN0
RTN1

OCP_min:24A
ISN0

ISN1
ISP0

VW1
ISP1
FB1

DY 1 2

G
S
S
S
2

Do Not Stuff
13
14
15
16
17
18
19
20
21
22
23
24

4
3
2
1
+VCC_CORE0
6265_COMP1

GNDA_VCORE G S
6265_VDIFF1
6265_VSEN0

6265_VSEN1

6265_VW1
6265_RTN0
6265_RTN1

ISP0 ISN1 UGATE0 PL3502

6265_FB1

ISN0 ISP1 PHASE0 1 2

+1.8V_SUS

SE330U2VDM-L-GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
1
16KR2F-GP

PTC3503

PTC3504

PTC3505
IND-D36UH-9-GP

1
+VCC_CORE0+VCC_CORE1

Do Not Stuff

PR3525
PR3523 PC3519 D
1

1
Do Not Stuff

PR3524
BOOT0 1 2 BOOT0_R 1 2

5
6
7
8
PR3522

A00 DY
1

D
D
D
D
10R2J-2-GP

10R2J-2-GP

SI7658ADP-T1-GE3-GP

PU3505
1R3J-L1-GP SCD22U25V3KX-GP PR3527
DY

2
PR3528

PR3526

8/22 1 2

1PHASE0_RC 2
Change PR3506,PR3514,PR3519,PR3529,PR3530,PR3532,PR3534 4K02R2F-GP
2

from 0 ohm to short pad PC3520

1 2
2

9/3

G
S
S
S

Do Not Stuff
Change PR3520 from 100K to 93.1K
10 CPU_VDD0_RUN_FB_H 1PR3529 Do
2 Not Stuff SCD1U16V3KX-3GP

4
3
2
1
Change PR3521 from 18K to 24K

PC3521
10 CPU_VDD0_RUN_FB_L 1PR3530 Do
2 Not Stuff G S PR3531 PR3533
LGATE0 ISP0_R
1PR3532 Do
2 Not Stuff
1 DY 2 1 DY 2
10 CPU_VDD1_RUN_FB_L DY

ISP0
CPU_VDD1_RUN_FB_H 1PR3534 Do
2 Not Stuff Do Not Stuff Do Not Stuff

ISN0
10 CPU_VDD1_RUN_FB_H

2
1

1
10R2J-2-GP

10R2J-2-GP
PR3535

PR3536

Parallel +PWR_SRC +VCC_CORE1_PWR_SRC

PG3506
2

1 2

Do Not Stuff

PTC3506
Do Not Stuff
Close to CPU socket PG3507

1
1 2
B B
6265_FB0_C DY Do Not Stuff

2
PG3508
PR3537 PC3522 PC3523 PC3524 PR3538 PC3525 PC3526 PC3527 1 2
1 2 1 2 1 2 1 2 1 2 6265_FB1_C 1 2 1 2 1 2
249R2F-GP Do Not Stuff
SC4700P50V2KX-1GP SC180P50V2JN-1GP SC1KP50V2KX-1GP 249R2F-GP SC4700P50V2KX-1GP SC180P50V2JN-1GP SC1KP50V2KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC4D7U25V5MX-1GP

SCD1U50V3KX-GP
PC3528

PC3530

PC3531

PC3529

PC3532
PR3542 +VCC_CORE1
PR3539 PR3540 PR3541 D Design Current: 12.6A

5
6
7
8

1
1 2 1 2 1 2 1 2

D
D
D
D
Peak current: 18A
SC1200P50V2KX-1GP

SC1200P50V2KX-1GP

SIR462DP-T1-GE3-GP

PU3506
1

1
54K9R2F-L-GP

PC3533

54K9R2F-L-GP

PC3534

1KR2F-3-GP 6K81R2F-1-GP 1KR2F-3-GP 6K81R2F-1-GP OCP_min:24A

2
1

1
PR3543

PR3544
2

G
S
S
S
2

6265_FB0_R 6265_FB1_R

4
3
2
1
G S +VCC_CORE1
UGATE1 PL3503
+VCC_CORE0 PHASE1 1 2

SE330U2VDM-L-GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP
CPU TYPE PR3536 PR3507

1
16KR2F-GP

PTC3507

PTC3508

PTC3509
D IND-D36UH-9-GP
1
Do Not Stuff

Do Not Stuff

PR3546

PR3547
PR3545 PC3535
*Griffin 10 ohm 3K32 ohm

5
6
7
8

1
PR3551

BOOT1 1 BOOT1_R 1
2 2 DY

D
D
D
D
SI7658ADP-T1-GE3-GP

PU3507
Tigris 10K ohm 4K53 ohm DY 1R3J-L1-GP SCD22U25V3KX-GP PR3548

PHASE1_RC 2

2
*DEFAULT 1 2
2

CPU_VDD1_RUN_FB_H 4K02R2F-GP
PC3536
X01

G
S
S
S
04/06 Change Spec
For power team test 1 2

4
3
2
1

Do Not Stuff
1.Reduced OCP setting value SCD1U16V3KX-3GP
G S
PR3550 PR3549

1
PC3537
LGATE1 ISP1_R 1
1 2 DY 2 DY
DY Do Not Stuff Do Not Stuff

ISP1

ISN1
A A

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Main Source

Inductor: 0.36UH PCMC104T-R36MN1R05J CYNTEC DCR 1.05(+5%~-5%)mohm
Isat =60Arms 68.R3610.20C Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01 Taipei Hsien 221, Taiwan, R.O.C.
H/S:VISHAY SiR462DP/ POWERPAK-8.2/810mOhm/ 4.5Vgs/ 84.00462.037 Title
L/S:VISHAY SI7658ADP/ POWERPAK-2.3/ 2.8mOhm/ 4.5Vgs/ 84.07658.037 VREG : +VCC_CORE&+VDDNB
Size Document Number Rev
A2
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 35 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_+1.1V_RUN
+PWR_SRC +1.1V_RUN_PWR_SRC

D
PG3701
1 2 RT8209BGQW for +1.1V_RUN D
Do Not Stuff
PG3702
+1.1V_RUN_PWR_SRC
1 2 PWM TYPE PR3701 PR3702
+5V_ALW
Do Not Stuff
*RT8209B 10 ohm 4.7 ohm

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP

Do Not Stuff
PG3703

PC3704

PC3702

PC3703

PC3705
1 2 TPS51117 300 ohm 0 ohm

1
SC1U10V3KX-3GP

1
PC3701

10R3J-3-GP
Do Not Stuff *DEFAULT DY
1

PR3701
PG3704

2
1 2

5
6
7
8
2

D
D
D
D
FDS8880-NL-GP

PU3702
Do Not Stuff

2
PG3705

SC1U10V3KX-3GP

PC3706
1 2

1
PR3702 PC3707 Design Current = 8.33A
Do Not Stuff +5V_ALW 1 2 +1.1V_LL1 1 2
Peak Current = 11.9A

G
S
S
S
2
4D7R3J-L1-GP SCD1U25V3KX-GP 13.09A<OCP < 16.6A
A

4
3
2
1
RB551V30-GP

PD3701

PU3701
+1.1V_VOUT_V5FILT 4 13 +1.1V_DRVH
VDD UGATE +1.1V_DRVL +1.1V_RUN_P +1.1V_RUN
10 VDDP LGATE 9
PL3701 PG3706
K

+1.1V_VOUT_VFB 5 12 +1.1V_LL 1 2 1 2
FB PHASE

SC4D7U6D3V5KX-3GP

SCD1U10V2KX-4GP

SE330U2D5VM-GP

PTC3701
+1.1V_VOUT_BST 14 BOOT

1
Do Not Stuff

Do Not Stuff

PC3708

PC3709
3 +1.1V_VOUT IND-1D5UH-23-GP Do Not Stuff
VOUT

1
PR3704
27 1.1V_GFX_RUN_EN 1 PR3713 2 Do Not Stuff PGOOD 6 1.1V_RUN_PWRGD 30 PG3708
PR3703 1 2 Do Not Stuff +1.1V_VOUT_EN
30,31,35,38 VCORE_RUN_EN DY 1 EN/DEM GND 7
DY 1 2

5
6
7
8

1
PG3707
C
PR3705 1 2 300KR2F-GP +1.1V_VOUT_TON 2 8 C

2
TON PGND

D
D
D
D
Do Not Stuff

FDS6676AS-GP

PU3703
+1.1V_VOUT_TRIP 11 15 Do Not Stuff

2
CS NC#15
PC3710

PG3709
1

1
7K87R2F-GP

Do Not Stuff

PC3711
RT8209EGQW-GP 1 2

2
1
PR3707

DY Do Not Stuff
DY
2

G
S
S
S
PG3710
X01

2
+1.1V_VOUT 1 2
2

4
3
2
1

Do Not Stuff
06/25 modify

1
18KR2F-GP
1.Change PU3701 to new version Do Not Stuff

1
PR3709

PC3712
A00 PG3711
DY 1 2
8/24

2
Change PR3713 from 0 ohm to short pad Do Not Stuff

2
+1.1V_VOUT_VFB PG3712
1 2

1
36K5R2F-GP
Close to VFB Pin (pin5)

PR3710
Do Not Stuff
PG3713
Vout=0.75V*(R1+R2)/R2 1 2

2
Do Not Stuff
PG3714
1 2

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Do Not Stuff

PG3715
Inductor: 1.5UH PCMC063T-1R5MN 18Arms CYNTEC/ 68.1R510.10K 1 2
O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L
Do Not Stuff
B
H/S: FDS8880-NL SO-8/9.6mohm/[email protected]/ 84.08880.037 B
L/S: FDS8672S SO-8/ 5.3mOhm/[email protected]/ 84.08672.A37
Ton = 300KOhm --> 250KHz
+1.1V_GFX_RUN

PG3716
1 2

+3.3V_ALW Do Not Stuff

PG3717
1 2

1
10KR2J-3-GP

PR3711
Do Not Stuff
PG3718
1 2

2
Do Not Stuff

A00
8/22
Change PQ3701 from 84.27002.B3F to 84.DMN66.03F

4
PQ3701 8/24
DMN66D0LDW-7-GP Change PR3712 from 64.10R05.55L to 63.10033.15L
Change PR3711 from 64.10025.6DL to 63.10334.1DL
+1.1V_GFX_RUN

3
A PR3712 A
Main Source
1 2

10R3J-3-GP
Wistron Corporation
+1.1V_VOUT_EN 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VREG : +1.1V_RUN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 37 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_+1.2V_RUN

+PWR_SRC +1.2V_RUN_PWR_SRC +1.2V_RUNP +1.2V_RUN

PG3801 PG3802
1 2 1 2
D Do Not Stuff Do Not Stuff D
PG3803 PG3804
1 2 1 2

Do Not Stuff Do Not Stuff

PG3805
1 2

Do Not Stuff
PG3806
1 2

Do Not Stuff
PG3807
1 2

Do Not Stuff

RT8209BGQW for +1.2V_RUN

C
+5V_ALW C
+1.2V_RUN_PWR_SRC
PWM TYPE PR3801 PR3802
SC1U10V3KX-3GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP

Do Not Stuff
*RT8209B 10 ohm 4.7 ohm
1
PC3801

10R3J-3-GP

PC3802

PC3803

PC3804
1

1
PR3801

TPS51117 300 ohm 0 ohm

DY

5
6
7
8
*DEFAULT
2

2
D
D
D
D
SIS412DN-T1-GE3-GP

PU3802
2
SC1U10V3KX-3GP

PC3805

Design Current = 3.279A

1

+5V_ALW Peak Current = 4.685A

PR3802 PC3806

G
S
S
S
5.154A<OCP<6.559A
2

1 2 +1.2V_LL1 1 2
A

4
3
2
1
RB551V30-GP

PD3801

PU3801 4D7R3J-L1-GP SCD1U25V3KX-GP

+1.2V_V5FILT 4 13 +1.2V_DRVH +1.2V_RUNP
VDD UGATE +1.2V_DRVL
10 VDDP LGATE 9
PL3801
K

+1.2V_VFB 5 12 +1.2V_LL 1 2
FB PHASE

SCD1U10V2KX-4GP

ST220U2VBM-3GP

PTC3801
+1.2V_VBST 14 BOOT

1
Do Not Stuff

Do Not Stuff

PC3807
3 +1.2V_VOUT IND-4D7UH-88-GP
VOUT

1
PR3804
PGOOD 6 RUNPWROK 27,29,30,40,41

5
6
7
8
PR3803 1 2 15KR2J-1-GP +1.2V_EN
30,31,35,37 VCORE_RUN_EN 1 EN/DEM GND 7
DY

1
D
D
D
D
SIS406DN-T1-GE3-GP

PU3803

PG3808
PR3805 1 2 300KR2F-GP +1.2V_TON 2 8

2
TON PGND
SCD1U16V2KX-3GP

+1.2V_TRIP 11 15

2
CS NC#15
PC3808
1

1
6K34R2F-GP

Do Not Stuff

PC3809
RT8209EGQW-GP

2
1
PR3807

B B

S
S
S
G
DY
2

4
3
2
1

2
X01
2

06/25 modify
1.Change PU3801 to new version +1.2V_VOUT
Vout=0.75V*(R1+R2)/R2

Do Not Stuff
1
18KR2F-GP

PC3810
1
PR3809
DY

2
2
+1.2V_VFB
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

1
30KR2F-GP
Inductor: 4.7uH PCMC063T-4R7MN 35mohm Isat =10Arms CYNTEC/68.4R710.20D

PR3810
O/P cap: 220U 2.5V TEPSLB20E227M(35)8R 35mOhm 1.558Arms NEC/TOKIN/ 77.C2271.26L
H/S:VISHAY SIS412DN-T1-GE3/ 24mohm/[email protected]/ 84.00412.037

2
L/S:VISHAY SIS406DN-T1-GE3/ 11.5mohm/[email protected]/ 84.00406.037
Ton = 300KOhm --> 250KHz

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VREG : +1.2V_RUN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 38 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_+1.8V RT8209BGQW for +1.8V_SUS

+PWR_SRC +1.8V_SUS_PWR_SRC

PG3901
1 2
+1.8V_SUS_P +1.8V_SUS
Do Not Stuff PG3904
PG3902 1 2
1 2
D Do Not Stuff D
Do Not Stuff +1.8V_SUS_PWR_SRC PG3906
+5V_ALW PG3903 1 2
1 2
PWM TYPE PR3901 PR3902 Do Not Stuff

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP

SCD1U50V3KX-GP

SC4D7U25V5KX-GP
Do Not Stuff PG3908
SC1U10V3KX-3GP

PC3902

PC3903

PC3904

PC3905

PC3906
PG3905
*RT8209B 10 ohm 4.7 ohm 1 2

1
PC3901

10R3J-3-GP
1 2
1

PR3901
TPS51117 300 ohm 0 ohm Do Not Stuff
Do Not Stuff PG3909

2
5
6
7
8
*DEFAULT PG3907 1 2
2

D
D
D
D
AOL1426-GP

PU3902
1 2

2
Do Not Stuff

SC1U10V3KX-3GP

PC3907
Do Not Stuff PG3910

1
PR3902 PC3908 1 2
+5V_ALW +1.8V_LL1 Design Current = 12.45A
1 2 1 2 X01

G
S
S
S
Do Not Stuff
2
4D7R3J-L1-GP SCD1U25V3KX-GP 04/03 modify Peak Current = 17.786A PG3911
A

4
3
2
1
RB551V30-GP

1.Change PL3901 form 1.0uH to 1.5uH

19.565A<OCP<24.9A 1 2
PD3901

PU3901
+1.8V_V5FILT 4 13 +1.8_DRVH +1.8V_SUS_P Do Not Stuff
VDD UGATE +1.8V_DRVL PG3912
10 VDDP LGATE 9
PL3901 1 2
K

+1.8V_FB 5 12 +1.8V_LL 1 2
FB PHASE

SCD1U10V2KX-4GP

SC4D7U6D3V5KX-3GP

SE330U2D5VM-GP

SE330U2D5VM-GP
+1.8V_BST 14 Do Not Stuff
BOOT

PTC3902

PTC3901
3 +1.8V_VOUT IND-1D5UH-34-GP PG3913
VOUT

PC3918

PC3909
PR3903 1 2 Do Not Stuff
19,27,30,31,40,41,51 PM_SLP_S3# DY PGOOD 6 1.8V_SUS_PWRGD 30 1 2

1
Do Not Stuff
PR3904 1 2 Do Not Stuff +1.8V_EN 1 7
19,27,51 PM_SLP_S5# EN/DEM GND

5
6
7
8

PR3907

Do Not Stuff
PR3905 1 2 300KR2F-GP +1.8V_TON 2 8 Do Not Stuff
TON PGND

D
D
D
D
AOL1412-GP

PU3903
+1.8_TRIP PG3915
C 11 15
DY C

2
CS NC#15

1
PG3914
X01 1 2
1
Do Not Stuff
PC3911

RT8209EGQW-GP

2
1

8K2R2F-1-GP
PR3908

02/23 modify Do Not Stuff

X01

Do Not Stuff
1.stuff PR3904 and empty PR3903 PG3916
DY

2
PC3910
G
S
S
S
06/25 modify 1 2
2

1
1.Change PU3901 to new version
A00
2

4
3
2
1
Do Not Stuff
8/24 X01 DY PG3917

2
Change PR3904 from 0 ohm to short pad 02/23 Change BOM 1 2
1.Change PR3908 from 7.32k to 8.2k .
Do Not Stuff
+1.8V_VOUT PG3918
1 2

1
42K2R2F-L-GP
Do Not Stuff

PR3910
PG3919
1 2

Do Not Stuff
X01

2
PG3920
+1.8V_FB 02/23 modify 1 2
1.Stuff PR3910,PR3911
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Do Not Stuff
Inductor: 1.5UH PCMC104T-1R5MN DCR: 3.8 ~4.2mohm Isat = 33Arms CYNTEC/ 68.1R510.10J

1
30KR2F-GP
PG3921

PR3911
O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L 1 2
H/S: AOL1426 PowerPAK/ 10.2mohm/[email protected]/84.01426.037 Do Not Stuff
L/S: AOL1412 PowerPAK/ 3.8mohm/[email protected]/ 84.01412.037 PG3922

2
Switching freq-->250KHz 1 2
B
Red: X01 Change Do Not Stuff
B

+3.3V_ALW

X01
SSID = PWR.Plane.Regulator_+0.9V

1
R3900 04/15 modify
10KR2J-3-GP 1.Use discharge circuit for power on/off.

TPS51100 for +0.9V_VTT

2
N_P5

+5V_ALW +1.8V_SUS Design Current = 1.225A A00

4
Peak Current = 1.75A PQ3900 8/22
SC1U10V2KX-1GP

SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

Change PQ3900 from 84.27002.B3F to 84.DMN66.03F

DMN66D0LDW-7-GP
PC3912

PC3913

PC3914

R3901
1

10R2J-2-GP

3
+1.8V_SUS
2

N_P3 1 2
PU3905
PM_SLP_S5#
PR3912 10 1 +0.9V_VTT_P +0.9V_VTT_P +0.9V_VTT
A DDR_VREF_ON VIN VDDQSNS PG3923 A
19,27,51 PM_SLP_S5# 1 2 9 S5 VLDOIN 2 Main Source
Do Not Stuff 8 3 1 2
GND VTT
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

1PR3913 2 0.9V_VTT_ON 7 S3 PGND 4

PC3915

PC3916

Do Not Stuff Do Not Stuff

+V_DDR_VREF_M 6 VTTREF VTTSNS 5
Wistron Corporation
1

1
SCD1U10V2KX-4GP

PG3924
GND

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

PC3917

X01 1 2
1

Taipei Hsien 221, Taiwan, R.O.C.

2

TPS51100DGQR-GP Do Not Stuff

11

03/31 modify Title

2

1.Change +0.9V_VTT power enable connect with SLP_S5

VREG : +1.8V_SUS&+0.9V_VTT
A00 Size Document Number Rev
Custom
8/22
Change PR3912,PR3913 from 0 ohm to short pad Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 39 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Plane.Regulator_1p5v

D
APL5930KAI for +1.5V_RUN D

+5V_ALW +1.8V_SUS

SC1U10V3KX-3GP

PC4001

SC10U6D3V5MX-3GP

PC4002

Do Not Stuff

PC4003
1

1
DY

2
+1.5V_RUN +/- 5%
Design Current: 0.805A
Peak current 1.15A

6
PU4001

VCNTL
27,29,30,38,41 RUNPWROK 7 POK VIN#5 5
9 +1.5V_RUN
PR4001 VIN#9
19,27,30,31,39,41,51 PM_SLP_S3# 1 2 1D5V_RUN_EN 8 3
EN VOUT#3

Do Not Stuff

SCD01U16V2KX-3GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
VOUT#4 4

PC4004

PC4005

PC4006

PC4007
2K2R2J-2-GP
Vo=0.8*(1+(R1/R2))

1
1KR2F-3-GP

PR4002
DY 2

GND
FB

2
APL5930KAI-TRG-GP

2
SO-8-P

1
1K13R2F-1-GP
C C

PR4003
2
Vout=0.8V*(R1+R2)/R2

SSID = PWR.Plane.Regulator_2p5v

B B

RT9013-25PB for +2.5V_RUN

+3.3V_RUN PU4002 +2.5V_RUN

1 VIN VOUT 5
SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP
2 GND
+2.5V_RUN +/- 5%
PC4008

PC4010
1PR4004 2 2D5V_RUN_EN 3 EN NC#4 4 Design Current: 175mA
1

1
PC4009

Do Not Stuff
Do Not Stuff

Peak current 250mA

1

RT9013-25PB-GP
DY
2

2
2

A00
8/22
Change PR4004 from 0 ohm to short pad

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VREG : +1.5V_RUN&+2.5V_RUN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 40 of 65
5 4 3 2 1
 A B C D E

+PWR_SRC +VGA_PWR_SRC +VCC_GFX_CORE_P +VCC_GFX_CORE

PG4101 PG4102
SSID = Video.PWR.Regulator TPS51117RGYR for +VCC_GFX_CORE 1 2 1 2

Do Not Stuff Do Not Stuff

PG4103 PG4104
1 2 1 2

+5V_ALW Do Not Stuff +VCC_GFX_CORE +/- 5% Do Not Stuff

PG4105 Design Current: 8.232A PG4106
X01 PU4102
1 2 Peak current 11.76A 1 2

4 02/23 modify 74LVC1G07GW Do Not Stuff 12.936<OCP<16.464 Do Not Stuff 4

1.change PR4103 from 3.3 ohm to 300 ohm PG4107
1 B
VCC 5 1 2
2 +VGA_PWR_SRC
27 GFX_CORE_EN A GFX_CORE_ON_R Do Not Stuff
+5V_ALW 3
DY Y 4
PG4108
GND
1 2

1
Do Not Stuff

SC2200P50V2KX-2GP

SCD1U25V3KX-GP

SC10U25V6KX-1GP

SC10U25V6KX-1GP
Do Not Stuff
SC1U10V3KX-3GP

PR4102
Do Not Stuff

1
PC4102

300R3-GP

PC4103

PC4104

PC4101

PC4105
Please place near KBC U2701. PG4109
DY
1

5
6
7
8

1
PR4103
1 2

D
D
D
D
FDS8880-NL-GP

PU4103
2
Do Not Stuff
2

2
2 PG4110
51117C_V5FILT 1 2
SC1U10V3KX-3GP

PC4106
+5V_ALW PR4104 PC4107

G
S
S
S
Do Not Stuff
1

1 2 51117C_LL1 1 2 PG4111

4
3
2
1
1 2
A
RB551V30-GP

0R3J-0-U-GP SCD1U25V3KX-GP
2
PD4101

Do Not Stuff
PU4101 PG4112
4 13 51117C_DRVH +VCC_GFX_CORE_P 1 2
V5FILT DRVH 51117C_DRVL
10 9
K

V5DRV DRVL PL4101 Do Not Stuff

51117C_VFB 5 12 51117C_LL 1 2 PG4113
VFB LL

SCD1U10V2KX-4GP

SE330U2D5VM-GP

PTC4101

SE330U2D5VM-GP

PTC4102
51117C_VBST 14 1 2
VBST

PC4108
3 51117_VOUT_VGA IND-1D5UH-34-GP
VOUT

1
Do Not Stuff

Do Not Stuff
GFX_CORE_EN 1 PR4105 2 Do Not Stuff 6 Do Not Stuff
PGOOD VCC_GFX_CORE_PWRGD 30

5
6
7
8

PR4107
3 PR4106 1 DY 2 Do Not Stuff GFX_CORE_ON_R 1 7 PG4115 3
19,27,30,31,39,40,51 PM_SLP_S3# EN_PSV GND

D
D
D
D
FDS6676AS-GP

PU4104
PR4108 1 2 300KR2F-GP 51117C_LL_TON 2 TON PGND 8
DY 1 2

2
1
51117C_TRIP 11 15
TRIP GND
Do Not Stuff

PG4114
Do Not Stuff
f=250kHz,Ton resister =300k

2
1
PC4109
7K87R2F-GP

TPS51117RGYR-GP PG4116
1

PR4109

Do Not Stuff
1 2

2
G
S
S
S
DY

1
PC4110
Do Not Stuff
2

4
3
2
1
DY
2

2
A00 51117_VOUT_VGA

1
10KR2F-2-GP
8/24

PR4110
Change PR4105 from 0 ohm to short pad

X01

2
51117C_VFB 04/14 Del
1.Del PR4117,PR4122 ,reserve closed-gap.
PWRCNTL_0 PWRCNTL_1 +VCC_GFX_CORE

1
47K5R2F-GP

Do Not Stuff
A00

52K3R2F-L-GP

PR4111

PR4112

PR4113
X H 1.05V
DY 08/22 modify
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L X X 1.DY PWRCNTL_0 circuit
Inductor: 1.5UH PCMC104T-1R5MN DCR:3.8 ~4.2mohm Isat =33Arms CYNTEC/ 68.1R510.10J 2.change PR4117,PR4122 to short pad

2
O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L X X 3.change PQ4101 & PQ4104 to high level ESD MOS

PWRCNTL_1#

PWRCNTL_0#
H/S: FDS8880-NL SO-8/9.6mohm/[email protected]/ 84.08880.037 X L 0.90V
L/S: FDS8672S SO-8/ 5.3mOhm/[email protected]/ 84.08672.A37 A00 +3.3V_DELAY
2 Switching freq-->250KHz 2
A00
PD4103

1
Do Not Stuff
0903 PR4126

PR4114
+3.3V_ALW PQ4102 +3.3V_DELAY Change PR4111 from 154K to 52.3K 1
DY 2 1
DY 2
Change PC4112 from 0.047u to 0.1u DY

D
SI2301BDS-T1-GP PQ4101 Do Not Stuff Do Not Stuff

2
PR4116 PR4117
S D
DY PWRCNTL_0_R PWRCNTL_0_1
G 1
DY 2 1
DY 2 PWRCNTL_0 55
1
100KR2J-1-GP

Do Not Stuff
Do Not Stuff Do Not Stuff

1
PR4115

Do Not Stuff

PC4111
Id: 2A Do Not Stuff
G

1
+3.3V_DELAY

PR4118
Rds: 0.15ohm

S
DY DY
2

1
10KR2J-3-GP
3.3V_ALW_1

PR4119
D
100R2F-L1-GP-U
6

PR4101 PQ4104

2
PR4120

1 2 PR4121 PR4122
27 3.3V_DELAY_EN
Do Not Stuff G PWRCNTL_1_R 1 2 PWRCNTL_1_1 1 2 PWRCNTL_1 55
DMN66D0LDW-7-GP 2N7002A-7-GP Do Not Stuff

1
PQ4103

Do Not Stuff
10KR2J-3-GP
1

1
PR4123
SCD1U10V2KX-4GP

PC4112
PD4102

S
PR4125
DY 1 2 1 2

2
3.3V_DELAY_1

2
5K1R2F-2-GP CH551H-30PT-GP
1 A00 Main Source 1
PR4124
3.3V_DELAY_EN_1 8/22
27,29,30,38,40 RUNPWROK 1
DY 2
Do Not Stuff

Change PQ4103 from 84.27002.B3F to 84.DMN66.03F

Do Not Stuff Wistron Corporation
1
PC4113

A00 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
DY 8/24
2

Change PR4101 from 0 ohm to short pad Title

VREG : +VCC_GFX_CORE
Optional RC network
Size Document Number Rev
to fine tune PWR SEQ. A3 A00
Riya Discrete
Date: Tuesday, September 08, 2009 Sheet 41 of 65
A B C D E
 5 4 3 2 1

SSID = VIDEO SSID = Inverter

X01
06/09 modify
1. Connect LCD1 pin37 to +LCDVDD
2. Del LCD1 pin38 LVDS CONNECTOR
X01
D
GFX_PWR_SRC
+LCDVDD +3.3V_RUN
06/25
1.Del
04/14
modify
D4201 Add R4205
Del
INVERTER POWER D
LCD1 1.Del R4203 ,reserve closed-gap

SCD1U10V2KX-4GP

SC1U10V3KX-3GP
49

1
C4201

C4202

Do Not Stuff

R4201
47 51
40
DY A00

2
39
38 R4205 GFX_PWR_SRC +PWR_SRC

2
37 1 2 LBKLT_CTL 54
36 F4201
35 100R2J-2-GP 1 2

SC1KP50V2KX-1GP

SCD1U25V3KX-GP
46 34 +3.3V_DELAY R4202
BRIGHTNESS_CN FUSE-3A32V-7-GP
33 1
DY2 BRIGHTNESS 27

1
C4203

C4204
32 Do Not Stuff
31 LCD_CBL_DET#_CN 1 2 LCD_CBL_DET# 27
30 R4210 100R2J-2-GP

2
29
28 BLON_OUT_CN 1 R4203 2100R2J-2-GP BLON_OUT 27
45 27 LCD_TST_CN 1 2 LCD_TST 27
26 LCD_DDCLK R4211 100R2J-2-GP
LCD_DDCLK 55
25 LCD_DDCDAT
LCD_DDCDAT 55
24 LCD_DET_G 1 2
23 VGA_TXBOUT0- R4204
VGA_TXBOUT0- 54
22 VGA_TXBOUT0+ 100R2J-2-GP
VGA_TXBOUT0+ 54
21
44 20 VGA_TXBOUT1-
VGA_TXBOUT1- 54
19 VGA_TXBOUT1+
VGA_TXBOUT1+ 54
18
17 VGA_TXBOUT2- A00
VGA_TXBOUT2- 54
16 VGA_TXBOUT2+
C VGA_TXBOUT2+ 54 C
15 08/22 modify
14 VGA_TXBCLK- 1.DY R4202, use R4205,
VGA_TXBCLK- 54
43 13 VGA_TXBCLK+
VGA_TXBCLK+ 54 2.change R4202,R4205,R4203 from 0 to 100ohm
12
11 VGA_TXAOUT0- 3.add R4210,R4211
VGA_TXAOUT0- 54
10 VGA_TXAOUT0+
VGA_TXAOUT0+ 54
9 0903 modify
8 VGA_TXAOUT1- 1. Connect LCD1 pin38 to GFX_PWR_SRC
VGA_TXAOUT1- 54
7 VGA_TXAOUT1+
42 6
5 VGA_TXAOUT2-
VGA_TXAOUT1+ 54

VGA_TXAOUT2- 54
2. Del LCD1 pin37
SSID = VIDEO
4 VGA_TXAOUT2+
VGA_TXAOUT2+ 54
3
2 VGA_TXACLK-
VGA_TXACLK- 54
1 VGA_TXACLK+
VGA_TXACLK+ 54
41 50

48

IPEX-CONN40-2R-GP
LCD POWER
20.F1093.040
X01
+3.3V_ALW +LCDVDD 06/16 modify
1.Change +LCDVDD power solution
R4206 1 2 150R2F-1-GP
A00
BRIGHTNESS_CN R4207 1 2 4K7R2J-2-GP A00
B 08/27 modify B
LCD_TST_CN 1.Chang EC4202 Pin1 from LCD_TST to LCD_TST_CN 8/22
Do Not Stuff

Do Not Stuff

Change Q4202 from 84.27002.B3F to 84.DMN66.03F

1

4
+15V_ALW
EC4202

EC4201

Q4202
DY DY
2

1
+3.3V_ALW +LCDVDD

100KR2J-1-GP
DMN66D0LDW-7-GP
80 mils

R4208
U4201 Layout Note
1 D D 6

2
For EMI request 2 D D 5
ENVDD 3 G S 4

1
Do Not Stuff

SCD1U25V2ZY-1GP

SC1U10V3KX-3GP

SC10U10V5KX-2GP
D4202 SI3456BDV-T1-GP

1
C4206

C4207
1 Q4201
54 LCDVDD_EN

1
R4209

C4205
3 OUT
3 ENVDD_D 2 R1 DY

2
IN 1 GND

2
2 R2
27 LCD_TST_EN
DDTC144EUA-7F-GP
BAT54CPT-GP
NPN 1'nd 84.03456.C3D
2'nd 84.00655.B3D

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
LCD&Inverter CONN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 42 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = Wireless SSID = SDIO

Mini Card Connector(802.11a/b/g) MINI1 +1.5V_RUN +3.3V_RUN
53

AFTP43
1 MINI_2_WAKE#
NP1
1
SD/XD/MS Card Reader
D D
2
3 SD_DAT0/XD_D6/MS_D0
46,53 WLAN_ACT
4 XD_D4/SD_DAT1
5 SD_DAT2/XD_RE#
46,53 BT_ACT
6 SD_DAT3/XD_WE#
7 R4401 SD_CMD
7 MINI1_CLK_REQ#
LPC_LFRAME#_IN1 Do Not Stuff SD_CLK
9
8
R4402DY 2 LPC_LFRAME# 18,27
SD_CD#
LPC_LAD3_IN Do Not Stuff LPC_LAD3 SD_WP
10 1
DY 2

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
11 R4403
7 MINI1_PCIE_CLK#

EC4402

EC4406

EC4405

EC4403

EC4407

EC4408

EC4404

EC4409
LPC_LAD2_IN Do Not Stuff LPC_LAD2
12 1
DY 2

1
13 R4404
7 MINI1_PCIE_CLK
LPC_LAD1_IN Do Not Stuff LPC_LAD1
R4405 1 2 Do Not Stuff
14 1
R4406DY 2 DY DY DY DY DY DY DY DY
18 80PORT_PLT_RST# DY 15

2
LPC_LAD0_IN Do Not Stuff LPC_LAD0
R4407 1 2 Do Not Stuff
16 1
DY 2
18 FWH_PCI_CLK DY
LPC_LAD[0..3] 18,27
R4408 1 2 Do Not Stuff E51_RXD_R
27 E51_RXD DY 17

R4409 1 2 Do Not Stuff E51_TXD_R

18 For EMI
27 E51_TXD DY 19
20 WIFI_RF_EN 27
21
22 MINI_PLT_RST#
MINI_PLT_RST# 18 +3.3V_RUN_CARD CARD1
14 PCIE_NRX_MINTX_N2 23
24 +3.3V_RUN
25 23 25 SD_DAT0/XD_D6/MS_D0 1
14 PCIE_NRX_MINTX_P2 SD_VCC SD_DAT0
26 14 29 XD_D4/SD_DAT1 1 AFTP37
MS_VCC SD_DAT1 SD_DAT2/XD_RE# AFTP40
27 1 33 XD_VCC SD_DAT2 10 1
28 AFTP39 11 SD_DAT3/XD_WE# 1 AFTP38
SD_DAT3 AFTP47
C 29 C
30 SMB_CLK_0 XD_D0 8 12 SD_CMD
SMB_CLK_0 7,12,13,19 25 XD_D0 XD_D0 SD_CMD SD_CMD 25
31 SD_CLK/XD_D1/MS_CLK 9 24 SD_CLK
14 PCIE_NTX_MINRX_N2 25 SD_CLK/XD_D1/MS_CLK XD_D1 SD_CLK SD_CLK 25
32 SMB_DATA_0 XD_D2/MS_D2 26 36 SD_CD#
SMB_DATA_0 7,12,13,19 25 XD_D2/MS_D2 XD_D2 SD_CD_SW SD_CD# 25
33 XD_D3/MS_D1 27 35 SD_WP
14 PCIE_NTX_MINRX_P2 25 XD_D3/MS_D1 XD_D3 SD_WP_SW SD_WP 25
34 XD_D4/SD_DAT1 28
25 XD_D4/SD_DAT1 XD_D4
XD_D5/MS_BS
35
36 FB_USB10_N
X01 25 XD_D5/MS_BS
SD_DAT0/XD_D6/MS_D0
30
31
XD_D5
19 SD_DAT0/XD_D6/MS_D0
25 SD_DAT0/XD_D6/MS_D0 XD_D6 MS_DATA0
37 04/08 modify XD_D7/MS_D3 32 20 XD_D3/MS_D1 1
1.Change Clk gen,Mini Card SMBus from Ch1 to Ch0 25 XD_D7/MS_D3 XD_D7 MS_DATA1
38 FB_USB10_P 18 XD_D2/MS_D2 1 AFTP48
XD_RDY MS_DATA2 XD_D7/MS_D3 AFTP50
+3.3V_RUN 39 25 XD_RDY 1 XD_R/B MS_DATA3 16 1
40 SD_DAT2/XD_RE# 2 AFTP49
25 SD_DAT2/XD_RE# XD_RE
41 XD_CE# 3 21 XD_D5/MS_BS 1 AFTP51
25 XD_CE# XD_CE MS_BS
42 1 XD_CLE 4 17 MS_INS#
25 XD_CLE XD_CLE MS_INS MS_INS# 25
1 43 AFTP54 XD_ALE 5 15 MS_CLK
25 XD_ALE XD_ALE MS_SCLK MS_CLK 25
AFTP53 44 SD_DAT3/XD_WE# 6
25 SD_DAT3/XD_WE# XD_WE
45 XD_WP# 7 G4402
25 XD_WP# XD_WP
46 1 XD_CD# 34 13 G4401 1 2
25 XD_CD# XD_CD_SW 4IN1_GND
47 AFTP55 22 1 2
4IN1_GND Do Not Stuff
48 NP1 NP1 4IN1_GND 38
49 NP2 37 1 Do Not Stuff
R4410 NP2 4IN1_GND AFTP52
50
+5V_MINICARD
+5V_ALW 1
DY 2 51
52 CARD-PUSH-36P-5-GP
Do Not Stuff NP2 20.I0081.011
+3.3V_RUN_CARD 1 SD_CMD
54 AFTP29 1 SD_CD#
AFTP28 1 SD_WP

Do Not Stuff

Do Not Stuff

Do Not Stuff

SCD1U16V2KX-3GP

SC2D2U10V3KX-1GP
AFTP30 1 MS_INS#

C4402

C4403

C4404

C4405

C4406
SKT-MINI52P-21-GP AFTP42 1 XD_D0

1
B 62.10043.581 AFTP41 1 XD_RDY B
AFTP32 XD_CE#
R4411 DY DY DY AFTP31
1
1 XD_CLE

2
FB_USB10_N 1 2 AFTP34 1 XD_ALE
USB10_N 19
Do Not Stuff AFTP33 1 XD_WP#
AFTP45 1 XD_CD#
AFTP44 1 SD_CLK
AFTP36 1 MS_CLK
R4412 AFTP35 1 SD_CLK/XD_D1/MS_CLK
FB_USB10_P 1 2 AFTP46
USB10_P 19
Do Not Stuff

A00
8/24
Change R4411,R4412 from 0 ohm to short pad

8/26
Del L4401 +5V_ALW +3.3V_RUN
Do Not Stuff

SCD1U16V2KX-3GP
C4401

C4407
1

DY
2

A WLAN_ACT A
1 Main Source
MINI1_PCIE_CLK# 1 AFTP56 WLAN_ACT +3.3V_RUN +1.5V_RUN
SC220P50V2KX-3GP

MINI1_PCIE_CLK 1 AFTP59
E51_TXD_R AFTP58
1
Wistron Corporation
EC4401

Do Not Stuff

Do Not Stuff

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

E51_RXD_R 1 AFTP61
1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

C4412

C4408

C4409

PCIE_NRX_MINTX_N2
1 AFTP65
1

Taipei Hsien 221, Taiwan, R.O.C.

C4410

C4411

PCIE_NTX_MINRX_P2
1 AFTP64
+3.3V_RUN AFTP67
1
DY DY
2

+1.5V_RUN 1 AFTP69 Title

MiniCard&Card Reader CONN
2

WIFI_RF_EN 1 AFTP72
MINI_PLT_RST# 1 AFTP71
SMB_CLK_0 1 AFTP73 Size Document Number Rev
Custom
SMB_DATA_0 1 AFTP75
AFTP74
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 44 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = SATA SATA HDD Connector

HDD1
AFTP10 1 16
NP1

AFTP11 1 S1

S2
S3
S4
D +5V_HDD +5V_RUN +5V_HDD S5
D

S6
S7

SC10U6D3V5MX-3GP

SCD1U16V2KX-3GP
G4501 S8

1
C4501

C4502
2 1 S9
S10
Do Not Stuff +3.3V_RUN S11

2
S12
G4502 S13

Do Not Stuff

Do Not Stuff
2 1 S14

1
C4503

C4504
S15
Do Not Stuff
DY DY P1

2
20 SATA_RX0P P2
20 SATA_RX0N P3
P4
20 SATA_TX0N P5
20 SATA_TX0P P6
P7
1 +3.3V_RUN
AFTP12 1 +5V_HDD NP2
AFTP14 1 SATA_RX0P 17
AFTP13 1 SATA_RX0N
AFTP16 1 SATA_TX0N SKT-SATA7P-15P-10-GP-U
AFTP15 1 SATA_TX0P 22.10300.431
AFTP17

C C

SSID = SATA ODD Connector

ODD1
1 8
+5V_MOD +5V_RUN AFTP18 NP1
S1
G4503
2 1 20 SATA_TX1P S2
20 SATA_TX1N S3
Do Not Stuff S4
G4504 20 SATA_RX1N S5
2 1 20 SATA_RX1P S6
S7
Do Not Stuff +5V_MOD
G4505 P1

SC10U6D3V5MX-3GP

SCD1U10V2KX-4GP
2 1 P2
P3

1
C4505

C4506
Do Not Stuff ODD_MD P4
G4506 P5
2 1 P6

2
NP2
Do Not Stuff 9
B B
SKT-SATA7P+6P-62-GP
22.10300.421

1 +5V_MOD
AFTP20 1 SATA_TX1N
AFTP21 1 SATA_TX1P
AFTP22 1 SATA_RX1N
AFTP24 1 SATA_RX1P
AFTP23 1 ODD_MD
AFTP19

SSID = Thermal Fan Connector

FAN1
4

EMC2102_FAN_TACH_1
29 EMC2102_FAN_TACH_1
AFTP25 1
3
2
3 1
A EMC2102_FAN_DRIVE A
29 EMC2102_FAN_DRIVE 1 Main Source
SC22U6D3V5MX-2GP

Layout 20 mil
K
RB551V30-GP

5
Wistron Corporation
1
C4507

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

D4501

ETY-CON3-4-GP
20.F0984.003 Taipei Hsien 221, Taiwan, R.O.C.
2

Title
HDD&ODD&FAN CONN
1 EMC2102_FAN_TACH_1
AFTP26 1 EMC2102_FAN_DRIVE Size Document Number Rev
Custom
AFTP27
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 45 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = KBC SSID = Touch.Pad

Internal KeyBoard Connector TouchPad Connector

KB1
29
D
1 KCOL10 1 +5V_RUN D

2 KCOL11 1 AFTP137
3 KCOL9 1 AFTP136

SCD1U16V2KX-3GP

SC1U10V3KX-3GP
4 KCOL14 1 AFTP138
5 KCOL13 1 AFTP140

1
C4601

C4602
6 KCOL15 1 AFTP139
7 KCOL16 1 AFTP142
8 KCOL12 1 AFTP141

2
9 KCOL0 1 AFTP144 +5V_RUN
10 KCOL2 1 AFTP143
KROW[0..7] 27
11 KCOL1 1 AFTP145
12 KCOL3 1 AFTP150
13 KCOL8 1 AFTP148 KCOL[0..16] 27

1
2
14 KCOL6 1 AFTP147

SRN10KJ-5-GP

RN4601
15 KCOL7 1 AFTP149
16 KCOL4 1 AFTP151 TPAD1
17 KCOL5 1 AFTP153 5
18 KROW0 1 AFTP152
19 KROW3 1 AFTP154 1

4
3
20 KROW1 1 AFTP156
21 KROW5 1 AFTP155 2
KROW2 AFTP158 27 TPCLK
22 1 27 TPDATA 3
23 KROW4 1 AFTP157 1 4
24 KROW6 1 AFTP159 AFTP146

1
1
25 KROW7 1 AFTP160 6
26 1 AFTP162 C4603 C4604
27 AFTP164 KB_DET# 27 SC33P50V2JN-3GP SC33P50V2JN-3GP ACES-CON4-10-GP-U

2
2
28 20.K0320.004
1
C
JAE-CON27-GP C
20.K0291.027 AFTP166

1 +5V_RUN
AFTP161 1 TPCLK
AFTP163 TPDATA
For EMI AFTP165
1

KCOL3 KCOL11
KCOL2 KCOL10
KCOL1 KCOL9
KCOL0 KCOL8
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
EC4601

EC4602

EC4603

EC4604

EC4605

EC4606

EC4607

EC4608
1

DY DY DY DY DY DY DY DY
2

SSID = User.Interface
KCOL7
KCOL6
KCOL5
KCOL4
KCOL15
KCOL14
KCOL13
KCOL12
Bluetooth Module conn.
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

B BT1 B
+3.3V_RUN
EC4609

EC4610

EC4611

EC4612

EC4613

EC4614

EC4615

EC4616

11
1

1
DY DY DY DY DY DY DY DY 2
2

44,53 BT_ACT
44,53 WLAN_ACT 3
4
19 USB6_P 5
19 USB6_N 6
27 BLUETOOTH_EN 7
KROW3 KCOL16 8
KROW2 9
KROW1 10

SC2D2U10V3KX-1GP

Do Not Stuff

Do Not Stuff

Do Not Stuff
KROW0 12

1
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

10KR2J-3-GP

EC4622

EC4623

EC4624
1

1
EC4617

EC4618

EC4619

EC4620

EC4621

R4601

R4602

C4605
FOX-CON10-GP-U
1

20.F0711.010
DY DY DY DY
DY DY DY DY DY

2
2

2
KROW7
KROW6
KROW5
KROW4 1 USB6_P
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

A AFTP116 USB6_N A
1 Main Source
EC4625

EC4626

EC4627

EC4628

AFTP115 1 BLUETOOTH_EN
1

AFTP117 1 WLAN_ACT
AFTP118 +3.3V_RUN
DY DY DY DY AFTP119
1
Wistron Corporation
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title
KeyBoard&TouchPad&BT CONN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 46 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = USB
Right USB Port CONN
+5V_USB2

6
D R4701 D
USB11_N 1 2 R_USB11_N A00
19 USB11_N
4 CN4701
Do Not Stuff 3 8/28
MLX-CON4-15-GP-U Change R_USB11_N,R_USB11_P from U4702 Pin3,4 to Pin1,6
2
R4702
USB11_P 1 2 R_USB11_P 1 1
19 USB11_P
AFTP127
Do Not Stuff 20.F0693.004
A00 U4702

5
8/26 R_USB11_N 6
Del L4701 R_USB11_P
1
+5V_USB2
9/3
Change R4701,R4702 from 0ohm to short pad
5 2

DY
4 3
Do Not Stuff
+5V_USB2
+5V_ALW U4701
at least 40 mil at least 40 mil
1 GND VOUT 8

SCD1U16V2KX-3GP

SC1U10V3KX-3GP

ST100U6D3VBM-5GP
2 VIN VOUT 7

1
Do Not Stuff

SCD1U25V3KX-GP

Do Not Stuff

C4702

C4703

TC4702
3 VIN VOUT 6

1
R4703
4 EN/EN# FLG# 5

1
TC4701

C4701
C DY DY C

2
RT9711BPF-GP

2
1 +5V_USB2
AFTP133 1 R_USB11_N
AFTP135 1 R_USB11_P
AFTP134

27,50 USB_PWR_EN# 19 USB_OC_2_#

B B

(Blanking)

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
USB CONN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Thursday, September 03, 2009 Sheet 47 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = Flash.ROM SSID = User.Interface

A00
SPI FLASH ROM (16M bits) Camera Connector 8/26
Del L4801
+3.3V_RTC_LDO
+3.3V_RTC_LDO 8/27
Change R4802,R4807 from 0 ohm to short pad

Do Not Stuff

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
CAMERA1
D D
10

1
C4801

C4802

C4803
8 CAMERA_DET# 27 1 R4802 2

1
2
100KR2J-1-GP

SRN100KJ-6-GP
AUD_DMIC_CLK_G_R R4803 1 2 33R2J-2-GP Do Not Stuff
DY 7
6
AUD_DMIC_CLK_G 23

2
R4801

RN4801
5 AUD_DMIC_IN0_R R4804 1 2 33R2J-2-GP AUD_DMIC_IN0 23 USB2_N 19
4 +3.3V_CAMERA
3 CAMERA_USB_N

2
2 CAMERA_USB_P

4
3

Do Not Stuff
USB2_P 19
1 1 AFTP107

1
C4804
9
1 R4807 2
ACES-CON8-3-GP-U DY Do Not Stuff

2
U4801 +3.3V_RTC_LDO 20.F0779.008 1 AFTP5

EC_SPI_CS# 1 8
27 EC_SPI_CS# CS# VCC
27 EC_SPI_DI 1 R4805 2 EC_SPI_DI_R 2 DO/IO1 HOLD#/IO3 7 EC_SPI_HOLD#
27 EC_SPI_WP#_R 1 R4806 2 EC_SPI_WP# 3 WP#/IO2 CLK 6 EC_SPI_CLK 27 X01 A00
SC4D7P50V2CN-1GP

4 5 R4808 1 2 33R2J-2-GP
GND DI/IO0 EC_SPI_DO 27

SC4D7P50V2CN-1GP

SC4D7P50V2CN-1GP
Do Not Stuff 04/14 Del 9/9 AUD_DMIC_IN0_R
1
EC4801

Do Not Stuff 1.Del R4809 ,reserve closed-gap. ADD AFTP5 test point,move EC4802,EC4803

1
EC4804

EC4805
W25Q16BVSSIG-GP AUD_DMIC_CLK_G_R

Do Not Stuff

Do Not Stuff
2

Digital Mic Power

1
EC4806

EC4807
+3.3V_RUN +3.3V_CAMERA DY DY
X01

2
04/14 Del 1 R4809 2

Do Not Stuff

SC4D7U6D3V3KX-GP
1.Del R4805 ,reserve closed-gap. Do Not Stuff
C Del R4806 ,reserve closed-gap.
A00 C

1
EC4808

C4805
9/9
Change U4801 from 72.25X16.A01 to 72.25Q16.001
DY 1 CAMERA_DET#

2
AFTP89 1 AUD_DMIC_CLK_G_R
AFTP88 1 AUD_DMIC_IN0_R
AFTP90 1 +3.3V_CAMERA
AFTP91 1 CAMERA_USB_N
AFTP93 1 CAMERA_USB_P
AFTP94

SSID = User.Interface SSID = RBATT

Power/Battery LED RTC Connector

A00
8/22 +3.3V_RTC_LDO
B ADD PWR_LED_B AFTE Pad U4802 B
+5V_ALW +RTC_CELL
9/9 2
Del PWR_LED_B AFTE Pad
3 RTC1

SC1U10V3KX-3GP
R4811
POWER LED 1 RTC_PWR 1 2 +RTC_VCC 1 PWR

1
C4806
AFTP125 1 2
LED1 1KR2J-1-GP GND
NP1 NP1
Q4801 R4810 SDMG0340LC7F-GP-U NP2

2
LED_PWR# PWR_LED_B NP2
C 1 2 3 White
Do Not Stuff

B R1
27 PWRLED
E 330R2J-3-GP 1 Width=20mils BAT-CON2-1-GP-U
1
EC4809

R2 62.70001.011
PDTC124EU-1-GP Amber
DY 2
2

AFTP126 1 +RTC_VCC
LED-OW-3-GP
83.00326.G70
BATT LED
Q4802 R4812
C LED_BAT# 1 2 BAT_LED_B
Do Not Stuff

B R1
27 BATLOW_LED
E 270R2F-GP
1
EC4810

R2
PDTC124EU-1-GP
DY
2

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
EEPROM&LED&Camera&RTC CONN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, September 09, 2009 Sheet 48 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = AUDIO

23 AUD_VREFOUT_B

SC1U10V3KX-3GP
Speaker MIC IN

1
4K7R2J-2-GP

4K7R2J-2-GP

C4901
1
D D

R4902

R4903
Connector A00

2
2

2
8/24

5
SPK1 Change R4901,R4904,R4905,R4906,R4907,R4908 from 0 ohm to short pad

23 AUD_SPK_L- R4901 1 2Do Not Stuff AUD_SPK_R_L- 1

MIC1
23 AUD_SPK_L+ R4904 1 2Do Not Stuff AUD_SPK_R_L+ 2 1 1
23 AUD_SPK_R- R4905 1 2Do Not Stuff AUD_SPK_R_R- 3 AFTP76
23 AUD_SPK_R+ R4906 1 2Do Not Stuff AUD_SPK_R_R+ 4 AUD_EXT_MIC_L C4902 2 1 SC1U10V3KX-3GP MIC_IN_L_2 R4907 2 Do
1 Not Stuff MIC_IN_L_C 2
Do Not Stuff 23 AUD_EXT_MIC_L

Do Not Stuff

Do Not Stuff

Do Not Stuff
6
MLX-CON4-15-GP-U

6
1

1
EC4901

EC4902

EC4903

EC4904
20.F0693.004 AUD_EXT_MIC_R C4903 2 1 SC1U10V3KX-3GP MIC_IN_R_2 R4908 1 2Do Not Stuff MIC_IN_R_C 3
23 AUD_EXT_MIC_R
DY DY DY DY 4
2

2
23 EXT_MIC_JD# 5

SC100P50V2JN-3GP

SC100P50V2JN-3GP
7
For EMI

EC4905

EC4906
8

1
9
10

2
PHONE-JK284-GP
1 AUD_SPK_R_L- 22.10133.D01
AFTP77 1 AUD_SPK_R_L+
AFTP79 1 AUD_SPK_R_R-
C
AFTP80 1 AUD_SPK_R_R+ C
AFTP78

1 MIC_IN_L_C
AFTP81
1 MIC_IN_R_C
AFTP82
1 EXT_MIC_JD#
AFTP83

Internal
Microphone
23 INT_MIC_L_R 1 CN4901 LINE1
SC1KP50V2KX-1GP

MICROPHONE-40-GP-U1
EC4907

23.42143.001
2
1

OUT
2

LOUT1
AUD_HP1_JACK_R2 AUD_HP1_JACK_L2 AFTP84 1 1

B AUD_HP1_JD# 2 B
23 AUD_HP1_JD#
D

Q4904 Q4905 23 AUD_HP1_JACK_L AUD_HP1_JACK_L R4909 1 2 AUD_HP1_JACK_L2 L4901 1 2 AUD_HP1_JACK_L1 6

P8503BMG-GP P8503BMG-GP 60D4R2F-GP BLM18BD601SN1D-GP
G G 23 AUD_HP1_JACK_R AUD_HP1_JACK_R R4910 1 2 AUD_HP1_JACK_R2 L4902 1 2 AUD_HP1_JACK_R1 3

SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP
60D4R2F-GP BLM18BD601SN1D-GP
DY DY

C4904

C4905

EC4908

EC4909
4
S

1
600ohm 100MHz 5
7
200mA 0.65ohm DC

2
MUTE_N1 MUTE_N2 8
+15V_ALW 9
Q4906 Q4907 10
S

P8503BMG-GP P8503BMG-GP
1

G G PHONE-JK284-GP
R4911 22.10133.D01
10KR2J-3-GP
DY
DY DY
2

1 AUD_HP1_JD#
AFTP85
HP_CODEC_MUTE 1 AUD_HP1_JACK_L1
AFTP86
1 AUD_HP1_JACK_R1
D

AFTP87
Q4903
DY
X01 G
X01
27 HP_MUTE#
04/14 Change 2N7002A-7-GP 03/31 modify
A 1.Change netname from HP_MUTE to HP_MUTE# 1.Use low RDS(on) MOSFET on audio de-pop circuit A
Main Source
S

A00
8/22 Wistron Corporation
Change Q4903 from 84.27002.N31 to 84.2N702.E31 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
9/8
DY Q4903,Q4904,Q4905,Q4906,Q4907.R4911 Title
Audio Jack
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, September 09, 2009 Sheet 49 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = PWR.Support +5V_ALW

1
15KR2J-1-GP

1
10KR2J-3-GP
D5001

R5001

R5002
DY Do Not Stuff

E
2
B +5V_ALW +3.3V_ALW

3
Q5001
CH3904PT-GP R5004 R5005

C
1

1
D D

100KR2J-1-GP

2K2R2J-2-GP
PSID_DISABLE#_R
1 2 1
DY 2 PSID_DISABLE# 27
D5002
I/O Board Connector

R5003

R5006
10KR2J-3-GP Do Not Stuff BAV99-4-GP

G
2

2
3
R5007
PS_ID D S 1 2

D
PSID_EC 27
Q5002 33R2J-2-GP
FDV301N-NL-GP

R5008

CN5001
1
DY 2

51 53 Do Not Stuff
NP1 52
The caps should be used
1 2 only as last resort for
3 4 1 AFTP167 EMI suppression.
5 6 +DC_IN +DC_IN_SS
7 8 U5002
9 10 1 S D 8

Do Not Stuff

Do Not Stuff

SC1U25V5KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SCD01U50V2KX-1GP

SC10U25V6KX-1GP
11 12 2 S D 7

1
EC5002

C5002

240KR3-GP
AFTP168 1 13 14 1 3 S D 6

1
C5003

C5004

C5005

C5006

C5007
AFTP169

R5009
G D
15
17
16
18
DY DY 4 5
55 VGA_RED

2
C 19 20 AO4407A-GP C

2
55 VGA_GRN 21 22 +3.3V_RTC_LDO

2
23 24 +5V_RUN
55 VGA_BLU 25 26 VGA_HSYNC 55,57
27 28 Q5004
VGA_VSYNC 55,57 R2
29 30 DDC_DATA_CON Q5003 E
DDC_DATA_CON 55
DDC_CLK_CON 3 OUT
31 32 DDC_CLK_CON 55 R1
B
DY
R1
+DC_IN_GATE
+5V_USB1 33
35
34
36 USB1_P
27 AD_OFF
IN
1
DY 2 GND
C
USB1_P 19

1
47KR3J-L-GP
37 38 USB1_N R2 Do Not Stuff
USB1_N 19

R5010
39 40 USB0_P
USB0_P 19
41 42 USB0_N Do Not Stuff
USB0_N 19
43 44
26 MDI0+ 45 46 MDI1+ 26

2
26 MDI0- 47 48 MDI1- 26
49 50 LCD_EC_DET 27
NP2 55
54 56

ACES-CONN50A-GP-U
20.F1318.050
USB Power Reserved for EMI
X01 Place near DCIN1
06/09 modify
1.Connect CN5001 pin50 to net LCD_EC_DET +5V_ALW U5001 +5V_USB1 +DC_IN
2.Connect CN5001 pin22 to net +3.3V_RTC_LDO

Do Not Stuff
+5V_RUN
at least 80 mil 1 GND OC1# 8 at least 80 mil

EC5003
2 IN OUT1 7

1
SCD01U16V2KX-3GP

Do Not Stuff

Do Not Stuff
3 EN1/EN1# OUT2 6
B
27,47 USB_PWR_EN# 4 EN2/EN2# OC2# 5
DY B
1

1
C5001

TC5001

EC5001

2
G546B2P1UF-GP DY DY
2

2
USB_OC_01_# 19

AFTP173 1 USB1_P
AFTP172 1 USB1_N
AFTP174 1 USB0_P
AFTP171 1 USB0_N

AFTP177 1 MDI1+
AFTP178 1 MDI1-
AFTP176 1 MDI0+
AFTP175 1 MDI0-

A AFTP179 VGA_RED A
1 Main Source
AFTP185 1 VGA_GRN
AFTP181 1 VGA_BLU
AFTP180 VGA_VSYNC
AFTP184
1
1 VGA_HSYNC Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AFTP182 1 DDC_DATA_CON Taipei Hsien 221, Taiwan, R.O.C.
AFTP183 1 DDC_CLK_CON
AFTP186 1 +5V_RUN Title
AFTP170 1 +5V_USB1 IO BOARD CONN
Size Document Number Rev
Custom A00
Riya Discrete
Date: Wednesday, August 26, 2009 Sheet 50 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = ExpressCard

D D

Express Card Connector

EXP1
31
NP1
1 2 1 AFTP120 U5101

CPPE# 3 4 14 17 +3.3V_ALW
19 CPPE# PCIE_NTX_EXPRX_P3 14 +1.5V_RUN 1_5VIN AUXIN
EXPCARD_CLK_REQ# 5 6 12 15 +3.3V_CARDAUX
7 EXPCARD_CLK_REQ# PCIE_NTX_EXPRX_N3 14 1_5VIN AUXOUT +3.3V_ALW
+3.3V_CARD 7 8
9 10 11 RN5101
PCIE_NRX_EXPTX_P3 14 +1.5V_CARD 1_5VOUT
PERST# 11 12 13 9 CPUSB# 3 2
PCIE_NRX_EXPTX_N3 14 1_5VOUT CPUSB# CPPE#
13
15
14
16 2
CPPE# 10 4
DY 1
+3.3V_CARDAUX EXP_PCIE_CLK 7 +3.3V_RUN 3_3VIN
17 18 4 1 Do Not Stuff
19,26 PCIE_WAKE# EXP_PCIE_CLK# 7 3_3VIN STBY# PM_SLP_S3# 19,27,30,31,39,40,41
19 20 6 NRST
+1.5V_CARD SYSRST#
21 22 3 8 PERST#
+3.3V_ALW +3.3V_CARD 3_3VOUT PERST#
23 24 LID_CLOSE# 5 19 EXPCARD_OC# 1 AFTP114
C 19 SMB_DATA LID_CLOSE# 27 3_3VOUT OC# C
25 26 CPUSB# 20 R5101
19 SMB_CLK SHDN# PM_SLP_S5# 19,27,39
1 CONN_TP2 27 28 USB4_P 1 2
USB4_P 19 EXP_PLT_RST# 18
AFTP123 1 CONN_TP3 29 30 USB4_N 18 Do Not Stuff
USB4_N 19 RCLKEN

Do Not Stuff

Do Not Stuff
AFTP122 C5101 1 Do Not Stuff
NP2 GND 21
DY 2

EC5101

EC5102
32 16 NC#16 GND 7

1
DY DY A00
FOX-CONN30A-9GP G577DSR91U-GP

2
20.F0908.030 8/22
Change R5101 from 0 ohm to short pad

+1.5V_CARD Max. 650mA, Average 500mA.

+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA

1 CPPE#
AFTP121 1 PCIE_NTX_EXPRX_P3
AFTP92 1 PCIE_NTX_EXPRX_N3
AFTP96 1 PCIE_NRX_EXPTX_P3
AFTP95 1 PCIE_NRX_EXPTX_N3
Place them Near to Chip AFTP98 1 EXP_PCIE_CLK
AFTP97 1 EXP_PCIE_CLK#
AFTP100 1 EXPCARD_CLK_REQ#
B +3.3V_ALW +1.5V_RUN +3.3V_RUN +3.3V_CARD +1.5V_CARD +3.3V_CARDAUX AFTP105 1 PCIE_WAKE# B
AFTP109 1 PERST#
SCD1U16V2KX-3GP

Do Not Stuff

SCD1U16V2KX-3GP

SC4D7U6D3V5KX-3GP

SC10U6D3V5MX-3GP

SCD1U16V2KX-3GP

SC10U6D3V5MX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
AFTP108 1 CPUSB#
AFTP102 1 USB4_P
1

1
C5102

C5103

C5104

C5105

C5106

C5107

C5108

C5109

C5110
AFTP103 1 USB4_N
AFTP104 SMB_DATA
DY AFTP111
1
1 SMB_CLK
2

2
AFTP113 1 LID_CLOSE#
AFTP101 1 +3.3V_ALW
AFTP99 1 +3.3V_CARD
AFTP106 1 +3.3V_CARDAUX
AFTP110 1 +1.5V_CARD
AFTP112

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Express Card Board CONN
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 51 of 65
5 4 3 2 1
 5 4 3 2 1

D D

(Blanking)

C C

SSID = User.Interface

Power Board to Board CONN

B B

CN5201
5
R5201
1 2 KBC_PWRBTN#_IN 1
27 KBC_PWRBTN#
Do Not Stuff

100R2J-2-GP 1 2

(Blanking)
EC5201

AFTP124 3
1

4
DY 6
2

ACES-CON4-10-GP-U
A00 20.K0320.004

8/22
Change R5201 from 0 ohm to 100 ohm

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Power Button&Hall Sensor&MDC
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 52 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = Mechanical

D D

For EMI
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
H5301 H5302 H5303 H5304 H5305 H5306
1

1
+5V_ALW +3.3V_ALW +VCC_GFX_CORE +VCC_CORE0

Do Not Stuff

Do Not Stuff

Do Not Stuff
EC5313 1
DY2Do Not Stuff

EC5312

EC5321

EC5330
1

1
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
H5307 H5308 H5309 H5310 H5311
EC5318 1
DY2Do Not Stuff DY DY DY
1

2
EC5331 1
DY2Do Not Stuff

C
+3.3V_RTC_LDO +3.3V_RUN +5V_ALW +5V_MOD C
44,46 WLAN_ACT
44,46 BT_ACT
Do Not Stuff

Do Not Stuff

H5312 H5313

Do Not Stuff

SC47P50V2JN-3GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
EC5301

EC5305

EC5306

EC5307

EC5308

EC5309

EC5310

EC5311

EC5316

EC5317

EC5314

EC5315
1

1
DY DY DY DY DY DY DY DY DY DY DY
1

2
HOLE

HOLE

HOLE

H5314 H5315 H5316

+0.9V_VTT +PWR_SRC +PWR_SRC

1

BOTTOM TOP BOTTOM

Do Not Stuff

Do Not Stuff

Do Not Stuff

SCD1U25V3KX-GP

SCD1U25V3KX-GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
EC5332

EC5333

EC5334

EC5322

EC5323

EC5324

EC5325

EC5326

EC5327

EC5328

EC5329
34.4W005.301 34.4W004.501 34.4W001.201

1
Mini Card BOSS New Card BOSS NB Thermal BOSS
DY DY DY DY DY DY DY DY DY
For BOSS

2
B B
H5317 H5318 H5319 H5320
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

X01 +5V_RUN +1.8V_SUS +3.3V_RUN

DY DY DY DY 04/16 Add
1

1.Add C5300,C5301,C5302,C5303,C5304,C5305 Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
EC5353

EC5341

EC5342

EC5335

EC5336

EC5337

EC5338

EC5339

EC5340

EC5358

EC5360

EC5361

EC5362

EC5363

EC5364
For S1G2 CPU SOCKET
1

1
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2

2
SPR5301 SPR5302 SPR5303 SPR5304 SPR5305 SW5301
SPRING-24-GP SPRING-24-GP SPRING-24-GP SPRING-24-GP SPRING-58-GP SPRING-24-GP
34.45T31.001 34.45T31.001 34.45T31.001 34.45T31.001 34.4B312.002 34.45T31.001
1

+PWR_SRC
Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
C5300

C5301

C5302

C5303

C5304

C5305
A A
Main Source
1

1
DY DY
DY DY DY DY
Wistron Corporation
2

2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Miscellaneous Components
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 53 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO
U4A 1 OF 7
PCIE_NTX_GRX_P[0..15]
PCIE_NTX_GRX_N[0..15] PCIE_NTX_GRX_P[0..15] 14
M92LP-S2 A12 : J310N PCIE_NTX_GRX_N[0..15] 14
PCIE_NRX_GTX_P[0..15]
PCIE_NRX_GTX_N[0..15] PCIE_NRX_GTX_P[0..15] 14
PCIE_NRX_GTX_N[0..15] 14
PCIE_NTX_GRX_P15 AF30 AH30 PCIE_NRX_GTX_C_P15 C5401 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P15
PCIE_NTX_GRX_N15 AE31 PCIE_RX0P PCIE_TX0P PCIE_NRX_GTX_C_N15 C5402
PCIE_RX0N PCIE_TX0N AG31 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N15
D D
PCIE_NTX_GRX_P14 AE29 AG29 PCIE_NRX_GTX_C_P14 C5403 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P14
PCIE_NTX_GRX_N14 AD28 PCIE_RX1P PCIE_TX1P PCIE_NRX_GTX_C_N14 C5404
PCIE_RX1N PCIE_TX1N AF28 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N14

PCIE_NTX_GRX_P13 AD30 AF27 PCIE_NRX_GTX_C_P13 C5405 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P13

PCIE_NTX_GRX_N13 AC31 PCIE_RX2P PCIE_TX2P PCIE_NRX_GTX_C_N13 C5406
PCIE_RX2N PCIE_TX2N AF26 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N13

PCIE_NTX_GRX_P12 AC29 AD27 PCIE_NRX_GTX_C_P12 C5407 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P12

PCIE_NTX_GRX_N12 AB28 PCIE_RX3P PCIE_TX3P PCIE_NRX_GTX_C_N12 C5408
PCIE_RX3N PCIE_TX3N AD26 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N12

PCIE_NTX_GRX_P11 AB30 AC25 PCIE_NRX_GTX_C_P11 C5409 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P11

PCIE_RX4P PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_NTX_GRX_N11 AA31 AB25 PCIE_NRX_GTX_C_N11 C5410 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N11
PCIE_RX4N PCIE_TX4N

PCIE_NTX_GRX_P10 AA29 Y23 PCIE_NRX_GTX_C_P10 C5411 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P10

PCIE_NTX_GRX_N10 PCIE_RX5P PCIE_TX5P PCIE_NRX_GTX_C_N10 C5412
Y28 PCIE_RX5N PCIE_TX5N Y24 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N10

PCIE_NTX_GRX_P9 Y30 AB27 PCIE_NRX_GTX_C_P9 C5413 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P9

PCIE_NTX_GRX_N9 PCIE_RX6P PCIE_TX6P PCIE_NRX_GTX_C_N9 C5414
W31 PCIE_RX6N PCIE_TX6N AB26 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N9

PCIE_NTX_GRX_P8 W29 Y27 PCIE_NRX_GTX_C_P8 C5415 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P8

PCIE_NTX_GRX_N8 PCIE_RX7P PCIE_TX7P PCIE_NRX_GTX_C_N8 C5416
V28 PCIE_RX7N PCIE_TX7N Y26 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N8

C
PCIE_NTX_GRX_P7 V30 W24 PCIE_NRX_GTX_C_P7 C5417 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P7 C
PCIE_NTX_GRX_N7 PCIE_RX8P PCIE_TX8P PCIE_NRX_GTX_C_N7 C5418
U31 PCIE_RX8N PCIE_TX8N W23 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N7 U4F 6 OF 7

PCIE_NTX_GRX_P6 U29 V27 PCIE_NRX_GTX_C_P6 C5419 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P6

PCIE_NTX_GRX_N6 PCIE_RX9P PCIE_TX9P PCIE_NRX_GTX_C_N6 C5420
T28 PCIE_RX9N PCIE_TX9N U26 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N6 LVDS CONTROL
VARY_BL AB11 LBKLT_CTL 42
DIGON AB12 LCDVDD_EN 42
PCIE_NTX_GRX_P5 T30 U24 PCIE_NRX_GTX_C_P5 C5421 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P5
PCIE_NTX_GRX_N5 PCIE_RX10P PCIE_TX10P PCIE_NRX_GTX_C_N5 C5422
R31 PCIE_RX10N PCIE_TX10N U23 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N5

1
10KR2J-3-GP

10KR2J-3-GP
R5402

R5403
AH20 VGA_TXBCLK+
TXCLK_UP_DPF3P VGA_TXBCLK+ 42
PCIE_NTX_GRX_P4 R29 T26 PCIE_NRX_GTX_C_P4 C5423 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P4 AJ19 VGA_TXBCLK-
PCIE_RX11P PCIE_TX11P TXCLK_UN_DPF3N VGA_TXBCLK- 42
PCIE_NTX_GRX_N4 P28 T27 PCIE_NRX_GTX_C_N4 C5424 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N4
PCIE_RX11N PCIE_TX11N VGA_TXBOUT0+
AL21 VGA_TXBOUT0+ 42

2
TXOUT_U0P_DPF2P VGA_TXBOUT0-
TXOUT_U0N_DPF2N AK20 VGA_TXBOUT0- 42
PCIE_NTX_GRX_P3 P30 T24 PCIE_NRX_GTX_C_P3 C5425 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P3
PCIE_NTX_GRX_N3 PCIE_RX12P PCIE_TX12P PCIE_NRX_GTX_C_N3 C5426
N31 PCIE_RX12N PCIE_TX12N T23 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N3
TXOUT_U1P_DPF1P AH22 VGA_TXBOUT1+
VGA_TXBOUT1+ 42
AJ21 VGA_TXBOUT1-
TXOUT_U1N_DPF1N VGA_TXBOUT1- 42
PCIE_NTX_GRX_P2 N29 P27 PCIE_NRX_GTX_C_P2 C5427 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P2 AL23 VGA_TXBOUT2+
PCIE_RX13P PCIE_TX13P TXOUT_U2P_DPF0P VGA_TXBOUT2+ 42
PCIE_NTX_GRX_N2 M28 P26 PCIE_NRX_GTX_C_N2 C5428 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N2 AK22 VGA_TXBOUT2-
PCIE_RX13N PCIE_TX13N TXOUT_U2N_DPF0N VGA_TXBOUT2- 42

TXOUT_U3P AK24
PCIE_NTX_GRX_P1 M30 P24 PCIE_NRX_GTX_C_P1 C5429 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P1 AJ23
PCIE_NTX_GRX_N1 PCIE_RX14P PCIE_TX14P PCIE_NRX_GTX_C_N1 C5430 TXOUT_U3N
L31 PCIE_RX14N PCIE_TX14N P23 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N1

LVTMDP
PCIE_NTX_GRX_P0 L29 M27 PCIE_NRX_GTX_C_P0 C5431 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_P0
PCIE_NTX_GRX_N0 PCIE_RX15P PCIE_TX15P PCIE_NRX_GTX_C_N0 C5432
K30 PCIE_RX15N PCIE_TX15N N26 1 2 SCD1U16V2KX-3GP PCIE_NRX_GTX_N0
TXCLK_LP_DPE3P AL15 VGA_TXACLK+
VGA_TXACLK+ 42
B AK14 VGA_TXACLK- B
TXCLK_LN_DPE3N VGA_TXACLK- 42
AH16 VGA_TXAOUT0+
TXOUT_L0P_DPE2P VGA_TXAOUT0+ 42
CLOCK AJ15 VGA_TXAOUT0-
TXOUT_L0N_DPE2N VGA_TXAOUT0- 42
VGA_PCIE_CLK AK30
7 VGA_PCIE_CLK PCIE_REFCLKP
VGA_PCIE_CLK# AK32 AL17 VGA_TXAOUT1+
7 VGA_PCIE_CLK# PCIE_REFCLKN TXOUT_L1P_DPE1P VGA_TXAOUT1+ 42
AK16 VGA_TXAOUT1-
TXOUT_L1N_DPE1N VGA_TXAOUT1- 42
CALIBRATION AH18 VGA_TXAOUT2+
TXOUT_L2P_DPE0P VGA_TXAOUT2+ 42
L9 Y22 M92_PCIE_CALRP R5401 1 2 1K27R2F-L-GP AJ17 VGA_TXAOUT2-
NC#L9 PCIE_CALRP TXOUT_L2N_DPE0N VGA_TXAOUT2- 42
N9 NC#N9
N10 AA22 M92_PCIE_CALRN R5404 1 2 2KR2F-3-GP +1.1V_GFX_RUN AL19
NC_PWRGOOD PCIE_CALRN TXOUT_L3P
TXOUT_L3N AK18

PLTRST_DELAY# AL27
27 PLTRST_DELAY# PERSTB

M92-S2-GP M92-S2-GP
J310N J310N

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VGA-PCIE/LVDS(1/4)
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 54 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

U4B 2 OF 7

TXCAP_DPA3P AF2
TXCAM_DPA3N AF4
+1.8V_GFX_RUN +DPLL_PVDD AG3
L5501 MUTI GFX TX0P_DPA2P
TX0M_DPA2N AG5
1 2 DPA

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SCD1U16V2KX-3GP

SCD01U16V2KX-3GP
D TX1P_DPA1P AH3 D
BLM15BD121SS1D-GP AH1
TX1M_DPA1N

C5501

C5502

C5503

C5504
120 ohm 300mA

1
AA1 DVPCNTL_MVP_0 TX2P_DPA0P AK3
Y4 DVPCNTL_MVP_1 TX2M_DPA0N AK1
AC7

2
DVPCNTL_0
Y2 DVPCNTL_1 TXCBP_DPB3P AK5
U5 DVPCNTL_2 TXCBM_DPB3N AM3
U1 DVPCLK
Y7 DVPDATA_0 TX3P_DPB2P AK6
V2 AM5 +DAC1_AVDD +1.8V_GFX_RUN
DVPDATA_1 DPB TX3M_DPB2N L5502
Y8 DVPDATA_2
+1.1V_GFX_RUN +DPLL_VDDC V4 AJ7 1 2
DVPDATA_3 TX4P_DPB1P

SCD01U16V2KX-3GP

SCD1U16V2KX-3GP

SC1U6D3V2KX-GP

SC4D7U6D3V5KX-3GP
L5503 AB7 AH6
DVPDATA_4 TX4M_DPB1N

C5505

C5506

C5507

C5508
1 2 W1 BLM15BD121SS1D-GP
DVPDATA_5

1
SC10U6D3V5KX-1GP

SC1U10V3KX-3GP

SCD1U16V2KX-3GP

SCD01U16V2KX-3GP
AB8 DVPDATA_6 TX5P_DPB0P AK8
BLM15BD121SS1D-GP W3 AL7 120 ohm 300mA
DVPDATA_7 TX5M_DPB0N

C5509

C5510

C5511

C5512
120 ohm 300mA AB9

2
DVPDATA_8

1
W5 DVPDATA_9
AC6 DVPDATA_10
W6

2
DVPDATA_11
AD7 DVPDATA_12
AA3 DVPDATA_13
AC8 +DAC1_VDD1DI +1.8V_GFX_RUN
DVPDATA_14 L5504
AA5 DVPDATA_15
AE8 DVPDATA_16 1 2

SCD01U16V2KX-3GP

SCD1U16V2KX-3GP

SC1U6D3V2KX-GP
AA6 DVPDATA_17

C5513

C5514

C5515
AE9 BLM15BD121SS1D-GP
DVPDATA_18

1
AB4 DVPDATA_19
57 DVPDATA20 AD9 DVPDATA_20 120 ohm 300mA
57 DVPDATA21 AB2

2
DVPDATA_21
57 DVPDATA22 AC10 DVPDATA_22
+3.3V_DELAY AC5
57 DVPDATA23 DVPDATA_23

1
Do Not Stuff

Do Not Stuff
R5501

R5502
DY DY I2C
2

2
C R5503 1 2 Do Not Stuff R1 C
42 LCD_DDCLK
R5504 1 DY 2 Do Not Stuff R3
SCL
42 LCD_DDCDAT DY SDA
AM26 VGA_RED VGA_RED 50
R R5505
R5506 GENERAL PURPOSE I/O
RB AK26 1 2 150R2F-1-GP
+3.3V_DELAY 1 2 VGA_CLK_REQ# U6
57 GPIO_VGA_00 GPIO_0
U10 AL25 VGA_GRN VGA_GRN 50
57 GPIO_VGA_01 GPIO_1 G R5507
10KR2J-3-GP
57 GPIO_VGA_02 T10 GPIO_2 GB AJ25 1 2 150R2F-1-GP
U8 GPIO_3_SMBDATA
U7 AH24 VGA_BLU VGA_BLU 50
GPIO_4_SMBCLK B R5508
57 GPIO_VGA_05 T9 GPIO_5_AC_BATT BB AG25 1 2 150R2F-1-GP
TP5502 1 T8 DAC1
PANEL_BKEN 1 R5509 2 GPIO_6
27 PANEL_BKEN T7 GPIO_7_BLON HSYNC AH26 VGA_HSYNC 50,57
Do Not Stuff P10 AJ27 VGA_VSYNC 50,57
57 GPIO_VGA_08 GPIO_8_ROMSO VSYNC
57 GPIO_VGA_09 P4 GPIO_9_ROMSI
P2 R5510 (Placed between this pin and AVSSQ)
GPIO_10_ROMSCK VGA_RSET
27 THERMTRIP_VGA# 57 GPIO_VGA_11 N6 GPIO_11 RSET AD22 1 2
N5 499R2F-2-GP
57 GPIO_VGA_12 GPIO_12 +DAC2_VDD2DI +1.8V_GFX_RUN
57 GPIO_VGA_13 N3 GPIO_13 70mA AVDD AG24 +DAC1_AVDD
Y9 GPIO_14_HPD2 AVSSQ AE22 40mA
41 PWRCNTL_0 N1 1 R5511 2
D

GPIO_15_PWRCNTL_0

Do Not Stuff

Do Not Stuff

Do Not Stuff
M4 AE23 +DAC1_VDD1DI Do Not Stuff
7 VGA_27M_SS_CLK GPIO_16_SSIN 45mA VDD1DI

C5516

C5517

C5518
Q5501 TP5503 1VGA_THERM# R6 GPIO_17_THERMAL_INT VSS1DI AD23

1
TP5504
DY 1 W10
THERMTRIP_VGA M2 GPIO_18_HPD3
Do Not Stuff
G
P8
GPIO_19_CTF
AM12
DY DY DY
41 PWRCNTL_1

2
R5512 1 GPIO_20_PWRCNTL_1 R2
2 10KR2J-3-GP P7 GPIO_21_BB_EN R2B AK12
57 GPIO_VGA_22 N8
S

VGA_CLK_REQ# N7 GPIO_22_ROMCSB
GPIO_23_CLKREQB G2 AL11
T11 GPIO_29_DRM_0 G2B AJ11
R11 GPIO_30_DRM_1
A00 B2 AK10
+DAC2_A2VDD
Need confirm rating. +3.3V_DELAY
JTAG_TRSTB L6 AL9
8/22 JTAG_TRSTB B2B
Change Q5501 from 84.27002.N31 to 84.2N702.E31
1 L5 JTAG_TDI 65mA
TP5501 1 L3 1 R5513 2
JTAG_TCK
1
1KR2J-1-GP

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff
TP5505 1 L1 AH12 Do Not Stuff
JTAG_TMS C
R5514

C5520

C5521

C5519

C5522
TP5506 1 K4 AM10
JTAG_TDO Y

1
TP5507 JTAG_TESTEN AF24 AJ9
TESTEN COMP
TP5509 1 AB13 DAC2 DY DY DY DY
2

2
GENERICA
TP5508 1GENERICB W8 GENERICB H2SYNC AL13 DAC2_HSYNC 57
B W9 AJ13 B
+1.8V_GFX_RUN GENERICC V2SYNC DAC2_VSYNC 57
W7 GENERICD
1
1KR2J-1-GP

1 AD10 GENERICE_HPD4
R5515

TP5510 AD19 +DAC2_VDD2DI

40mA VDD2DI
1
499R2F-2-GP

1 AC14 HPD1 VSS2DI AC19

+DAC2_A2VDDQ +1.8V_GFX_RUN
R5516

TP5511
1mA L5505
2

VREFG VOLTAGE DIVIDER IS AE20 1 2

65mA A2VDD +DAC2_A2VDD

SCD1U16V2KX-3GP

SC1U6D3V2KX-GP
(VREFG = VDDR4,5(1.8V) / 3 = .6V)
2

C5523

C5524
AE17 +DAC2_A2VDDQ +3.3V_DELAY BLM15BD121SS1D-GP
1mA A2VDDQ

1
VGA_VREFG AC16 VREFG
SCD1U16V2KX-3GP

A2VSSQ AE19 120 ohm 300mA

1
249R2F-GP

C5525

2
1

1
R5517

2K2R2J-2-GP

2K2R2J-2-GP
R5518

R5519

R5520
AG13 VGA_R2SET 1 2
R2SET
2

715R2F-GP
2

2
+DPLL_PVDD DDC/AUX AE6 LCD_DDCLK_R 1 R5521 2 Do Not Stuff
DDC1CLK LCD_DDCLK 42
PLL/CLOCK
DDC1DATA AE5 LCD_DDCDAT_R 1 R5522 2 Do Not Stuff LCD_DDCDAT 42
AF14 DPLL_PVDD 120mA
+DPLL_VDDC AE14 AD2
DPLL_PVSS AUX1P
AUX1N AD4
R5523 Do Not Stuff
M92CRT_DDCCLK DDC_CLK_CON
AD14 DPLL_VDDC 300mA DDC2CLK AC11
M92CRT_DDCDATA
1 DY 2
DDC_DATA_CON
X01
R5525 DDC2DATA AC13 1 DY 2
04/14 Del
1 2 XTALIN_R AM28 AD13 R5524 Do Not Stuff 1.Del R5521 ,reserve closed-gap.
7 VGA_27M_NSS_CLK XTALIN AUX2P Del R5522 ,reserve closed-gap.
1 AK28 XTALOUT AUX2N AD11
1
150R2F-1-GP

124R2F-U-GP TP5512
R5526

NC#AB22 AB22
NC#AC22 AC22
+3.3V_DELAY
2

29 VGA_THERMDA T4 DPLUS
T2 THERMAL
+1.8V_GFX_RUN 29 VGA_THERMDC DMINUS
AE16 RN5502
DDCAUX5P
DDCAUX5N AD16 4 1
L5506 TP5513 1 FAN_PWM R5 3 2
+TSVDD TS_FDO +3.3V_DELAY
1 2 AD17 TSVDD 20mA DDC6CLK AC1
AC17 AC3 SRN4K7J-8-GP
A TSVSS DDC6DATA A
SC1U10V3KX-3GP

SCD1U16V2KX-3GP

BLM15BD121SS1D-GP
C5526

C5527

120 ohm 300mA NC_DDCAUX7P AD20

1

NC_DDCAUX7N AC20 U5501

M92CRT_DDCDATA 4 3 DDC_DATA_CON
DDC_DATA_CON 50
2

M92-S2-GP 5 2 Main Source

J310N
DDC_CLK_CON 6 1 M92CRT_DDCCLK
50 DDC_CLK_CON
Wistron Corporation
DMN66D0LDW-7-GP 5V @ CRT side 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
A00 Taipei Hsien 221, Taiwan, R.O.C.
8/22
Title
Change U5501 from 84.27002.B3F to 84.DMN66.03F
VGA-TV/CRT/DP PORT(2/4)
Size Document Number Rev
A2
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 55 of 65
5 4 3 2 1
 A B C D E

U4E 5 OF 7

SSID = VIDEO +1.8V_GFX_RUN +1.8V_GFX_RUN

AA27 PCIE_VSS GND A3
AB24 PCIE_VSS GND A30

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
AB32 PCIE_VSS GND AA13
AC24 PCIE_VSS GND AA16

1
C5601

C5602

C5603

C5604

C5605

C5606

C5607

C5608

C5609

C5610

C5611
AC26 PCIE_VSS GND AB10

1
AC27 PCIE_VSS GND AB15
AD25 AB6

2
PCIE_VSS GND
AD32 AC9

2
PCIE_VSS GND
AE27 PCIE_VSS GND AD6
AF32 PCIE_VSS GND AD8
AG27 PCIE_VSS GND AE7
AH32 PCIE_VSS GND AG12
K28 PCIE_VSS GND AH10

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
K32 AH28 U4D 4 OF 7
PCIE_VSS GND
L27 PCIE_VSS GND B10

1
+1.8V_GFX_RUN

C5612

C5613

C5614

C5615

C5616

C5617

C5618
1 M32 B12 MEM I/O 1
PCIE_VSS GND PCIE
N25 PCIE_VSS GND B14
N27 B16 H13 AB23

2
PCIE_VSS GND VDDR1 PCIE_VDDR

SCD01U16V2KX-3GP

SCD1U16V2KX-3GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP
P25 PCIE_VSS GND B18 H16 VDDR1 PCIE_VDDR AC23

C5628

C5619

C5620

C5621

C5622

C5629

C5623
P32 PCIE_VSS GND B20 H19 VDDR1 PCIE_VDDR AD24

1
R27 B22 J10 AE24

500mA
PCIE_VSS GND VDDR1 PCIE_VDDR
T25 PCIE_VSS GND B24 J23 VDDR1 PCIE_VDDR AE25
T32 B26 J24 AE26

2
PCIE_VSS GND VDDR1 PCIE_VDDR
U25 PCIE_VSS GND B6 J9 VDDR1 PCIE_VDDR AF25

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP
U27 PCIE_VSS GND B8 K10 VDDR1 PCIE_VDDR AG26

C5624

C5625

C5626

C5630

C5627
V32 C1 K23 2.2A +1.1V_GFX_RUN
PCIE_VSS GND VDDR1

1
W25 PCIE_VSS GND C32 K24 VDDR1
W26 PCIE_VSS GND E28 K9 VDDR1 PCIE_VDDC L23

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP
W27 F10 L11 L24

2
PCIE_VSS GND VDDR1 PCIE_VDDC

C5631

C5632

C5633

C5634

C5635

C5636

C5637

C5638

C5639
Y25 PCIE_VSS GND F12 L12 VDDR1 PCIE_VDDC L25

1
Y32 PCIE_VSS GND F14 L13 VDDR1 PCIE_VDDC L26
GND F16 L20 VDDR1 PCIE_VDDC M22
F18 L21 N22

2
GND VDDR1 PCIE_VDDC
GND F2 L22 VDDR1
2A PCIE_VDDC N23
F20 +1.8V_GFX_RUN N24
GND L5601 PCIE_VDDC
M6 GND GND F22 PCIE_VDDC R22
N11 F24 1 2 +VDD_CT T22
GND GND PCIE_VDDC

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
N12 F26 LEVEL U22
GND GND BLM15BD121SS1D-GP TRANSLATION PCIE_VDDC +VCC_GFX_CORE
N13 GND GND F6 PCIE_VDDC V22

1
C5640

C5641

C5642

C5643

C5644
N16 F8 AA20
N18
GND
GND GND
G10 120 ohm 300mA AA21
VDD_CT

136mA
GND GND VDD_CT
N21 G27 AB20 AA15

2
GND GND VDD_CT VDDC

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
P6 G31 AB21 CORE N15
GND GND VDD_CT VDDC

C5645

C5646

C5647

C5648

C5649

C5650

C5651

C5652

C5653

C5654

C5655

C5656

C5657

C5658

C5659
P9 GND GND G8 VDDC N17

1
R12 GND GND H14 VDDC R13
R15 H17 I/O R16
GND GND VDDC
R17 H2 AA17 R18

2
GND GND +3.3V_DELAY VDDR3 VDDC
R20 H20 AA18 R21

60mA
GND GND VDDR3 VDDC
T13 GND GND H6 AB17 VDDR3 VDDC T12
T16 GND GND J27 AB18 VDDR3 VDDC T15

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
T18 GND GND J31 VDDC T17
T21 GND GND K11 VDDC T20

1
C5660

C5661

C5662

C5663
T6 GND GND K2 U11 VDDR5 VDDC U13
U15 K22 U12 U16

170mA
GND GND VDDR5 VDDC
U17 K6 V11 U18

2
GND GND VDDR5 VDDC
U20 GND V12 VDDR5 VDDC U21

POWER
2 U3 GND VDDC V15 2
U9 GND VDDC V17
V13 GND AA11 VDDR4 VDDC V20
V16 +1.8V_GFX_RUN AA12 V21

170mA
GND VDDR4 VDDC
V18 GND Y11 VDDR4 VDDC Y13
V6 GND Y12 VDDR4 VDDC Y16

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
Y10 GND VSS_MECH A32 VDDC Y18
Y15 AM1 +1.8V_GFX_RUN Y21
GND VSS_MECH VDDC

1
C5664

C5665

C5666

C5667
Y17 AM32 L5602 MEM CLK
GND VSS_MECH +VDDRHA
Y20 GND 1 2 L17 VDDRHA
Y6

2
GND

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP
BLM15BD121SS1D-GP L16 ISOLATED +VCC_GFX_CORE
VSSRHA

1
C5668

C5669
CORE I/O
120 ohm 300mA +PCIE_PVDD
VDDCI M13

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP
M92-S2-GP PLL M15

2
VDDCI

C5670

C5671

C5672

C5673

C5674

C5675
J310N AM30 M16
PCIE_PVDD 68mA VDDCI

1
+1.8V_GFX_RUN +PCIE_PVDD M17
L5603 VDDCI
VDDCI M18
1 2 L8 M20

2
NC_MPV18 VDDCI

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD01U16V2KX-3GP
VDDCI M21

C5676

C5677

C5678

C5679
BLM15BD121SS1D-GP N20
VDDCI

1
+SPV10 H7 NC_SPV18
120 ohm 300mA
H8 35mA
2

2
SPV10 +VCC_GFX_CORE
J7 SPVSS

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
C5680

C5681

C5682

C5683
+VCC_GFX_CORE +SPV10 +VCC_GFX_CORE

1
L5604 BACK BIAS
1 2 M11 BBP#1
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD01U16V2KX-3GP
M12 144mA

2
BBP#2
C5684

C5685

C5686

C5687
BLM15BD121SS1D-GP
1

1
120 ohm 300mA
M92-S2-GP
2

2
J310N
+1.8V_GFX_RUN
L5605
1 2
SC4D7U6D3V5KX-3GP SC4D7U6D3V5KX-3GP SC4D7U6D3V5KX-3GP SC4D7U6D3V5KX-3GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP
C5688

C5689

C5690

3 BLM15BD121SS1D-GP 3
1

120 ohm 300mA U4G 7 of 7

2

DP E/F POWER DP A/B POWER

+1.1V_GFX_RUN +DPE_VDD18 AG15 AE11

200mA

L5606 DPE_VDD18 NC_DPA_VDD18

AG16 DPE_VDD18 NC_DPA_VDD18 AF11
1 2 +1.1V_GFX_RUN
SC1U6D3V2KX-GP

SCD1U16V2KX-3GP
C5691

C5692

C5693

BLM18PG300SN-GP
1

+DPE_VDD10 AG20 AF6 +DPA_VDD101 R5601 2

170mA

200mA

DPE_VDD10 DPA_VDD10 Do Not Stuff

30 ohm 1A AG21 DPE_VDD10 DPA_VDD10 AF7
2

AG14 DPE_VSSR DPA_VSSR AE1

+1.8V_GFX_RUN AH14 AE3
L5607 DPE_VSSR DPA_VSSR
AM14 DPE_VSSR DPA_VSSR AG1
1 2 AM16 DPE_VSSR DPA_VSSR AG6
SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

AM18 DPE_VSSR DPA_VSSR AH5

C5694

C5695

C5696

BLM15BD121SS1D-GP
1

120 ohm 300mA +DPF_VDD18 AF16 AE13

200mA
2

DPF_VDD18 NC_DPB_VDD18
AG17 DPF_VDD18 NC_DPB_VDD18 AF13
+1.1V_GFX_RUN
+1.1V_GFX_RUN
L5608
1 2 +DPF_VDD10 AF22 AF8 +DPB_VDD101 R5602 2
170mA

200mA

DPF_VDD10 DPB_VDD10
SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

AG22 AF9 Do Not Stuff

DPF_VDD10 DPB_VDD10
C5697

C5698

C5699

BLM18PG300SN-GP
1

30 ohm 1A AF23 DPF_VSSR DPB_VSSR AF10

AG23 AG9
2

DPF_VSSR DPB_VSSR
AM20 DPF_VSSR DPB_VSSR AH8
AM22 DPF_VSSR DPB_VSSR AM6
AM24 DPF_VSSR DPB_VSSR AM8
+1.8V_GFX_RUN
L5609
1 2
SC4D7U6D3V5KX-3GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

R5603 R5604
4 4
C5700

C5701

C5702

BLM15BD121SS1D-GP 1 2 AF17 AE10 1 2

DPEF_CALR DPAB_CALR
1

150R2F-1-GP 150R2F-1-GP +1.8V_GFX_RUN

120 ohm 300mA
20mA 20mA
2

+DPE_PVDD AG18 DP PLL POWER AG8 +DPA_PVDD 1 R5605 2

DPE_PVDD DPA_PVDD Do Not Stuff
AF19 DPE_PVSS DPA_PVSS AG7
Main Source
+1.8V_GFX_RUN +1.8V_GFX_RUN
L5610 20mA
1 2 +DPF_PVDD AG19 NC_DPF_PVDD DPB_PVDD AG10 +DPB_PVDD 1 R5606 2 Wistron Corporation
SC4D7U6D3V5KX-3GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

AF20 AG11 Do Not Stuff 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
NC_DPF_PVSS DPB_PVSS
C5703

C5704

C5705

BLM15BD121SS1D-GP Taipei Hsien 221, Taiwan, R.O.C.

1

120 ohm 300mA Title

M92-S2-GP VGA-POWER/GND(3/4)
2

J310N
Size Document Number Rev
A2 Riya Discrete A00
Date: Friday, September 04, 2009 Sheet 56 of 65
A B C D E
 A B C D E

X01
SSID = VIDEO 58,59 MDA[0..63]
U4C 3 OF 7 04/10 modify
1. Stuff R5702,R5703
+3.3V_DELAY

ATI RESERVED CONFIGURATION STRAPS

MAA[0..12] 58,59
MDA0 K27 K17 MAA0 55 GPIO_VGA_00 R5702 1 2 10KR2J-3-GP ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
MDA1 DQA_0 MAA_0 MAA1
J29 DQA_1 MAA_1 J20 THEY MUST NOT CONFLICT DURING RESE
MDA2 H30 H23 MAA2
MDA3 DQA_2 MAA_2 MAA3 R5703
H32 DQA_3 MAA_3 G23 55 GPIO_VGA_01 1 2 10KR2J-3-GP
MDA4 MAA4 GPIO3 , H2SYNC , V2SYNC

MEMORY INTERFACE
G29 DQA_4 MAA_4 G24
MDA5 F28 H24 MAA5
MDA6 DQA_5 MAA_5 MAA6 R5704
F32 DQA_6 MAA_6 J19 55 GPIO_VGA_02 1 DY 2 Do Not Stuff PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
MDA7 F30 K19 MAA7 THEY MUST NOT CONFLICT DURING RESET
MDA8 DQA_7 MAA_7 MAA8
C30 DQA_8 MAA_8 J14
MDA9 MAA9 R5705 2 Do Not Stuff
MDA10
F27
A28
DQA_9 MAA_9 K14
J11 MAA10
55 GPIO_VGA_05 1 DY
MDA11 DQA_10 MAA_10 MAA11
C28 DQA_11 MAA_11 J13 If BIOS_ROM_EN (GPIO22) = 0 If BIOS_ROM_EN (GPIO22) = 1
MDA12 MAA12 R5707 2 Do Not Stuff
MDA13
E27
G26
DQA_12 MAA_12 H11
G11 BA2
55 GPIO_VGA_08 1 DY Size of the primary
DQA_13 MAA_13/BA2 BA2 58,59
MDA14 BA0
1
MDA15
D26 DQA_14 MAA_14/BA0 J16
BA1
BA0 58,59
R5708 memory apertures GPIO[13,12,11] Manufacturer Part Number GPIO[13,12,11] 1
F25 DQA_15 MAA_15/BA1 L15 BA1 58,59 55 GPIO_VGA_09 1 DY 2 Do Not Stuff
MDA16 A25
MDA17 DQA_16 DQMA#0
C25 DQA_17 DQMA_0 E32 DQMA#0 58 M25P05A x100
MDA18 E25 E30 DQMA#1 R5709 1 2 10KR2J-3-GP 128MB x000 ST
MDA19 DQA_18 DQMA_1 DQMA#2
DQMA#1 58 55 GPIO_VGA_11 M25P10A x101
MDA20
D24
E23
DQA_19 DQMA_2 A21
C21 DQMA#3
DQMA#2 58 * 256MB x001 Microelectronics M25P20 x101
DQA_20 DQMA_3 DQMA#3 58 64MB x010
MDA21 DQMA#4 R5710 2 Do Not Stuff
MDA22
F23
D22
DQA_21 DQMA_4 E13
D12 DQMA#5
DQMA#4 59 55 GPIO_VGA_12 1 DY 32MB Not Supported
M25P40 x101
DQA_22 DQMA_5 DQMA#5 59 M25P80 x101
MDA23 F21 E3 DQMA#6
DQA_23 DQMA_6 DQMA#6 59 512MB Not Supported
MDA24 DQMA#7 R5711 2 Do Not Stuff
MDA25
E21
D20
DQA_24 DQMA_7 F4 DQMA#7 59 55 GPIO_VGA_13 1 DY 1GB Not Supported
MDA26 DQA_25 RDQSA0
F19 DQA_26 RDQSA_0 H28 RDQSA0 58 2GB Not Supported Chingis
MDA27 RDQSA1 R5712 2 Do Not Stuff Pm25LV512A x100
MDA28
A19
D18
DQA_27 RDQSA_1 C27
A23 RDQSA2
RDQSA1 58 55 GPIO_VGA_22 1 DY 4GB Not Supported (formerly PMC) Pm25LV010A x101
DQA_28 RDQSA_2 RDQSA2 58
MDA29 F17 E19 RDQSA3
DQA_29 RDQSA_3 RDQSA3 58
MDA30 RDQSA4 R5713 2 Do Not Stuff
MDA31
A17
C17
DQA_30 RDQSA_4 E15
D10 RDQSA5
RDQSA4 59 55 DAC2_VSYNC 1 DY
DQA_31 RDQSA_5 RDQSA5 59
MDA32 E17 D6 RDQSA6 STRAPS PIN DESCRIPTION
DQA_32 RDQSA_6 RDQSA6 59
MDA33 RDQSA7 R5714 2 Do Not Stuff
MDA34
D16
F15
DQA_33 RDQSA_7 G5 RDQSA7 59 55 DAC2_HSYNC 1 DY Tansmitter Power Savings Enable
MDA35 DQA_34 WDQSA0
VRAM TYPE R5701 R5724 A15 DQA_35 WDQSA_0 H27 WDQSA0 58 TX_PWRS_ENB GPIO0 0= 50% Tx output swing
MDA36 WDQSA1 R5715 2 10KR2J-3-GP
MDA37
D14 DQA_36 WDQSA_1 A27
WDQSA2
WDQSA1 58 50,55 VGA_VSYNC 1
(Internal PD)
* 1= Full Tx output swing
* DDR2 100R
MDA38
F13
A13
DQA_37 WDQSA_2 C23
C19 WDQSA3
WDQSA2 58
DQA_38 WDQSA_3 WDQSA3 58
DDR3 40.2R MDA39 C13 C15 WDQSA4 R5716 1 2 10KR2J-3-GP Transmitter De-emphasis Enable
DQA_39 WDQSA_4 WDQSA4 59 50,55 VGA_HSYNC
MDA40 E11 E9 WDQSA5 TX_DEEMPH_EN GPIO1 0= Tx de-emphasis disabled
DQA_40 WDQSA_5 WDQSA5 59
*DEFAULT MDA41 WDQSA6
MDA42
A11
C11
DQA_41 WDQSA_6 C5
H4 WDQSA7
WDQSA6 59
(Internal PD)
* 1= Tx de-emphasis enabled
DQA_42 WDQSA_7 WDQSA7 59
( 0.5 * VDDR1 ) ( for SSTL-1.8/SSTL-2/DDR2 ) MDA43 F11
MDA44 DQA_43 ODTA0
( 0.7 * VDDR1 ) ( for GDDR3/GDDR4 ) A9 DQA_44 ODTA0 L18 ODTA0 58 * 0 = Advertises the PCI-E device
MDA45 C9 K16 ODTA1 BIF_GEN2_EN_A GPIO2 as 2.5GT/s
DQA_45 ODTA1 ODTA1 59
MDA46 F9 1 = Advertises the PCI-E device
MDA47 DQA_46 CLKA0
D8 DQA_47 CLKA0 H26 CLKA0 58 as 5GT/s
+1.8V_GFX_RUN MDA48 E7 H25 CLKA0#
DQA_48 CLKA0B CLKA0# 58
MDA49 A7 DQA_49
100R2F-L1-GP-U

MDA50 C7 G9 CLKA1
DQA_50 CLKA1 CLKA1 59
1

MDA51 F7 H9 CLKA1#
DQA_51 CLKA1B CLKA1# 59
R5701

MDA52 BIF_CLK_PM_EN GPIO8 0= Disable CLKREQ#power management capability

MDA53
A5
E5
DQA_52
G22 RASA0#
* 1= Enable CLKREQ# power management capability
DQA_53 RASA0B RASA0# 58
MDA54 C3 G17 RASA1#
DQA_54 RASA1B RASA1# 59
2 MDA55 E1 2
2

MDA56 DQA_55 CASA0#

G7 DQA_56 CASA0B G19 CASA0# 58
MDA57 G6 G16 CASA1# ROMIDCFG[3:0] if BIOS_ROM_EN=1,then Config[3:0]
DQA_57 CASA1B CASA1# 59
100R2F-L1-GP-U

SCD01U16V2KX-3GP

SCD1U16V2KX-3GP

MDA58 G1 GPIO[13,12,11] defines the ROM type

DQA_58
1

C5707

C5708

MDA59 G3 H22 CSA0_0# (Internal PD) if BIOS_ROM_EN=0,then Config[3:0]

DQA_59 CSA0B_0 CSA0_0# 58
1

+1.8V_GFX_RUN
R5717

MDA60 J6 J22
MDA61 DQA_60 CSA0B_1 defines the primary memory apeture size
J1 DQA_61
+1.8V_GFX_RUN MDA62 J3 G13 CSA1_0#
CSA1_0# 59
2

MDA63 DQA_62 CSA1B_0 R5746

J5 K13 55 DVPDATA20 1 DY 2 Do Not Stuff
2

DQA_63 CSA1B_1
100R2F-L1-GP-U

Enable external BIOS ROM device

1

MVREFD CKEA0 BIOS_ROM_EN GPIO_22_ROMCSB

K26 MVREFDA CKEA0 K20 CKEA0 58 * 0= Disable external BIOS ROM device
R5724

MVREFS CKEA1 R5747 2 Do Not Stuff

+1.8V_GFX_RUN
J26 MVREFSA CKEA1 J17 CKEA1 59 55 DVPDATA21 1 DY (Internal PD)
1= Enable external BIOS ROM device
R5726 1 2 Do Not Stuff WEA0#
R5728 1 DY 2 Do Not Stuff
J25 NC_MEM_CALRN0 WEA0B G25
WEA1#
WEA0# 58
R5748 2 Do Not Stuff AUD[1:0]
DY K7 H10 WEA1# 59 55 DVPDATA22 1 DY
2

NC_MEM_CALRN1 WEA1B
R5730 1 2 243R2F-2-GP J8 AB16 AUD[1] VGA_HSYNC
* 00:No audio function
MEM_CALRP1 RSVD#1 01:Audio for DisplayPort and HDMI
100R2F-L1-GP-U

SCD01U16V2KX-3GP

SCD1U16V2KX-3GP

R5731 1 2 Do Not Stuff R5749 2 Do Not Stuff

DY K25 NC_MEM_CALRP0 RSVD#2 G14 55 DVPDATA23 1 DY AUD[0] VGA_VSYNC ( if adapter is detected)
1

C5706

C5709

RSVD#3 G20
1

10:Audio for DisplayPort only

R5733

L10 DRAM_RST
(Internal PD) 11:Audio for both DisplayPort and HDMI
K8
2

CLKTESTA
L7
2

CLKTESTB
1

1
4K7R2J-2-GP

4K7R2J-2-GP
R5738

R5739

M92-S2-GP STRAPS PIN DESCRIPTION

J310N

MEM_TYPE DVPDATA(23:20) MEMORY TYPE,MAKE AND SIZE INFO

2

(Internal PD)
* 0000 - GDDR2 64Mx16 500MHz HYNIX
0001 - GDDR2 64Mx16 500MHz SAMSUNG
0010 - Reserve
0011 - Reserve

*DEFAULT

3 3

4 4

Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VGA-MEMORY/STRAPS(4/4)
Size Document Number Rev
A2
Riya Discrete A00
Date: Wednesday, August 26, 2009 Sheet 57 of 65
A B C D E
 5 4 3 2 1

SSID = VIDEO VRAM

1'st 72.51G63.A0U
2'nd 72.41164.G0U
MDA[0..63] 57,59 MDA[0..63] 57,59
U5801 U5802
D MDA15 MDA17 D
57,59 BA0 L2 BA0 DQ15 B9 57,59 BA0 L2 BA0 DQ15 B9
L3 B1 MDA8 L3 B1 MDA20
57,59 BA1 BA1 DQ14 57,59 BA1 BA1 DQ14
D9 MDA14 D9 MDA19
57,59 MAA[0..12] DQ13 57,59 MAA[0..12] DQ13
MAA12 R2 D1 MDA9 MAA12 R2 D1 MDA23
MAA11 A12 DQ12 MDA12 MAA11 A12 DQ12 MDA22
P7 A11 DQ11 D3 P7 A11 DQ11 D3
MAA10 M2 D7 MDA10 MAA10 M2 D7 MDA18
MAA9 A10/AP DQ10 MDA13 MAA9 A10/AP DQ10 MDA21
P3 A9 DQ9 C2 P3 A9 DQ9 C2
MAA8 P8 C8 MDA11 MAA8 P8 C8 MDA16
MAA7 A8 DQ8 MDA28 MAA7 A8 DQ8 MDA1
P2 A7 DQ7 F9 P2 A7 DQ7 F9
MAA6 N7 F1 MDA24 MAA6 N7 F1 MDA2
MAA5 A6 DQ6 MDA30 MAA5 A6 DQ6 MDA0
N3 A5 DQ5 H9 N3 A5 DQ5 H9
MAA4 N8 H1 MDA26 MAA4 N8 H1 MDA6
MAA3 A4 DQ4 MDA25 MAA3 A4 DQ4 MDA5
N2 A3 DQ3 H3 N2 A3 DQ3 H3
MAA2 M7 H7 MDA31 MAA2 M7 H7 MDA3
MAA1 A2 DQ2 MDA29 MAA1 A2 DQ2 MDA4
M3 A1 DQ1 G2 M3 A1 DQ1 G2
MAA0 M8 G8 MDA27 MAA0 M8 G8 MDA7
A0 DQ0 A0 DQ0

K8 A9 +1.8V_GFX_RUN K8 A9 +1.8V_GFX_RUN
57 CLKA0# CK# VDDQ 57 CLKA0# CK# VDDQ
57 CLKA0 J8 CK VDDQ C1 57 CLKA0 J8 CK VDDQ C1
VDDQ C3 VDDQ C3
57 CKEA0 K2 CKE VDDQ C7 57 CKEA0 K2 CKE VDDQ C7
VDDQ C9 VDDQ C9
VDDQ E9 VDDQ E9
VDDQ G1 VDDQ G1
57 CSA0_0# L8 CS# VDDQ G3 57 CSA0_0# L8 CS# VDDQ G3

BLM15BD121SS1D-GP SC1U6D3V3KX-1GP

BLM15BD121SS1D-GP SC1U6D3V3KX-1GP
VDDQ G7 VDDQ G7
57 WEA0# K3 WE# VDDQ G9 57 WEA0# K3 WE# VDDQ G9

1
C 57 RASA0# K7 RAS# VDD A1 57 RASA0# K7 RAS# VDD A1 C
VDD E1 VDD E1

L5801

L5802
57 CASA0# L7 CAS# VDD J9 120 ohm @ 100MHz,300mA 57 CASA0# L7 CAS# VDD J9
VDD M9 VDD M9 120 ohm @ 100MHz,300mA
57 DQMA#3 F3 LDM VDD R1 57 DQMA#0 F3 LDM VDD R1
57 DQMA#1 B3 57 DQMA#2 B3

2
UDM VDDL_VRAM1 UDM VDDL_VRAM2
VDDL J1 VDDL J1
VSSDL J7 VSSDL J7 Layout Note: 50 mil for VSSDL

C5802
57 ODTA0 K9 ODT Layout Note: 50 mil for VSSDL 57 ODTA0 K9 ODT

1
C5801
57 RDQSA3 F7 57 RDQSA0 F7

2
+1.8V_GFX_RUN LDQS +1.8V_GFX_RUN LDQS
57 WDQSA3 E8 LDQS# VSSQ A7 57 WDQSA0 E8 LDQS# VSSQ A7
VSSQ B2 VSSQ B2
VSSQ B8 VSSQ B8
1

1
4K99R2F-L-GP 4K99R2F-L-GP

4K99R2F-L-GP 4K99R2F-L-GP
VSSQ D2 VSSQ D2
R5805

R5801
57 RDQSA1 B7 UDQS VSSQ D8 57 RDQSA2 B7 UDQS VSSQ D8
57 WDQSA1 A8 UDQS# VSSQ E7 57 WDQSA2 A8 UDQS# VSSQ E7
VSSQ F2 VSSQ F2
F8 F8
2

2
MEM_VREF_CHIP1 VSSQ MEM_VREF_CHIP2 VSSQ
J2 VREF VSSQ H2 J2 VREF VSSQ H2
SCD1U10V2KX-4GP

VSSQ H8 VSSQ H8
1

1
C5803

SCD1U10V2KX-4GP

C5804
A2 NC#A2 A2 NC#A2
1

1
R5806

R5802
E2 NC#E2 VSS A3 E2 NC#E2 VSS A3
57,59 BA2 L1 BA2 VSS E3 57,59 BA2 L1 BA2 VSS E3
R3 J3 R3 J3
2

2
NC#R3 VSS NC#R3 VSS
R7 N1 R7 N1
2

2
NC#R7 VSS NC#R7 VSS
R8 NC#R8 VSS P9 R8 NC#R8 VSS P9

B H5PS1G63EFR-20L-GP H5PS1G63EFR-20L-GP B
C034T$AA C034T$AA

CLKA0

1
+1.8V_GFX_RUN +1.8V_GFX_RUN

56R2F-1-GP
Place below decoupling caps close VDD pin. Place below decoupling caps close VDD pin.

R5803
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C5805

C5806

C5807

C5808

C5809

C5810

C5811

C5812

C5813

C5820

C5821

C5818

C5817

C5816

C5819

C5814

C5815

C5822
C5823

2
1

1
1 2

1
56R2F-1-GP
SC470P50V3JN-2GP
2

R5804
2
CLKA0#

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VRAM_(1/2)
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, September 09, 2009 Sheet 58 of 65
5 4 3 2 1
 5 4 3 2 1

SSID = VIDEO

MDA[0..63] 57,58 MDA[0..63] 57,58

U5901 U5902
L2 B9 MDA63 L2 B9 MDA46
57,58 BA0 BA0 DQ15 57,58 BA0 BA0 DQ15
L3 B1 MDA60 L3 B1 MDA45
57,58 BA1 BA1 DQ14 57,58 BA1 BA1 DQ14
D9 MDA61 D9 MDA44
D 57,58 MAA[0..12] DQ13 57,58 MAA[0..12] DQ13 D
MAA12 R2 D1 MDA56 MAA12 R2 D1 MDA43
MAA11 A12 DQ12 MDA57 MAA11 A12 DQ12 MDA40
P7 A11 DQ11 D3 P7 A11 DQ11 D3
MAA10 M2 D7 MDA58 MAA10 M2 D7 MDA41
MAA9 A10/AP DQ10 MDA59 MAA9 A10/AP DQ10 MDA42
P3 A9 DQ9 C2 P3 A9 DQ9 C2
MAA8 P8 C8 MDA62 MAA8 P8 C8 MDA47
MAA7 A8 DQ8 MDA33 MAA7 A8 DQ8 MDA51
P2 A7 DQ7 F9 P2 A7 DQ7 F9
MAA6 N7 F1 MDA34 MAA6 N7 F1 MDA48
MAA5 A6 DQ6 MDA35 MAA5 A6 DQ6 MDA50
N3 A5 DQ5 H9 N3 A5 DQ5 H9
MAA4 N8 H1 MDA36 MAA4 N8 H1 MDA55
MAA3 A4 DQ4 MDA37 MAA3 A4 DQ4 MDA54
N2 A3 DQ3 H3 N2 A3 DQ3 H3
MAA2 M7 H7 MDA38 MAA2 M7 H7 MDA49
MAA1 A2 DQ2 MDA39 MAA1 A2 DQ2 MDA53
M3 A1 DQ1 G2 M3 A1 DQ1 G2
MAA0 M8 G8 MDA32 MAA0 M8 G8 MDA52
A0 DQ0 A0 DQ0

K8 A9 +1.8V_GFX_RUN K8 A9 +1.8V_GFX_RUN
57 CLKA1# CK# VDDQ 57 CLKA1# CK# VDDQ
57 CLKA1 J8 CK VDDQ C1 57 CLKA1 J8 CK VDDQ C1
VDDQ C3 VDDQ C3
57 CKEA1 K2 CKE VDDQ C7 57 CKEA1 K2 CKE VDDQ C7
VDDQ C9 VDDQ C9
VDDQ E9 VDDQ E9
VDDQ G1 VDDQ G1
57 CSA1_0# L8 CS# VDDQ G3 57 CSA1_0# L8 CS# VDDQ G3

BLM15BD121SS1D-GP SC1U6D3V3KX-1GP

BLM15BD121SS1D-GP SC1U6D3V3KX-1GP
VDDQ G7 VDDQ G7
57 WEA1# K3 WE# VDDQ G9 57 WEA1# K3 WE# VDDQ G9

1
57 RASA1# K7 RAS# VDD A1 57 RASA1# K7 RAS# VDD A1
VDD E1 VDD E1

L5901

L5902
57 CASA1# L7 CAS# VDD J9 57 CASA1# L7 CAS# VDD J9
C VDD M9 120 ohm @ 100MHz,300mA VDD M9 120 ohm @ 100MHz,300mA C
57 DQMA#4 F3 LDM VDD R1 57 DQMA#6 F3 LDM VDD R1
57 DQMA#7 B3 57 DQMA#5 B3

2
UDM VDDL_VRAM3 UDM VDDL_VRAM4
VDDL J1 VDDL J1
VSSDL J7 Layout Note: 50 mil for VSSDL VSSDL J7 Layout Note: 50 mil for VSSDL

C5901

C5902
57 ODTA1 K9 ODT 57 ODTA1 K9 ODT

1
57 RDQSA4 F7 57 RDQSA6 F7

2
+1.8V_GFX_RUN LDQS +1.8V_GFX_RUN LDQS
57 WDQSA4 E8 LDQS# VSSQ A7 57 WDQSA6 E8 LDQS# VSSQ A7
VSSQ B2 VSSQ B2
VSSQ B8 VSSQ B8
1

1
4K99R2F-L-GP 4K99R2F-L-GP

4K99R2F-L-GP 4K99R2F-L-GP
VSSQ D2 VSSQ D2
R5905

R5901
57 RDQSA7 B7 UDQS VSSQ D8 57 RDQSA5 B7 UDQS VSSQ D8
57 WDQSA7 A8 UDQS# VSSQ E7 57 WDQSA5 A8 UDQS# VSSQ E7
VSSQ F2 VSSQ F2
F8 F8
2

2
MEM_VREF_CHIP3 VSSQ MEM_VREF_CHIP4 VSSQ
J2 VREF VSSQ H2 J2 VREF VSSQ H2
SCD1U10V2KX-4GP

VSSQ H8 VSSQ H8
1

1
C5903

SCD1U10V2KX-4GP

C5904
A2 NC#A2 A2 NC#A2
1

1
R5906

R5902
E2 NC#E2 VSS A3 E2 NC#E2 VSS A3
57,58 BA2 L1 BA2 VSS E3 57,58 BA2 L1 BA2 VSS E3
R3 J3 R3 J3
2

2
NC#R3 VSS NC#R3 VSS
R7 N1 R7 N1
2

2
NC#R7 VSS NC#R7 VSS
R8 NC#R8 VSS P9 R8 NC#R8 VSS P9

H5PS1G63EFR-20L-GP H5PS1G63EFR-20L-GP
C034T$AA C034T$AA

B B

CLKA1
+1.8V_GFX_RUN +1.8V_GFX_RUN
Place below decoupling caps close VDD pin. Place below decoupling caps close VDD pin.

1
56R2F-1-GP

R5903
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C5905

C5906

C5907

C5908

C5909

C5910

C5911

C5912

C5913

C5914

C5915

C5916

C5917

C5918

C5919

C5920

C5921

C5922
1

1
C5923

2
1 2
2

1
56R2F-1-GP
SC470P50V3JN-2GP

R5904
2
CLKA1#

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
VRAM_(2/2)
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, September 09, 2009 Sheet 59 of 65
5 4 3 2 1
 5 4 3 2 1

CLOCK BLOCK DIAGRAM

CPU
DDR2 DIMM1 AMD S1G2 DDR2 DIMM1
MEM_MA_CLK0_P MEM_MB_CLK0_P
CK0 MA_CLK_H1 MB_CLK_H1 CK0
MEM_MA_CLK0_N MEM_MB_CLK0_N
CK0# MA_CLK_L1 MB_CLK_L1 CK0#
MEM_MA_CLK1_P MEM_MB_CLK1_P
D
CK1 MA_CLK_H7 MB_CLK_H7 CK1 D
MEM_MA_CLK1_N MEM_MB_CLK1_N
CK1# MA_CLK_L7 MB_CLK_L7 CK1#

CLOCK GEN
MINI CARD
ICS9LPRS480
MINI1_PCIE_CLK CPU_CLK
PIN 13 SRC1T_LPRS CPUKG0T_LPRS CLKIN_H L0_CLKOUT_L1
MINI1_PCIE_CLK# CPU_CLK#
PIN 11 SRC1C_LPRS CPUKG0C_LPRS CLKIN_L L0_CLKOUT_H1
MINI1_CLK_REQ# L0_CLKOUT_L0
PIN 7 CLKREQ1#
L0_CLKOUT_H0

L0_CLKIN_L1
EXP CARD L0_CLKIN_H1
EXP_PCIE_CLK L0_CLKIN_L0
PIN 16 SRC2T_LPRS
EXP_PCIE_CLK# L0_CLKIN_H0
PIN 18 SRC2C_LPRS
C EXPCARD_CLK_REQ# C
PIN 5 CLKREQ2#

NB
LAN 
AMD RS780M HT_NB_CPU_CLK_H0
RTL8103EL HT_TXCLK0P
LAN_PCIE_CLK HT_NB_CPU_CLK_L0
EFCLK_P SRC3T_LPRS HT_TXCLK0N
LAN_PCIE_CLK# CLK_NBHT_CLK HT_NB_CPU_CLK_H1
REFCLK_M SRC3C_LPRS HTT0T_LPRS/66M HT_REFCLKP HT_TXCLK1P
CLK_NBHT_CLK# HT_NB_CPU_CLK_L1
HTT0C_LPRS/66M HT_REFCLKN HT_TXCLK1N
NB_GPPSB_CLK
SB_SRC0T_LPRS GPPSB_REFCLKP HT_CPU_NB_CLK_H0
GPU NB_GPPSB_CLK# HT_RXCLK0P
SB_SRC0C_LPRS GPPSB_REFCLKN HT_CPU_NB_CLK_L0
HT_RXCLK0N
ATi ATI M92S2-LP VGA_PCIE_CLK NB_GFX_CLK HT_CPU_NB_CLK_H1
PCIE_REFCLKP ATIG0T_LPRS ATIG1T_LPRS GFX_REFCLKP HT_RXCLK1P
VGA_PCIE_CLK# NB_GFX_CLK# HT_CPU_NB_CLK_L1
PCIE_REFCLKN ATIG0C_LPRS ATIG1C_LPRS GFX_REFCLKN HT_RXCLK1N
VGA_27M_SS_CLK
GPIO_16_SSIN SRC7T_LPRS/27MHZ_SS
B VGA_27M_NSS_CLK B
XTALIN SRC7C_LPRS/27MHZ_NS
SB 32K_X1
X1
SB_PCIE_CLK AMD SB700
SB_SRC1T_LPRS PCIE_RCLKP/NB_LNK_CLKP
SB_PCIE_CLK#
SB_SRC1C_LPRS PCIE_RCLKN/NB_LNK_CLKN
32K_X2
X2
USB_48M_CLK 32.768KHz
48MHZ_0 USBCLK/14M_25M_48M_OSC
SATA_X1
SATA_X1

KBC KBC_XO
SATA_X2 32KX2
SATA_X2
25MHz WPCE773L
KBC_PCI_CLK
CLKGEN_X1 X1 PCICLK0 LCLK
KBC_XI
32KX1/32KCLKIN
A
32.768KHz A
14.318 MHz Main Source

CLKGEN_X2 X2 Card Reader  Wistron Corporation

CARD_48M_CLK
XTLIRTS5159 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CLOCK BLOCK DIAGRAM
Size Document Number Rev
Custom
Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 60 of 65
5 4 3 2 1
 5 4 3 2 1

D D

RESET BLOCK DIAGRAM

CPU GPU
AMD S1G2 ATi ATI M92S2-LP
RESET_L PERSTB

CPU_LDT_RST#
C C
LAN 
RTL8103EL
NB PERST#
AMD RS780M
+3.3V_PHY
SYSRESET#
RC DELAY
MINI CARD
Card Reader 
RTS5159
CARD_R_PLT_RST# PIN 22
RST#

G577BR91U
KBC SB
WPCE773L KBRCIN# AMD SB700 PERST#
B KBRST# KBRST#/GEVENT1# LDT_RST# SYSRST# PERST# B

KBC_RSMRST#
LRESET# GPIO43/TMS RSMRST# PLT_RST#
A_RST# BUFFER

AZ_RST# EXP CARD

AUDIO CODEC
IDT 92HD81 SB_AZ_CODEC_RST#
HDA_RST# PIN 11

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
RESET BLOCK DIAGRAM
Size Document Number Rev
Custom A00
Riya Discrete
Date: Monday, August 24, 2009 Sheet 61 of 65
5 4 3 2 1
 5 4 3 2 1

Charger
POWER SEQUENCE MAX8731A

Adapter(+19.5V) +DC_IN S AO4407A D +DC_IN_SS D AO4407A S +PWR_SRC S AO4407A D +PBATT

G G G AC MODE
ACAV_IN +PWR_SRC
CPU
+3.3V_RTC_LDO
D
AMD S1G2 Battery
D

TPS51125RGER VBAT(+RTC_CELL)
3V_5V_EN ENTRIP1 +3.3V_ALW
CPU_LDT_PWRGD CPU_PWRGD_SVID_REG ENTRIP2 KBC_ROM_STRAPS
PWROK
3V_5V_POK PGOOD +5V_ALW
160 ms
S5_ENABLE

RT9013-12PB
+5V_AUX +3.3V_ALW
+1.2V_ALW
NB EN
+5V_ALW
AMD RS780M +3.3V_RTC_LDO

S5_ROM_STRAPS
ISL6265HRTZ-T
CPU_PWRGD_SVID_REG PWROK +VCC_CORE0

30 ms
WAKE#(PCIE_WAKE#)
VCORE_RUN_EN ENABLE
POWERGOOD CPU_VCORE_PWRGD PGOOD +VCC_CORE1 RSMRST#(KBC_RSMRST#)

PWR_BTN#(PM_PWRBTN#)
+VDDNB
C SB PM_SLP_S3# C
SB_PWRGD SLP_S3#/SLP_S5#
AMD SB700 RT8209BGQW
1D8_NB_PWRGD
CPU_LDT_PWRGD
PM_SLP_S3#
RUNPWROK
3V_5V_POK

VCORE_RUN_EN EN/DEM +1.1V_RUN +1.8V_SUS

1.1V_RUN_PWRGD 1.1V_RUN_PWRGD PGOOD
+0.9V_VTT
NB_PWRGD
RUN_POWRE(SLP_S3#)
LDT_PG
SB_PWRGD VCORE_RUN_EN
PWR_GOOD
RT8209BGQW
PM_SLP_S5#
SLP_S5# VCORE_RUN_EN EN/DEM +1.2V_RUN +1.2V_RUN +1.1V_RUN +VCC_CORE +1.8V_GFX_RUN
<20 ms
SLP_S3#

2 ms
RUNPWROK RUNPWROK PGOOD
PWR_BTN# 1.8V_GFX_RUN_PWRGD#(KBC GPI23)
RSMRST#
3.3V_DELAY_EN
VBAT +RTC_CELL SDMG0340LC7F

+3.3V_DELAY
KBC_RSMRST#
PM_PWRBTN#
PM_SLP_S3#
RUNPWROK

RT8209BGQW
RTC-BAT PM_SLP_S3# EN/DEM +1.8V_SUS SB_PWRGD
B KBC B
1.8V_SUS_PWRGD PGOOD
WPCE773L S0_ROM_STRAPS
VCC APL5930KAI
S5_ENABLE PM_SLP_S3# EN NB_PWRGD(1D8_NB_PWRGD)
GPIO36
+1.5V_RUN
RUNPWROK POK
GPIO43/TMS
LDT_PG(CPU_LDT_PWRGD)
GPIO20/TA2 RT8209BGQW
PM_SLP_S5# S5 +0.9V_VTT KBRST#(KBRCIN#)
GPIO01/TB2
PM_SLP_S3# S3
GPIO31 G D
AO4468 A_RST#(PLT_RST#)
GPIO40/F_PWM S

GPIO23 +1.8V_RUN PCIRST#(TP_PCIRST#)

GPIO46/TRST# VCORE_RUN_EN LDT_RST#(CPU_LDT_RST#)
TPS51117RGYR G AO4468 D
S
KBC_PWRBTN# PM_SLP_S3# EN_PSV +VCC_GFX_CORE
GPIO03
+5V_RUN
VCC_GFX_CORE_PWRGD PGOOD

+3.3V_DELAY G AO4468 D
A
EMC2102 S
Main Source A

PURE_HW_SHUTDOWN# G AO4468 D +3.3V_RUN

SYS_SHDN# Wistron Corporation
S
RESET# S 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
3.3V_DELAY_EN G SI2301BDS D +1.8V_GFX_RUN
RT9013-25PB Taipei Hsien 221, Taiwan, R.O.C.
1.8V_GFX_RUN_PWRGD#
EN Title
POWER SEQUENCE
+2.5V_RUN Size Document Number Rev
A3 A00
Riya Discrete
Date: Monday, August 24, 2009 Sheet 62 of 65
5 4 3 2 1
 5 4 3 2 1

DATE VERSON ITEM PAGE Modify List Issue Description OWNER

2009/03/31 X01 1 19 Change DIMM SPD SMBus from Ch1 to Ch0 AGESA by default will look at SMBUS0 for SPD information EE
2 49 Use low RDS(on) MOSFET on audio de-pop circuit Follow DA1's MOSFET to de-pop noise. EE
3 19 Change Bluetooth from USB Port-12 to Port-6 Per BIOS request, change bluetooth to port-6 BIOS,EE
Per AMD design guideline, VTT should be turn on when S3,so
4 39 Change +0.9V_VTT power enable connect with SLP_S5 VTT enable signal should tied to SLP_S5#. EE
5 20 Add SB GPIO48 To detect LCD Size Add LCD Size detect Pin EE
6 7 Change R709/R710 from 33 ohm to 22 ohm clock EA test report, vendor recommend change R709/R710 from 33 ohm to 22 ohm. EE
7 39 Stuff PR3904 and empty PR3903 Correct BOM errors on schematic EE
D 41 Change PR4103 from 3.3 ohm to 300 ohm D

39 Stuff PR3910,PR3911
8 41 Stuff PR4105 Dummy PR4106,PC4109 Update schematic base on power on/off fine tune result. EE
37 Stuff PR3713 Dummy PR3703
31 Stuff R3115 Dummy R3117
31 Change R3107 from 200K to 20K ohm
Change R3103 from 10K to 0 ohm
38 Change R3803 from 0 to 15K ohm
Stuff PC3808 to 0.1u
2009/04/06 9 20 Change SATA HD from Port-3 to Port-0 Per BIOS request, change SATA HD to port-0 EE
10 19 Change R1914 from 33 0hm to 47 ohm Fine tune damping for HD Audio signal EA test result. EE
11 26 Change C2611/C2613 from 18P to 15P Update crystal cap base on x'tal test report EE
20 Change C2009/C2010 from 10P to 12P
12 27 Add EC GPIO05 To detect LCD Size Add LCD Size detect Pin EE
2009/04/08 13 19 Change Clk gen,Mini Card SMBus from Ch1 to Ch0 reduce component quantity , decrease the production cost EE
14 18,25 Del R2504,C2510,R1817 Card reader System reset depend on 3.3V_Run power rails, Not reserve for A_RST. EE
15 31 Del R3109,R3110,R3111,R3113,R3114,R3116 Not reserve,for try Power Plane Enable. EE
2009/04/09 16 10,19 Change CPU SID/SIC from SB_SMBus_Ch1 Reduce component quantity , save level shift circuit cost. EE
to SCL3_LV/SDA3_LV.
2009/04/10 17 57 Stuff R5702 For GPU setting : Full Tx output swing EE
Stuff R5703 For GPU setting : Tx de-emphasis enabled
C C
2009/04/14 18 18 Change C1810/C1812 from 18P to 15P Update crystal cap base on x'tal test report EE
19 27,49 Change netname from HP_MUTE to HP_MUTE# This signal is low active, so we need to correct the Netname EE
20 29,10 Stuff R2917 Dummy R1022. SYS_THERMTRIP# By THERMAL IC control EE
21 10,15 DEL R1001,R1002,R1003,R1510,R1511 Reduce component quantity , delete 0 ohm ,reserve closed-gap. EE
19,27,29 R1902,R2705,R2731,R2905
32,42 R3203,R4202,R4203
48,55 R4805,R4806,R4809,R5521,R5522
2009/04/15 22 07 Add EC703 For EMI This is the solution to solve 999MHz peak issue. EMI,EE
23 39 Add R3900,R3901,PQ3900 Use discharge circuit for power on/off. EE
2009/04/16 24 53 Add C5300,C5301,C5302,C5303,C5304,C5305 Reserve for straddle mot. EE
2009/04/17 25 15 Del R1508 Not Reserve LDT_RST connect to SYSRESET. EE
2009/06/09 26 20 Del R2009 R2010 EE
27 26 stuff C2623 add R2609 EE
28 27 Del R2736 R2737 EE
29 27 Connect net LCD_EC_DET to I/O connector EE
30 42 Connect LCD1 pin37 to +LCDVDD,Del LCD1 pin38 EE
31 50 Connect CN5001 pin50 to net LCD_EC_DET,Connect CN5001 pin22 to net +3.3V_RTC_LDO EE
2009/06/11 32 35
Change PU3501 Ver. from ISL6265HRTZ to ISL6265AHRTZ EE
2009/06/16 33 23
Change U2301 to new version EE
34 42 Change +LCDVDD power solution EE
B B
2009/06/22 35 29 Empty D2901, Stuff R2902 EE
2009/06/25 36 37,38,39 Change PU3701 PU3801 PU3901 to new version EE
37 42 Del D4201 Add R4205 EE

A A

Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change List - EE
Size Document Number Rev
A2
Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 63 of 65
5 4 3 2 1
 5 4 3 2 1

DATE VERSON ITEM PAGE Modify List Issue Description OWNER

2009/03/31 X01 1 39 Change PL3901 ( 1.8V choke ) form 1.0uH to 1.5uH Update schematic base on power report fine tune result. Power Team
2009/04/06 2 34 Stuff PR3405,PC3413 Reduced 3.3V H/S MOSFET Vds voltage Power Team
3 35 Change PR3507 from 4.53k to 3.32k. Reduced OCP setting value Power Team
D D
4 35 Change PC3505 Footprint from 1210 to 1206 Fine tune BOM , merge the same size,value component Power Team
5 39 Change PR3908 from 7.32k to 8.2k . Increasing OCP setting value Power Team
2009/04/09 6 34 Stuff PR3406,PC3414 Reduced 5V H/S MOSFET Vds voltage Power Team
2009/04/14 7 35 DEL PR3509, PR3517, PR3518 Reduce component quantity , delete 0 ohm ,reserve closed-gap. Power Team
41 PR4117, PR4122
34 PR3416, PR3417
33 PR3309

C C

B B

A A
Main Source

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change List - Power
Size Document Number Rev
Custom
Riya Discrete A00
Date: Monday, August 24, 2009 Sheet 64 of 65
5 4 3 2 1
 5 4 3 2 1

DATE VERSON ITEM PAGE Modify List Issue Description OWNER

2009/08/22 A00 change PQ3701,PQ3900,PQ4103,Q3104,Q4202,U2702,U5501 Power Team
1 change low level ESD mos to high level material.
to 84.DMN66.03F Power Team
Change PQ3301,PQ3302,PQ3303,PQ3304,PQ3401,PQ3402,PQ3403, Power Team
2 PQ4101,PQ4104,Q2602,Q2902,Q2903,Q3101,Q3102,Q3103,Q4903, change low level ESD mos to high level material. Power Team
Q5501 to 84.2N702.E31. Power Team
D D
1.DY R4202, use R4205; Power Team
3 2.change R4202,R4205,R4203 from 0 to 100ohm protect KBC avoid LCD plug-in/out ESD damage. Power Team
42
3.add R4210,R4211
4 30 change C3001 from 1uf to 0.1uf. for sloving CORE_RUN_EN signal shake.

5 41
1.DY PWRCNTL_0 circuit change for GFX power control
2.change PR4117,PR4122 to 0 ohm resistor.
6 27 DY R2720, add R2718 change PCB version
7 7 change U701 to 71.08628.003. change CLK GEN main soure to Selligo
8 52 change R5201 from 0 ohm to 100 ohm. for KBC ESD protect
change PR3420, PR3506, PR3514,PR3519,PR3529,PR3530,PR3532,
9 PR3534,PR3912,PR3913,PR4004,R1509,R1920,R1921,R2509,R2510, for cost down
R2724,R5101 from 0 ohm to short pad.
10 19 Change R1903 from 11.8k to 10.7k for USB issue

11 48 ADD PWR_LED_B AFTE Pad for AFTE test

C C
change R701,R702,R704,R1812,R1907,L2003,R2302,R2303,
R2304,R2501,R2512,R2508,R2511,R2723,R2902,
12 R3014,R3115,PR3316,PR3713,PR3904,PR4101,PR4105,R4411, for cost down
R4412,R4901,R4904,R4905,R4906,R4907,
R4908 from 0 ohm to short pad.
Change PR3712 from 64.10R05.55L to 63.10033.15L for cost down
13 37
Change PR3711 from 64.10025.6DL to 63.10334.1DL
14 Del L2502,L4401.L4701,L4801 for PSE don't like co-layout
15 42 Chang EC4202 Pin1 from LCD_TST to LCD_TST_CN
16 48 Change R4802,R4807 from 0 ohm to short pad
17 49 Change R_USB11_N,R_USB11_P from U4702 Pin3,4 to Pin1,6
18 19 Change R1903 from 10K7R2D to 10k7R2F 0903

19 35
Change PR3520 from 100K to 93.1K CPU_CORE OCP 0903
Change PR3521 from 18K to 24K
20 41
Change PR4111 from 154K to 52.3K VGA_CORE OVP 0903
B Change PC4112 from 0.047u to 0.1u B
21 42
1. Connect LCD1 pin38 to GFX_PWR_SRC 0903
2. Del LCD1 pin37
22 47 Change R4701,R4702 from 0ohm to short pad 0903
23 Change RS780 P/N to N131K,SB700 P/N to Y708D 0903
24 18 Add TP_25M_X1,TP_25M_X2 ATE request 0908

25 33
Change PC3306,PC3307,PC3314,PC3315 0908
from 78.10622.53L to 78.10622.52L
26 49 DY Q4903,Q4904,Q4905,Q4906,Q4907.R4911 0908
27 23 Change U2301 to new version,from 71.92H81.E03 to 71.92H81.G03 0908

Main Source
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Change List - Power
Size Document Number Rev
Custom
Riya Discrete A00
Date: Wednesday, September 09, 2009 Sheet 65 of 65