Scribd
Upload
63 views

Virgil Bistriceanu Illinois Institute of Technology

This document provides an overview of the contents of a textbook on computer design. It outlines 10 chapters that cover fundamentals of computer design, basic computer organization, instruction set design, addressing modes, CPU implementation, interrupts, and the memory hierarchy including caches and virtual memory. The document lists the section titles and numbers for each chapter to preview the topics and organization covered in the textbook.

Uploaded by

ESSIM DANIEL EGBE
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
63 views

Virgil Bistriceanu Illinois Institute of Technology

This document provides an overview of the contents of a textbook on computer design. It outlines 10 chapters that cover fundamentals of computer design, basic computer organization, instruction set design, addressing modes, CPU implementation, interrupts, and the memory hierarchy including caches and virtual memory. The document lists the section titles and numbers for each chapter to preview the topics and organization covered in the textbook.

Uploaded by

ESSIM DANIEL EGBE
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

CONTENTS

1. Fundamentals of Computer Design 3


1.1 Introduction 3
1.2 Performance definition 5
1.3 What drives the work of a computer designer 8
1.3.1 Qualitative aspects of design 10
1.3.2 Quantitative aspects 12

2. Basic Organization of a Computer 19


2.1 The block diagram 19
2.2 Computation and control in CPU 20
2.3 Instruction cycle 25

3. Instruction Set Design 29


3.1 RISC/CISC, where is the difference 29
3.2 How many addresses? 32
3.2.1 Three-address machines 34
3.2.2 Two-address machines 37
3.2.3 One-address machines (Accumulator machines) 39
3.2.4 Zero-address machines (Stack machines) 40
3.3 Register or memory? 42
3.4 Problems in instruction set design 47
3.4.1 Operations in the instruction set 47

4. Addressing Modes 55
4.1 Interpreting memory addresses 55
4.2 A classification of addressing modes 63
4.3 Immediate addressing 66
4.4 Displacement addressing 67
4.5 Indirect addressing (memory indirect) 68
4.6 Indexed addressing 70

5. CPU Implementation 75
5.1 Defining an instruction set 75
5.2 The instruction set 78
5.3 Executing an instruction 87
5.4 Hardwired control 90
5.5 Performance for Hardwired Control 104

6. Interrupts 109
6.1 Examples and alternate names 109
6.2 A classification of interrupts 110
6.3 Checking for interrupts 111
6.4 Some problems in checking for interrupts 116
6.5 What is really hard about interrupts 118
6.6 A case study: interrupts in MIPS 118

Virgil Bistriceanu Illinois Institute of Technology


1
7. The Memory Hierarchy (1) 123
7.1 The principle of locality 124
7.2 Finite memory latency and performance 125
7.3 Some definitions 127
7.4 Defining the performance for a memory hierarchy 129
7.5 Hardware/Software support for a memory hierarchy 132
7.6 How does data migrate between the hierarchy's levels 133

8. The Memory Hierarchy (2): The Cache 135


8.1 Some values 135
8.2 Placing a block in the cache 136
8.3 Finding a block in the cache 138
8.4 Replacing policies 145
8.5 Cache write policies 149
8.6 The cache performance 151
8.7 Sources for cache misses 154
8.8 Unified caches or instruction/data only? 154

9. The Memory Hierarchy (3): Main Memory 157


9.1 DRAM/SRAM 157
9.2 Possible organizations for main memory 161

10. Virtual Memory 169


10.1 Some definitions 170
10.2 How virtual memory works 175
10.3 More about TLB 178
10.4 Problems in selecting a page size 180

Virgil Bistriceanu Illinois Institute of Technology


2

You might also like