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Q3. Explain The Need To Demultiplex The Bus AD7-AD0. How Demultiplexing Is Done For The Bus AD7-AD0? How Control Signal Are Generated?

The bus AD7-AD0 needs to be demultiplexed to properly latch the low-order address. This is done using a latch and the ALE signal. When ALE is high, the latch is transparent and the low-order address passes through. When ALE goes low, the address is latched. Control signals for memory and I/O operations are generated by combining the RD-bar, WR-bar, and IO/M-bar signals using OR gates functioning as negative NAND gates. The demultiplexed address and data buses along with the generated control signals allow the 8085 microprocessor to interface with memory and I/O devices.

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3K views5 pages

Q3. Explain The Need To Demultiplex The Bus AD7-AD0. How Demultiplexing Is Done For The Bus AD7-AD0? How Control Signal Are Generated?

The bus AD7-AD0 needs to be demultiplexed to properly latch the low-order address. This is done using a latch and the ALE signal. When ALE is high, the latch is transparent and the low-order address passes through. When ALE goes low, the address is latched. Control signals for memory and I/O operations are generated by combining the RD-bar, WR-bar, and IO/M-bar signals using OR gates functioning as negative NAND gates. The demultiplexed address and data buses along with the generated control signals allow the 8085 microprocessor to interface with memory and I/O devices.

Uploaded by

AbhiJeetSinh Ghariya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as RTF, PDF, TXT or read online on Scribd
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Q3.

Explain the need to demultiplex the bus


AD7-AD0. How demultiplexing is done for the bus AD7-AD0? How control
signal are generated?

Ans:- The need for demultiplexing the bus AD7-AD0 become easier to understand after
examining fig(1)

fig(1):- Timing transfer of byte from memory to MPU

Fig(1) shows that the address on the high-order bus (20H) remains on the bus for three clock
periods. However, the low-order (05H) is lost after the first clock period. This address need to be
latched and used for identifying the memory address. If the bus AD7-AD0 is used to indentify
the memory location (2005H). The address will change to 204FH after the 1 st clock period.

Fig(2) show a schematic that uses a latch and the ALE signal to demultiplex the bus. The bus
AD7-AD0 is connected as the input to the latch 74LS373. The signal is connected to the enable
(G) pin of the latch, and the Output control (OC bar) signal of the latch id grounded.
Fig(2):- schematic of latching low-order address bus

Fig(1) shows that the ALE goes high during T1. When the ALE is high , the latch is transparent;
this means that the output changes according to input data. During T1, the output of the latch is
05H. When the ALE goes low. The data byte 05H is latched until the next ALE. And the output of
the latch represent the low-order address A7-A0after the latching operation.

Intel has circumvented the problem of demultiplexing the low-order bus by designing special
devices such as the 8155 (256 bytes of R/W memory+I/Os). Which is compatible with the 8085.
Multiplexed bus. There devices internally demultiplex. The bus using the ALE signal.

After carefully examining fig(3). We an make the following observations:-

1. The machine code 4FH (0100 10000 is a one-byte instruction that copies the connects of the
accumulator into register C.

2. The 8085 microprocessor requires one external operations—fetching a machine code* from
memory location 2005H.

3. The entire operation—fetching, Decoding and executing—requires four clock periods.


Now we can define three terms---instruction cycle, machine cycle and T-state---and use there terms later
for examining timings of various 8085 operations.

Instruction cycle is define as the time required to complete the execution of an instruction. The 8085
instruction cycle consists of one to six machine cycles or one to six operations.

Machine cycle is define as the time required to complete one operation of accessing memory, I/O, or
acknowledging an external request. This cycle may consist of three to six T-states. In Fig(1) the
instruction cycle consists and the number cycle are the same.

T- state is define as one subdivision of the operation performed in one clock period. These subdivision
are internal states synchronized with the system clock, and each T-state is precisely equal to one clock
period. The terms T-state and clock period are often used synonymously.

GENERATING CONTROL SIGNALS


Fig(1) shoes the RD-bar(read) as a control signal. Because this signal is used both for reading memory
and for reading an input device, it is necessary to generated two different read signals: one for memory
and another for input. Similarly, two separate write signals must be generated.

Fig(3):- Schematic to generated read/write control signals for memory and I/O

Fig(3) shows that four different control signals are generated by combining the signals RD-bar, WR-bar
and IO/M-bar. The signal IO/M-bar goes low the memory operation. The signals is ANDed with RD-bar
and WR-bar signals by using the 74LS32 quadruple two inputs OR gates, as shown in fig(3) The OR gates
are functionally connected as negative NAND gates. When both inputs signals go low, the outputs of the
gates go low and generate. MEMR-bar (memory read) and MEMW-bar (memory write)control signals.
When the IO/M-bar signal goes high, it indicates the peripheral IO operation. Fig(3) shows that this
signal is complemented using the HEX inverter 74LS04 and ANDed with the RD-bar and WR-bar signals
to generate IOR-bar (I/O read) and IOW-bar (I/O write) control signals.

Fig(4):-8085 Demultiplexed address and data bus with control signals

To demultiplexed the bus and to generate the necessary control signals, the 8085 microprocessor
requires a latch and logic gates to build the MPU, as shown in fig(4). The MPU can be interfaced with
any memory or I/O.

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