SET-1:

Answer to the interview questions:

1. Tell about Recent Project

Sol:

2. Challenges in Project
Sol: Design Dependent (Need some inputs)

3.Explain regarding special cells ( Power switches, Isolation or clamp cells and Level Shifters)
Sol:

(1) Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and
Latch type level shifters are available. In general H2L LS’s are very simple, L2H LS’s are little complex and are in general
larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle
noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths.
With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale.

(2) Isolation Cell: These are special cells required at the interface between blocks which are shut-down and always on.
They clamp the output node to a known voltage. These cells needs to be placed in an ‘always on’ region only and the enable
signal of the isolation cell needs to be ‘always_on’. In a nut-shell, an  isolation cell is necessary to isolate floating inputs.

Isolation cells are used to isolate the output signals of a powered down domain. Output signals
of a powered down domain has an intermediate voltage levels because of power gating effect.
When such intermediate voltage signals are feed as input to powered up domain, it could result
in crowbar currents which affects the proper functioning of the powered up domain. Isolation
cells helps to drive a valid logic value either zero or one. Isolation cells are otherwise called as
“clamp cells” because they are used to clamp the signals to a specified logic state.
.
There are 2 types of isolation cells (a) Retain “0″ (b) Retain “1″

(3) Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.

(4) Retention Flops: These cells are special flops with multiple power supply. They are typically used as a shadow register
to retain its value even if the block in which its residing is shut-down. All the paths leading to this register need to be
‘always_on’ and hence special care must be taken to synthesize/place/route them. In a nut-shell, “When design blocks are
switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state,
retention flip-flops must be used”.

The retention flop has the same structure as a standard master-slave flop. However, the retention flop has a balloon latch
that is connected to true-Vdd. With the proper series of control signals before sleep, the data in the flop can be written into
the balloon latch. Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.

(5) AON cells: Generally these are buffers, that remain always powered irrespective of where they are placed. They can be
either special cells or regular buffers. If special cells are used, they have thier own secondary power supply and hence can
be placed any where in the design. Using regular buffers as AON cells restricts the placement of these cells in a specific
region.

                                    
Picture above gives an idea about how/why/when they are required. In a nut-shell, “If data needs to be routed through or
from sleep blocks to active blocks and If the routing distance is excessively long or the driving load is excessively large, then
buffers might be needed to drive the nets. In these cases, the always-on buffers can be used.”

                                         

(6) Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-threshold CMOS, where low-Vt gates are used for
speed, and high-Vt gates are used for low leakage. By using high-Vt transistors as header switches, blocks of cells can be
switched off to sleep-mode, such that leakage power is greatly reduced. MTCMOS switches can be implemented in various
different ways. First, they can be implemented as PMOS (header) or NMOS (footer) switches. Secondly, their granularity can
be implemented on a cell-level (fine-grain) or on a block-level (coarse-grain). That is, the switches can be either built into
every standard cell, or they can be used to switch off a large design block of standard cells.

 Depending on the design characteristics, if these cells are readily available, we can start looking at how to use these cells in
successfully implementing a Multi-Voltage Design.

4. Working on those special cells.

Sol: Locations of these special cells are decided in power network synthesis and power network analysis, Further
during placement these cells are instantiated from the library.

5. How many power domains and how are they inter linked each other?
Sol:There were 3 power domains. As per the power domain information given in UPF, they are inter linked through
special cells given in libraries.

6. Congestion and its solving kind of approach?

High standard cell density in particular area
Sol: Congestion occurs at different stages,
a> Placement Stage: placement congestion: solution → Spreading the standard cells (avoid cell clustering)

During placement can use congestion driven effort low,medium, high

can use placement blockage

Soft blockage :allows buffer and inverters to place inside

Hard blockage:’wont allow any cells to place inside.
Partial blockage:- it allows cells to place according to percentage wise.

Cell padding, keep out margin ,usage of placement constraints like region, guide ,fence

, .
b> Routing Stage: routing congestion: solution → Adding regular routing blockages on the memory block,
jogging, Area based routing optimizations.

7. What are End-cap and Tap Cells and there uses ?

Sol: End-caps and Tap cells are used to connect power and ground rails across an area and are also
used to ensure gaps do not occur between well or implant layers which could cause design rule
violations.
Tap cells are mainly used for preventing latchup problem.
Tap cells and End-caps are very technology dependent. Some technologies don't require them at
all (or, the taps are built in to the std cells), and for other technologies you may need a welltap
every X microns, and endcaps at the end of every std cell row as the end boundaries for the
standard cells placement.

8. How many kinds of power switches used and there type of connection why?
Sol: Types/ kinds of power switch below,
Power gating uses low-leakage PMOS transistors as header switches to shut off power
supplies to parts of a design in standby or sleep mode.
NMOS footer switches can also be used as sleep transistors. Inserting the sleep transistors
splits the chip's power network into a permanent power network connected to the power supply
and a virtual power network that drives the cells and can be turned off.

a> fine-grain.
Fine-grain power gating encapsulates the switching transistor as a part of the standard cell
logic. b> coarse-grain
The coarse-grained approach implements the grid style sleep transistors which drives cells
locally through shared virtual power networks

There are two ways of implementing a coarse-grain structure:

 Ring-based methodology: The power gates are placed around the perimeter of the
module that is being switched-off as a ring. Special corner cells are used to turn the power signals
around the corners.

 Column-based methodology: The power gates are inserted within the module with the
cells abutted to each other in the form of columns. The global power is the higher layers of metal,
while the switched power is in the lower layers.

9. How do you handle cross talk why it occurs ? explain problems associated with it?
Sol: Cross talk problem and fixing:

Problem:Transition on an aggressor net causes logic level glitch on victim net and its receiver.
Symptom: unintended logic transitions on receiver.
Result: Repeatable failures of certain logic operations. Dynamic logic fails. Static logic has timing problems.
Fixing: by various proven techniques:
a> Buffer insertion
b> Driver upsizing
c> Increasing spacing between lines
d> Shielding

10. Why do you target for less latency number and skew number? need to explain according to project
Sol: Effects of less latency and skew:
a> we see considerably less setup and hold timing violations.
b> if skew is very tightly constrained large number of buffers/inverters get added in CTS.
c> if more latency, then OCV will impact timing.

11. What is min pulse width and explain its importance?

Sol: Minimum width of the clock required to accurately latch the data (D).Minimum pulse width violations can affect
setup and hold.

12. Do you tape-out the chip if there is more fan-out and if it has transition and capacitance limits are met?
Sol:

13. What are kinds of derating factors used in your design?

Sol:clock path derating factors
Data path derating factors

Usually, we don't derate for setup check because it is already analyzed in ideal condition whereas for hold check we
use negative derating factor (scaling factor) for pessimistic analysis.

14. What is main difference between AOCV and OCV?

Sol:Difference is below,
OCV applies blanket margin across the chip for increasing variation due to process, voltage and temperature
and variation across the devices.
AOCV solution determines derating values as a function of logic depth and/or cell, and net location. These two
variables determining how much a specific path in a design is impacted by the process variation.

15. What is meant by CPPR?

Sol:
If there is common path for launch path and capture path in case of launch path common path are
multiplied by late derate and capture clk path cells are multiplied by early derate values so  same cells
cant have diif delay values so we will remove the extra pessimism added This is called as common
path Reconvergence pessimism removal

16. How do you calculate depth and distance for AOCV derated Paths explain briefly only it?
Sol:

17. what is setup and hold time and how do you handle it ?
Sol: Setup time: the amount of time the synchronous input (D) must be stable before the active
edge of the clock.
Hold time: the amount of time the synchronous input (D) must be stable after the active edge of the
clock.
Setup time fixing:
1) reducing combinational logic delay by minimizing number of logic levels
2) splitting the combinational logic
3) Implementing Pipelining 
4) Using double synchronizer using flip-flops
Hold time fixing:
1) Can be fixed by adding delays on input ports
2) adjusting clock speed.
#steps to remove violations
#Setup
=> LVT SWAP
=> upsizing the driver (ecochangecell -inst inst name -upsize)
=> Downsizing the receiver
=> buffer long wire (ecoAddRepeater -term inst name -cell cell name)
=> delete unnecessary buffers
=> late clocking EndFF
=> early clocking startFF
=> Fixing crosstalk if net in the critical path has huge crosstalk delay
=> Check the Placement of cells in the path. If tool is doing very bad
placement, you can create region/fence/guide to direct tool to do the desired
placement

#Hold
=> HVT Swap (LVT-to-SVT-to-HVT)
=> Downsize cell to increase the delay
=> Insert buffer
=> clksizing (upsize EndFF clock or Downsize StartFF clock path)
=> Fix delta on huge delta delay net (crosstalk)

SET-2:

Answer to the interview questions:

1. What are the issues u faced in 10nm ?
Sol: We have not worked on 10nm. (need inputs on the same)

2. How much clocks are there in your current block ?

Sol: In my design there was a single master clock and 5 generated clocks.

3. Explain the flow by each stage?

Sol: Flow below,
1.Data flow Preparations → creation of library and directory structure.
a> Technology files (.tf file)
b> LEF files (.lef file)
c> Timing Library files (.lib file)
d> SDC constraints (.sdc file)
e> Celview/FRAM constraints files (.celview file).
f> Table Look up (TLU+) files
g> Netlist file (.v)
h> UPF power constraints file (.upf file).
i> Pin information files (.io file)
2. Sanity checks → checking whether the given files and libraries contains unconnected ports, instances,
floating pins, missing information.
3. Design Planning → this has 2 stages:
a> Floorplan → Die/Core Area, Aspect ratio, utilization and manual macro placement and halos.
b> Powerplan → Power ring, power stripes, power rails(VDD and VSS).
4. Placement → 2 steps : a> Global placement and b> In-Place-Optimization
5. CTS → 2 steps: a> pre-CTS loading clock spec file and checking clock spec file and b> post-CTS building
up the clock tree and global route.
6. Routing & PV → Detail Route – SI aware routing optimizations
4.How you will fix the die size and core size ?
Sol: core size = standard cell area/ core utlisation
Die size = std cell area+macro area+ channelarea+pad area /total utilisation
Or (Die size = core size + 2*pad width + 2* spacing from core to pad)

5. Upto how much utilization u have reached ?

Sol: In one of the case, target was 75% and we achieved upto 73% after pnr.
6. How much corners you have in current project ?
Sol: In our design minimum corner used is 18 and maximum is 32.

7. How much setup corners and hold corners ?

Sol: In our design, Setup corner: 9, hold corners: 9

8. How you have met timing in each corners ?

Sol: Need inputs on the same (Because every corners has different solutions).

9. What are the different methods you have used in placement stage ?
Sol: We have used,
Preplacement
Inplacement
postplacement
.

10. Explain about aocv and pocv ?

Sol: AOCV: Advanced on-chip variation (AOCV) analysis reduces unnecessary pessimism by taking the design
methodology and fabrication process variation into account. AOCV determines derating factors based on
metrics of path logic depth and the physical distance traversed by a particular path. A longer path that has
more gates tends to have less total variation because the random variations from gate to gate tend to cancel
each other out. A path that spans a larger physical distance across the chip tends to have larger systematic
variations. AOCV is less pessimistic than a traditional OCV analysis, which relies on constant derating factors
that do not take path-specific metrics into account.
POCV: Is the next generation of variation analysis targeted at 14/16nm and below processes. It provides a
lightweight statistical margining approach to variation margining. It offers Graph-based Analysis(GBA)
pessimism reduction, improved PrimeTime ECO turnaround time, and simpler library characterization than the
Advanced OCV approach. Pocv provides:
a. Reduced pessimism gap between graph-based analysis and path-based analysis.
b. Less overhead for incremental timing analysis

11. Explain the critical issues you faced in one of the project to fix timing ?
Sol: Need inputs on the same (Because these issues are Design dependent)

12. Have you used useful skew techniques ?

Sol: Useful skew concept is if there are three registers. path between last two has met timing
but slack value is highly positive. Now timing between first two flops are not meeting . You can
match the skew by adding buffer or removing buffer but at last timing should be met in all
three registers. This s similar to time borrowing that is skew balancing.

ANS:-Useful skew is to add buffers in clock path… ie including delays in clock path… in order
to overcome setup violations.

Adv:- it can be done for fixing timing critical paths.

Disadv:-Hold will be affected because of adding buffers in clock paths.

But concept is similar to below:

When achieved skew is less than target skew then some paths can be deliberately delayed to solve setup violations
provided further paths have enough positive slack.

13. why we want to fix full chip timing ?

Sol: Any hold violations in the entire chip leads to chip failure, so we need to fix chip timing.

14. Why we have feed through paths (in to out)?

Sol: in order to avoid lengthy routing we use in to out paths.

15. What is skew and latency ?

Sol: Clock skew: clock skew is difference of clock signal arrival time between two flops.
If you have two flops which works on the same clock frequency but due to position in the
chip they are farther from each other, then there is a possibility is that u will see this problem.
Latency:latency of 2 types
Source latency :time taken for the signal to reach from source to clock port of block
Network latency:time taken for the signal to reach from clock port to sink point of flop otherwise called as insertion
delay

16. what is your maximum target skew ?

Sol: We usually decide maximum target skew depending on the target % of IR drop (Need some inputs)
75ps for 1Ghz… 150ps for 500MHZ it depends upon the frequency and the cell delay values used in corresponding
foundry.

17. How you used to balance the skew and insertion delay ?
Steps to reduce skew:

1.clock balancing (clock tree is built (h tree)

2.NDR rule (width is high and inversely proportional to resistance delay is less )
3.high drive strength buffer (width is high same)

insertion delay

1.Reduce the fanout number so you can reduce the sink points.
2.place clock gating cells near source

18. If your skew is zero but you have more insertion delay what is the effect ?
Sol: If our skew is zero and have more latency then we need to work on latency because to avoid the
effects of OCV,clock jitter, which will be effecting the launch and capture path. “ But ideally we don't
close design with zero skew”.
(Insertion delay with respect to OCV has a large impact because the larger the insertion delay the
greater the impact on capture path and thus the greater the impact will be on your setup time. If
your insertion delay includes a large portion of common path, then CRPR will help reduce the
impact of OCV)

19. Have you worked on low power techniques ?

Sol: Yes.

20. How much duration you used to take to close the block ?
Sol: Approximately 3 months for design > 200k gates.

SET-3:

Answer to the interview questions:

1. How you start PD once you get inputs and what are the checks ?
Sol: Once we get inputs,
a> Data flow Preparations → creation of library and directory structure.
a> Technology files (.tf file)
b> LEF files (.lef file)
 c> Timing Library files (.lib file)
d> SDC constraints (.sdc file)
e> Celview/FRAM constraints files (.celview file).
f> Table Look up (TLU+) files
g> Netlist file (.v)
h> UPF power constraints file (.upf file).
i> Pin information files (.io file)
b> Sanity checks → checking
a> Loops in the design (like unconnected ports, floating pins, multi-ports).
b> missing libraries, io's, power files.
c> critical constraints in SDC missing.
d> Netlist missing.
e> Celview/FRAM view of macros missing in the hierarchy.
f> technology file missing.

2. How much micron blockage you put on memory and why ?

Sol: Depending on technology nodes, for the size of blockages(halos) we refer memory IP datasheet.

3. On what basis you come with that number (apart from congestion problem)
Sol: we refer IP Datasheet for the same (need some inputs on the same).

4. Why design ports are not placed in Metal1 and metal2?

Sol: Generally we will take Metal1 for std cell pin package and Metal2 is used for power rails. If we use metal1
and metal2 as ports it may occur short between the nets while routing.

5. What is CRPR, OCV,POCV, how it affect your design with respect to setup and hold scenario?
Sol: OCV: On Chip Variations refers to the variations of delay properties between digital components and
interconnect in the same chip/die. OCV includes random and deterministic components of variation. By
random OCV component, we mean the variation in gate-oxide thickness, implant doses, metal or dielectric
thickness etc.
POCV: Is the next generation of variation analysis targeted at 14/16nm and below processes. It provides a
lightweight statistical margining approach to variation margining. It offers Graph-based Analysis(GBA)
pessimism reduction, improved PrimeTime ECO turnaround time, and simpler library characterization than the
Advanced OCV approach.
CRPR: When applying derating factors for launch and capture paths, OCV derates get applied to cells which are
common for both paths which is over pessimistic analysis.

“Hence through CRPR this extra pessimism is removed by applying the difference of OCV derates for setup and hold
on the clock re-convergence point”.

6. How you balance or fix the skew ?

Sol: By adding,
a> clock Buffers.
b> clock Inverters.
c> Optimum depth of clock tree.
d> Register stacking.

7. What type of cells to be used while fixing hold and how does these cell behave with different scenario?
Sol: Usually we swap the LVT cells to HVT type of cells during CTS to fix hold violations, at high voltage and
nominal temperature hold is fixed and this may not help in closing hold at high temperature scenario.

8. How you do power planning for different power domain?

Sol: The different power domains are partitioned into different voltage areas which are again defined in a power
constraint file known as UPF. In power planning stage we use this UPF for creating different voltage areas in
floorplan.

9. What are switch cells, when and why we use it?

Sol: Power switches has the potential to reduce overall power consumption substantially because it lowers leakage
power as well as switching power.
Power switches are used during PNS (Power network synthesis) to power-down and power-up.
10. What is cross talk ? how you fix it and how does it affect for hold corner?
Sol: Problem:Transition on an aggressor net causes logic level glitch on victim net and its receiver.
Symptom: unintended logic transitions on receiver.
Result: Repeatable failures of certain logic operations. Dynamic logic fails. Static logic has timing problems.
Fixing: by various proven techniques:
a> Buffer insertion
b> Driver Upsizing
c> Increasing spacing between lines
d> Shielding
“Yes it affects the hold corner.”

11. What is NDR, what are the rules used, when and on which nets you apply?
Sol: NDR → Non Default Rule: Apart from vendor specified rules,
Double width double spacing ,triple spacing
NDR is user defined constraints.
There are different NDR rules at different stages:
a> CTS stage.
b> Routing stage.
“Usually we apply on the clock and critical nets”