5.1 WHAT THE INSTRUCTION SET IS ‘A computer, no matter how sophisticated, can do only what itis instructed to do, A program is a sequence of instructions, each of which is recognized by the computer and causes it to perform an operation. Once a program is placed in memory space tat Is accessible to your CPU, you may run that same sequence of ine structions as often as you wish to solve the same problem or to do the same function. The set of instructions to whicn the 8085A CPU will respond is permanently fixed in the design of the chip. Each computer instruction allows you to ini- tiate the pectormance of a specitic operation. The 8085A implements a group of Instructions that move data between registers, between a fagister and mamory, and between a register and an YO port. It also has arithmetic and logic Insteuctions, conditional and unconditional branch instructions, and machine control in- structions. The CPU recognizes these instruc tions only wnen they are coded in binary form, 52 SYMBOLS AND ABBREVIATIONS: The following symbols and abbreviations are Used in the subsequent description of ine 8085A instructions: SYMBOLS MEANING. accumulator Ragister A ager 16dit address quantity data abit quantity data 16 16-bit data quantity, byte 2 The second byte of the instruc- tion byte3 The third byte of the instruc: tion port Bit address of an VO device neta ‘One of the recistere ARC fi CHAPTER § THE INSTRUCTION SET o00,sss ° RP m The bit pattern designating ne of the registers A,8,C,0, E,H,L (DOD =destination, S8S'= source): 000 or REGISTER sss NAME Wm ‘00 01 O10 on 100 101 One of the register pairs: 8 represents the 8,C pair with 8 a3 the high-order register ang Cas the low-order register; O represents the O.€ pair with D as the highorder register and & as the low-order register H represents the H,L pair with H as the high-order register and Las the low-order register: SP represents the 16-bit stack rrmooa> pointer register The bit- pattern designating one of the register pairs B.O.M.SP: REGISTER aa PAIR 00 BC o oe 10 HEL " SP The first (high-order) register of a designated register pair. (low-order)1 o_______ 2. tame condicon wat met, the content ofthe register fae WZ are outout an the adress ines (Agr) the contents afte prayram counter (PC) tend of near eye (MI) tay an inst Tor only) Bye, containing te 99 cade. is 12. Ite consition wat not met, sub-eyles M4 and MS re sigond the socetoe intend proceeds immediately 20” out trom memory snat handing pingructon een (Mi he nest uno GH REAOY is amped sigh 14. tf anion wat at mat sb-yee MZane M sna TSae sent eats fr apy $8 eracian ch i ol ne eeeintsonon ce Completay ara ote CPU. The com . ee movaceguneetesremt® 9, conaron es Sessa Ra) a Epencttgecemscoco | Eomnmes iadenideiemaiaenl NC = no carry (CY =O) o10 eT nmacvemed — Sieieaen ghana M = minus ($= 1) a OY signal is not required during the sean 18 VO mid-cycle: the 1/0 port's Bit select code is dupti- {ovches M2 and Mt. The HOLD signa cated on address tines 07 (Agr) aod 815 (Ag.ss). Sa M2 and MA, The SYNC signals mot gene {and M2, Owing ene extcuton of OAD, 19, Outout bere ‘required fr an incerna cepieoaie 36; 20. The oroeesoe will erin ie in the hae ae net sof these arithmetic, logical of rors ‘quent is scenoted, be CPU enters the hold mode after the ot maved nto the acoumaletar (AD unt hold mode i tarminate, the proces returns 9 the halt Gieseinnresion cycle That it Aitlowed ‘Sate, Altar asa scented ne procesor Dein exec: $5e000 [wave ‘oa ott 190 ior hapter 5 080A/8085A struction Set — ———— —— = =.= == ==> OTS —— — — =S=== —— = — === = a a — — a —_ = a A A — — wae —_ — =o wo _— wee eee wee lee SS—— eee = ===> =— == —— 25 2S S5= " | tal |THE INSTRUCTION SET _ eit program counter feiater (OCH and PCL are (ha to cafr to the Mgh-order Sra low-order 8 bits respec tei Tit stack pointer register (SPH and SPL aroused toreler to the nighrorder anc low order Boits respectively) it mot the register its are umber F through 0 from itt torah. 160it address of subroutine The condition tags: zero Sign Parity cary Autliary Cary The contents of tne memory Iocation or ragisters enclosed Inthe parentheses “is vanstered to" Logieat ano Exciusive OR Inclusive OF Adsivion Two's complement suotaction Multiplication is exchanged with The one's comploment(o.g. The estar number 9 through 7 Tne binary representation 000 through 11 for restart number S rough 7 respectively an set encyclopedia is a detailed Tine 80054 instruction set Each " deserbed in tne Tollowing mane 15 macro assembler format, con: the instruction mnemonic and ads, is printed in BOLDFACE on of the instruction is enciosed in 's following the mnemonic. tes contain a symbolic description instruction does, awed by a narrative description of ‘on of the instruction + S.The boxes describe the binary codes that comprise the machine instruction. 6. The last four lines contain information about the execution of the instruction. The number ‘of machine cycles and states raquired to ex- ecute the instruction are listed first, Ifthe in- struction has two possible execution times, as in a conditional jump, both times are listed, separated by a slash. Next, data ad-_ ‘dressing modes are listed i! applicable. The {| last line lists any of the five flags that are al § fected by the execution of the instruction. 5.3 INSTRUCTION AND DATA FORMATS j Memory used in the MOSS system is organ-3| latin totes, Each ytehas auncveeatonn physical memory. That location is described by one o a sequence of 1Ebit binary adcresses. The BOSSA can! Address up 0 64K (K = 1024, oF 210; nence, 64K} ‘represents the decimal number 65,536) bytes ot memory, which may consis of both random-access, j feadewrite memory (RAM) and read-only memory (ROM), which is also random-access, Data in the 8085A is stored in the form of bit binary integers: DATA WORO 7" Dy! Ds. 04. 03'02' Dy Dy J SeRDALCSECHACaADsAOICS] 1s8 wise ; Wnen a register or data word contains a binary rumen a recessar to establish the oe n whch these ofthe numba are wite. nie ne SoeSA, BIT Os olaredt asthe toast Signfeant BI (LSBX and SIT Tot an 8.98 number) isteterred to 38h Moat Signilieant Bt (Sa). i ‘An 8085 program instruction may be one, two oF tnve bytes in length Multipiedyt instructions mes Da sorninsuconve meray wean adress th eat yt aways wed the areas the Strction. te exactitration format wil depend Gn the parieular operation To be executed. Single Byte Instructions i Pt) o; 9} Op Code Two-Byte Instructions oreo! 05] Op code ‘One » ayefgr TT tT Tt Two 7 ata or 0] address: THE INSTRUCTION SET Three-Byte instructions She | Or 06] Op code arte eo [et TT TTT Toh one or os ome] Tree [OF Do Address 5.4 ADDRESSING MODES: Often the data that is to be operated on is stored in memory. When multibyte numeric data is used, the ata, ike instructions, is stored in successive memory ‘ocations, with the least significant byte first, follow ed by increasingly significant bytes, The SOSA has four different modes for addressing data stored in memory or In register + Direct — Bytes 2 and 3 of the instruction contain the exact memory ad- ress of the data item (the low- ‘order bits of the address ara In byte 2. the high-order bits ia byte 3) + Register — The Instruction specifies the ‘register of cegister pair in which the data Is located, Indirect — The Instruction specifies a register pair which contains tne memory address where the data Is locates (the high-order bits of the address are in the first register of the alr the loworder bits in the Second). + Immediate — The Instruction contains the data Itsell. This is either an S.bit quantity or a 16-bit quanti- ty (least significant Byte first, ‘most significant byte second). Uniess directed by an Interrupt or branch in: stitution, the execution of instructions pro- ceeds through consecutivaly increasing memory locations. A branch instruction can Specity the addrass of tha next instruction to be ‘executed in one of two ways: * Direct — The branch instruction contains the address of the next instruc: tion to be executed. (Except for the "RST' instruction, byte 2 contains the low-order address and byte 3 tne high-order ad. dress) * + Register + Register indirect — The branch instruc: tion indicates a registerpair which contains the address of the next instruction to be ex ecuted. (The high-order bits of the address are in the first register of the pair, the low: ‘order bits in the second) ‘The RST instruction is a special one-byte call in- struction (usually used during interrupt se. Quences). AST includes a three-bit field: pros gram control is transferred to the instruction whose address is eight times the contents of this three-bit field, 5.3 CONDITION FLAGS: There are tive condition flags associated with the execution of instructions on the 8085A. They are Zero, Sign, Parity, Carry, and Auxiliary Carry. Each is represented by a 1 bit register (or {tip-flop) in the CPU. A flag i3 set by forcing the bit to 1; itis reset by forcing the bit to 0. Uniess indicated otherwise, when an insteuc- tion afteets a flag, It affects it in the following Zero: If the result of an instruction has the value 0; this flag is set: otherwise itis reset H the most significant bit of the ‘esult of tha operation has the value 1, this flag is set; other. wise It is reset. it he modulo 2 sum of the bits of the result of tne operation is 6, (i.e. it the result has even parity), this flag is set; other wise itis reset (i.e, if the result hhas odd parity) IW the instruction resulted in a carry (trom addition), or a bor. ow (trom subtraction or a com- parison) out of the high-order this flag Is set; otherwise it eset. ‘Auxiliary Carry: If the instruction caused a Carry out of bit 3 and into bit 4 of the resul Hiary carry itis reset, This flag is affected by single-precision additions, sub- tractions, increments, decre- ments, comparisons, and logi- cal operations, but is principal- ly Used with additions and in- crements preceding @ DAA (Gecimal Adjust Accumulator) instruction. Sign: Parity Carry:THE INSTRUCTION Sq ucrion SeT ENCYCLOPEDIA wing dozen pages, the complete Webaset ts deserved, grouped in iv atten’ functional headings, Transter Group — Moves data be- A registers or between memory lions and registers. Includes moves, 3, ‘stores, and exchanges. (See matic Group — Adds, subtracts, In- tents, or decraments data’ in FS Or memory. (See page 5-13.) Group — ANDs, ORs, XORs, com- 5, rotates, or complements data In ters or between memory and a ter. (See page 5-16) ch Group — Initiates conditional or ditional jumps, calls, returns, and Fis. (See page 5:20.) MOV r, M (Move from memory) (= HD The content of the memory location, whose | address is in registers H and t, is moved to register ¢. Lit ep, data 16 (Load register pair immediate) (ch) ~ (byte), (@) — (oyte 2) Byte 3 of the instruction is moved into the high-order register (h) of the register pair ‘fp. Byte 2 of the instruction is moved into the low-order register (of the register pair *. T e THE INSTRUCTION SET LHLD addr (Load H and L direct) (U=l(Oyte 3yoyte 2) (H)~((byte 3yoyte 2)+1) The content of the memory location, whose address is specified in byte 2 and byte'3 of the instruction, is moved to register \. The content of the memory location at the suc. Ceeding address is moved to register H. MOV M,¢ (Move to memory) ey (Uy — (9) J ‘Tha content of register ris moved to the | memory location whose address isin registers H and L. Come ae eon ieee eta! UO, and Machine Control Group Gycles: 2 ludes Insteuetions for maintaining States: 7 Stack, reading from Input. ports, Addressing: rag, indirect 19.10. output ports, satting “and Flags: nono 1g Interrupt masks, and setting and ig flags. (See page 5-22) MVIr, data (Move immediate) (= yte 2) Tha content of byte 2 of the instruction Is 3 described in the encyclopedia moves to register assembly language processed by T 4 Gazsanaier useawihmeinatect | 9 9 |o!o lo [1 1 0 systems, data Ceaniter Seer 5] * Cycles: 2 {instructions tvarSters data to and States: 7 {3 and memory. Condition flags are Addressing: Immediate by any Instruction In thia group. Flags: none MVIM, data (Move to memory immediate) (Move Register) (0) = oye a 2 The contant of byte 2 of the instruction i ent of register 2 is moved to moved to the memory location whose ad- a dress isin registers H and L. TT TT TI oo o]s sis oo 1 to 4 4 ' 0 Cycles: 1 ata 4 (0088), 5 (6080) pte Gyles: 3 none States: 10 Addressing: immed.reg. indirect Tosa o 0 0 4 ale TTT 09 9 1 0 1 0 49 low-order data low-order addr L hignordr data hignerder acer Cycles: 3 5 ~ Sites: to is Accresaing: Immediate aacresiing: Sec fags: Aone fone LOA der Load Accumulator rect (A) ~ ((byte 3ybyte 2) The content of the memory location, whose address is specified in byte 2 and byte 3 of the Instruction, is mavad ta ragister A. Oo 1 4 ta dg low-order addr high-order agar LE Cycles: States: 13 Addressing: dicect Flags: none STA addr (Store Accumulator direct) (byte aybyte 2) — (a) Tha content of the accuniulator is moved to tne memory location whose address. ig ‘specified in byte 2 and byte 3 of the instruc. tion, low-order adar (SHLD addr) (Store H and L direct) ((oyte afoyte 2)—(U) Woyte 3ybyte 2)+1)—(4) The content of register L Is moved to the memory location whose “address ‘ig Specified in byte 2 and dyte 3. Tha content Of register H is moved to the succeeding memory location, low-order addr Gyles: 5 States: 16 Addressing: direct Flags: none LOAX tp (Load accumulator indirect) = (oy The content of the memory location, whose address is in the register pair rp, is moved fo register A. Note: only register pairs ‘p=B (registers 8 and C) or cp=0 (egisters D and E) may be specified. high-order ader ] N c (el eee eo] Flags: none "ssing: reg.THE INSTRUCTION SET (Stove accumulator Insect ine ot ter A ved to the intent of register A is moved to Ty location wnose accross is inthe wt par rp Note omy register paves (fegisers and’ Gar p28 1158 ana © may specified, 29. Indirect none (Exchange H and L with D and &) 2 3 tents of registers H and L are ex 1d with the contents of registers O REET] Gycies: 1 States: 4 \ddressing: register Flags: none up ions performs arithmetic on data in registers and 1d otherwise tect the Zero, Sign, Parity, Carry, Y Carry flage. according to the stan: fon operations are performed via ‘ement arithmetic and set the carry te Indicate a borrow and clear it to borrow. (ads Registon aoa then ragister «is added to the the accumulatar The result wine accumulator ea el : o og o/s s s cycles: 1 States: 4 foressing: register Flags: ZS,P.cV.AC wv ADO M (Add memory) ) = (4) + (HQ) The content of the memory location whose address is contained in the Hand L registers is added to the content ol the ac ‘cumulator. The result is placed in the ac. cumulator. 2 7 Addressing: reg. indirect Flags: ZS,P,CY,AC ADI data (Add immediate) (A) ~ (A) + (byte 2) The content of the second byte of the in- struction is added to the content of the ac. cumulator. The result is placed in the ac. o aoc M (Add memory with carry) WA) + HL) + cM The content of the memory location whose address is contained in the Hand t ‘registers and the content of the CY flag are added to the accumulator. The result Is placed in the accumulator. THE INSTRUCTION SET sua M (Subtract memory) (A) = (A) ~ (4) (O) The content of the m address is contain: registers is sub the accumulate accumulator. lemary location whose led in the Hand L tracted from the content of 9. The result is placed in the ACI data (Add immediate with carry) A) ~ (A) + (byte 2 + (CY) The content of the second byte of the in- struction and the content of the CY flag are a Ue rere teTnsea Tape 10 0 0 1 4 4 lg et Ome ee vente! 2 Cycles: 2 7 States: 7 29. indirect Addressing: reg. indirect ZS.P,CYAC Flags: ZS,P.cY,ac SUI data (Subtract immediate) (A) = (A) ~ (byte 2) The content of the second byte of the in- 1 eae ee Tt 0 O 4 4 4 1 1 0 4 Oo 1 49 deta cata data wet En, gos? Soar? Flags: ZS.P,CYAC Flags: Z,S.P,CY,AC Flags: ZS,P,CY,AC eating ranaiecanentct | 88, cuss age on the carry bit are added to the content of the accumulator, The result is placed in the ac- cumulator. j w= -"o The content of register Is subtracted from the content of the accumulator. The result is placed in the accumulator, (Subtract Register with borrow) 4) =) = = (CY) The content of ragister rand the content of the CY flag are both subtracted from the accumulator. The result is placed in the ao. cumulator, Addressing: Flags: 4 Addressing: register Flags: 2.S,P,CY,AC‘THE INSTRUCTION SET (Subtract memory with borrow) = (ey (Uy = (CY) INRM += (Increment memory) (HY = (HY) +t ‘The content of tha memory location whose THE INSTRUCTION SET INX ep (increment register pair) (en) (nt) — (ener) +41 DAA (Decimal Adjust Accumulator) The eight-bit number in the accumulator is 1 eee cation whose The content of the register pair rp is in- adjusted to form two fourbit Binary-Coues. © 3 Somtained in thee and L caress 13 contained in the Hand remented by one. Note: No condition flags Decimal digits by the following process @ id ts contents the Cis lag are Gratton sags sxeapt CY deo sitected, eee Tif the value ofthe lease significant 4 bits @ | ‘acted from the accumulator. The condition flags except CY ar 5 of the accumulator is greater than 9 orit fecline sceuclaee 7 r m4 the AC fag is set, 61s acces to the ac-_g TTT Ogio) newer |onaor neues cumulator. 77 oto it oli! 00 2.1! the value of the most significant 4 bits, € oy 4/410 of the accumulator is now greater than 9, Qycles: 1 - or ifthe CY fag is set Sis added to tne © | most. significant’ 4 bits of the. ae. | ree States: 6 (8085), 5 (6080) cumueta ©} oo States: 10 Addressing: register : ‘States: 7 Addressing: rag. indirect poe none NOTE: All ilags are aftected | ressing: reg. Indirect Flags, ZS,P,AC e | Flags: Z.5,P,CY,AC | DOK Oy _ fOgarementrepatr pai € Subtract immediate with +E) ot) — (ery) — Sorow Dens _ (Deeroment Resistor he content ie ease pa pi Qycies: 1 e toyed - Cn, 1 on of registers decremented by lecremented by one. Note: No’ condition States: 4 re of thei 1 content of register ris flags are affected, = Sha tho contents ofthe CY fag ‘one. Note: All condition flags except CY eoeeae Flags: ZS,P,CY,AC i ‘ubtracted from the accumulator. are affected. — a é fete ecceetaae fe] Tota! a | seers ii : To'oto i oi] This group of instructions performs is G/U of instructions pertorms logical | a (Boolean) operations on data in registers and € o 1 14 40 oo memory and on condition flags, a States: 6 (8085), 5 (8080) Uniess indicated otherwise, ail instructions in € ay yeles: 1 Addressing: register this group affect the Zero, Sign, Parity, Auuia Slates: 40065, 58080) Flags: none Garry, and Carry tags accovding to'the stan Addressing: register ard cules, 2 Flags: ZS,PAC © cycles: States: 7 « iressing: immediate t Flags: ZS,P.CY,AC Dao (Add register pair to Hand) ANAT (AND Register Poe Os (au oe A) = A) 0 4 ecrement memo "@ content of tha raglster pale rp is The content of registers logically ANDed See er ATER to the content of the register pair and L- with the content of the accumulator, The {Increment Register) Gre cantent of the memory location whose The result Is placed in the register pair H fesult is placed in the accumulator. The CY 1 Decry ECCI nE ES teRan and L. Note: Only the CY llag is affected. it fag is cleared and AC Is sot (8085). The cy € at of register is incremented by Pee ten is set if tere is a carry out of the double Mag a cleared and AC is antto the Ong g ell condition Bags le==ebc Conaltion flags except CY are affected Precision add; otherwise it Is resat. ‘of Bits 3 of the operands (8080), ed. € T T Tomei ateaiaeal gel T TTT € 7 ToT tea tely o'olaelitato'g rio'slolols's o'o'oj1 0 0 ooo 1 4 ¢ cycles: 1 Gyles: 3 to Sees Stales aoe e080 fees otras Fegiter Acdessing: —fegister teasing: git, Flags’ | ZS PAC oY Flags. 2EPCYACTHE INSTRUCTION SET {AND memory) ayn (HD (LD) antents of the memory location dares is contained In the H and L {3 is logically ANOed with tne con- f the accumulator. The result is in the accumulator. The CY flag is |/and AC is set (8085). The CY flag is and AC Is sat to the OR'Ing of bits 3 »perands (8080). Cycles: 2 States: 7 Addressing: reg. indirect Flags: Z,S,P,CY,AC {ANO immediate) valoyed Ment "Ch tne second byte of ine in Inv ogialy ANOed with the con: WP the Bccumstator The results in the accumulator. The CY fag is nd a is sot 089, The CY Hage ind AGIs sat tothe OW ng of be 3 oranda 0000, 10 oO 1 1 0 data Cyctes: 2 slates 7 adores: immediate Flags: ZSPCY.AC (Exclusive OR Registen yin ent Ot register «is excusie-oma b ontent of the accumuater, The $ laced'n ne secumuater The CY Hage are ch XRAM (Exclusive OR Memory) (a) = (A) () (L) The content of the memory location whose address is contained in the Hand L registers is exclusive-OR’é with the con. tent of tne accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. Cycles: 2 States: 7 Addeessing: reg. indirect Flags: Z.S:P,CYAC XAldata (Exclusive OR immediate) (A) ~ (A) (byte 2) ‘The content of the second byte of the in- struction is exclusive-OF'é with the con- tent of the accumulator. The cesult is laced In the accumulator. The CY and AC flags are cleared. Tape apne pe ape gic Tere 1o4 oto 1 4 4 0 data cycles: 2 States: 7 Addressing: immediate Flags) 2,5,P,CY,AC ORAc (OR Register) WAV The content of register ris inclusive. OR'é with the content of the accumulator. The result is placed in the accumulator. The CY land AC flags are cleared. THE INSTRUCTION SET ORAM (OR memory) = AV H)() The content of the memory location whose address is contained in the Hand L. ‘egisters is inclusive-OR'd with the content of the accumulator. The result is placed ia the accumulator. The CY and AC flags are cleared. Gyctes: 2 States: Addressing: “reg. indirect Flags: Z,S,P,CY,AC ORI data (OR Immediate) 1A) = (A) v (byte 2) The content of the second byte of the in- struction is inclusive-OR'd with the content of the accumulator, The result Is placed in the accumulator. The CY and AC flags are cleared. Gyctes: 2 States: 7 Addressing: immediate Flags; Z,S,P.CY,AC cM r (Compare Ragisten) W =) The content of register is subtracted trom the accumulator. The accumulator remains unchanged. The condition flags are Set 23 4 result of the subtraction, The Z flag is set to THA) = (9, The CY flag a set to 1) eee eee Bags keperac "sing: register CMP M (Compare memo w. = MH) (LD ” 'e content ofthe memory ication whos acaress I. containeg in. then eee fegisters is subtracted’ om “ane umulator. The accumulator romstes a changed. The concition fags ara ser au, result of the subtraction, The 2 lag isan to 1 if (A) =((H) (L)). The CY flag is set to if ] [ofofr]a]x]o[ofo Program Counter After Restart PUSH Psw high-order eight bits of register PC. The content of register L is moved to the low. order eight bits of register PC. 6 (8085), § (a080) register none Se EBS {SWE TOTand Wachine Control Group 9 This group of instructions pertorms UO, manips lates the Stack, and alters Internal control tags. Uniess otherwise specified, condition flags are not affected by any Instructions In this group. PUSH rm (Push) _ ASP) - 1) = (emp (SP) ~ 2 ~ (ay) ASP) ~ (SP) = 2 The content of the highorder register of tagistor pair rp is moved to the memory location whose address Is one less than the content of ragistar SP. The content of the low-order register of register pair rp I moved to the memory location whost dress I two less than the content of fegister SP. The content of register SP 13 decramented by 2. Note: Register pale rp = ‘SP may not be specified, CELE Ee) orcs 9 ates: 12 (2089, 11 Addressing: reg. indirect © ae Fags Ne (Push processor status word) (SP) = 1) ~ (a) (SP) ~ 2 — (Cr), (SP) — 2), — x (SP) ~ 2 — (7), (SP) ~ 25 x (38 2 B= BO AGP a ox = Ba — B.S?) ~ 2h ~ (5) 8) BB tine {0 the memory location whose address i two less than the content of register Sit he content of register SP is decremented y two : Snot, 00e rxo wor Dy Os 0s O% Ds 02 OY oO POP rp (Pop) () = (SP) The contant ofthe memary location, whose aacress Is. Specified by’ the’ ontant ot feglster SP, ls moved to. the laworder feglater of ragatar pair rp. The contort of the memory location, whose accrons eke more than the content of register SB ‘moved tothe highorder register af reget 1B. ‘The. content of ragiater, See sremented by 2. Note: Register pale ‘SP may not be specified. ae COE ERT] Gycles: 3 States: 10 Addressing: rag.indirect Flags: none‘THE INSTRUCTION SET (Pop processor status word) (SP he 3A (SP). SPle SP) SP) + 1) (SP) +2 tent of the memory location whose s is specified by the content of SP is used to restore the condition The content of the memory location address |s one more than tha con- register SP Is moved to register A, tent of register SP Is incremented Gycles: 3 States: 10 \earessing: cag. Indirect Flags: 3,P,CY,AG (Exchange stack top with H and 4) spy) (A+ ‘tent of the L register Is exchanged |e content of tna memory lecation address Is specified by the content ster SP. The content of tha H regist hanged with the content of the y location wnose address Is one ‘an the content of register SP. ae SPHL. (Move HL to SP} (SF) - HY The contents of registers H and L (16 bits) are moved to register SP. Gycles: 1 States: 6 (8086), 5 (8080) Addressing: register Flags: none IN port (input) (A)—(data) The data placed on the eight bit bi- directional data bus by the specified port is moved to register A. 4 ‘THE INSTRUCTION SET ~ a (Enable interrupts) The interrupt system is enabled following the execution of the next instruction, inter. rupts are not recognized during the £1 Instruction. Cycles: 1 States: 4 Flags: none NOTE: Placing an El instruction on the bus in fesponse to INTA during an INA cycle Sees hibited. (8085) or (Disable interrupts) The interrupt system is disabled ately following the execution of the Dl In. struction. Interrupts are not recognized during the DI instruction, port ay cycles: 3 Slates: 10 Addressing: direct Flags: none Flags: none NOTE: Placing a 01 instruction on the bus ia i: response to INTA Our gor, (Outeud ited. (8085) The contont of register A is placed on the sight. bit bi-directional data bus for Py aly transmission to the specitied port. 0 pert : | Gycies: § gycies: 3 fates; 16 (2088), 182080) States; to srasaing: tage indlect Adsressing, rect Fogel ek Faget hone The processor is stopped. The registers and flags are unatfected. (8080) A second ALE Is generated during the execution of HUT to strobe out the Halt cycle status in- formation, (8085) eT] Cycles: 1+ (8085), 1 (@080) States: 5 (6085), 7 (8080) Flags: none Nop (No op) No operation is pertormed. The registers and flags are unaffected. Gyles: 1 States: 4 Flags: none. RIM (Read Interrupt Masks) (8085 only) The RIM instruction loads data into the ac: Cumulator relating to interrupts and the serial input. This data contains the follow: ing information: * Current interrupt mask status for the AST 85, 6.5, and 7.5 hardware inter. ‘upts (1'= ‘mask disabled) + Current interrupt enable flag status (1 Interrupts enabled) except im- mediately following a TRAP interrupt, (See below.) + Hardware interrupts pending (ie, signal received but not yet serviced), on the AST 5.5, 85, and 7.5 lines. + Serlal input data, Immediately following a TRAP interupt, the FIM instruction must te executed a3 2 art of the service routine if you need to Fetcieve current interrupt status later. Bit 3 of the accumulator is (in this special case only) loaded with the interrupt enable (6) flag status that oxisted prior to the TRAP interrupt. Following an RST §.5, 6.5, 7.5, or INTR interrupt, the Interrupt tag ilip-tiog feflects the current interrupt enable status Bit 6 of the accumulator (17.5) 18 loaded with the status of the AST 75 tlip-tlop, which is always set (edge-triggered) by an Input on the AST 7.5 input line, even when that interrupt has been praviously masked. (See SIM Instruction) cocoae: anor tine| 0 fr-s] ms] ss] re fars|mesuess Lert naoia Fag Cycles: 1 States: 4 Flags: noneTHE INSTRUCTION SET (et Interrupt Masks) (8085 only) » execution of the SIM instruction uses contents of the accumulator (which st be previously loaded) to perform the owing functions: Program the interrupt mask for ine AST 5.5, 65, and 7.5 hardware inter rupts. Reset the edge-triggered AST 7.5 in- ut latch. Load the SOO output latch rogram the interrupt masks, fist set ac- aulator bit 3to 1 and set to 1 any bits 0, fad 2, which disable interrupts AST 5.5, ‘and 7.5, respectively. Then do a SIM in: Ietion. f accumulator bit 3 is O when the instruction is executed, the interrupt sk register will not change. I! ac: tulator bit 4 is 1 when the SIM instruc. Is executed, the RST 7.5 laten is then 4M. AST 7.5 is distinguished by tne fact its latch is always set by a rising edge he RST 7S input pin, even if the jump to ice routine is inhibited by masking aten remains nigh until cleared by 4 FETIN, by a SIM instruction with ac: ‘ulator'oit 4 nigh, or by an internal pro- sor acknowledge to an AST 75 interrupt Sequent to the removal of the mask (oy IM instruction). The RESET IN signal ays sets all three AST mask bits, scumulator bit § is at the 1 level when SIM instruction is executed, the state ecumulator Bit 7 is loaded into tne SOD and tnus becomes available for inter to an external device. The SOO latcn is ected by the SIM insteuction if Bit 61s, (00 is always eset by the HESET TN al Urrbsuom Cycles: 1 States: 4 Flags: none o 085A 8080A/8085A INSTRUCTION SET INDEX Table 5-1 — Pa |aancm] =wesw j . sossa v 20858 CPU INSTRUCTIONS IN OPERATION CODE SEQUENCE 8085A INSTRUCTION SET SUMMARY BY FUNCTIONAL GROUPING Table 5:2 Table 5-3 cox» | #8 [wow Ince wae [or faa a Mev teompwnmm ($1 88 8s se came beer tease sue [ue lkoo oma e [oc fcc Ser teeta ae Gomer ot tibet eae Soo [31 [et spore] Se | how Isso = oe 8 foo |o x | & [tow ° oe O18 DELLS ELE remaae ™M T tns 3" 21m [key ‘ oe wie oe pa ae nae naa ce Jom Ser ci stieia ae ee